?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
fix uninitialized warnings with 'type.ref'
[tinycc.git] / i386-asm.c
blob6e1314cf3697e6d6122e9da8e6bc99330e5a6d3d
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 * Copyright (c) 2009 Frédéric Feret (x86_64 support)
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #define MAX_OPERANDS 3
23
24 #define TOK_ASM_first TOK_ASM_clc
25 #define TOK_ASM_last TOK_ASM_emms
26
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used with OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #ifdef TCC_TARGET_X86_64
41 # define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
42 # define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
43 # define OPC_WLX OPC_WLQ
44 #else
45 # define OPC_WLX OPC_WL
46 #endif
47
48 #define OPC_GROUP_SHIFT 13
49
50 /* in order to compress the operand type, we use specific operands and
51 we or only with EA */
52 enum {
53 OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
54 OPT_REG16, /* warning: value is hardcoded from TOK_ASM_xxx */
55 OPT_REG32, /* warning: value is hardcoded from TOK_ASM_xxx */
56 #ifdef TCC_TARGET_X86_64
57 OPT_REG64, /* warning: value is hardcoded from TOK_ASM_xxx */
58 #endif
59 OPT_MMX, /* warning: value is hardcoded from TOK_ASM_xxx */
60 OPT_SSE, /* warning: value is hardcoded from TOK_ASM_xxx */
61 OPT_CR, /* warning: value is hardcoded from TOK_ASM_xxx */
62 OPT_TR, /* warning: value is hardcoded from TOK_ASM_xxx */
63 OPT_DB, /* warning: value is hardcoded from TOK_ASM_xxx */
64 OPT_SEG,
65 OPT_ST,
66 OPT_IM8,
67 OPT_IM8S,
68 OPT_IM16,
69 OPT_IM32,
70 #ifdef TCC_TARGET_X86_64
71 OPT_IM64,
72 #endif
73 OPT_EAX, /* %al, %ax, %eax or %rax register */
74 OPT_ST0, /* %st(0) register */
75 OPT_CL, /* %cl register */
76 OPT_DX, /* %dx register */
77 OPT_ADDR, /* OP_EA with only offset */
78 OPT_INDIR, /* *(expr) */
79 /* composite types */
80 OPT_COMPOSITE_FIRST,
81 OPT_IM, /* IM8 | IM16 | IM32 | IM64 */
82 OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
83 OPT_REGW, /* REG16 | REG32 | REG64 */
84 OPT_IMW, /* IM16 | IM32 | IM64 */
85 #ifdef TCC_TARGET_X86_64
86 OPT_IMNO64, /* IM16 | IM32 */
87 #endif
88 /* can be ored with any OPT_xxx */
89 OPT_EA = 0x80
90 };
91
92 #define OP_REG8 (1 << OPT_REG8)
93 #define OP_REG16 (1 << OPT_REG16)
94 #define OP_REG32 (1 << OPT_REG32)
95 #define OP_MMX (1 << OPT_MMX)
96 #define OP_SSE (1 << OPT_SSE)
97 #define OP_CR (1 << OPT_CR)
98 #define OP_TR (1 << OPT_TR)
99 #define OP_DB (1 << OPT_DB)
100 #define OP_SEG (1 << OPT_SEG)
101 #define OP_ST (1 << OPT_ST)
102 #define OP_IM8 (1 << OPT_IM8)
103 #define OP_IM8S (1 << OPT_IM8S)
104 #define OP_IM16 (1 << OPT_IM16)
105 #define OP_IM32 (1 << OPT_IM32)
106 #define OP_EAX (1 << OPT_EAX)
107 #define OP_ST0 (1 << OPT_ST0)
108 #define OP_CL (1 << OPT_CL)
109 #define OP_DX (1 << OPT_DX)
110 #define OP_ADDR (1 << OPT_ADDR)
111 #define OP_INDIR (1 << OPT_INDIR)
112 #ifdef TCC_TARGET_X86_64
113 # define OP_REG64 (1 << OPT_REG64)
114 # define OP_IM64 (1 << OPT_IM64)
115 #else
116 # define OP_REG64 0
117 # define OP_IM64 0
118 #endif
119
120 #define OP_EA 0x40000000
121 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
122
123 #ifdef TCC_TARGET_X86_64
124 # define OP_IM OP_IM64
125 # define TREG_XAX TREG_RAX
126 # define TREG_XCX TREG_RCX
127 # define TREG_XDX TREG_RDX
128 #else
129 # define OP_IM OP_IM32
130 # define TREG_XAX TREG_EAX
131 # define TREG_XCX TREG_ECX
132 # define TREG_XDX TREG_EDX
133 #endif
134
135 typedef struct ASMInstr {
136 uint16_t sym;
137 uint16_t opcode;
138 uint16_t instr_type;
139 uint8_t nb_ops;
140 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
141 } ASMInstr;
142
143 typedef struct Operand {
144 uint32_t type;
145 int8_t reg; /* register, -1 if none */
146 int8_t reg2; /* second register, -1 if none */
147 uint8_t shift;
148 ExprValue e;
149 } Operand;
150
151 static const uint8_t reg_to_size[9] = {
152 /*
153 [OP_REG8] = 0,
154 [OP_REG16] = 1,
155 [OP_REG32] = 2,
156 #ifdef TCC_TARGET_X86_64
157 [OP_REG64] = 3,
158 #endif
159 */
160 0, 0, 1, 0, 2, 0, 0, 0, 3
161 };
162
163 #define NB_TEST_OPCODES 30
164
165 static const uint8_t test_bits[NB_TEST_OPCODES] = {
166 0x00, /* o */
167 0x01, /* no */
168 0x02, /* b */
169 0x02, /* c */
170 0x02, /* nae */
171 0x03, /* nb */
172 0x03, /* nc */
173 0x03, /* ae */
174 0x04, /* e */
175 0x04, /* z */
176 0x05, /* ne */
177 0x05, /* nz */
178 0x06, /* be */
179 0x06, /* na */
180 0x07, /* nbe */
181 0x07, /* a */
182 0x08, /* s */
183 0x09, /* ns */
184 0x0a, /* p */
185 0x0a, /* pe */
186 0x0b, /* np */
187 0x0b, /* po */
188 0x0c, /* l */
189 0x0c, /* nge */
190 0x0d, /* nl */
191 0x0d, /* ge */
192 0x0e, /* le */
193 0x0e, /* ng */
194 0x0f, /* nle */
195 0x0f, /* g */
196 };
197
198 static const uint8_t segment_prefixes[] = {
199 0x26, /* es */
200 0x2e, /* cs */
201 0x36, /* ss */
202 0x3e, /* ds */
203 0x64, /* fs */
204 0x65 /* gs */
205 };
206
207 static const ASMInstr asm_instrs[] = {
208 #define ALT(x) x
209 #define DEF_ASM_OP0(name, opcode)
210 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
211 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
212 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
213 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
214 #ifdef TCC_TARGET_X86_64
215 # include "x86_64-asm.h"
216 #else
217 # include "i386-asm.h"
218 #endif
219 /* last operation */
220 { 0, },
221 };
222
223 static const uint16_t op0_codes[] = {
224 #define ALT(x)
225 #define DEF_ASM_OP0(x, opcode) opcode,
226 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
227 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
228 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
229 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
230 #ifdef TCC_TARGET_X86_64
231 # include "x86_64-asm.h"
232 #else
233 # include "i386-asm.h"
234 #endif
235 };
236
237 static inline int get_reg_shift(TCCState *s1)
238 {
239 int shift, v;
240 #ifdef I386_ASM_16
241 if (s1->seg_size == 16)
242 error("invalid effective address");
243 #endif
244 v = asm_int_expr(s1);
245 switch(v) {
246 case 1:
247 shift = 0;
248 break;
249 case 2:
250 shift = 1;
251 break;
252 case 4:
253 shift = 2;
254 break;
255 case 8:
256 shift = 3;
257 break;
258 default:
259 expect("1, 2, 4 or 8 constant");
260 shift = 0;
261 break;
262 }
263 return shift;
264 }
265
266 static int asm_parse_reg(void)
267 {
268 int reg = 0;
269 if (tok != '%')
270 goto error_32;
271 next();
272 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
273 reg = tok - TOK_ASM_eax;
274 #ifdef TCC_TARGET_X86_64
275 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
276 reg = tok - TOK_ASM_rax;
277 #endif
278 #ifdef I386_ASM_16
279 } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) {
280 reg = tok - TOK_ASM_ax;
281 #endif
282 } else {
283 error_32:
284 expect("register");
285 }
286 next();
287 return reg;
288 }
289
290 static void parse_operand(TCCState *s1, Operand *op)
291 {
292 ExprValue e;
293 int reg, indir;
294 const char *p;
295
296 indir = 0;
297 if (tok == '*') {
298 next();
299 indir = OP_INDIR;
300 }
301
302 if (tok == '%') {
303 next();
304 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
305 reg = tok - TOK_ASM_al;
306 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
307 op->reg = reg & 7;
308 if ((op->type & OP_REG) && op->reg == TREG_XAX)
309 op->type |= OP_EAX;
310 else if (op->type == OP_REG8 && op->reg == TREG_XCX)
311 op->type |= OP_CL;
312 else if (op->type == OP_REG16 && op->reg == TREG_XDX)
313 op->type |= OP_DX;
314 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
315 op->type = OP_DB;
316 op->reg = tok - TOK_ASM_dr0;
317 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
318 op->type = OP_SEG;
319 op->reg = tok - TOK_ASM_es;
320 } else if (tok == TOK_ASM_st) {
321 op->type = OP_ST;
322 op->reg = 0;
323 next();
324 if (tok == '(') {
325 next();
326 if (tok != TOK_PPNUM)
327 goto reg_error;
328 p = tokc.cstr->data;
329 reg = p[0] - '0';
330 if ((unsigned)reg >= 8 || p[1] != '\0')
331 goto reg_error;
332 op->reg = reg;
333 next();
334 skip(')');
335 }
336 if (op->reg == 0)
337 op->type |= OP_ST0;
338 goto no_skip;
339 } else {
340 reg_error:
341 error("unknown register");
342 }
343 next();
344 no_skip: ;
345 } else if (tok == '$') {
346 /* constant value */
347 next();
348 asm_expr(s1, &e);
349 op->type = OP_IM;
350 op->e.v = e.v;
351 op->e.sym = e.sym;
352 if (!op->e.sym) {
353 if (op->e.v == (uint8_t)op->e.v)
354 op->type |= OP_IM8;
355 if (op->e.v == (int8_t)op->e.v)
356 op->type |= OP_IM8S;
357 if (op->e.v == (uint16_t)op->e.v)
358 op->type |= OP_IM16;
359 #ifdef TCC_TARGET_X86_64
360 if (op->e.v == (uint32_t)op->e.v)
361 op->type |= OP_IM32;
362 #endif
363 }
364 } else {
365 /* address(reg,reg2,shift) with all variants */
366 op->type = OP_EA;
367 op->reg = -1;
368 op->reg2 = -1;
369 op->shift = 0;
370 if (tok != '(') {
371 asm_expr(s1, &e);
372 op->e.v = e.v;
373 op->e.sym = e.sym;
374 } else {
375 op->e.v = 0;
376 op->e.sym = NULL;
377 }
378 if (tok == '(') {
379 next();
380 if (tok != ',') {
381 op->reg = asm_parse_reg();
382 }
383 if (tok == ',') {
384 next();
385 if (tok != ',') {
386 op->reg2 = asm_parse_reg();
387 }
388 if (tok == ',') {
389 next();
390 op->shift = get_reg_shift(s1);
391 }
392 }
393 skip(')');
394 }
395 if (op->reg == -1 && op->reg2 == -1)
396 op->type |= OP_ADDR;
397 }
398 op->type |= indir;
399 }
400
401 static void gen_expr32(ExprValue *pe)
402 {
403 gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
404 }
405
406 #ifdef TCC_TARGET_X86_64
407 static void gen_expr64(ExprValue *pe)
408 {
409 gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
410 }
411 #endif
412
413 /* XXX: unify with C code output ? */
414 static void gen_disp32(ExprValue *pe)
415 {
416 Sym *sym = pe->sym;
417 if (sym && sym->r == cur_text_section->sh_num) {
418 /* same section: we can output an absolute value. Note
419 that the TCC compiler behaves differently here because
420 it always outputs a relocation to ease (future) code
421 elimination in the linker */
422 gen_le32(pe->v + sym->jnext - ind - 4);
423 } else {
424 gen_addrpc32(VT_SYM, sym, pe->v);
425 }
426 }
427
428 #ifdef I386_ASM_16
429 static void gen_expr16(ExprValue *pe)
430 {
431 if (pe->sym)
432 greloc(cur_text_section, pe->sym, ind, R_386_16);
433 gen_le16(pe->v);
434 }
435 static void gen_disp16(ExprValue *pe)
436 {
437 Sym *sym;
438 sym = pe->sym;
439 if (sym) {
440 if (sym->r == cur_text_section->sh_num) {
441 /* same section: we can output an absolute value. Note
442 that the TCC compiler behaves differently here because
443 it always outputs a relocation to ease (future) code
444 elimination in the linker */
445 gen_le16(pe->v + sym->jnext - ind - 2);
446 } else {
447 greloc(cur_text_section, sym, ind, R_386_PC16);
448 gen_le16(pe->v - 2);
449 }
450 } else {
451 /* put an empty PC32 relocation */
452 put_elf_reloc(symtab_section, cur_text_section,
453 ind, R_386_PC16, 0);
454 gen_le16(pe->v - 2);
455 }
456 }
457 #endif
458
459 /* generate the modrm operand */
460 static inline void asm_modrm(int reg, Operand *op)
461 {
462 int mod, reg1, reg2, sib_reg1;
463
464 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
465 g(0xc0 + (reg << 3) + op->reg);
466 } else if (op->reg == -1 && op->reg2 == -1) {
467 /* displacement only */
468 #ifdef I386_ASM_16
469 if (tcc_state->seg_size == 16) {
470 g(0x06 + (reg << 3));
471 gen_expr16(&op->e);
472 } else if (tcc_state->seg_size == 32)
473 #endif
474 {
475 g(0x05 + (reg << 3));
476 gen_expr32(&op->e);
477 }
478 } else {
479 sib_reg1 = op->reg;
480 /* fist compute displacement encoding */
481 if (sib_reg1 == -1) {
482 sib_reg1 = 5;
483 mod = 0x00;
484 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
485 mod = 0x00;
486 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
487 mod = 0x40;
488 } else {
489 mod = 0x80;
490 }
491 /* compute if sib byte needed */
492 reg1 = op->reg;
493 if (op->reg2 != -1)
494 reg1 = 4;
495 #ifdef I386_ASM_16
496 if (tcc_state->seg_size == 32) {
497 #endif
498 g(mod + (reg << 3) + reg1);
499 if (reg1 == 4) {
500 /* add sib byte */
501 reg2 = op->reg2;
502 if (reg2 == -1)
503 reg2 = 4; /* indicate no index */
504 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
505 }
506 #ifdef I386_ASM_16
507 } else if (tcc_state->seg_size == 16) {
508 /* edi = 7, esi = 6 --> di = 5, si = 4 */
509 if ((reg1 == 6) || (reg1 == 7)) {
510 reg1 -= 2;
511 /* ebx = 3 --> bx = 7 */
512 } else if (reg1 == 3) {
513 reg1 = 7;
514 /* o32 = 5 --> o16 = 6 */
515 } else if (reg1 == 5) {
516 reg1 = 6;
517 /* sib not valid in 16-bit mode */
518 } else if (reg1 == 4) {
519 reg2 = op->reg2;
520 /* bp + si + offset */
521 if ((sib_reg1 == 5) && (reg2 == 6)) {
522 reg1 = 2;
523 /* bp + di + offset */
524 } else if ((sib_reg1 == 5) && (reg2 == 7)) {
525 reg1 = 3;
526 /* bx + si + offset */
527 } else if ((sib_reg1 == 3) && (reg2 == 6)) {
528 reg1 = 0;
529 /* bx + di + offset */
530 } else if ((sib_reg1 == 3) && (reg2 == 7)) {
531 reg1 = 1;
532 } else {
533 error("invalid effective address");
534 }
535 if (op->e.v == 0)
536 mod = 0;
537 } else {
538 error("invalid register");
539 }
540 g(mod + (reg << 3) + reg1);
541 }
542 #endif
543 /* add offset */
544 if (mod == 0x40) {
545 g(op->e.v);
546 } else if (mod == 0x80 || op->reg == -1) {
547 #ifdef I386_ASM_16
548 if (tcc_state->seg_size == 16)
549 gen_expr16(&op->e);
550 else if (tcc_state->seg_size == 32)
551 #endif
552 gen_expr32(&op->e);
553 }
554 }
555 }
556
557 static void asm_opcode(TCCState *s1, int opcode)
558 {
559 const ASMInstr *pa;
560 int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
561 int nb_ops, s;
562 Operand ops[MAX_OPERANDS], *pop;
563 int op_type[3]; /* decoded op type */
564 #ifdef I386_ASM_16
565 static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;
566 #endif
567
568 /* get operands */
569 pop = ops;
570 nb_ops = 0;
571 seg_prefix = 0;
572 for(;;) {
573 if (tok == ';' || tok == TOK_LINEFEED)
574 break;
575 if (nb_ops >= MAX_OPERANDS) {
576 error("incorrect number of operands");
577 }
578 parse_operand(s1, pop);
579 if (tok == ':') {
580 if (pop->type != OP_SEG || seg_prefix)
581 error("incorrect prefix");
582 seg_prefix = segment_prefixes[pop->reg];
583 next();
584 parse_operand(s1, pop);
585 #ifndef I386_ASM_16
586 if (!(pop->type & OP_EA)) {
587 error("segment prefix must be followed by memory reference");
588 }
589 #endif
590 }
591 pop++;
592 nb_ops++;
593 if (tok != ',')
594 break;
595 next();
596 }
597
598 is_short_jmp = 0;
599 s = 0; /* avoid warning */
600
601 /* optimize matching by using a lookup table (no hashing is needed
602 !) */
603 for(pa = asm_instrs; pa->sym != 0; pa++) {
604 s = 0;
605 if (pa->instr_type & OPC_FARITH) {
606 v = opcode - pa->sym;
607 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
608 continue;
609 } else if (pa->instr_type & OPC_ARITH) {
610 if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
611 continue;
612 s = (opcode - pa->sym) % NBWLX;
613 } else if (pa->instr_type & OPC_SHIFT) {
614 if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
615 continue;
616 s = (opcode - pa->sym) % NBWLX;
617 } else if (pa->instr_type & OPC_TEST) {
618 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
619 continue;
620 } else if (pa->instr_type & OPC_B) {
621 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
622 continue;
623 s = opcode - pa->sym;
624 } else if (pa->instr_type & OPC_WLX) {
625 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
626 continue;
627 s = opcode - pa->sym + 1;
628 } else {
629 if (pa->sym != opcode)
630 continue;
631 }
632 if (pa->nb_ops != nb_ops)
633 continue;
634 /* now decode and check each operand */
635 for(i = 0; i < nb_ops; i++) {
636 int op1, op2;
637 op1 = pa->op_type[i];
638 op2 = op1 & 0x1f;
639 switch(op2) {
640 case OPT_IM:
641 v = OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64;
642 break;
643 case OPT_REG:
644 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
645 break;
646 case OPT_REGW:
647 v = OP_REG16 | OP_REG32 | OP_REG64;
648 break;
649 case OPT_IMW:
650 v = OP_IM16 | OP_IM32 | OP_IM64;
651 break;
652 #ifdef TCC_TARGET_X86_64
653 case OPT_IMNO64:
654 v = OP_IM16 | OP_IM32;
655 break;
656 #endif
657 default:
658 v = 1 << op2;
659 break;
660 }
661 if (op1 & OPT_EA)
662 v |= OP_EA;
663 op_type[i] = v;
664 if ((ops[i].type & v) == 0)
665 goto next;
666 }
667 /* all is matching ! */
668 break;
669 next: ;
670 }
671 if (pa->sym == 0) {
672 if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
673 int b;
674 b = op0_codes[opcode - TOK_ASM_first];
675 #ifdef I386_ASM_16
676 if (opcode == TOK_ASM_o32) {
677 if (s1->seg_size == 32)
678 error("incorrect prefix");
679 else
680 o32 = data32 = 1;
681 } else if (opcode == TOK_ASM_a32) {
682 if (s1->seg_size == 32)
683 error("incorrect prefix");
684 else
685 a32 = addr32 = 1;
686 }
687 #endif
688 if (b & 0xff00)
689 g(b >> 8);
690 g(b);
691 return;
692 } else {
693 error("unknown opcode '%s'",
694 get_tok_str(opcode, NULL));
695 }
696 }
697 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
698 if (s == NBWLX-1) {
699 for(i = 0; s == NBWLX-1 && i < nb_ops; i++) {
700 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
701 s = reg_to_size[ops[i].type & OP_REG];
702 }
703 if (s == NBWLX-1) {
704 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
705 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))
706 s = 2;
707 else
708 error("cannot infer opcode suffix");
709 }
710 }
711
712 #ifdef I386_ASM_16
713 for(i = 0; i < nb_ops; i++) {
714 if (ops[i].type & OP_REG32) {
715 if (s1->seg_size == 16)
716 o32 = 1;
717 } else if (!(ops[i].type & OP_REG32)) {
718 if (s1->seg_size == 32)
719 o32 = 1;
720 }
721 }
722
723
724 if (s == 1 || (pa->instr_type & OPC_D16)) {
725 if (s1->seg_size == 32)
726 o32 = 1;
727 } else if (s == 2) {
728 if (s1->seg_size == 16) {
729 if (!(pa->instr_type & OPC_D16))
730 o32 = 1;
731 }
732 }
733
734 /* generate a16/a32 prefix if needed */
735 if ((a32 == 1) && (addr32 == 0))
736 g(0x67);
737 /* generate o16/o32 prefix if needed */
738 if ((o32 == 1) && (data32 == 0))
739 g(0x66);
740
741 addr32 = data32 = 0;
742 #else
743 /* generate data16 prefix if needed */
744 if (s == 1 || (pa->instr_type & OPC_D16))
745 g(0x66);
746 #ifdef TCC_TARGET_X86_64
747 else if (s == 3) {
748 /* generate REX prefix */
749 if ((opcode != TOK_ASM_push && opcode != TOK_ASM_pop)
750 || !(ops[0].type & OP_REG64))
751 g(0x48);
752 }
753 #endif
754 #endif
755
756 /* now generates the operation */
757 if (pa->instr_type & OPC_FWAIT)
758 g(0x9b);
759 if (seg_prefix)
760 g(seg_prefix);
761
762 v = pa->opcode;
763 if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
764 /* kludge for imul $im, %reg */
765 nb_ops = 3;
766 ops[2] = ops[1];
767 op_type[2] = op_type[1];
768 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
769 v--; /* int $3 case */
770 nb_ops = 0;
771 } else if ((v == 0x06 || v == 0x07)) {
772 if (ops[0].reg >= 4) {
773 /* push/pop %fs or %gs */
774 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
775 } else {
776 v += ops[0].reg << 3;
777 }
778 nb_ops = 0;
779 } else if (v <= 0x05) {
780 /* arith case */
781 v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
782 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
783 /* fpu arith case */
784 v += ((opcode - pa->sym) / 6) << 3;
785 }
786 if (pa->instr_type & OPC_REG) {
787 for(i = 0; i < nb_ops; i++) {
788 if (op_type[i] & (OP_REG | OP_ST)) {
789 v += ops[i].reg;
790 break;
791 }
792 }
793 /* mov $im, %reg case */
794 if (pa->opcode == 0xb0 && s >= 1)
795 v += 7;
796 }
797 if (pa->instr_type & OPC_B)
798 v += s >= 1;
799 if (pa->instr_type & OPC_TEST)
800 v += test_bits[opcode - pa->sym];
801 if (pa->instr_type & OPC_SHORTJMP) {
802 Sym *sym;
803 int jmp_disp;
804
805 /* see if we can really generate the jump with a byte offset */
806 sym = ops[0].e.sym;
807 if (!sym)
808 goto no_short_jump;
809 if (sym->r != cur_text_section->sh_num)
810 goto no_short_jump;
811 jmp_disp = ops[0].e.v + sym->jnext - ind - 2;
812 if (jmp_disp == (int8_t)jmp_disp) {
813 /* OK to generate jump */
814 is_short_jmp = 1;
815 ops[0].e.v = jmp_disp;
816 } else {
817 no_short_jump:
818 if (pa->instr_type & OPC_JMP) {
819 /* long jump will be allowed. need to modify the
820 opcode slightly */
821 if (v == 0xeb)
822 v = 0xe9;
823 else
824 v += 0x0f10;
825 } else {
826 error("invalid displacement");
827 }
828 }
829 }
830 op1 = v >> 8;
831 if (op1)
832 g(op1);
833 g(v);
834
835 /* search which operand will used for modrm */
836 modrm_index = 0;
837 if (pa->instr_type & OPC_SHIFT) {
838 reg = (opcode - pa->sym) / NBWLX;
839 if (reg == 6)
840 reg = 7;
841 } else if (pa->instr_type & OPC_ARITH) {
842 reg = (opcode - pa->sym) / NBWLX;
843 } else if (pa->instr_type & OPC_FARITH) {
844 reg = (opcode - pa->sym) / 6;
845 } else {
846 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
847 }
848 if (pa->instr_type & OPC_MODRM) {
849 /* first look for an ea operand */
850 for(i = 0;i < nb_ops; i++) {
851 if (op_type[i] & OP_EA)
852 goto modrm_found;
853 }
854 /* then if not found, a register or indirection (shift instructions) */
855 for(i = 0;i < nb_ops; i++) {
856 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
857 goto modrm_found;
858 }
859 #ifdef ASM_DEBUG
860 error("bad op table");
861 #endif
862 modrm_found:
863 modrm_index = i;
864 /* if a register is used in another operand then it is
865 used instead of group */
866 for(i = 0;i < nb_ops; i++) {
867 v = op_type[i];
868 if (i != modrm_index &&
869 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
870 reg = ops[i].reg;
871 break;
872 }
873 }
874
875 asm_modrm(reg, &ops[modrm_index]);
876 }
877
878 /* emit constants */
879 #ifndef TCC_TARGET_X86_64
880 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
881 /* ljmp or lcall kludge */
882 #ifdef I386_ASM_16
883 if (s1->seg_size == 16 && o32 == 0)
884 gen_expr16(&ops[1].e);
885 else
886 #endif
887 gen_expr32(&ops[1].e);
888 if (ops[0].e.sym)
889 error("cannot relocate");
890 gen_le16(ops[0].e.v);
891 return;
892 }
893 #endif
894 for(i = 0;i < nb_ops; i++) {
895 v = op_type[i];
896 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
897 /* if multiple sizes are given it means we must look
898 at the op size */
899 if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
900 if (s == 0)
901 v = OP_IM8;
902 else if (s == 1)
903 v = OP_IM16;
904 else if (s == 2 || (v & OP_IM64) == 0)
905 v = OP_IM32;
906 else
907 v = OP_IM64;
908 }
909 if (v & (OP_IM8 | OP_IM8S)) {
910 if (ops[i].e.sym)
911 goto error_relocate;
912 g(ops[i].e.v);
913 } else if (v & OP_IM16) {
914 #ifdef I386_ASM_16
915 if (s1->seg_size == 16)
916 gen_expr16(&ops[i].e);
917 else
918 #endif
919 if (ops[i].e.sym)
920 error_relocate:
921 error("cannot relocate");
922 else
923 gen_le16(ops[i].e.v);
924 } else {
925 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
926 if (is_short_jmp)
927 g(ops[i].e.v);
928 #ifdef I386_ASM_16
929 else if (s1->seg_size == 16)
930 gen_disp16(&ops[i].e);
931 #endif
932 else
933 gen_disp32(&ops[i].e);
934 } else {
935 #ifdef I386_ASM_16
936 if (s1->seg_size == 16 && !((o32 == 1) && (v & OP_IM32)))
937 gen_expr16(&ops[i].e);
938 else
939 #endif
940 #ifdef TCC_TARGET_X86_64
941 if (v & OP_IM64)
942 gen_expr64(&ops[i].e);
943 else
944 #endif
945 gen_expr32(&ops[i].e);
946 }
947 }
948 #ifdef I386_ASM_16
949 } else if (v & (OP_REG16 | OP_REG32)) {
950 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
951 /* jmp $r */
952 g(0xE0 + ops[i].reg);
953 }
954 #endif
955 #ifdef TCC_TARGET_X86_64
956 } else if (v & (OP_REG32 | OP_REG64)) {
957 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
958 /* jmp $r */
959 g(0xE0 + ops[i].reg);
960 }
961 #endif
962 }
963 }
964 #ifdef I386_ASM_16
965 a32 = o32 = 0;
966 #endif
967 }
968
969 #define NB_SAVED_REGS 3
970 #define NB_ASM_REGS 8
971
972 /* return the constraint priority (we allocate first the lowest
973 numbered constraints) */
974 static inline int constraint_priority(const char *str)
975 {
976 int priority, c, pr;
977
978 /* we take the lowest priority */
979 priority = 0;
980 for(;;) {
981 c = *str;
982 if (c == '\0')
983 break;
984 str++;
985 switch(c) {
986 case 'A':
987 pr = 0;
988 break;
989 case 'a':
990 case 'b':
991 case 'c':
992 case 'd':
993 case 'S':
994 case 'D':
995 pr = 1;
996 break;
997 case 'q':
998 pr = 2;
999 break;
1000 case 'r':
1001 pr = 3;
1002 break;
1003 case 'N':
1004 case 'M':
1005 case 'I':
1006 case 'i':
1007 case 'm':
1008 case 'g':
1009 pr = 4;
1010 break;
1011 default:
1012 error("unknown constraint '%c'", c);
1013 pr = 0;
1014 }
1015 if (pr > priority)
1016 priority = pr;
1017 }
1018 return priority;
1019 }
1020
1021 static const char *skip_constraint_modifiers(const char *p)
1022 {
1023 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1024 p++;
1025 return p;
1026 }
1027
1028 #define REG_OUT_MASK 0x01
1029 #define REG_IN_MASK 0x02
1030
1031 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1032
1033 static void asm_compute_constraints(ASMOperand *operands,
1034 int nb_operands, int nb_outputs,
1035 const uint8_t *clobber_regs,
1036 int *pout_reg)
1037 {
1038 ASMOperand *op;
1039 int sorted_op[MAX_ASM_OPERANDS];
1040 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1041 const char *str;
1042 uint8_t regs_allocated[NB_ASM_REGS];
1043
1044 /* init fields */
1045 for(i=0;i<nb_operands;i++) {
1046 op = &operands[i];
1047 op->input_index = -1;
1048 op->ref_index = -1;
1049 op->reg = -1;
1050 op->is_memory = 0;
1051 op->is_rw = 0;
1052 }
1053 /* compute constraint priority and evaluate references to output
1054 constraints if input constraints */
1055 for(i=0;i<nb_operands;i++) {
1056 op = &operands[i];
1057 str = op->constraint;
1058 str = skip_constraint_modifiers(str);
1059 if (isnum(*str) || *str == '[') {
1060 /* this is a reference to another constraint */
1061 k = find_constraint(operands, nb_operands, str, NULL);
1062 if ((unsigned)k >= i || i < nb_outputs)
1063 error("invalid reference in constraint %d ('%s')",
1064 i, str);
1065 op->ref_index = k;
1066 if (operands[k].input_index >= 0)
1067 error("cannot reference twice the same operand");
1068 operands[k].input_index = i;
1069 op->priority = 5;
1070 } else {
1071 op->priority = constraint_priority(str);
1072 }
1073 }
1074
1075 /* sort operands according to their priority */
1076 for(i=0;i<nb_operands;i++)
1077 sorted_op[i] = i;
1078 for(i=0;i<nb_operands - 1;i++) {
1079 for(j=i+1;j<nb_operands;j++) {
1080 p1 = operands[sorted_op[i]].priority;
1081 p2 = operands[sorted_op[j]].priority;
1082 if (p2 < p1) {
1083 tmp = sorted_op[i];
1084 sorted_op[i] = sorted_op[j];
1085 sorted_op[j] = tmp;
1086 }
1087 }
1088 }
1089
1090 for(i = 0;i < NB_ASM_REGS; i++) {
1091 if (clobber_regs[i])
1092 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1093 else
1094 regs_allocated[i] = 0;
1095 }
1096 /* esp cannot be used */
1097 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1098 /* ebp cannot be used yet */
1099 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1100
1101 /* allocate registers and generate corresponding asm moves */
1102 for(i=0;i<nb_operands;i++) {
1103 j = sorted_op[i];
1104 op = &operands[j];
1105 str = op->constraint;
1106 /* no need to allocate references */
1107 if (op->ref_index >= 0)
1108 continue;
1109 /* select if register is used for output, input or both */
1110 if (op->input_index >= 0) {
1111 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1112 } else if (j < nb_outputs) {
1113 reg_mask = REG_OUT_MASK;
1114 } else {
1115 reg_mask = REG_IN_MASK;
1116 }
1117 try_next:
1118 c = *str++;
1119 switch(c) {
1120 case '=':
1121 goto try_next;
1122 case '+':
1123 op->is_rw = 1;
1124 /* FALL THRU */
1125 case '&':
1126 if (j >= nb_outputs)
1127 error("'%c' modifier can only be applied to outputs", c);
1128 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1129 goto try_next;
1130 case 'A':
1131 /* allocate both eax and edx */
1132 if (is_reg_allocated(TREG_XAX) ||
1133 is_reg_allocated(TREG_XDX))
1134 goto try_next;
1135 op->is_llong = 1;
1136 op->reg = TREG_XAX;
1137 regs_allocated[TREG_XAX] |= reg_mask;
1138 regs_allocated[TREG_XDX] |= reg_mask;
1139 break;
1140 case 'a':
1141 reg = TREG_XAX;
1142 goto alloc_reg;
1143 case 'b':
1144 reg = 3;
1145 goto alloc_reg;
1146 case 'c':
1147 reg = TREG_XCX;
1148 goto alloc_reg;
1149 case 'd':
1150 reg = TREG_XDX;
1151 goto alloc_reg;
1152 case 'S':
1153 reg = 6;
1154 goto alloc_reg;
1155 case 'D':
1156 reg = 7;
1157 alloc_reg:
1158 if (is_reg_allocated(reg))
1159 goto try_next;
1160 goto reg_found;
1161 case 'q':
1162 /* eax, ebx, ecx or edx */
1163 for(reg = 0; reg < 4; reg++) {
1164 if (!is_reg_allocated(reg))
1165 goto reg_found;
1166 }
1167 goto try_next;
1168 case 'r':
1169 /* any general register */
1170 for(reg = 0; reg < 8; reg++) {
1171 if (!is_reg_allocated(reg))
1172 goto reg_found;
1173 }
1174 goto try_next;
1175 reg_found:
1176 /* now we can reload in the register */
1177 op->is_llong = 0;
1178 op->reg = reg;
1179 regs_allocated[reg] |= reg_mask;
1180 break;
1181 case 'i':
1182 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1183 goto try_next;
1184 break;
1185 case 'I':
1186 case 'N':
1187 case 'M':
1188 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1189 goto try_next;
1190 break;
1191 case 'm':
1192 case 'g':
1193 /* nothing special to do because the operand is already in
1194 memory, except if the pointer itself is stored in a
1195 memory variable (VT_LLOCAL case) */
1196 /* XXX: fix constant case */
1197 /* if it is a reference to a memory zone, it must lie
1198 in a register, so we reserve the register in the
1199 input registers and a load will be generated
1200 later */
1201 if (j < nb_outputs || c == 'm') {
1202 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1203 /* any general register */
1204 for(reg = 0; reg < 8; reg++) {
1205 if (!(regs_allocated[reg] & REG_IN_MASK))
1206 goto reg_found1;
1207 }
1208 goto try_next;
1209 reg_found1:
1210 /* now we can reload in the register */
1211 regs_allocated[reg] |= REG_IN_MASK;
1212 op->reg = reg;
1213 op->is_memory = 1;
1214 }
1215 }
1216 break;
1217 default:
1218 error("asm constraint %d ('%s') could not be satisfied",
1219 j, op->constraint);
1220 break;
1221 }
1222 /* if a reference is present for that operand, we assign it too */
1223 if (op->input_index >= 0) {
1224 operands[op->input_index].reg = op->reg;
1225 operands[op->input_index].is_llong = op->is_llong;
1226 }
1227 }
1228
1229 /* compute out_reg. It is used to store outputs registers to memory
1230 locations references by pointers (VT_LLOCAL case) */
1231 *pout_reg = -1;
1232 for(i=0;i<nb_operands;i++) {
1233 op = &operands[i];
1234 if (op->reg >= 0 &&
1235 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1236 !op->is_memory) {
1237 for(reg = 0; reg < 8; reg++) {
1238 if (!(regs_allocated[reg] & REG_OUT_MASK))
1239 goto reg_found2;
1240 }
1241 error("could not find free output register for reloading");
1242 reg_found2:
1243 *pout_reg = reg;
1244 break;
1245 }
1246 }
1247
1248 /* print sorted constraints */
1249 #ifdef ASM_DEBUG
1250 for(i=0;i<nb_operands;i++) {
1251 j = sorted_op[i];
1252 op = &operands[j];
1253 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1254 j,
1255 op->id ? get_tok_str(op->id, NULL) : "",
1256 op->constraint,
1257 op->vt->r,
1258 op->reg);
1259 }
1260 if (*pout_reg >= 0)
1261 printf("out_reg=%d\n", *pout_reg);
1262 #endif
1263 }
1264
1265 static void subst_asm_operand(CString *add_str,
1266 SValue *sv, int modifier)
1267 {
1268 int r, reg, size, val;
1269 char buf[64];
1270
1271 r = sv->r;
1272 if ((r & VT_VALMASK) == VT_CONST) {
1273 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1274 cstr_ccat(add_str, '$');
1275 if (r & VT_SYM) {
1276 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1277 if (sv->c.i != 0) {
1278 cstr_ccat(add_str, '+');
1279 } else {
1280 return;
1281 }
1282 }
1283 val = sv->c.i;
1284 if (modifier == 'n')
1285 val = -val;
1286 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1287 cstr_cat(add_str, buf);
1288 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1289 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1290 cstr_cat(add_str, buf);
1291 } else if (r & VT_LVAL) {
1292 reg = r & VT_VALMASK;
1293 if (reg >= VT_CONST)
1294 error("internal compiler error");
1295 snprintf(buf, sizeof(buf), "(%%%s)",
1296 get_tok_str(TOK_ASM_eax + reg, NULL));
1297 cstr_cat(add_str, buf);
1298 } else {
1299 /* register case */
1300 reg = r & VT_VALMASK;
1301 if (reg >= VT_CONST)
1302 error("internal compiler error");
1303
1304 /* choose register operand size */
1305 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1306 size = 1;
1307 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1308 size = 2;
1309 #ifdef TCC_TARGET_X86_64
1310 else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
1311 size = 8;
1312 #endif
1313 else
1314 size = 4;
1315 if (size == 1 && reg >= 4)
1316 size = 4;
1317
1318 if (modifier == 'b') {
1319 if (reg >= 4)
1320 error("cannot use byte register");
1321 size = 1;
1322 } else if (modifier == 'h') {
1323 if (reg >= 4)
1324 error("cannot use byte register");
1325 size = -1;
1326 } else if (modifier == 'w') {
1327 size = 2;
1328 #ifdef TCC_TARGET_X86_64
1329 } else if (modifier == 'q') {
1330 size = 8;
1331 #endif
1332 }
1333
1334 switch(size) {
1335 case -1:
1336 reg = TOK_ASM_ah + reg;
1337 break;
1338 case 1:
1339 reg = TOK_ASM_al + reg;
1340 break;
1341 case 2:
1342 reg = TOK_ASM_ax + reg;
1343 break;
1344 default:
1345 reg = TOK_ASM_eax + reg;
1346 break;
1347 #ifdef TCC_TARGET_X86_64
1348 case 8:
1349 reg = TOK_ASM_rax + reg;
1350 break;
1351 #endif
1352 }
1353 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1354 cstr_cat(add_str, buf);
1355 }
1356 }
1357
1358 /* generate prolog and epilog code for asm statment */
1359 static void asm_gen_code(ASMOperand *operands, int nb_operands,
1360 int nb_outputs, int is_output,
1361 uint8_t *clobber_regs,
1362 int out_reg)
1363 {
1364 uint8_t regs_allocated[NB_ASM_REGS];
1365 ASMOperand *op;
1366 int i, reg;
1367 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1368
1369 /* mark all used registers */
1370 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1371 for(i = 0; i < nb_operands;i++) {
1372 op = &operands[i];
1373 if (op->reg >= 0)
1374 regs_allocated[op->reg] = 1;
1375 }
1376 if (!is_output) {
1377 /* generate reg save code */
1378 for(i = 0; i < NB_SAVED_REGS; i++) {
1379 reg = reg_saved[i];
1380 if (regs_allocated[reg]) {
1381 #ifdef I386_ASM_16
1382 if (tcc_state->seg_size == 16)
1383 g(0x66);
1384 #endif
1385 g(0x50 + reg);
1386 }
1387 }
1388
1389 /* generate load code */
1390 for(i = 0; i < nb_operands; i++) {
1391 op = &operands[i];
1392 if (op->reg >= 0) {
1393 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1394 op->is_memory) {
1395 /* memory reference case (for both input and
1396 output cases) */
1397 SValue sv;
1398 sv = *op->vt;
1399 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1400 load(op->reg, &sv);
1401 } else if (i >= nb_outputs || op->is_rw) {
1402 /* load value in register */
1403 load(op->reg, op->vt);
1404 if (op->is_llong) {
1405 SValue sv;
1406 sv = *op->vt;
1407 sv.c.ul += 4;
1408 load(TREG_XDX, &sv);
1409 }
1410 }
1411 }
1412 }
1413 } else {
1414 /* generate save code */
1415 for(i = 0 ; i < nb_outputs; i++) {
1416 op = &operands[i];
1417 if (op->reg >= 0) {
1418 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1419 if (!op->is_memory) {
1420 SValue sv;
1421 sv = *op->vt;
1422 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1423 load(out_reg, &sv);
1424
1425 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1426 store(op->reg, &sv);
1427 }
1428 } else {
1429 store(op->reg, op->vt);
1430 if (op->is_llong) {
1431 SValue sv;
1432 sv = *op->vt;
1433 sv.c.ul += 4;
1434 store(TREG_XDX, &sv);
1435 }
1436 }
1437 }
1438 }
1439 /* generate reg restore code */
1440 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1441 reg = reg_saved[i];
1442 if (regs_allocated[reg]) {
1443 #ifdef I386_ASM_16
1444 if (tcc_state->seg_size == 16)
1445 g(0x66);
1446 #endif
1447 g(0x58 + reg);
1448 }
1449 }
1450 }
1451 }
1452
1453 static void asm_clobber(uint8_t *clobber_regs, const char *str)
1454 {
1455 int reg;
1456 TokenSym *ts;
1457
1458 if (!strcmp(str, "memory") ||
1459 !strcmp(str, "cc"))
1460 return;
1461 ts = tok_alloc(str, strlen(str));
1462 reg = ts->tok;
1463 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1464 reg -= TOK_ASM_eax;
1465 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1466 reg -= TOK_ASM_ax;
1467 #ifdef TCC_TARGET_X86_64
1468 } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1469 reg -= TOK_ASM_rax;
1470 #endif
1471 } else {
1472 error("invalid clobber register '%s'", str);
1473 }
1474 clobber_regs[reg] = 1;
1475 }
Tiny C Compiler main repository