src/runtime/x86-64-arch.c

   1 /*
   2  * This software is part of the SBCL system. See the README file for
   3  * more information.
   4  *
   5  * This software is derived from the CMU CL system, which was
   6  * written at Carnegie Mellon University and released into the
   7  * public domain. The software is in the public domain and is
   8  * provided with absolutely no warranty. See the COPYING and CREDITS
   9  * files for more information.
  10  */
  11
  12 #include <stdio.h>
  13
  14 #include "sbcl.h"
  15 #include "runtime.h"
  16 #include "globals.h"
  17 #include "validate.h"
  18 #include "os.h"
  19 #include "sbcl.h"
  20 #include "arch.h"
  21 #include "lispregs.h"
  22 #include "signal.h"
  23 #include "alloc.h"
  24 #include "interrupt.h"
  25 #include "interr.h"
  26 #include "breakpoint.h"
  27 #include "thread.h"
  28 #include "pseudo-atomic.h"
  29
  30 #include "genesis/static-symbols.h"
  31 #include "genesis/symbol.h"
  32
  33 #define BREAKPOINT_INST 0xcc    /* INT3 */
  34 #define UD2_INST 0x0b0f         /* UD2 */
  35
  36 #ifndef LISP_FEATURE_UD2_BREAKPOINTS
  37 #define BREAKPOINT_WIDTH 1
  38 #else
  39 #define BREAKPOINT_WIDTH 2
  40 #endif
  41
  42 unsigned int cpuid_fn1_ecx;
  43 unsigned int avx_supported = 0;
  44
  45 static void cpuid(unsigned info, unsigned subinfo,
  46                   unsigned *eax, unsigned *ebx, unsigned *ecx, unsigned *edx)
  47 {
  48 #ifdef _MSC_VER
  49   int regs[4];
  50   __cpuid(regs, info);
  51   *eax = regs[0];
  52   *ebx = regs[1];
  53   *ecx = regs[2];
  54   *edx = regs[3];
  55 #else
  56   __asm__("cpuid;"                                            /* assembly code */
  57           :"=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) /* outputs */
  58           :"a" (info), "c" (subinfo)                          /* input: info into eax,
  59                                                                  subinfo to ecx */
  60            /* clobbers: none */
  61           );
  62 #endif
  63 }
  64
  65 static void xgetbv(unsigned *eax, unsigned *edx)
  66 {
  67   __asm__("xgetbv;"
  68           :"=a" (*eax), "=d" (*edx)
  69           : "c" (0));
  70 }
  71
  72 void arch_init(void)
  73 {
  74   unsigned int eax, ebx, ecx, edx;
  75
  76   cpuid(0, 0, &eax, &ebx, &ecx, &edx);
  77   if (eax >= 1) { // see if we can execute basic id function 1
  78       unsigned avx_mask = 0x18000000; // OXSAVE and AVX
  79       cpuid(1, 0, &eax, &ebx, &ecx, &edx);
  80       cpuid_fn1_ecx = ecx;
  81       if ((ecx & avx_mask) == avx_mask) {
  82           xgetbv(&eax, &edx);
  83           if ((eax & 0x06) == 0x06) // YMM and XMM
  84               avx_supported = 1;
  85       }
  86   }
  87 }
  88
  89 #define FILL_VECTOR_T "FILL-VECTOR/T"
  90
  91 // Poke in a byte that changes an opcode to enable faster vector fill.
  92 // Using fixed offsets and bytes is no worse than what we do elsewhere.
  93 void tune_asm_routines_for_microarch(void)
  94 {
  95     // I don't know if this works on Windows
  96 #ifndef _MSC_VER
  97     unsigned int eax, ebx, ecx, edx;
  98     cpuid(0, 0, &eax, &ebx, &ecx, &edx);
  99     if (eax >= 7) {
 100         cpuid(7, 0, &eax, &ebx, &ecx, &edx);
 101         if (ebx & (1<<9)) // Enhanced Repeat Movs/Stos
 102           asm_routine_poke(FILL_VECTOR_T, 0x12, 0x7C); // Change JMP to JL
 103     }
 104 #endif
 105 }
 106
 107 /* Undo code patches so that the core file applies to the most generic
 108    microarchitecture on startup. As it happens, FILL-VECTOR/T is fine
 109    either way, but in general this might not be true for code using
 110    instructions that don't exist on some cpu family members */
 111 void untune_asm_routines_for_microarch(void)
 112 {
 113     asm_routine_poke(FILL_VECTOR_T, 0x12, 0xEB); // Change JL to JMP
 114 }
 115
 116 #ifndef _WIN64
 117 os_vm_address_t
 118 arch_get_bad_addr(int sig, siginfo_t *code, os_context_t *context)
 119 {
 120     return (os_vm_address_t)code->si_addr;
 121 }
 122 #endif
 123
 124 \f
 125 /*
 126  * hacking signal contexts
 127  *
 128  * (This depends both on architecture, which determines what we might
 129  * want to get to, and on OS, which determines how we get to it.)
 130  */
 131
 132 os_context_register_t *
 133 context_eflags_addr(os_context_t *context)
 134 {
 135 #if defined __linux__ || defined __sun
 136     /* KLUDGE: As of kernel 2.2.14 on Red Hat 6.2, there's code in the
 137      * <sys/ucontext.h> file to define symbolic names for offsets into
 138      * gregs[], but it's conditional on __USE_GNU and not defined, so
 139      * we need to do this nasty absolute index magic number thing
 140      * instead. */
 141     return (os_context_register_t*)&context->uc_mcontext.gregs[17];
 142 #elif defined LISP_FEATURE_FREEBSD || defined(__DragonFly__)
 143     return &context->uc_mcontext.mc_rflags;
 144 #elif defined LISP_FEATURE_DARWIN
 145     return CONTEXT_ADDR_FROM_STEM(rflags);
 146 #elif defined __OpenBSD__
 147     return &context->sc_rflags;
 148 #elif defined __NetBSD__
 149     return CONTEXT_ADDR_FROM_STEM(RFLAGS);
 150 #elif defined _WIN64
 151     return (os_context_register_t*)&context->win32_context->EFlags;
 152 #else
 153 #error unsupported OS
 154 #endif
 155 }
 156 \f
 157 void arch_skip_instruction(os_context_t *context)
 158 {
 159     /* Assuming we get here via an INT3 xxx instruction, the PC now
 160      * points to the interrupt code (a Lisp value) so we just move
 161      * past it. Skip the code; after that, if the code is an
 162      * error-trap or cerror-trap then skip the data bytes that follow. */
 163
 164     long code;
 165
 166     /* Get and skip the Lisp interrupt code. */
 167     code = *(char*)(*os_context_pc_addr(context))++;
 168     switch (code)
 169         {
 170         case trap_Error:
 171         case trap_Cerror:
 172             skip_internal_error(context);
 173
 174             break;
 175
 176         case trap_Breakpoint:           /* not tested */
 177         case trap_FunEndBreakpoint: /* not tested */
 178             break;
 179
 180 #ifdef LISP_FEATURE_SB_SAFEPOINT
 181         case trap_GlobalSafepoint:
 182         case trap_CspSafepoint:
 183 #endif
 184         case trap_PendingInterrupt:
 185         case trap_Halt:
 186         case trap_SingleStepAround:
 187         case trap_SingleStepBefore:
 188         case trap_InvalidArgCount:
 189             /* only needed to skip the Code */
 190             break;
 191
 192         default:
 193             fprintf(stderr,"[arch_skip_inst invalid code %ld\n]\n",code);
 194             break;
 195         }
 196
 197     FSHOW((stderr,
 198            "/[arch_skip_inst resuming at %x]\n",
 199            *os_context_pc_addr(context)));
 200 }
 201
 202 unsigned char *
 203 arch_internal_error_arguments(os_context_t *context)
 204 {
 205     return 1 + (unsigned char *)(*os_context_pc_addr(context));
 206 }
 207
 208 boolean
 209 arch_pseudo_atomic_atomic(os_context_t *context)
 210 {
 211     return get_pseudo_atomic_atomic(arch_os_get_current_thread());
 212 }
 213
 214 void
 215 arch_set_pseudo_atomic_interrupted(os_context_t *context)
 216 {
 217     struct thread *thread = arch_os_get_current_thread();
 218     set_pseudo_atomic_interrupted(thread);
 219 }
 220
 221 void
 222 arch_clear_pseudo_atomic_interrupted(os_context_t *context)
 223 {
 224     struct thread *thread = arch_os_get_current_thread();
 225     clear_pseudo_atomic_interrupted(thread);
 226 }
 227 \f
 228 /*
 229  * This stuff seems to get called for TRACE and debug activity.
 230  */
 231
 232 unsigned int
 233 arch_install_breakpoint(void *pc)
 234 {
 235     unsigned int result = *(unsigned int*)pc;
 236
 237 #ifndef LISP_FEATURE_UD2_BREAKPOINTS
 238     *(char*)pc = BREAKPOINT_INST;               /* x86 INT3       */
 239     *((char*)pc+1) = trap_Breakpoint;           /* Lisp trap code */
 240 #else
 241     *(char*)pc = UD2_INST & 0xff;
 242     *((char*)pc+1) = UD2_INST >> 8;
 243     *((char*)pc+2) = trap_Breakpoint;
 244 #endif
 245
 246     return result;
 247 }
 248
 249 void
 250 arch_remove_breakpoint(void *pc, unsigned int orig_inst)
 251 {
 252     *((char *)pc) = orig_inst & 0xff;
 253     *((char *)pc + 1) = (orig_inst & 0xff00) >> 8;
 254 #if BREAKPOINT_WIDTH > 1
 255     *((char *)pc + 2) = (orig_inst & 0xff0000) >> 16;
 256 #endif
 257 }
 258 \f
 259 /* When single stepping, single_stepping holds the original instruction
 260  * PC location. */
 261 unsigned int *single_stepping = NULL;
 262 #ifdef CANNOT_GET_TO_SINGLE_STEP_FLAG
 263 unsigned int  single_step_save1;
 264 unsigned int  single_step_save2;
 265 unsigned int  single_step_save3;
 266 #endif
 267
 268 void
 269 arch_do_displaced_inst(os_context_t *context, unsigned int orig_inst)
 270 {
 271     unsigned int *pc = (unsigned int*)(*os_context_pc_addr(context));
 272
 273     /* Put the original instruction back. */
 274     arch_remove_breakpoint(pc, orig_inst);
 275
 276 #ifdef CANNOT_GET_TO_SINGLE_STEP_FLAG
 277     /* Install helper instructions for the single step:
 278      * pushf; or [esp],0x100; popf. */
 279     single_step_save1 = *(pc-3);
 280     single_step_save2 = *(pc-2);
 281     single_step_save3 = *(pc-1);
 282     *(pc-3) = 0x9c909090;
 283     *(pc-2) = 0x00240c81;
 284     *(pc-1) = 0x9d000001;
 285 #else
 286     *context_eflags_addr(context) |= 0x100;
 287 #endif
 288
 289     single_stepping = pc;
 290
 291 #ifdef CANNOT_GET_TO_SINGLE_STEP_FLAG
 292     *os_context_pc_addr(context) = (os_context_register_t)((char *)pc - 9);
 293 #endif
 294 }
 295
 296 void
 297 arch_handle_breakpoint(os_context_t *context)
 298 {
 299     *os_context_pc_addr(context) -= BREAKPOINT_WIDTH;
 300     handle_breakpoint(context);
 301 }
 302
 303 void
 304 arch_handle_fun_end_breakpoint(os_context_t *context)
 305 {
 306     *os_context_pc_addr(context) -= BREAKPOINT_WIDTH;
 307     *os_context_pc_addr(context) =
 308         (uword_t)handle_fun_end_breakpoint(context);
 309 }
 310
 311 void
 312 arch_handle_single_step_trap(os_context_t *context, int trap)
 313 {
 314     arch_skip_instruction(context);
 315     /* On x86-64 the fdefn / function is always in RAX, so we pass
 316      * 0 as the register_offset. */
 317     handle_single_step_trap(context, trap, 0);
 318 }
 319
 320 \f
 321 void
 322 restore_breakpoint_from_single_step(os_context_t * context)
 323 {
 324 #ifdef CANNOT_GET_TO_SINGLE_STEP_FLAG
 325     /* Un-install single step helper instructions. */
 326     *(single_stepping-3) = single_step_save1;
 327     *(single_stepping-2) = single_step_save2;
 328     *(single_stepping-1) = single_step_save3;
 329 #else
 330     *context_eflags_addr(context) &= ~0x100;
 331 #endif
 332     /* Re-install the breakpoint if possible. */
 333     if (((char *)*os_context_pc_addr(context) >
 334          (char *)single_stepping) &&
 335         ((char *)*os_context_pc_addr(context) <=
 336          (char *)single_stepping + BREAKPOINT_WIDTH)) {
 337         fprintf(stderr, "warning: couldn't reinstall breakpoint\n");
 338     } else {
 339         arch_install_breakpoint(single_stepping);
 340     }
 341
 342     single_stepping = NULL;
 343     return;
 344 }
 345
 346 void
 347 sigtrap_handler(int signal, siginfo_t *info, os_context_t *context)
 348 {
 349     unsigned int trap;
 350
 351     if (single_stepping) {
 352         restore_breakpoint_from_single_step(context);
 353         return;
 354     }
 355
 356     /* This is just for info in case the monitor wants to print an
 357      * approximation. */
 358     access_control_stack_pointer(arch_os_get_current_thread()) =
 359         (lispobj *)*os_context_sp_addr(context);
 360
 361     /* On entry %eip points just after the INT3 byte and aims at the
 362      * 'kind' value (eg trap_Cerror). For error-trap and Cerror-trap a
 363      * number of bytes will follow, the first is the length of the byte
 364      * arguments to follow. */
 365     trap = *(unsigned char *)(*os_context_pc_addr(context));
 366
 367     handle_trap(context, trap);
 368 }
 369
 370 void
 371 sigill_handler(int signal, siginfo_t *siginfo, os_context_t *context) {
 372     /* Triggering SIGTRAP using int3 is unreliable on OS X/x86, so
 373      * we need to use illegal instructions for traps.
 374      */
 375 #if defined(LISP_FEATURE_UD2_BREAKPOINTS) && !defined(LISP_FEATURE_MACH_EXCEPTION_HANDLER)
 376     if (*((unsigned short *)*os_context_pc_addr(context)) == UD2_INST) {
 377         *os_context_pc_addr(context) += 2;
 378         return sigtrap_handler(signal, siginfo, context);
 379     }
 380 #endif
 381
 382     fake_foreign_function_call(context);
 383     lose("Unhandled SIGILL at %p.", *os_context_pc_addr(context));
 384 }
 385
 386 #ifdef X86_64_SIGFPE_FIXUP
 387 #define MXCSR_IE (0x01)         /* Invalid Operation */
 388 #define MXCSR_DE (0x02)         /* Denormal */
 389 #define MXCSR_ZE (0x04)         /* Devide-by-Zero */
 390 #define MXCSR_OE (0x08)         /* Overflow */
 391 #define MXCSR_UE (0x10)         /* Underflow */
 392 #define MXCSR_PE (0x20)         /* Precision */
 393
 394 static inline int
 395 mxcsr_to_code(unsigned int mxcsr)
 396 {
 397     /* Extract unmasked exception bits. */
 398     mxcsr &= ~(mxcsr >> 7) & 0x3F;
 399
 400     /* This order is defined at "Intel 64 and IA-32 Architectures
 401      * Software Developerfs Manual" Volume 1: "Basic Architecture",
 402      * 4.9.2 "Floating-Point Exception Priority". */
 403     if (mxcsr & MXCSR_IE)
 404         return FPE_FLTINV;
 405     else if (mxcsr & MXCSR_ZE)
 406         return FPE_FLTDIV;
 407     else if (mxcsr & MXCSR_DE)
 408         return FPE_FLTUND;
 409     else if (mxcsr & MXCSR_OE)
 410         return FPE_FLTOVF;
 411     else if (mxcsr & MXCSR_UE)
 412         return FPE_FLTUND;
 413     else if (mxcsr & MXCSR_PE)
 414         return FPE_FLTRES;
 415
 416     return 0;
 417 }
 418
 419 static void
 420 sigfpe_handler(int signal, siginfo_t *siginfo, os_context_t *context)
 421 {
 422     unsigned int *mxcsr = arch_os_context_mxcsr_addr(context);
 423
 424 #ifndef LISP_FEATURE_DARWIN
 425     /* Darwin doesn't handle accrued bits right. */
 426     if (siginfo->si_code == 0)
 427 #endif
 428     { /* XMM exception */
 429         siginfo->si_code = mxcsr_to_code(*mxcsr);
 430
 431         /* Clear sticky exception flag. */
 432         *mxcsr &= ~0x3F;
 433     }
 434
 435     interrupt_handle_now(signal, siginfo, context);
 436 }
 437 #endif
 438
 439 void
 440 arch_install_interrupt_handlers()
 441 {
 442     SHOW("entering arch_install_interrupt_handlers()");
 443
 444     /* Note: The old CMU CL code here used sigtrap_handler() to handle
 445      * SIGILL as well as SIGTRAP. I couldn't see any reason to do
 446      * things that way. So, I changed to separate handlers when
 447      * debugging a problem on OpenBSD, where SBCL wasn't catching
 448      * SIGILL properly, but was instead letting the process be
 449      * terminated with an "Illegal instruction" output. If this change
 450      * turns out to break something (maybe breakpoint handling on some
 451      * OS I haven't tested on?) and we have to go back to the old CMU
 452      * CL way, I hope there will at least be a comment to explain
 453      * why.. -- WHN 2001-06-07 */
 454 #if !defined(LISP_FEATURE_MACH_EXCEPTION_HANDLER) && !defined(LISP_FEATURE_WIN32)
 455     undoably_install_low_level_interrupt_handler(SIGILL , sigill_handler);
 456     undoably_install_low_level_interrupt_handler(SIGTRAP, sigtrap_handler);
 457 #endif
 458
 459 #if defined(X86_64_SIGFPE_FIXUP) && !defined(LISP_FEATURE_WIN32)
 460     undoably_install_low_level_interrupt_handler(SIGFPE, sigfpe_handler);
 461 #endif
 462
 463     SHOW("returning from arch_install_interrupt_handlers()");
 464 }
 465 \f
 466 #ifdef LISP_FEATURE_LINKAGE_TABLE
 467 /* FIXME: It might be cleaner to generate these from the lisp side of
 468  * things.
 469  */
 470
 471 void
 472 arch_write_linkage_table_jmp(char *reloc_addr, void *target_addr)
 473 {
 474     uword_t addr = (uword_t)target_addr;
 475     int i;
 476
 477     *reloc_addr++ = 0xFF; /* Opcode for near jump to absolute reg/mem64. */
 478     *reloc_addr++ = 0x25; /* ModRM #b00 100 101, i.e. RIP-relative. */
 479     *reloc_addr++ = 0x00; /* 32-bit displacement field = 0 */
 480     *reloc_addr++ = 0x00; /* ... */
 481     *reloc_addr++ = 0x00; /* ... */
 482     *reloc_addr++ = 0x00; /* ... */
 483
 484     for (i = 0; i < 8; i++) {
 485         *reloc_addr++ = addr & 0xff;
 486         addr >>= 8;
 487     }
 488
 489     /* write a nop for good measure. */
 490     *reloc_addr = 0x90;
 491 }
 492
 493 void
 494 arch_write_linkage_table_ref(void *reloc_addr, void *target_addr)
 495 {
 496     *(uword_t *)reloc_addr = (uword_t)target_addr;
 497 }
 498
 499 #endif
 500
 501 /* These setup and check *both* the sse2 and x87 FPUs. While lisp code
 502    only uses the sse2 FPU, other code (such as libc) may use the x87 FPU.
 503  */
 504
 505 unsigned int
 506 arch_get_fp_modes()
 507 {
 508     unsigned int temp;
 509     unsigned int result;
 510     /* return the x87 exception flags ored in with the sse2
 511      * control+status flags */
 512     asm ("fnstsw %0" : "=m" (temp));
 513     result = temp;
 514     result &= 0x3F;
 515     asm ("stmxcsr %0" : "=m" (temp));
 516     result |= temp;
 517     /* flip exception mask bits */
 518     return result ^ (0x3F << 7);
 519 }
 520
 521 struct fpenv
 522 {
 523     unsigned short cw;
 524     unsigned short unused1;
 525     unsigned short sw;
 526     unsigned short unused2;
 527     unsigned int other_regs[5];
 528 };
 529
 530 void
 531 arch_set_fp_modes(unsigned int mxcsr)
 532 {
 533     struct fpenv f_env;
 534     unsigned int temp;
 535
 536     /* turn trap enable bits into exception mask */
 537     mxcsr ^= 0x3F << 7;
 538
 539     /* set x87 modes */
 540     asm ("fnstenv %0" : "=m" (f_env));
 541     /* set control word: always long double precision
 542      * get traps and rounding from mxcsr word */
 543     f_env.cw = 0x300 | ((mxcsr >> 7) & 0x3F) | (((mxcsr >> 13) & 0x3) << 10);
 544     /* set status word: only override exception flags, from mxcsr */
 545     f_env.sw &= ~0x3F;
 546     f_env.sw |= (mxcsr & 0x3F);
 547
 548     asm ("fldenv %0" : : "m" (f_env));
 549
 550     /* now, simply, load up the mxcsr register */
 551     temp = mxcsr;
 552     asm ("ldmxcsr %0" : : "m" (temp));
 553 }
 554
 555 #ifdef LISP_FEATURE_IMMOBILE_CODE
 556 /// Return the Lisp object that fdefn's raw_addr slot jumps to.
 557 /// This will either be:
 558 /// (1) a simple-fun,
 559 /// (2) a funcallable-instance with an embedded trampoline that makes
 560 ///     it resemble a simple-fun in terms of call convention, or
 561 /// (3) a code-component with no simple-fun within it, that makes
 562 ///     closures and other funcallable-instances look like simple-funs.
 563 lispobj fdefn_raw_referent(struct fdefn* fdefn) {
 564     extern unsigned ASM_ROUTINES_END;
 565     if (((lispobj)fdefn->raw_addr & 0xFE) == 0xE8) {  // looks good
 566         unsigned int raw_fun = (int)(long)&fdefn->raw_addr + 5 // length of "JMP rel32"
 567           + *(int*)((char*)&fdefn->raw_addr + 1);
 568         switch (((unsigned char*)&fdefn->raw_addr)[5]) {
 569         case 0x00: // no closure/fin trampoline
 570           // If the target is an assembly routine, there is no simple-fun
 571           // that corresponds to the entry point. The code is kept live
 572           // by *ASSEMBLER-OBJECTS*. Otherwise, return the simple-fun.
 573           return raw_fun < ASM_ROUTINES_END ? 0 : raw_fun - FUN_RAW_ADDR_OFFSET;
 574         case 0x48: // embedded funcallable instance trampoline
 575           return (raw_fun - (4<<WORD_SHIFT)) | FUN_POINTER_LOWTAG;
 576         case 0x90: // general closure/fin trampoline
 577           return (raw_fun - offsetof(struct code, constants)) | OTHER_POINTER_LOWTAG;
 578         }
 579     } else if (fdefn->raw_addr == 0)
 580         return 0;
 581     lose("Can't decode fdefn raw addr @ %p: %p\n", fdefn, fdefn->raw_addr);
 582 }
 583 #endif