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Fix tms9918a transparent color rendering
[qemu/z80.git] / cpu-exec.c
blobd614c42c5278f775027cc65190742fb1f4372223
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23 #include "tcg.h"
24 #include "kvm.h"
25
26 #if !defined(CONFIG_SOFTMMU)
27 #undef EAX
28 #undef ECX
29 #undef EDX
30 #undef EBX
31 #undef ESP
32 #undef EBP
33 #undef ESI
34 #undef EDI
35 #undef EIP
36 #include <signal.h>
37 #ifdef __linux__
38 #include <sys/ucontext.h>
39 #endif
40 #endif
41
42 #if defined(__sparc__) && !defined(HOST_SOLARIS)
43 // Work around ugly bugs in glibc that mangle global register contents
44 #undef env
45 #define env cpu_single_env
46 #endif
47
48 int tb_invalidated_flag;
49
50 //#define DEBUG_EXEC
51 //#define DEBUG_SIGNAL
52
53 int qemu_cpu_has_work(CPUState *env)
54 {
55 return cpu_has_work(env);
56 }
57
58 void cpu_loop_exit(void)
59 {
60 /* NOTE: the register at this point must be saved by hand because
61 longjmp restore them */
62 regs_to_env();
63 longjmp(env->jmp_env, 1);
64 }
65
66 /* exit the current TB from a signal handler. The host registers are
67 restored in a state compatible with the CPU emulator
68 */
69 void cpu_resume_from_signal(CPUState *env1, void *puc)
70 {
71 #if !defined(CONFIG_SOFTMMU)
72 #ifdef __linux__
73 struct ucontext *uc = puc;
74 #elif defined(__OpenBSD__)
75 struct sigcontext *uc = puc;
76 #endif
77 #endif
78
79 env = env1;
80
81 /* XXX: restore cpu registers saved in host registers */
82
83 #if !defined(CONFIG_SOFTMMU)
84 if (puc) {
85 /* XXX: use siglongjmp ? */
86 #ifdef __linux__
87 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
88 #elif defined(__OpenBSD__)
89 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
90 #endif
91 }
92 #endif
93 env->exception_index = -1;
94 longjmp(env->jmp_env, 1);
95 }
96
97 /* Execute the code without caching the generated code. An interpreter
98 could be used if available. */
99 static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
100 {
101 unsigned long next_tb;
102 TranslationBlock *tb;
103
104 /* Should never happen.
105 We only end up here when an existing TB is too long. */
106 if (max_cycles > CF_COUNT_MASK)
107 max_cycles = CF_COUNT_MASK;
108
109 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
110 max_cycles);
111 env->current_tb = tb;
112 /* execute the generated code */
113 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
114
115 if ((next_tb & 3) == 2) {
116 /* Restore PC. This may happen if async event occurs before
117 the TB starts executing. */
118 cpu_pc_from_tb(env, tb);
119 }
120 tb_phys_invalidate(tb, -1);
121 tb_free(tb);
122 }
123
124 static TranslationBlock *tb_find_slow(target_ulong pc,
125 target_ulong cs_base,
126 uint64_t flags)
127 {
128 TranslationBlock *tb, **ptb1;
129 unsigned int h;
130 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
131
132 tb_invalidated_flag = 0;
133
134 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
135
136 /* find translated block using physical mappings */
137 phys_pc = get_phys_addr_code(env, pc);
138 phys_page1 = phys_pc & TARGET_PAGE_MASK;
139 phys_page2 = -1;
140 h = tb_phys_hash_func(phys_pc);
141 ptb1 = &tb_phys_hash[h];
142 for(;;) {
143 tb = *ptb1;
144 if (!tb)
145 goto not_found;
146 if (tb->pc == pc &&
147 tb->page_addr[0] == phys_page1 &&
148 tb->cs_base == cs_base &&
149 tb->flags == flags) {
150 /* check next page if needed */
151 if (tb->page_addr[1] != -1) {
152 virt_page2 = (pc & TARGET_PAGE_MASK) +
153 TARGET_PAGE_SIZE;
154 phys_page2 = get_phys_addr_code(env, virt_page2);
155 if (tb->page_addr[1] == phys_page2)
156 goto found;
157 } else {
158 goto found;
159 }
160 }
161 ptb1 = &tb->phys_hash_next;
162 }
163 not_found:
164 /* if no translated code available, then translate it now */
165 tb = tb_gen_code(env, pc, cs_base, flags, 0);
166
167 found:
168 /* we add the TB in the virtual pc hash table */
169 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
170 return tb;
171 }
172
173 static inline TranslationBlock *tb_find_fast(void)
174 {
175 TranslationBlock *tb;
176 target_ulong cs_base, pc;
177 int flags;
178
179 /* we record a subset of the CPU state. It will
180 always be the same before a given translated block
181 is executed. */
182 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
183 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
184 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
185 tb->flags != flags)) {
186 tb = tb_find_slow(pc, cs_base, flags);
187 }
188 return tb;
189 }
190
191 static CPUDebugExcpHandler *debug_excp_handler;
192
193 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
194 {
195 CPUDebugExcpHandler *old_handler = debug_excp_handler;
196
197 debug_excp_handler = handler;
198 return old_handler;
199 }
200
201 static void cpu_handle_debug_exception(CPUState *env)
202 {
203 CPUWatchpoint *wp;
204
205 if (!env->watchpoint_hit)
206 TAILQ_FOREACH(wp, &env->watchpoints, entry)
207 wp->flags &= ~BP_WATCHPOINT_HIT;
208
209 if (debug_excp_handler)
210 debug_excp_handler(env);
211 }
212
213 /* main execution loop */
214
215 int cpu_exec(CPUState *env1)
216 {
217 #define DECLARE_HOST_REGS 1
218 #include "hostregs_helper.h"
219 int ret, interrupt_request;
220 TranslationBlock *tb;
221 uint8_t *tc_ptr;
222 unsigned long next_tb;
223
224 if (cpu_halted(env1) == EXCP_HALTED)
225 return EXCP_HALTED;
226
227 cpu_single_env = env1;
228
229 /* first we save global registers */
230 #define SAVE_HOST_REGS 1
231 #include "hostregs_helper.h"
232 env = env1;
233
234 env_to_regs();
235 #if defined(TARGET_I386)
236 /* put eflags in CPU temporary format */
237 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
238 DF = 1 - (2 * ((env->eflags >> 10) & 1));
239 CC_OP = CC_OP_EFLAGS;
240 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
241 #elif defined(TARGET_SPARC)
242 #elif defined(TARGET_M68K)
243 env->cc_op = CC_OP_FLAGS;
244 env->cc_dest = env->sr & 0xf;
245 env->cc_x = (env->sr >> 4) & 1;
246 #elif defined(TARGET_ALPHA)
247 #elif defined(TARGET_ARM)
248 #elif defined(TARGET_PPC)
249 #elif defined(TARGET_MICROBLAZE)
250 #elif defined(TARGET_MIPS)
251 #elif defined(TARGET_SH4)
252 #elif defined(TARGET_CRIS)
253 #elif defined(TARGET_Z80)
254 /* XXXXX */
255 #else
256 #error unsupported target CPU
257 #endif
258 env->exception_index = -1;
259
260 /* prepare setjmp context for exception handling */
261 for(;;) {
262 if (setjmp(env->jmp_env) == 0) {
263 #if defined(__sparc__) && !defined(HOST_SOLARIS)
264 #undef env
265 env = cpu_single_env;
266 #define env cpu_single_env
267 #endif
268 env->current_tb = NULL;
269 /* if an exception is pending, we execute it here */
270 if (env->exception_index >= 0) {
271 if (env->exception_index >= EXCP_INTERRUPT) {
272 /* exit request from the cpu execution loop */
273 ret = env->exception_index;
274 if (ret == EXCP_DEBUG)
275 cpu_handle_debug_exception(env);
276 break;
277 } else {
278 #if defined(CONFIG_USER_ONLY)
279 /* if user mode only, we simulate a fake exception
280 which will be handled outside the cpu execution
281 loop */
282 #if defined(TARGET_I386)
283 do_interrupt_user(env->exception_index,
284 env->exception_is_int,
285 env->error_code,
286 env->exception_next_eip);
287 /* successfully delivered */
288 env->old_exception = -1;
289 #endif
290 ret = env->exception_index;
291 break;
292 #else
293 #if defined(TARGET_I386)
294 /* simulate a real cpu exception. On i386, it can
295 trigger new exceptions, but we do not handle
296 double or triple faults yet. */
297 do_interrupt(env->exception_index,
298 env->exception_is_int,
299 env->error_code,
300 env->exception_next_eip, 0);
301 /* successfully delivered */
302 env->old_exception = -1;
303 #elif defined(TARGET_PPC)
304 do_interrupt(env);
305 #elif defined(TARGET_MICROBLAZE)
306 do_interrupt(env);
307 #elif defined(TARGET_MIPS)
308 do_interrupt(env);
309 #elif defined(TARGET_SPARC)
310 do_interrupt(env);
311 #elif defined(TARGET_ARM)
312 do_interrupt(env);
313 #elif defined(TARGET_SH4)
314 do_interrupt(env);
315 #elif defined(TARGET_ALPHA)
316 do_interrupt(env);
317 #elif defined(TARGET_CRIS)
318 do_interrupt(env);
319 #elif defined(TARGET_M68K)
320 do_interrupt(0);
321 #endif
322 #endif
323 }
324 env->exception_index = -1;
325 }
326 #ifdef CONFIG_KQEMU
327 if (kqemu_is_ok(env) && env->interrupt_request == 0 && env->exit_request == 0) {
328 int ret;
329 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
330 ret = kqemu_cpu_exec(env);
331 /* put eflags in CPU temporary format */
332 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
333 DF = 1 - (2 * ((env->eflags >> 10) & 1));
334 CC_OP = CC_OP_EFLAGS;
335 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
336 if (ret == 1) {
337 /* exception */
338 longjmp(env->jmp_env, 1);
339 } else if (ret == 2) {
340 /* softmmu execution needed */
341 } else {
342 if (env->interrupt_request != 0 || env->exit_request != 0) {
343 /* hardware interrupt will be executed just after */
344 } else {
345 /* otherwise, we restart */
346 longjmp(env->jmp_env, 1);
347 }
348 }
349 }
350 #endif
351
352 if (kvm_enabled()) {
353 kvm_cpu_exec(env);
354 longjmp(env->jmp_env, 1);
355 }
356
357 next_tb = 0; /* force lookup of first TB */
358 for(;;) {
359 interrupt_request = env->interrupt_request;
360 if (unlikely(interrupt_request)) {
361 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
362 /* Mask out external interrupts for this step. */
363 interrupt_request &= ~(CPU_INTERRUPT_HARD |
364 CPU_INTERRUPT_FIQ |
365 CPU_INTERRUPT_SMI |
366 CPU_INTERRUPT_NMI);
367 }
368 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
369 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
370 env->exception_index = EXCP_DEBUG;
371 cpu_loop_exit();
372 }
373 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
374 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
375 defined(TARGET_MICROBLAZE)
376 if (interrupt_request & CPU_INTERRUPT_HALT) {
377 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
378 env->halted = 1;
379 env->exception_index = EXCP_HLT;
380 cpu_loop_exit();
381 }
382 #endif
383 #if defined(TARGET_I386)
384 if (env->hflags2 & HF2_GIF_MASK) {
385 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
386 !(env->hflags & HF_SMM_MASK)) {
387 svm_check_intercept(SVM_EXIT_SMI);
388 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
389 do_smm_enter();
390 next_tb = 0;
391 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
392 !(env->hflags2 & HF2_NMI_MASK)) {
393 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
394 env->hflags2 |= HF2_NMI_MASK;
395 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
396 next_tb = 0;
397 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
398 (((env->hflags2 & HF2_VINTR_MASK) &&
399 (env->hflags2 & HF2_HIF_MASK)) ||
400 (!(env->hflags2 & HF2_VINTR_MASK) &&
401 (env->eflags & IF_MASK &&
402 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
403 int intno;
404 svm_check_intercept(SVM_EXIT_INTR);
405 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
406 intno = cpu_get_pic_interrupt(env);
407 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
408 #if defined(__sparc__) && !defined(HOST_SOLARIS)
409 #undef env
410 env = cpu_single_env;
411 #define env cpu_single_env
412 #endif
413 do_interrupt(intno, 0, 0, 0, 1);
414 /* ensure that no TB jump will be modified as
415 the program flow was changed */
416 next_tb = 0;
417 #if !defined(CONFIG_USER_ONLY)
418 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
419 (env->eflags & IF_MASK) &&
420 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
421 int intno;
422 /* FIXME: this should respect TPR */
423 svm_check_intercept(SVM_EXIT_VINTR);
424 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
425 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
426 do_interrupt(intno, 0, 0, 0, 1);
427 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
428 next_tb = 0;
429 #endif
430 }
431 }
432 #elif defined(TARGET_PPC)
433 #if 0
434 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
435 cpu_ppc_reset(env);
436 }
437 #endif
438 if (interrupt_request & CPU_INTERRUPT_HARD) {
439 ppc_hw_interrupt(env);
440 if (env->pending_interrupts == 0)
441 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
442 next_tb = 0;
443 }
444 #elif defined(TARGET_MICROBLAZE)
445 if ((interrupt_request & CPU_INTERRUPT_HARD)
446 && (env->sregs[SR_MSR] & MSR_IE)
447 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
448 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
449 env->exception_index = EXCP_IRQ;
450 do_interrupt(env);
451 next_tb = 0;
452 }
453 #elif defined(TARGET_MIPS)
454 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
455 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
456 (env->CP0_Status & (1 << CP0St_IE)) &&
457 !(env->CP0_Status & (1 << CP0St_EXL)) &&
458 !(env->CP0_Status & (1 << CP0St_ERL)) &&
459 !(env->hflags & MIPS_HFLAG_DM)) {
460 /* Raise it */
461 env->exception_index = EXCP_EXT_INTERRUPT;
462 env->error_code = 0;
463 do_interrupt(env);
464 next_tb = 0;
465 }
466 #elif defined(TARGET_SPARC)
467 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
468 (env->psret != 0)) {
469 int pil = env->interrupt_index & 15;
470 int type = env->interrupt_index & 0xf0;
471
472 if (((type == TT_EXTINT) &&
473 (pil == 15 || pil > env->psrpil)) ||
474 type != TT_EXTINT) {
475 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
476 env->exception_index = env->interrupt_index;
477 do_interrupt(env);
478 env->interrupt_index = 0;
479 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
480 cpu_check_irqs(env);
481 #endif
482 next_tb = 0;
483 }
484 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
485 //do_interrupt(0, 0, 0, 0, 0);
486 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
487 }
488 #elif defined(TARGET_ARM)
489 if (interrupt_request & CPU_INTERRUPT_FIQ
490 && !(env->uncached_cpsr & CPSR_F)) {
491 env->exception_index = EXCP_FIQ;
492 do_interrupt(env);
493 next_tb = 0;
494 }
495 /* ARMv7-M interrupt return works by loading a magic value
496 into the PC. On real hardware the load causes the
497 return to occur. The qemu implementation performs the
498 jump normally, then does the exception return when the
499 CPU tries to execute code at the magic address.
500 This will cause the magic PC value to be pushed to
501 the stack if an interrupt occured at the wrong time.
502 We avoid this by disabling interrupts when
503 pc contains a magic address. */
504 if (interrupt_request & CPU_INTERRUPT_HARD
505 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
506 || !(env->uncached_cpsr & CPSR_I))) {
507 env->exception_index = EXCP_IRQ;
508 do_interrupt(env);
509 next_tb = 0;
510 }
511 #elif defined(TARGET_SH4)
512 if (interrupt_request & CPU_INTERRUPT_HARD) {
513 do_interrupt(env);
514 next_tb = 0;
515 }
516 #elif defined(TARGET_ALPHA)
517 if (interrupt_request & CPU_INTERRUPT_HARD) {
518 do_interrupt(env);
519 next_tb = 0;
520 }
521 #elif defined(TARGET_CRIS)
522 if (interrupt_request & CPU_INTERRUPT_HARD
523 && (env->pregs[PR_CCS] & I_FLAG)) {
524 env->exception_index = EXCP_IRQ;
525 do_interrupt(env);
526 next_tb = 0;
527 }
528 if (interrupt_request & CPU_INTERRUPT_NMI
529 && (env->pregs[PR_CCS] & M_FLAG)) {
530 env->exception_index = EXCP_NMI;
531 do_interrupt(env);
532 next_tb = 0;
533 }
534 #elif defined(TARGET_M68K)
535 if (interrupt_request & CPU_INTERRUPT_HARD
536 && ((env->sr & SR_I) >> SR_I_SHIFT)
537 < env->pending_level) {
538 /* Real hardware gets the interrupt vector via an
539 IACK cycle at this point. Current emulated
540 hardware doesn't rely on this, so we
541 provide/save the vector when the interrupt is
542 first signalled. */
543 env->exception_index = env->pending_vector;
544 do_interrupt(1);
545 next_tb = 0;
546 }
547 #elif defined(TARGET_Z80)
548 if (interrupt_request & CPU_INTERRUPT_HARD) {
549 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
550 /* TODO: Add support for NMIs */
551 do_interrupt(env);
552 }
553 #endif
554 /* Don't use the cached interupt_request value,
555 do_interrupt may have updated the EXITTB flag. */
556 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
557 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
558 /* ensure that no TB jump will be modified as
559 the program flow was changed */
560 next_tb = 0;
561 }
562 }
563 if (unlikely(env->exit_request)) {
564 env->exit_request = 0;
565 env->exception_index = EXCP_INTERRUPT;
566 cpu_loop_exit();
567 }
568 #ifdef DEBUG_EXEC
569 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
570 /* restore flags in standard format */
571 regs_to_env();
572 #if defined(TARGET_I386)
573 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
574 log_cpu_state(env, X86_DUMP_CCOP);
575 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
576 #elif defined(TARGET_ARM)
577 log_cpu_state(env, 0);
578 #elif defined(TARGET_SPARC)
579 log_cpu_state(env, 0);
580 #elif defined(TARGET_PPC)
581 log_cpu_state(env, 0);
582 #elif defined(TARGET_M68K)
583 cpu_m68k_flush_flags(env, env->cc_op);
584 env->cc_op = CC_OP_FLAGS;
585 env->sr = (env->sr & 0xffe0)
586 | env->cc_dest | (env->cc_x << 4);
587 log_cpu_state(env, 0);
588 #elif defined(TARGET_MICROBLAZE)
589 log_cpu_state(env, 0);
590 #elif defined(TARGET_MIPS)
591 log_cpu_state(env, 0);
592 #elif defined(TARGET_SH4)
593 log_cpu_state(env, 0);
594 #elif defined(TARGET_ALPHA)
595 log_cpu_state(env, 0);
596 #elif defined(TARGET_CRIS)
597 log_cpu_state(env, 0);
598 #elif defined(TARGET_Z80)
599 log_cpu_state(env, 0);
600 #else
601 #error unsupported target CPU
602 #endif
603 }
604 #endif
605 spin_lock(&tb_lock);
606 tb = tb_find_fast();
607 /* Note: we do it here to avoid a gcc bug on Mac OS X when
608 doing it in tb_find_slow */
609 if (tb_invalidated_flag) {
610 /* as some TB could have been invalidated because
611 of memory exceptions while generating the code, we
612 must recompute the hash index here */
613 next_tb = 0;
614 tb_invalidated_flag = 0;
615 }
616 #ifdef DEBUG_EXEC
617 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
618 (long)tb->tc_ptr, tb->pc,
619 lookup_symbol(tb->pc));
620 #endif
621 /* see if we can patch the calling TB. When the TB
622 spans two pages, we cannot safely do a direct
623 jump. */
624 {
625 if (next_tb != 0 &&
626 #ifdef CONFIG_KQEMU
627 (env->kqemu_enabled != 2) &&
628 #endif
629 tb->page_addr[1] == -1) {
630 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
631 }
632 }
633 spin_unlock(&tb_lock);
634 env->current_tb = tb;
635
636 /* cpu_interrupt might be called while translating the
637 TB, but before it is linked into a potentially
638 infinite loop and becomes env->current_tb. Avoid
639 starting execution if there is a pending interrupt. */
640 if (unlikely (env->exit_request))
641 env->current_tb = NULL;
642
643 while (env->current_tb) {
644 tc_ptr = tb->tc_ptr;
645 /* execute the generated code */
646 #if defined(__sparc__) && !defined(HOST_SOLARIS)
647 #undef env
648 env = cpu_single_env;
649 #define env cpu_single_env
650 #endif
651 next_tb = tcg_qemu_tb_exec(tc_ptr);
652 env->current_tb = NULL;
653 if ((next_tb & 3) == 2) {
654 /* Instruction counter expired. */
655 int insns_left;
656 tb = (TranslationBlock *)(long)(next_tb & ~3);
657 /* Restore PC. */
658 cpu_pc_from_tb(env, tb);
659 insns_left = env->icount_decr.u32;
660 if (env->icount_extra && insns_left >= 0) {
661 /* Refill decrementer and continue execution. */
662 env->icount_extra += insns_left;
663 if (env->icount_extra > 0xffff) {
664 insns_left = 0xffff;
665 } else {
666 insns_left = env->icount_extra;
667 }
668 env->icount_extra -= insns_left;
669 env->icount_decr.u16.low = insns_left;
670 } else {
671 if (insns_left > 0) {
672 /* Execute remaining instructions. */
673 cpu_exec_nocache(insns_left, tb);
674 }
675 env->exception_index = EXCP_INTERRUPT;
676 next_tb = 0;
677 cpu_loop_exit();
678 }
679 }
680 }
681 /* reset soft MMU for next block (it can currently
682 only be set by a memory fault) */
683 #if defined(CONFIG_KQEMU)
684 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
685 if (kqemu_is_ok(env) &&
686 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
687 cpu_loop_exit();
688 }
689 #endif
690 } /* for(;;) */
691 } else {
692 env_to_regs();
693 }
694 } /* for(;;) */
695
696
697 #if defined(TARGET_I386)
698 /* restore flags in standard format */
699 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
700 #elif defined(TARGET_ARM)
701 /* XXX: Save/restore host fpu exception state?. */
702 #elif defined(TARGET_SPARC)
703 #elif defined(TARGET_PPC)
704 #elif defined(TARGET_M68K)
705 cpu_m68k_flush_flags(env, env->cc_op);
706 env->cc_op = CC_OP_FLAGS;
707 env->sr = (env->sr & 0xffe0)
708 | env->cc_dest | (env->cc_x << 4);
709 #elif defined(TARGET_MICROBLAZE)
710 #elif defined(TARGET_MIPS)
711 #elif defined(TARGET_SH4)
712 #elif defined(TARGET_ALPHA)
713 #elif defined(TARGET_CRIS)
714 #elif defined(TARGET_Z80)
715 /* XXXXX */
716 #else
717 #error unsupported target CPU
718 #endif
719
720 /* restore global registers */
721 #include "hostregs_helper.h"
722
723 /* fail safe : never use cpu_single_env outside cpu_exec() */
724 cpu_single_env = NULL;
725 return ret;
726 }
727
728 /* must only be called from the generated code as an exception can be
729 generated */
730 void tb_invalidate_page_range(target_ulong start, target_ulong end)
731 {
732 /* XXX: cannot enable it yet because it yields to MMU exception
733 where NIP != read address on PowerPC */
734 #if 0
735 target_ulong phys_addr;
736 phys_addr = get_phys_addr_code(env, start);
737 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
738 #endif
739 }
740
741 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
742
743 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
744 {
745 CPUX86State *saved_env;
746
747 saved_env = env;
748 env = s;
749 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
750 selector &= 0xffff;
751 cpu_x86_load_seg_cache(env, seg_reg, selector,
752 (selector << 4), 0xffff, 0);
753 } else {
754 helper_load_seg(seg_reg, selector);
755 }
756 env = saved_env;
757 }
758
759 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
760 {
761 CPUX86State *saved_env;
762
763 saved_env = env;
764 env = s;
765
766 helper_fsave(ptr, data32);
767
768 env = saved_env;
769 }
770
771 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
772 {
773 CPUX86State *saved_env;
774
775 saved_env = env;
776 env = s;
777
778 helper_frstor(ptr, data32);
779
780 env = saved_env;
781 }
782
783 #endif /* TARGET_I386 */
784
785 #if !defined(CONFIG_SOFTMMU)
786
787 #if defined(TARGET_I386)
788
789 /* 'pc' is the host PC at which the exception was raised. 'address' is
790 the effective address of the memory exception. 'is_write' is 1 if a
791 write caused the exception and otherwise 0'. 'old_set' is the
792 signal set which should be restored */
793 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
794 int is_write, sigset_t *old_set,
795 void *puc)
796 {
797 TranslationBlock *tb;
798 int ret;
799
800 if (cpu_single_env)
801 env = cpu_single_env; /* XXX: find a correct solution for multithread */
802 #if defined(DEBUG_SIGNAL)
803 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
804 pc, address, is_write, *(unsigned long *)old_set);
805 #endif
806 /* XXX: locking issue */
807 if (is_write && page_unprotect(h2g(address), pc, puc)) {
808 return 1;
809 }
810
811 /* see if it is an MMU fault */
812 ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
813 if (ret < 0)
814 return 0; /* not an MMU fault */
815 if (ret == 0)
816 return 1; /* the MMU fault was handled without causing real CPU fault */
817 /* now we have a real cpu fault */
818 tb = tb_find_pc(pc);
819 if (tb) {
820 /* the PC is inside the translated code. It means that we have
821 a virtual CPU fault */
822 cpu_restore_state(tb, env, pc, puc);
823 }
824 if (ret == 1) {
825 #if 0
826 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
827 env->eip, env->cr[2], env->error_code);
828 #endif
829 /* we restore the process signal mask as the sigreturn should
830 do it (XXX: use sigsetjmp) */
831 sigprocmask(SIG_SETMASK, old_set, NULL);
832 raise_exception_err(env->exception_index, env->error_code);
833 } else {
834 /* activate soft MMU for this block */
835 env->hflags |= HF_SOFTMMU_MASK;
836 cpu_resume_from_signal(env, puc);
837 }
838 /* never comes here */
839 return 1;
840 }
841
842 #elif defined(TARGET_ARM)
843 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
844 int is_write, sigset_t *old_set,
845 void *puc)
846 {
847 TranslationBlock *tb;
848 int ret;
849
850 if (cpu_single_env)
851 env = cpu_single_env; /* XXX: find a correct solution for multithread */
852 #if defined(DEBUG_SIGNAL)
853 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
854 pc, address, is_write, *(unsigned long *)old_set);
855 #endif
856 /* XXX: locking issue */
857 if (is_write && page_unprotect(h2g(address), pc, puc)) {
858 return 1;
859 }
860 /* see if it is an MMU fault */
861 ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
862 if (ret < 0)
863 return 0; /* not an MMU fault */
864 if (ret == 0)
865 return 1; /* the MMU fault was handled without causing real CPU fault */
866 /* now we have a real cpu fault */
867 tb = tb_find_pc(pc);
868 if (tb) {
869 /* the PC is inside the translated code. It means that we have
870 a virtual CPU fault */
871 cpu_restore_state(tb, env, pc, puc);
872 }
873 /* we restore the process signal mask as the sigreturn should
874 do it (XXX: use sigsetjmp) */
875 sigprocmask(SIG_SETMASK, old_set, NULL);
876 cpu_loop_exit();
877 /* never comes here */
878 return 1;
879 }
880 #elif defined(TARGET_SPARC)
881 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
882 int is_write, sigset_t *old_set,
883 void *puc)
884 {
885 TranslationBlock *tb;
886 int ret;
887
888 if (cpu_single_env)
889 env = cpu_single_env; /* XXX: find a correct solution for multithread */
890 #if defined(DEBUG_SIGNAL)
891 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
892 pc, address, is_write, *(unsigned long *)old_set);
893 #endif
894 /* XXX: locking issue */
895 if (is_write && page_unprotect(h2g(address), pc, puc)) {
896 return 1;
897 }
898 /* see if it is an MMU fault */
899 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
900 if (ret < 0)
901 return 0; /* not an MMU fault */
902 if (ret == 0)
903 return 1; /* the MMU fault was handled without causing real CPU fault */
904 /* now we have a real cpu fault */
905 tb = tb_find_pc(pc);
906 if (tb) {
907 /* the PC is inside the translated code. It means that we have
908 a virtual CPU fault */
909 cpu_restore_state(tb, env, pc, puc);
910 }
911 /* we restore the process signal mask as the sigreturn should
912 do it (XXX: use sigsetjmp) */
913 sigprocmask(SIG_SETMASK, old_set, NULL);
914 cpu_loop_exit();
915 /* never comes here */
916 return 1;
917 }
918 #elif defined (TARGET_PPC)
919 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
920 int is_write, sigset_t *old_set,
921 void *puc)
922 {
923 TranslationBlock *tb;
924 int ret;
925
926 if (cpu_single_env)
927 env = cpu_single_env; /* XXX: find a correct solution for multithread */
928 #if defined(DEBUG_SIGNAL)
929 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
930 pc, address, is_write, *(unsigned long *)old_set);
931 #endif
932 /* XXX: locking issue */
933 if (is_write && page_unprotect(h2g(address), pc, puc)) {
934 return 1;
935 }
936
937 /* see if it is an MMU fault */
938 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
939 if (ret < 0)
940 return 0; /* not an MMU fault */
941 if (ret == 0)
942 return 1; /* the MMU fault was handled without causing real CPU fault */
943
944 /* now we have a real cpu fault */
945 tb = tb_find_pc(pc);
946 if (tb) {
947 /* the PC is inside the translated code. It means that we have
948 a virtual CPU fault */
949 cpu_restore_state(tb, env, pc, puc);
950 }
951 if (ret == 1) {
952 #if 0
953 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
954 env->nip, env->error_code, tb);
955 #endif
956 /* we restore the process signal mask as the sigreturn should
957 do it (XXX: use sigsetjmp) */
958 sigprocmask(SIG_SETMASK, old_set, NULL);
959 cpu_loop_exit();
960 } else {
961 /* activate soft MMU for this block */
962 cpu_resume_from_signal(env, puc);
963 }
964 /* never comes here */
965 return 1;
966 }
967
968 #elif defined(TARGET_M68K)
969 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
970 int is_write, sigset_t *old_set,
971 void *puc)
972 {
973 TranslationBlock *tb;
974 int ret;
975
976 if (cpu_single_env)
977 env = cpu_single_env; /* XXX: find a correct solution for multithread */
978 #if defined(DEBUG_SIGNAL)
979 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
980 pc, address, is_write, *(unsigned long *)old_set);
981 #endif
982 /* XXX: locking issue */
983 if (is_write && page_unprotect(address, pc, puc)) {
984 return 1;
985 }
986 /* see if it is an MMU fault */
987 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
988 if (ret < 0)
989 return 0; /* not an MMU fault */
990 if (ret == 0)
991 return 1; /* the MMU fault was handled without causing real CPU fault */
992 /* now we have a real cpu fault */
993 tb = tb_find_pc(pc);
994 if (tb) {
995 /* the PC is inside the translated code. It means that we have
996 a virtual CPU fault */
997 cpu_restore_state(tb, env, pc, puc);
998 }
999 /* we restore the process signal mask as the sigreturn should
1000 do it (XXX: use sigsetjmp) */
1001 sigprocmask(SIG_SETMASK, old_set, NULL);
1002 cpu_loop_exit();
1003 /* never comes here */
1004 return 1;
1005 }
1006
1007 #elif defined (TARGET_MIPS)
1008 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1009 int is_write, sigset_t *old_set,
1010 void *puc)
1011 {
1012 TranslationBlock *tb;
1013 int ret;
1014
1015 if (cpu_single_env)
1016 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1017 #if defined(DEBUG_SIGNAL)
1018 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1019 pc, address, is_write, *(unsigned long *)old_set);
1020 #endif
1021 /* XXX: locking issue */
1022 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1023 return 1;
1024 }
1025
1026 /* see if it is an MMU fault */
1027 ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1028 if (ret < 0)
1029 return 0; /* not an MMU fault */
1030 if (ret == 0)
1031 return 1; /* the MMU fault was handled without causing real CPU fault */
1032
1033 /* now we have a real cpu fault */
1034 tb = tb_find_pc(pc);
1035 if (tb) {
1036 /* the PC is inside the translated code. It means that we have
1037 a virtual CPU fault */
1038 cpu_restore_state(tb, env, pc, puc);
1039 }
1040 if (ret == 1) {
1041 #if 0
1042 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1043 env->PC, env->error_code, tb);
1044 #endif
1045 /* we restore the process signal mask as the sigreturn should
1046 do it (XXX: use sigsetjmp) */
1047 sigprocmask(SIG_SETMASK, old_set, NULL);
1048 cpu_loop_exit();
1049 } else {
1050 /* activate soft MMU for this block */
1051 cpu_resume_from_signal(env, puc);
1052 }
1053 /* never comes here */
1054 return 1;
1055 }
1056
1057 #elif defined (TARGET_MICROBLAZE)
1058 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1059 int is_write, sigset_t *old_set,
1060 void *puc)
1061 {
1062 TranslationBlock *tb;
1063 int ret;
1064
1065 if (cpu_single_env)
1066 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1067 #if defined(DEBUG_SIGNAL)
1068 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1069 pc, address, is_write, *(unsigned long *)old_set);
1070 #endif
1071 /* XXX: locking issue */
1072 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1073 return 1;
1074 }
1075
1076 /* see if it is an MMU fault */
1077 ret = cpu_mb_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1078 if (ret < 0)
1079 return 0; /* not an MMU fault */
1080 if (ret == 0)
1081 return 1; /* the MMU fault was handled without causing real CPU fault */
1082
1083 /* now we have a real cpu fault */
1084 tb = tb_find_pc(pc);
1085 if (tb) {
1086 /* the PC is inside the translated code. It means that we have
1087 a virtual CPU fault */
1088 cpu_restore_state(tb, env, pc, puc);
1089 }
1090 if (ret == 1) {
1091 #if 0
1092 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1093 env->PC, env->error_code, tb);
1094 #endif
1095 /* we restore the process signal mask as the sigreturn should
1096 do it (XXX: use sigsetjmp) */
1097 sigprocmask(SIG_SETMASK, old_set, NULL);
1098 cpu_loop_exit();
1099 } else {
1100 /* activate soft MMU for this block */
1101 cpu_resume_from_signal(env, puc);
1102 }
1103 /* never comes here */
1104 return 1;
1105 }
1106
1107 #elif defined (TARGET_SH4)
1108 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1109 int is_write, sigset_t *old_set,
1110 void *puc)
1111 {
1112 TranslationBlock *tb;
1113 int ret;
1114
1115 if (cpu_single_env)
1116 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1117 #if defined(DEBUG_SIGNAL)
1118 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1119 pc, address, is_write, *(unsigned long *)old_set);
1120 #endif
1121 /* XXX: locking issue */
1122 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1123 return 1;
1124 }
1125
1126 /* see if it is an MMU fault */
1127 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1128 if (ret < 0)
1129 return 0; /* not an MMU fault */
1130 if (ret == 0)
1131 return 1; /* the MMU fault was handled without causing real CPU fault */
1132
1133 /* now we have a real cpu fault */
1134 tb = tb_find_pc(pc);
1135 if (tb) {
1136 /* the PC is inside the translated code. It means that we have
1137 a virtual CPU fault */
1138 cpu_restore_state(tb, env, pc, puc);
1139 }
1140 #if 0
1141 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1142 env->nip, env->error_code, tb);
1143 #endif
1144 /* we restore the process signal mask as the sigreturn should
1145 do it (XXX: use sigsetjmp) */
1146 sigprocmask(SIG_SETMASK, old_set, NULL);
1147 cpu_loop_exit();
1148 /* never comes here */
1149 return 1;
1150 }
1151
1152 #elif defined (TARGET_ALPHA)
1153 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1154 int is_write, sigset_t *old_set,
1155 void *puc)
1156 {
1157 TranslationBlock *tb;
1158 int ret;
1159
1160 if (cpu_single_env)
1161 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1162 #if defined(DEBUG_SIGNAL)
1163 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1164 pc, address, is_write, *(unsigned long *)old_set);
1165 #endif
1166 /* XXX: locking issue */
1167 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1168 return 1;
1169 }
1170
1171 /* see if it is an MMU fault */
1172 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1173 if (ret < 0)
1174 return 0; /* not an MMU fault */
1175 if (ret == 0)
1176 return 1; /* the MMU fault was handled without causing real CPU fault */
1177
1178 /* now we have a real cpu fault */
1179 tb = tb_find_pc(pc);
1180 if (tb) {
1181 /* the PC is inside the translated code. It means that we have
1182 a virtual CPU fault */
1183 cpu_restore_state(tb, env, pc, puc);
1184 }
1185 #if 0
1186 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1187 env->nip, env->error_code, tb);
1188 #endif
1189 /* we restore the process signal mask as the sigreturn should
1190 do it (XXX: use sigsetjmp) */
1191 sigprocmask(SIG_SETMASK, old_set, NULL);
1192 cpu_loop_exit();
1193 /* never comes here */
1194 return 1;
1195 }
1196 #elif defined (TARGET_CRIS)
1197 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1198 int is_write, sigset_t *old_set,
1199 void *puc)
1200 {
1201 TranslationBlock *tb;
1202 int ret;
1203
1204 if (cpu_single_env)
1205 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1206 #if defined(DEBUG_SIGNAL)
1207 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1208 pc, address, is_write, *(unsigned long *)old_set);
1209 #endif
1210 /* XXX: locking issue */
1211 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1212 return 1;
1213 }
1214
1215 /* see if it is an MMU fault */
1216 ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1217 if (ret < 0)
1218 return 0; /* not an MMU fault */
1219 if (ret == 0)
1220 return 1; /* the MMU fault was handled without causing real CPU fault */
1221
1222 /* now we have a real cpu fault */
1223 tb = tb_find_pc(pc);
1224 if (tb) {
1225 /* the PC is inside the translated code. It means that we have
1226 a virtual CPU fault */
1227 cpu_restore_state(tb, env, pc, puc);
1228 }
1229 /* we restore the process signal mask as the sigreturn should
1230 do it (XXX: use sigsetjmp) */
1231 sigprocmask(SIG_SETMASK, old_set, NULL);
1232 cpu_loop_exit();
1233 /* never comes here */
1234 return 1;
1235 }
1236
1237 #else
1238 #error unsupported target CPU
1239 #endif
1240
1241 #if defined(__i386__)
1242
1243 #if defined(__APPLE__)
1244 # include <sys/ucontext.h>
1245
1246 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1247 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1248 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1249 # define MASK_sig(context) ((context)->uc_sigmask)
1250 #elif defined(__OpenBSD__)
1251 # define EIP_sig(context) ((context)->sc_eip)
1252 # define TRAP_sig(context) ((context)->sc_trapno)
1253 # define ERROR_sig(context) ((context)->sc_err)
1254 # define MASK_sig(context) ((context)->sc_mask)
1255 #else
1256 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1257 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1258 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1259 # define MASK_sig(context) ((context)->uc_sigmask)
1260 #endif
1261
1262 int cpu_signal_handler(int host_signum, void *pinfo,
1263 void *puc)
1264 {
1265 siginfo_t *info = pinfo;
1266 #if defined(__OpenBSD__)
1267 struct sigcontext *uc = puc;
1268 #else
1269 struct ucontext *uc = puc;
1270 #endif
1271 unsigned long pc;
1272 int trapno;
1273
1274 #ifndef REG_EIP
1275 /* for glibc 2.1 */
1276 #define REG_EIP EIP
1277 #define REG_ERR ERR
1278 #define REG_TRAPNO TRAPNO
1279 #endif
1280 pc = EIP_sig(uc);
1281 trapno = TRAP_sig(uc);
1282 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1283 trapno == 0xe ?
1284 (ERROR_sig(uc) >> 1) & 1 : 0,
1285 &MASK_sig(uc), puc);
1286 }
1287
1288 #elif defined(__x86_64__)
1289
1290 #ifdef __NetBSD__
1291 #define PC_sig(context) _UC_MACHINE_PC(context)
1292 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
1293 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
1294 #define MASK_sig(context) ((context)->uc_sigmask)
1295 #elif defined(__OpenBSD__)
1296 #define PC_sig(context) ((context)->sc_rip)
1297 #define TRAP_sig(context) ((context)->sc_trapno)
1298 #define ERROR_sig(context) ((context)->sc_err)
1299 #define MASK_sig(context) ((context)->sc_mask)
1300 #else
1301 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
1302 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1303 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1304 #define MASK_sig(context) ((context)->uc_sigmask)
1305 #endif
1306
1307 int cpu_signal_handler(int host_signum, void *pinfo,
1308 void *puc)
1309 {
1310 siginfo_t *info = pinfo;
1311 unsigned long pc;
1312 #ifdef __NetBSD__
1313 ucontext_t *uc = puc;
1314 #elif defined(__OpenBSD__)
1315 struct sigcontext *uc = puc;
1316 #else
1317 struct ucontext *uc = puc;
1318 #endif
1319
1320 pc = PC_sig(uc);
1321 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1322 TRAP_sig(uc) == 0xe ?
1323 (ERROR_sig(uc) >> 1) & 1 : 0,
1324 &MASK_sig(uc), puc);
1325 }
1326
1327 #elif defined(_ARCH_PPC)
1328
1329 /***********************************************************************
1330 * signal context platform-specific definitions
1331 * From Wine
1332 */
1333 #ifdef linux
1334 /* All Registers access - only for local access */
1335 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1336 /* Gpr Registers access */
1337 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1338 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1339 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1340 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1341 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1342 # define LR_sig(context) REG_sig(link, context) /* Link register */
1343 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1344 /* Float Registers access */
1345 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1346 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1347 /* Exception Registers access */
1348 # define DAR_sig(context) REG_sig(dar, context)
1349 # define DSISR_sig(context) REG_sig(dsisr, context)
1350 # define TRAP_sig(context) REG_sig(trap, context)
1351 #endif /* linux */
1352
1353 #ifdef __APPLE__
1354 # include <sys/ucontext.h>
1355 typedef struct ucontext SIGCONTEXT;
1356 /* All Registers access - only for local access */
1357 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1358 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1359 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1360 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1361 /* Gpr Registers access */
1362 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1363 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1364 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1365 # define CTR_sig(context) REG_sig(ctr, context)
1366 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1367 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1368 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1369 /* Float Registers access */
1370 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1371 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1372 /* Exception Registers access */
1373 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1374 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1375 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1376 #endif /* __APPLE__ */
1377
1378 int cpu_signal_handler(int host_signum, void *pinfo,
1379 void *puc)
1380 {
1381 siginfo_t *info = pinfo;
1382 struct ucontext *uc = puc;
1383 unsigned long pc;
1384 int is_write;
1385
1386 pc = IAR_sig(uc);
1387 is_write = 0;
1388 #if 0
1389 /* ppc 4xx case */
1390 if (DSISR_sig(uc) & 0x00800000)
1391 is_write = 1;
1392 #else
1393 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1394 is_write = 1;
1395 #endif
1396 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1397 is_write, &uc->uc_sigmask, puc);
1398 }
1399
1400 #elif defined(__alpha__)
1401
1402 int cpu_signal_handler(int host_signum, void *pinfo,
1403 void *puc)
1404 {
1405 siginfo_t *info = pinfo;
1406 struct ucontext *uc = puc;
1407 uint32_t *pc = uc->uc_mcontext.sc_pc;
1408 uint32_t insn = *pc;
1409 int is_write = 0;
1410
1411 /* XXX: need kernel patch to get write flag faster */
1412 switch (insn >> 26) {
1413 case 0x0d: // stw
1414 case 0x0e: // stb
1415 case 0x0f: // stq_u
1416 case 0x24: // stf
1417 case 0x25: // stg
1418 case 0x26: // sts
1419 case 0x27: // stt
1420 case 0x2c: // stl
1421 case 0x2d: // stq
1422 case 0x2e: // stl_c
1423 case 0x2f: // stq_c
1424 is_write = 1;
1425 }
1426
1427 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1428 is_write, &uc->uc_sigmask, puc);
1429 }
1430 #elif defined(__sparc__)
1431
1432 int cpu_signal_handler(int host_signum, void *pinfo,
1433 void *puc)
1434 {
1435 siginfo_t *info = pinfo;
1436 int is_write;
1437 uint32_t insn;
1438 #if !defined(__arch64__) || defined(HOST_SOLARIS)
1439 uint32_t *regs = (uint32_t *)(info + 1);
1440 void *sigmask = (regs + 20);
1441 /* XXX: is there a standard glibc define ? */
1442 unsigned long pc = regs[1];
1443 #else
1444 #ifdef __linux__
1445 struct sigcontext *sc = puc;
1446 unsigned long pc = sc->sigc_regs.tpc;
1447 void *sigmask = (void *)sc->sigc_mask;
1448 #elif defined(__OpenBSD__)
1449 struct sigcontext *uc = puc;
1450 unsigned long pc = uc->sc_pc;
1451 void *sigmask = (void *)(long)uc->sc_mask;
1452 #endif
1453 #endif
1454
1455 /* XXX: need kernel patch to get write flag faster */
1456 is_write = 0;
1457 insn = *(uint32_t *)pc;
1458 if ((insn >> 30) == 3) {
1459 switch((insn >> 19) & 0x3f) {
1460 case 0x05: // stb
1461 case 0x15: // stba
1462 case 0x06: // sth
1463 case 0x16: // stha
1464 case 0x04: // st
1465 case 0x14: // sta
1466 case 0x07: // std
1467 case 0x17: // stda
1468 case 0x0e: // stx
1469 case 0x1e: // stxa
1470 case 0x24: // stf
1471 case 0x34: // stfa
1472 case 0x27: // stdf
1473 case 0x37: // stdfa
1474 case 0x26: // stqf
1475 case 0x36: // stqfa
1476 case 0x25: // stfsr
1477 case 0x3c: // casa
1478 case 0x3e: // casxa
1479 is_write = 1;
1480 break;
1481 }
1482 }
1483 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1484 is_write, sigmask, NULL);
1485 }
1486
1487 #elif defined(__arm__)
1488
1489 int cpu_signal_handler(int host_signum, void *pinfo,
1490 void *puc)
1491 {
1492 siginfo_t *info = pinfo;
1493 struct ucontext *uc = puc;
1494 unsigned long pc;
1495 int is_write;
1496
1497 #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
1498 pc = uc->uc_mcontext.gregs[R15];
1499 #else
1500 pc = uc->uc_mcontext.arm_pc;
1501 #endif
1502 /* XXX: compute is_write */
1503 is_write = 0;
1504 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1505 is_write,
1506 &uc->uc_sigmask, puc);
1507 }
1508
1509 #elif defined(__mc68000)
1510
1511 int cpu_signal_handler(int host_signum, void *pinfo,
1512 void *puc)
1513 {
1514 siginfo_t *info = pinfo;
1515 struct ucontext *uc = puc;
1516 unsigned long pc;
1517 int is_write;
1518
1519 pc = uc->uc_mcontext.gregs[16];
1520 /* XXX: compute is_write */
1521 is_write = 0;
1522 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1523 is_write,
1524 &uc->uc_sigmask, puc);
1525 }
1526
1527 #elif defined(__ia64)
1528
1529 #ifndef __ISR_VALID
1530 /* This ought to be in <bits/siginfo.h>... */
1531 # define __ISR_VALID 1
1532 #endif
1533
1534 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1535 {
1536 siginfo_t *info = pinfo;
1537 struct ucontext *uc = puc;
1538 unsigned long ip;
1539 int is_write = 0;
1540
1541 ip = uc->uc_mcontext.sc_ip;
1542 switch (host_signum) {
1543 case SIGILL:
1544 case SIGFPE:
1545 case SIGSEGV:
1546 case SIGBUS:
1547 case SIGTRAP:
1548 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1549 /* ISR.W (write-access) is bit 33: */
1550 is_write = (info->si_isr >> 33) & 1;
1551 break;
1552
1553 default:
1554 break;
1555 }
1556 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1557 is_write,
1558 &uc->uc_sigmask, puc);
1559 }
1560
1561 #elif defined(__s390__)
1562
1563 int cpu_signal_handler(int host_signum, void *pinfo,
1564 void *puc)
1565 {
1566 siginfo_t *info = pinfo;
1567 struct ucontext *uc = puc;
1568 unsigned long pc;
1569 int is_write;
1570
1571 pc = uc->uc_mcontext.psw.addr;
1572 /* XXX: compute is_write */
1573 is_write = 0;
1574 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1575 is_write, &uc->uc_sigmask, puc);
1576 }
1577
1578 #elif defined(__mips__)
1579
1580 int cpu_signal_handler(int host_signum, void *pinfo,
1581 void *puc)
1582 {
1583 siginfo_t *info = pinfo;
1584 struct ucontext *uc = puc;
1585 greg_t pc = uc->uc_mcontext.pc;
1586 int is_write;
1587
1588 /* XXX: compute is_write */
1589 is_write = 0;
1590 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1591 is_write, &uc->uc_sigmask, puc);
1592 }
1593
1594 #elif defined(__hppa__)
1595
1596 int cpu_signal_handler(int host_signum, void *pinfo,
1597 void *puc)
1598 {
1599 struct siginfo *info = pinfo;
1600 struct ucontext *uc = puc;
1601 unsigned long pc;
1602 int is_write;
1603
1604 pc = uc->uc_mcontext.sc_iaoq[0];
1605 /* FIXME: compute is_write */
1606 is_write = 0;
1607 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1608 is_write,
1609 &uc->uc_sigmask, puc);
1610 }
1611
1612 #else
1613
1614 #error host CPU specific signal handler needed
1615
1616 #endif
1617
1618 #endif /* !defined(CONFIG_SOFTMMU) */
Z80 target for QEMU