hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "pci.h"
  29 #include "vmware_vga.h"
  30 #include "monitor.h"
  31 #include "fw_cfg.h"
  32 #include "hpet_emul.h"
  33 #include "smbios.h"
  34 #include "loader.h"
  35 #include "elf.h"
  36 #include "multiboot.h"
  37 #include "mc146818rtc.h"
  38 #include "msix.h"
  39 #include "sysbus.h"
  40 #include "sysemu.h"
  41
  42 /* output Bochs bios info messages */
  43 //#define DEBUG_BIOS
  44
  45 /* debug PC/ISA interrupts */
  46 //#define DEBUG_IRQ
  47
  48 #ifdef DEBUG_IRQ
  49 #define DPRINTF(fmt, ...)                                       \
  50     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  51 #else
  52 #define DPRINTF(fmt, ...)
  53 #endif
  54
  55 #define BIOS_FILENAME "bios.bin"
  56
  57 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  58
  59 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  60 #define ACPI_DATA_SIZE       0x10000
  61 #define BIOS_CFG_IOPORT 0x510
  62 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  63 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  64 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  65 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  66 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  67
  68 #define MSI_ADDR_BASE 0xfee00000
  69
  70 #define E820_NR_ENTRIES         16
  71
  72 struct e820_entry {
  73     uint64_t address;
  74     uint64_t length;
  75     uint32_t type;
  76 };
  77
  78 struct e820_table {
  79     uint32_t count;
  80     struct e820_entry entry[E820_NR_ENTRIES];
  81 };
  82
  83 static struct e820_table e820_table;
  84
  85 void isa_irq_handler(void *opaque, int n, int level)
  86 {
  87     IsaIrqState *isa = (IsaIrqState *)opaque;
  88
  89     DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
  90     if (n < 16) {
  91         qemu_set_irq(isa->i8259[n], level);
  92     }
  93     if (isa->ioapic)
  94         qemu_set_irq(isa->ioapic[n], level);
  95 };
  96
  97 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  98 {
  99 }
 100
 101 /* MSDOS compatibility mode FPU exception support */
 102 static qemu_irq ferr_irq;
 103
 104 void pc_register_ferr_irq(qemu_irq irq)
 105 {
 106     ferr_irq = irq;
 107 }
 108
 109 /* XXX: add IGNNE support */
 110 void cpu_set_ferr(CPUX86State *s)
 111 {
 112     qemu_irq_raise(ferr_irq);
 113 }
 114
 115 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 116 {
 117     qemu_irq_lower(ferr_irq);
 118 }
 119
 120 /* TSC handling */
 121 uint64_t cpu_get_tsc(CPUX86State *env)
 122 {
 123     return cpu_get_ticks();
 124 }
 125
 126 /* SMM support */
 127
 128 static cpu_set_smm_t smm_set;
 129 static void *smm_arg;
 130
 131 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 132 {
 133     assert(smm_set == NULL);
 134     assert(smm_arg == NULL);
 135     smm_set = callback;
 136     smm_arg = arg;
 137 }
 138
 139 void cpu_smm_update(CPUState *env)
 140 {
 141     if (smm_set && smm_arg && env == first_cpu)
 142         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 143 }
 144
 145
 146 /* IRQ handling */
 147 int cpu_get_pic_interrupt(CPUState *env)
 148 {
 149     int intno;
 150
 151     intno = apic_get_interrupt(env->apic_state);
 152     if (intno >= 0) {
 153         /* set irq request if a PIC irq is still pending */
 154         /* XXX: improve that */
 155         pic_update_irq(isa_pic);
 156         return intno;
 157     }
 158     /* read the irq from the PIC */
 159     if (!apic_accept_pic_intr(env->apic_state)) {
 160         return -1;
 161     }
 162
 163     intno = pic_read_irq(isa_pic);
 164     return intno;
 165 }
 166
 167 static void pic_irq_request(void *opaque, int irq, int level)
 168 {
 169     CPUState *env = first_cpu;
 170
 171     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 172     if (env->apic_state) {
 173         while (env) {
 174             if (apic_accept_pic_intr(env->apic_state)) {
 175                 apic_deliver_pic_intr(env->apic_state, level);
 176             }
 177             env = env->next_cpu;
 178         }
 179     } else {
 180         if (level)
 181             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 182         else
 183             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 184     }
 185 }
 186
 187 /* PC cmos mappings */
 188
 189 #define REG_EQUIPMENT_BYTE          0x14
 190
 191 static int cmos_get_fd_drive_type(int fd0)
 192 {
 193     int val;
 194
 195     switch (fd0) {
 196     case 0:
 197         /* 1.44 Mb 3"5 drive */
 198         val = 4;
 199         break;
 200     case 1:
 201         /* 2.88 Mb 3"5 drive */
 202         val = 5;
 203         break;
 204     case 2:
 205         /* 1.2 Mb 5"5 drive */
 206         val = 2;
 207         break;
 208     default:
 209         val = 0;
 210         break;
 211     }
 212     return val;
 213 }
 214
 215 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 216                          ISADevice *s)
 217 {
 218     int cylinders, heads, sectors;
 219     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 220     rtc_set_memory(s, type_ofs, 47);
 221     rtc_set_memory(s, info_ofs, cylinders);
 222     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 223     rtc_set_memory(s, info_ofs + 2, heads);
 224     rtc_set_memory(s, info_ofs + 3, 0xff);
 225     rtc_set_memory(s, info_ofs + 4, 0xff);
 226     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 227     rtc_set_memory(s, info_ofs + 6, cylinders);
 228     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 229     rtc_set_memory(s, info_ofs + 8, sectors);
 230 }
 231
 232 /* convert boot_device letter to something recognizable by the bios */
 233 static int boot_device2nibble(char boot_device)
 234 {
 235     switch(boot_device) {
 236     case 'a':
 237     case 'b':
 238         return 0x01; /* floppy boot */
 239     case 'c':
 240         return 0x02; /* hard drive boot */
 241     case 'd':
 242         return 0x03; /* CD-ROM boot */
 243     case 'n':
 244         return 0x04; /* Network boot */
 245     }
 246     return 0;
 247 }
 248
 249 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 250 {
 251 #define PC_MAX_BOOT_DEVICES 3
 252     int nbds, bds[3] = { 0, };
 253     int i;
 254
 255     nbds = strlen(boot_device);
 256     if (nbds > PC_MAX_BOOT_DEVICES) {
 257         error_report("Too many boot devices for PC");
 258         return(1);
 259     }
 260     for (i = 0; i < nbds; i++) {
 261         bds[i] = boot_device2nibble(boot_device[i]);
 262         if (bds[i] == 0) {
 263             error_report("Invalid boot device for PC: '%c'",
 264                          boot_device[i]);
 265             return(1);
 266         }
 267     }
 268     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 269     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 270     return(0);
 271 }
 272
 273 static int pc_boot_set(void *opaque, const char *boot_device)
 274 {
 275     return set_boot_dev(opaque, boot_device, 0);
 276 }
 277
 278 /* hd_table must contain 4 block drivers */
 279 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 280                   const char *boot_device, DriveInfo **hd_table,
 281                   FDCtrl *floppy_controller, ISADevice *s)
 282 {
 283     int val;
 284     int fd0, fd1, nb;
 285     int i;
 286
 287     /* various important CMOS locations needed by PC/Bochs bios */
 288
 289     /* memory size */
 290     val = 640; /* base memory in K */
 291     rtc_set_memory(s, 0x15, val);
 292     rtc_set_memory(s, 0x16, val >> 8);
 293
 294     val = (ram_size / 1024) - 1024;
 295     if (val > 65535)
 296         val = 65535;
 297     rtc_set_memory(s, 0x17, val);
 298     rtc_set_memory(s, 0x18, val >> 8);
 299     rtc_set_memory(s, 0x30, val);
 300     rtc_set_memory(s, 0x31, val >> 8);
 301
 302     if (above_4g_mem_size) {
 303         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 304         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 305         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 306     }
 307
 308     if (ram_size > (16 * 1024 * 1024))
 309         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 310     else
 311         val = 0;
 312     if (val > 65535)
 313         val = 65535;
 314     rtc_set_memory(s, 0x34, val);
 315     rtc_set_memory(s, 0x35, val >> 8);
 316
 317     /* set the number of CPU */
 318     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 319
 320     /* set boot devices, and disable floppy signature check if requested */
 321     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 322         exit(1);
 323     }
 324
 325     /* floppy type */
 326
 327     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 328     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 329
 330     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 331     rtc_set_memory(s, 0x10, val);
 332
 333     val = 0;
 334     nb = 0;
 335     if (fd0 < 3)
 336         nb++;
 337     if (fd1 < 3)
 338         nb++;
 339     switch (nb) {
 340     case 0:
 341         break;
 342     case 1:
 343         val |= 0x01; /* 1 drive, ready for boot */
 344         break;
 345     case 2:
 346         val |= 0x41; /* 2 drives, ready for boot */
 347         break;
 348     }
 349     val |= 0x02; /* FPU is there */
 350     val |= 0x04; /* PS/2 mouse installed */
 351     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 352
 353     /* hard drives */
 354
 355     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 356     if (hd_table[0])
 357         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv, s);
 358     if (hd_table[1])
 359         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv, s);
 360
 361     val = 0;
 362     for (i = 0; i < 4; i++) {
 363         if (hd_table[i]) {
 364             int cylinders, heads, sectors, translation;
 365             /* NOTE: bdrv_get_geometry_hint() returns the physical
 366                 geometry.  It is always such that: 1 <= sects <= 63, 1
 367                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 368                 geometry can be different if a translation is done. */
 369             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 370             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 371                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 372                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 373                     /* No translation. */
 374                     translation = 0;
 375                 } else {
 376                     /* LBA translation. */
 377                     translation = 1;
 378                 }
 379             } else {
 380                 translation--;
 381             }
 382             val |= translation << (i * 2);
 383         }
 384     }
 385     rtc_set_memory(s, 0x39, val);
 386 }
 387
 388 static void handle_a20_line_change(void *opaque, int irq, int level)
 389 {
 390     CPUState *cpu = opaque;
 391
 392     /* XXX: send to all CPUs ? */
 393     cpu_x86_set_a20(cpu, level);
 394 }
 395
 396 /***********************************************************/
 397 /* Bochs BIOS debug ports */
 398
 399 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 400 {
 401     static const char shutdown_str[8] = "Shutdown";
 402     static int shutdown_index = 0;
 403
 404     switch(addr) {
 405         /* Bochs BIOS messages */
 406     case 0x400:
 407     case 0x401:
 408         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 409         exit(1);
 410     case 0x402:
 411     case 0x403:
 412 #ifdef DEBUG_BIOS
 413         fprintf(stderr, "%c", val);
 414 #endif
 415         break;
 416     case 0x8900:
 417         /* same as Bochs power off */
 418         if (val == shutdown_str[shutdown_index]) {
 419             shutdown_index++;
 420             if (shutdown_index == 8) {
 421                 shutdown_index = 0;
 422                 qemu_system_shutdown_request();
 423             }
 424         } else {
 425             shutdown_index = 0;
 426         }
 427         break;
 428
 429         /* LGPL'ed VGA BIOS messages */
 430     case 0x501:
 431     case 0x502:
 432         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 433         exit(1);
 434     case 0x500:
 435     case 0x503:
 436 #ifdef DEBUG_BIOS
 437         fprintf(stderr, "%c", val);
 438 #endif
 439         break;
 440     }
 441 }
 442
 443 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 444 {
 445     int index = e820_table.count;
 446     struct e820_entry *entry;
 447
 448     if (index >= E820_NR_ENTRIES)
 449         return -EBUSY;
 450     entry = &e820_table.entry[index];
 451
 452     entry->address = address;
 453     entry->length = length;
 454     entry->type = type;
 455
 456     e820_table.count++;
 457     return e820_table.count;
 458 }
 459
 460 static void *bochs_bios_init(void)
 461 {
 462     void *fw_cfg;
 463     uint8_t *smbios_table;
 464     size_t smbios_len;
 465     uint64_t *numa_fw_cfg;
 466     int i, j;
 467
 468     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 469     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 470     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 471     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 472     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 473
 474     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 475     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 476     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 477     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 478
 479     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 480
 481     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 482     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 483     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 484                      acpi_tables_len);
 485     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 486
 487     smbios_table = smbios_get_table(&smbios_len);
 488     if (smbios_table)
 489         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 490                          smbios_table, smbios_len);
 491     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 492                      sizeof(struct e820_table));
 493
 494     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 495                      sizeof(struct hpet_fw_config));
 496     /* allocate memory for the NUMA channel: one (64bit) word for the number
 497      * of nodes, one word for each VCPU->node and one word for each node to
 498      * hold the amount of memory.
 499      */
 500     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 501     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 502     for (i = 0; i < smp_cpus; i++) {
 503         for (j = 0; j < nb_numa_nodes; j++) {
 504             if (node_cpumask[j] & (1 << i)) {
 505                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 506                 break;
 507             }
 508         }
 509     }
 510     for (i = 0; i < nb_numa_nodes; i++) {
 511         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 512     }
 513     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 514                      (1 + smp_cpus + nb_numa_nodes) * 8);
 515
 516     return fw_cfg;
 517 }
 518
 519 static long get_file_size(FILE *f)
 520 {
 521     long where, size;
 522
 523     /* XXX: on Unix systems, using fstat() probably makes more sense */
 524
 525     where = ftell(f);
 526     fseek(f, 0, SEEK_END);
 527     size = ftell(f);
 528     fseek(f, where, SEEK_SET);
 529
 530     return size;
 531 }
 532
 533 static void load_linux(void *fw_cfg,
 534                        const char *kernel_filename,
 535                        const char *initrd_filename,
 536                        const char *kernel_cmdline,
 537                        target_phys_addr_t max_ram_size)
 538 {
 539     uint16_t protocol;
 540     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 541     uint32_t initrd_max;
 542     uint8_t header[8192], *setup, *kernel, *initrd_data;
 543     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 544     FILE *f;
 545     char *vmode;
 546
 547     /* Align to 16 bytes as a paranoia measure */
 548     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 549
 550     /* load the kernel header */
 551     f = fopen(kernel_filename, "rb");
 552     if (!f || !(kernel_size = get_file_size(f)) ||
 553         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 554         MIN(ARRAY_SIZE(header), kernel_size)) {
 555         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 556                 kernel_filename, strerror(errno));
 557         exit(1);
 558     }
 559
 560     /* kernel protocol version */
 561 #if 0
 562     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 563 #endif
 564     if (ldl_p(header+0x202) == 0x53726448)
 565         protocol = lduw_p(header+0x206);
 566     else {
 567         /* This looks like a multiboot kernel. If it is, let's stop
 568            treating it like a Linux kernel. */
 569         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 570                            kernel_cmdline, kernel_size, header))
 571             return;
 572         protocol = 0;
 573     }
 574
 575     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 576         /* Low kernel */
 577         real_addr    = 0x90000;
 578         cmdline_addr = 0x9a000 - cmdline_size;
 579         prot_addr    = 0x10000;
 580     } else if (protocol < 0x202) {
 581         /* High but ancient kernel */
 582         real_addr    = 0x90000;
 583         cmdline_addr = 0x9a000 - cmdline_size;
 584         prot_addr    = 0x100000;
 585     } else {
 586         /* High and recent kernel */
 587         real_addr    = 0x10000;
 588         cmdline_addr = 0x20000;
 589         prot_addr    = 0x100000;
 590     }
 591
 592 #if 0
 593     fprintf(stderr,
 594             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 595             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 596             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 597             real_addr,
 598             cmdline_addr,
 599             prot_addr);
 600 #endif
 601
 602     /* highest address for loading the initrd */
 603     if (protocol >= 0x203)
 604         initrd_max = ldl_p(header+0x22c);
 605     else
 606         initrd_max = 0x37ffffff;
 607
 608     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 609         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 610
 611     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 612     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 613     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 614                      (uint8_t*)strdup(kernel_cmdline),
 615                      strlen(kernel_cmdline)+1);
 616
 617     if (protocol >= 0x202) {
 618         stl_p(header+0x228, cmdline_addr);
 619     } else {
 620         stw_p(header+0x20, 0xA33F);
 621         stw_p(header+0x22, cmdline_addr-real_addr);
 622     }
 623
 624     /* handle vga= parameter */
 625     vmode = strstr(kernel_cmdline, "vga=");
 626     if (vmode) {
 627         unsigned int video_mode;
 628         /* skip "vga=" */
 629         vmode += 4;
 630         if (!strncmp(vmode, "normal", 6)) {
 631             video_mode = 0xffff;
 632         } else if (!strncmp(vmode, "ext", 3)) {
 633             video_mode = 0xfffe;
 634         } else if (!strncmp(vmode, "ask", 3)) {
 635             video_mode = 0xfffd;
 636         } else {
 637             video_mode = strtol(vmode, NULL, 0);
 638         }
 639         stw_p(header+0x1fa, video_mode);
 640     }
 641
 642     /* loader type */
 643     /* High nybble = B reserved for Qemu; low nybble is revision number.
 644        If this code is substantially changed, you may want to consider
 645        incrementing the revision. */
 646     if (protocol >= 0x200)
 647         header[0x210] = 0xB0;
 648
 649     /* heap */
 650     if (protocol >= 0x201) {
 651         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 652         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 653     }
 654
 655     /* load initrd */
 656     if (initrd_filename) {
 657         if (protocol < 0x200) {
 658             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 659             exit(1);
 660         }
 661
 662         initrd_size = get_image_size(initrd_filename);
 663         if (initrd_size < 0) {
 664             fprintf(stderr, "qemu: error reading initrd %s\n",
 665                     initrd_filename);
 666             exit(1);
 667         }
 668
 669         initrd_addr = (initrd_max-initrd_size) & ~4095;
 670
 671         initrd_data = qemu_malloc(initrd_size);
 672         load_image(initrd_filename, initrd_data);
 673
 674         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 675         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 676         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 677
 678         stl_p(header+0x218, initrd_addr);
 679         stl_p(header+0x21c, initrd_size);
 680     }
 681
 682     /* load kernel and setup */
 683     setup_size = header[0x1f1];
 684     if (setup_size == 0)
 685         setup_size = 4;
 686     setup_size = (setup_size+1)*512;
 687     kernel_size -= setup_size;
 688
 689     setup  = qemu_malloc(setup_size);
 690     kernel = qemu_malloc(kernel_size);
 691     fseek(f, 0, SEEK_SET);
 692     if (fread(setup, 1, setup_size, f) != setup_size) {
 693         fprintf(stderr, "fread() failed\n");
 694         exit(1);
 695     }
 696     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 697         fprintf(stderr, "fread() failed\n");
 698         exit(1);
 699     }
 700     fclose(f);
 701     memcpy(setup, header, MIN(sizeof(header), setup_size));
 702
 703     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 704     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 705     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 706
 707     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 708     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 709     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 710
 711     option_rom[nb_option_roms] = "linuxboot.bin";
 712     nb_option_roms++;
 713 }
 714
 715 #define NE2000_NB_MAX 6
 716
 717 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 718                                               0x280, 0x380 };
 719 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 720
 721 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 722 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 723
 724 void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic)
 725 {
 726     struct soundhw *c;
 727
 728     for (c = soundhw; c->name; ++c) {
 729         if (c->enabled) {
 730             if (c->isa) {
 731                 c->init.init_isa(pic);
 732             } else {
 733                 if (pci_bus) {
 734                     c->init.init_pci(pci_bus);
 735                 }
 736             }
 737         }
 738     }
 739 }
 740
 741 void pc_init_ne2k_isa(NICInfo *nd)
 742 {
 743     static int nb_ne2k = 0;
 744
 745     if (nb_ne2k == NE2000_NB_MAX)
 746         return;
 747     isa_ne2000_init(ne2000_io[nb_ne2k],
 748                     ne2000_irq[nb_ne2k], nd);
 749     nb_ne2k++;
 750 }
 751
 752 int cpu_is_bsp(CPUState *env)
 753 {
 754     /* We hard-wire the BSP to the first CPU. */
 755     return env->cpu_index == 0;
 756 }
 757
 758 DeviceState *cpu_get_current_apic(void)
 759 {
 760     if (cpu_single_env) {
 761         return cpu_single_env->apic_state;
 762     } else {
 763         return NULL;
 764     }
 765 }
 766
 767 static DeviceState *apic_init(void *env, uint8_t apic_id)
 768 {
 769     DeviceState *dev;
 770     SysBusDevice *d;
 771     static int apic_mapped;
 772
 773     dev = qdev_create(NULL, "apic");
 774     qdev_prop_set_uint8(dev, "id", apic_id);
 775     qdev_prop_set_ptr(dev, "cpu_env", env);
 776     qdev_init_nofail(dev);
 777     d = sysbus_from_qdev(dev);
 778
 779     /* XXX: mapping more APICs at the same memory location */
 780     if (apic_mapped == 0) {
 781         /* NOTE: the APIC is directly connected to the CPU - it is not
 782            on the global memory bus. */
 783         /* XXX: what if the base changes? */
 784         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
 785         apic_mapped = 1;
 786     }
 787
 788     msix_supported = 1;
 789
 790     return dev;
 791 }
 792
 793 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 794    BIOS will read it and start S3 resume at POST Entry */
 795 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 796 {
 797     ISADevice *s = opaque;
 798
 799     if (level) {
 800         rtc_set_memory(s, 0xF, 0xFE);
 801     }
 802 }
 803
 804 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 805 {
 806     CPUState *s = opaque;
 807
 808     if (level) {
 809         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 810     }
 811 }
 812
 813 static void pc_cpu_reset(void *opaque)
 814 {
 815     CPUState *env = opaque;
 816
 817     cpu_reset(env);
 818     env->halted = !cpu_is_bsp(env);
 819 }
 820
 821 static CPUState *pc_new_cpu(const char *cpu_model)
 822 {
 823     CPUState *env;
 824
 825     env = cpu_init(cpu_model);
 826     if (!env) {
 827         fprintf(stderr, "Unable to find x86 CPU definition\n");
 828         exit(1);
 829     }
 830     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 831         env->cpuid_apic_id = env->cpu_index;
 832         env->apic_state = apic_init(env, env->cpuid_apic_id);
 833     }
 834     qemu_register_reset(pc_cpu_reset, env);
 835     pc_cpu_reset(env);
 836     return env;
 837 }
 838
 839 void pc_cpus_init(const char *cpu_model)
 840 {
 841     int i;
 842
 843     /* init CPUs */
 844     if (cpu_model == NULL) {
 845 #ifdef TARGET_X86_64
 846         cpu_model = "qemu64";
 847 #else
 848         cpu_model = "qemu32";
 849 #endif
 850     }
 851
 852     for(i = 0; i < smp_cpus; i++) {
 853         pc_new_cpu(cpu_model);
 854     }
 855 }
 856
 857 void pc_memory_init(ram_addr_t ram_size,
 858                     const char *kernel_filename,
 859                     const char *kernel_cmdline,
 860                     const char *initrd_filename,
 861                     ram_addr_t *below_4g_mem_size_p,
 862                     ram_addr_t *above_4g_mem_size_p)
 863 {
 864     char *filename;
 865     int ret, linux_boot, i;
 866     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 867     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 868     int bios_size, isa_bios_size;
 869     void *fw_cfg;
 870
 871     if (ram_size >= 0xe0000000 ) {
 872         above_4g_mem_size = ram_size - 0xe0000000;
 873         below_4g_mem_size = 0xe0000000;
 874     } else {
 875         below_4g_mem_size = ram_size;
 876     }
 877     *above_4g_mem_size_p = above_4g_mem_size;
 878     *below_4g_mem_size_p = below_4g_mem_size;
 879
 880     linux_boot = (kernel_filename != NULL);
 881
 882     /* allocate RAM */
 883     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 884     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 885     cpu_register_physical_memory(0x100000,
 886                  below_4g_mem_size - 0x100000,
 887                  ram_addr + 0x100000);
 888
 889     /* above 4giga memory allocation */
 890     if (above_4g_mem_size > 0) {
 891 #if TARGET_PHYS_ADDR_BITS == 32
 892         hw_error("To much RAM for 32-bit physical address");
 893 #else
 894         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 895         cpu_register_physical_memory(0x100000000ULL,
 896                                      above_4g_mem_size,
 897                                      ram_addr);
 898 #endif
 899     }
 900
 901
 902     /* BIOS load */
 903     if (bios_name == NULL)
 904         bios_name = BIOS_FILENAME;
 905     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 906     if (filename) {
 907         bios_size = get_image_size(filename);
 908     } else {
 909         bios_size = -1;
 910     }
 911     if (bios_size <= 0 ||
 912         (bios_size % 65536) != 0) {
 913         goto bios_error;
 914     }
 915     bios_offset = qemu_ram_alloc(bios_size);
 916     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 917     if (ret != 0) {
 918     bios_error:
 919         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 920         exit(1);
 921     }
 922     if (filename) {
 923         qemu_free(filename);
 924     }
 925     /* map the last 128KB of the BIOS in ISA space */
 926     isa_bios_size = bios_size;
 927     if (isa_bios_size > (128 * 1024))
 928         isa_bios_size = 128 * 1024;
 929     cpu_register_physical_memory(0x100000 - isa_bios_size,
 930                                  isa_bios_size,
 931                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 932
 933     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 934     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 935
 936     /* map all the bios at the top of memory */
 937     cpu_register_physical_memory((uint32_t)(-bios_size),
 938                                  bios_size, bios_offset | IO_MEM_ROM);
 939
 940     fw_cfg = bochs_bios_init();
 941     rom_set_fw(fw_cfg);
 942
 943     if (linux_boot) {
 944         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 945     }
 946
 947     for (i = 0; i < nb_option_roms; i++) {
 948         rom_add_option(option_rom[i]);
 949     }
 950 }
 951
 952 qemu_irq *pc_allocate_cpu_irq(void)
 953 {
 954     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 955 }
 956
 957 void pc_vga_init(PCIBus *pci_bus)
 958 {
 959     if (cirrus_vga_enabled) {
 960         if (pci_bus) {
 961             pci_cirrus_vga_init(pci_bus);
 962         } else {
 963             isa_cirrus_vga_init();
 964         }
 965     } else if (vmsvga_enabled) {
 966         if (pci_bus)
 967             pci_vmsvga_init(pci_bus);
 968         else
 969             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 970     } else if (std_vga_enabled) {
 971         if (pci_bus) {
 972             pci_vga_init(pci_bus, 0, 0);
 973         } else {
 974             isa_vga_init();
 975         }
 976     }
 977 }
 978
 979 static void cpu_request_exit(void *opaque, int irq, int level)
 980 {
 981     CPUState *env = cpu_single_env;
 982
 983     if (env && level) {
 984         cpu_exit(env);
 985     }
 986 }
 987
 988 void pc_basic_device_init(qemu_irq *isa_irq,
 989                           FDCtrl **floppy_controller,
 990                           ISADevice **rtc_state)
 991 {
 992     int i;
 993     DriveInfo *fd[MAX_FD];
 994     PITState *pit;
 995     qemu_irq rtc_irq = NULL;
 996     qemu_irq *a20_line;
 997     ISADevice *i8042;
 998     qemu_irq *cpu_exit_irq;
 999
1000     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1001
1002     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1003
1004     if (!no_hpet) {
1005         DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);
1006
1007         for (i = 0; i < 24; i++) {
1008             sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
1009         }
1010         rtc_irq = qdev_get_gpio_in(hpet, 0);
1011     }
1012     *rtc_state = rtc_init(2000, rtc_irq);
1013
1014     qemu_register_boot_set(pc_boot_set, *rtc_state);
1015
1016     pit = pit_init(0x40, isa_reserve_irq(0));
1017     pcspk_init(pit);
1018
1019     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1020         if (serial_hds[i]) {
1021             serial_isa_init(i, serial_hds[i]);
1022         }
1023     }
1024
1025     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1026         if (parallel_hds[i]) {
1027             parallel_init(i, parallel_hds[i]);
1028         }
1029     }
1030
1031     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
1032     i8042 = isa_create_simple("i8042");
1033     i8042_setup_a20_line(i8042, a20_line);
1034     vmmouse_init(i8042);
1035
1036     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1037     DMA_init(0, cpu_exit_irq);
1038
1039     for(i = 0; i < MAX_FD; i++) {
1040         fd[i] = drive_get(IF_FLOPPY, 0, i);
1041     }
1042     *floppy_controller = fdctrl_init_isa(fd);
1043 }
1044
1045 void pc_pci_device_init(PCIBus *pci_bus)
1046 {
1047     int max_bus;
1048     int bus;
1049
1050     max_bus = drive_get_max_bus(IF_SCSI);
1051     for (bus = 0; bus <= max_bus; bus++) {
1052         pci_create_simple(pci_bus, -1, "lsi53c895a");
1053     }
1054 }