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notifier: Pass data argument to callback
[qemu/stefanha.git] / hw / rtl8139.c
blob5214b8cb7c2feaaf891f533050e027caab315a79
1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49 */
50
51 /* For crc32 */
52 #include <zlib.h>
53
54 #include "hw.h"
55 #include "pci.h"
56 #include "qemu-timer.h"
57 #include "net.h"
58 #include "loader.h"
59 #include "sysemu.h"
60 #include "iov.h"
61
62 /* debug RTL8139 card */
63 //#define DEBUG_RTL8139 1
64
65 #define PCI_FREQUENCY 33000000L
66
67 /* debug RTL8139 card C+ mode only */
68 //#define DEBUG_RTL8139CP 1
69
70 #define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73 /* arg % size for size which is a power of 2 */
74 #define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
77 #define ETHER_ADDR_LEN 6
78 #define ETHER_TYPE_LEN 2
79 #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
80 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
81 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
82 #define ETH_MTU 1500
83
84 #define VLAN_TCI_LEN 2
85 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
86
87 #if defined (DEBUG_RTL8139)
88 # define DPRINTF(fmt, ...) \
89 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
90 #else
91 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
92 {
93 return 0;
94 }
95 #endif
96
97 /* Symbolic offsets to registers. */
98 enum RTL8139_registers {
99 MAC0 = 0, /* Ethernet hardware address. */
100 MAR0 = 8, /* Multicast filter. */
101 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
102 /* Dump Tally Conter control register(64bit). C+ mode only */
103 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
104 RxBuf = 0x30,
105 ChipCmd = 0x37,
106 RxBufPtr = 0x38,
107 RxBufAddr = 0x3A,
108 IntrMask = 0x3C,
109 IntrStatus = 0x3E,
110 TxConfig = 0x40,
111 RxConfig = 0x44,
112 Timer = 0x48, /* A general-purpose counter. */
113 RxMissed = 0x4C, /* 24 bits valid, write clears. */
114 Cfg9346 = 0x50,
115 Config0 = 0x51,
116 Config1 = 0x52,
117 FlashReg = 0x54,
118 MediaStatus = 0x58,
119 Config3 = 0x59,
120 Config4 = 0x5A, /* absent on RTL-8139A */
121 HltClk = 0x5B,
122 MultiIntr = 0x5C,
123 PCIRevisionID = 0x5E,
124 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
125 BasicModeCtrl = 0x62,
126 BasicModeStatus = 0x64,
127 NWayAdvert = 0x66,
128 NWayLPAR = 0x68,
129 NWayExpansion = 0x6A,
130 /* Undocumented registers, but required for proper operation. */
131 FIFOTMS = 0x70, /* FIFO Control and test. */
132 CSCR = 0x74, /* Chip Status and Configuration Register. */
133 PARA78 = 0x78,
134 PARA7c = 0x7c, /* Magic transceiver parameter register. */
135 Config5 = 0xD8, /* absent on RTL-8139A */
136 /* C+ mode */
137 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
138 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
139 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
140 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
141 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
142 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
143 TxThresh = 0xEC, /* Early Tx threshold */
144 };
145
146 enum ClearBitMasks {
147 MultiIntrClear = 0xF000,
148 ChipCmdClear = 0xE2,
149 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
150 };
151
152 enum ChipCmdBits {
153 CmdReset = 0x10,
154 CmdRxEnb = 0x08,
155 CmdTxEnb = 0x04,
156 RxBufEmpty = 0x01,
157 };
158
159 /* C+ mode */
160 enum CplusCmdBits {
161 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
162 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
163 CPlusRxEnb = 0x0002,
164 CPlusTxEnb = 0x0001,
165 };
166
167 /* Interrupt register bits, using my own meaningful names. */
168 enum IntrStatusBits {
169 PCIErr = 0x8000,
170 PCSTimeout = 0x4000,
171 RxFIFOOver = 0x40,
172 RxUnderrun = 0x20,
173 RxOverflow = 0x10,
174 TxErr = 0x08,
175 TxOK = 0x04,
176 RxErr = 0x02,
177 RxOK = 0x01,
178
179 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
180 };
181
182 enum TxStatusBits {
183 TxHostOwns = 0x2000,
184 TxUnderrun = 0x4000,
185 TxStatOK = 0x8000,
186 TxOutOfWindow = 0x20000000,
187 TxAborted = 0x40000000,
188 TxCarrierLost = 0x80000000,
189 };
190 enum RxStatusBits {
191 RxMulticast = 0x8000,
192 RxPhysical = 0x4000,
193 RxBroadcast = 0x2000,
194 RxBadSymbol = 0x0020,
195 RxRunt = 0x0010,
196 RxTooLong = 0x0008,
197 RxCRCErr = 0x0004,
198 RxBadAlign = 0x0002,
199 RxStatusOK = 0x0001,
200 };
201
202 /* Bits in RxConfig. */
203 enum rx_mode_bits {
204 AcceptErr = 0x20,
205 AcceptRunt = 0x10,
206 AcceptBroadcast = 0x08,
207 AcceptMulticast = 0x04,
208 AcceptMyPhys = 0x02,
209 AcceptAllPhys = 0x01,
210 };
211
212 /* Bits in TxConfig. */
213 enum tx_config_bits {
214
215 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
216 TxIFGShift = 24,
217 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
218 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
219 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
220 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
221
222 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
223 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
224 TxClearAbt = (1 << 0), /* Clear abort (WO) */
225 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
226 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
227
228 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
229 };
230
231
232 /* Transmit Status of All Descriptors (TSAD) Register */
233 enum TSAD_bits {
234 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
235 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
236 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
237 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
238 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
239 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
240 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
241 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
242 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
243 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
244 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
245 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
246 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
247 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
248 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
249 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
250 };
251
252
253 /* Bits in Config1 */
254 enum Config1Bits {
255 Cfg1_PM_Enable = 0x01,
256 Cfg1_VPD_Enable = 0x02,
257 Cfg1_PIO = 0x04,
258 Cfg1_MMIO = 0x08,
259 LWAKE = 0x10, /* not on 8139, 8139A */
260 Cfg1_Driver_Load = 0x20,
261 Cfg1_LED0 = 0x40,
262 Cfg1_LED1 = 0x80,
263 SLEEP = (1 << 1), /* only on 8139, 8139A */
264 PWRDN = (1 << 0), /* only on 8139, 8139A */
265 };
266
267 /* Bits in Config3 */
268 enum Config3Bits {
269 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
270 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
271 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
272 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
273 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
274 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
275 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
276 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
277 };
278
279 /* Bits in Config4 */
280 enum Config4Bits {
281 LWPTN = (1 << 2), /* not on 8139, 8139A */
282 };
283
284 /* Bits in Config5 */
285 enum Config5Bits {
286 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
287 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
288 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
289 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
290 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
291 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
292 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
293 };
294
295 enum RxConfigBits {
296 /* rx fifo threshold */
297 RxCfgFIFOShift = 13,
298 RxCfgFIFONone = (7 << RxCfgFIFOShift),
299
300 /* Max DMA burst */
301 RxCfgDMAShift = 8,
302 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
303
304 /* rx ring buffer length */
305 RxCfgRcv8K = 0,
306 RxCfgRcv16K = (1 << 11),
307 RxCfgRcv32K = (1 << 12),
308 RxCfgRcv64K = (1 << 11) | (1 << 12),
309
310 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
311 RxNoWrap = (1 << 7),
312 };
313
314 /* Twister tuning parameters from RealTek.
315 Completely undocumented, but required to tune bad links on some boards. */
316 /*
317 enum CSCRBits {
318 CSCR_LinkOKBit = 0x0400,
319 CSCR_LinkChangeBit = 0x0800,
320 CSCR_LinkStatusBits = 0x0f000,
321 CSCR_LinkDownOffCmd = 0x003c0,
322 CSCR_LinkDownCmd = 0x0f3c0,
323 */
324 enum CSCRBits {
325 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
326 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
327 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
328 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
329 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
330 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
331 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
332 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
333 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
334 };
335
336 enum Cfg9346Bits {
337 Cfg9346_Lock = 0x00,
338 Cfg9346_Unlock = 0xC0,
339 };
340
341 typedef enum {
342 CH_8139 = 0,
343 CH_8139_K,
344 CH_8139A,
345 CH_8139A_G,
346 CH_8139B,
347 CH_8130,
348 CH_8139C,
349 CH_8100,
350 CH_8100B_8139D,
351 CH_8101,
352 } chip_t;
353
354 enum chip_flags {
355 HasHltClk = (1 << 0),
356 HasLWake = (1 << 1),
357 };
358
359 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
360 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
361 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
362
363 #define RTL8139_PCI_REVID_8139 0x10
364 #define RTL8139_PCI_REVID_8139CPLUS 0x20
365
366 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
367
368 /* Size is 64 * 16bit words */
369 #define EEPROM_9346_ADDR_BITS 6
370 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
371 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
372
373 enum Chip9346Operation
374 {
375 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
376 Chip9346_op_read = 0x80, /* 10 AAAAAA */
377 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
378 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
379 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
380 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
381 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
382 };
383
384 enum Chip9346Mode
385 {
386 Chip9346_none = 0,
387 Chip9346_enter_command_mode,
388 Chip9346_read_command,
389 Chip9346_data_read, /* from output register */
390 Chip9346_data_write, /* to input register, then to contents at specified address */
391 Chip9346_data_write_all, /* to input register, then filling contents */
392 };
393
394 typedef struct EEprom9346
395 {
396 uint16_t contents[EEPROM_9346_SIZE];
397 int mode;
398 uint32_t tick;
399 uint8_t address;
400 uint16_t input;
401 uint16_t output;
402
403 uint8_t eecs;
404 uint8_t eesk;
405 uint8_t eedi;
406 uint8_t eedo;
407 } EEprom9346;
408
409 typedef struct RTL8139TallyCounters
410 {
411 /* Tally counters */
412 uint64_t TxOk;
413 uint64_t RxOk;
414 uint64_t TxERR;
415 uint32_t RxERR;
416 uint16_t MissPkt;
417 uint16_t FAE;
418 uint32_t Tx1Col;
419 uint32_t TxMCol;
420 uint64_t RxOkPhy;
421 uint64_t RxOkBrd;
422 uint32_t RxOkMul;
423 uint16_t TxAbt;
424 uint16_t TxUndrn;
425 } RTL8139TallyCounters;
426
427 /* Clears all tally counters */
428 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
429
430 /* Writes tally counters to specified physical memory address */
431 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
432
433 typedef struct RTL8139State {
434 PCIDevice dev;
435 uint8_t phys[8]; /* mac address */
436 uint8_t mult[8]; /* multicast mask array */
437
438 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
439 uint32_t TxAddr[4]; /* TxAddr0 */
440 uint32_t RxBuf; /* Receive buffer */
441 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
442 uint32_t RxBufPtr;
443 uint32_t RxBufAddr;
444
445 uint16_t IntrStatus;
446 uint16_t IntrMask;
447
448 uint32_t TxConfig;
449 uint32_t RxConfig;
450 uint32_t RxMissed;
451
452 uint16_t CSCR;
453
454 uint8_t Cfg9346;
455 uint8_t Config0;
456 uint8_t Config1;
457 uint8_t Config3;
458 uint8_t Config4;
459 uint8_t Config5;
460
461 uint8_t clock_enabled;
462 uint8_t bChipCmdState;
463
464 uint16_t MultiIntr;
465
466 uint16_t BasicModeCtrl;
467 uint16_t BasicModeStatus;
468 uint16_t NWayAdvert;
469 uint16_t NWayLPAR;
470 uint16_t NWayExpansion;
471
472 uint16_t CpCmd;
473 uint8_t TxThresh;
474
475 NICState *nic;
476 NICConf conf;
477 int rtl8139_mmio_io_addr;
478
479 /* C ring mode */
480 uint32_t currTxDesc;
481
482 /* C+ mode */
483 uint32_t cplus_enabled;
484
485 uint32_t currCPlusRxDesc;
486 uint32_t currCPlusTxDesc;
487
488 uint32_t RxRingAddrLO;
489 uint32_t RxRingAddrHI;
490
491 EEprom9346 eeprom;
492
493 uint32_t TCTR;
494 uint32_t TimerInt;
495 int64_t TCTR_base;
496
497 /* Tally counters */
498 RTL8139TallyCounters tally_counters;
499
500 /* Non-persistent data */
501 uint8_t *cplus_txbuffer;
502 int cplus_txbuffer_len;
503 int cplus_txbuffer_offset;
504
505 /* PCI interrupt timer */
506 QEMUTimer *timer;
507 int64_t TimerExpire;
508
509 /* Support migration to/from old versions */
510 int rtl8139_mmio_io_addr_dummy;
511 } RTL8139State;
512
513 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
514
515 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
516 {
517 DPRINTF("eeprom command 0x%02x\n", command);
518
519 switch (command & Chip9346_op_mask)
520 {
521 case Chip9346_op_read:
522 {
523 eeprom->address = command & EEPROM_9346_ADDR_MASK;
524 eeprom->output = eeprom->contents[eeprom->address];
525 eeprom->eedo = 0;
526 eeprom->tick = 0;
527 eeprom->mode = Chip9346_data_read;
528 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
529 eeprom->address, eeprom->output);
530 }
531 break;
532
533 case Chip9346_op_write:
534 {
535 eeprom->address = command & EEPROM_9346_ADDR_MASK;
536 eeprom->input = 0;
537 eeprom->tick = 0;
538 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
539 DPRINTF("eeprom begin write to address 0x%02x\n",
540 eeprom->address);
541 }
542 break;
543 default:
544 eeprom->mode = Chip9346_none;
545 switch (command & Chip9346_op_ext_mask)
546 {
547 case Chip9346_op_write_enable:
548 DPRINTF("eeprom write enabled\n");
549 break;
550 case Chip9346_op_write_all:
551 DPRINTF("eeprom begin write all\n");
552 break;
553 case Chip9346_op_write_disable:
554 DPRINTF("eeprom write disabled\n");
555 break;
556 }
557 break;
558 }
559 }
560
561 static void prom9346_shift_clock(EEprom9346 *eeprom)
562 {
563 int bit = eeprom->eedi?1:0;
564
565 ++ eeprom->tick;
566
567 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
568 eeprom->eedo);
569
570 switch (eeprom->mode)
571 {
572 case Chip9346_enter_command_mode:
573 if (bit)
574 {
575 eeprom->mode = Chip9346_read_command;
576 eeprom->tick = 0;
577 eeprom->input = 0;
578 DPRINTF("eeprom: +++ synchronized, begin command read\n");
579 }
580 break;
581
582 case Chip9346_read_command:
583 eeprom->input = (eeprom->input << 1) | (bit & 1);
584 if (eeprom->tick == 8)
585 {
586 prom9346_decode_command(eeprom, eeprom->input & 0xff);
587 }
588 break;
589
590 case Chip9346_data_read:
591 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
592 eeprom->output <<= 1;
593 if (eeprom->tick == 16)
594 {
595 #if 1
596 // the FreeBSD drivers (rl and re) don't explicitly toggle
597 // CS between reads (or does setting Cfg9346 to 0 count too?),
598 // so we need to enter wait-for-command state here
599 eeprom->mode = Chip9346_enter_command_mode;
600 eeprom->input = 0;
601 eeprom->tick = 0;
602
603 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
604 #else
605 // original behaviour
606 ++eeprom->address;
607 eeprom->address &= EEPROM_9346_ADDR_MASK;
608 eeprom->output = eeprom->contents[eeprom->address];
609 eeprom->tick = 0;
610
611 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
612 eeprom->address, eeprom->output);
613 #endif
614 }
615 break;
616
617 case Chip9346_data_write:
618 eeprom->input = (eeprom->input << 1) | (bit & 1);
619 if (eeprom->tick == 16)
620 {
621 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
622 eeprom->address, eeprom->input);
623
624 eeprom->contents[eeprom->address] = eeprom->input;
625 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
626 eeprom->tick = 0;
627 eeprom->input = 0;
628 }
629 break;
630
631 case Chip9346_data_write_all:
632 eeprom->input = (eeprom->input << 1) | (bit & 1);
633 if (eeprom->tick == 16)
634 {
635 int i;
636 for (i = 0; i < EEPROM_9346_SIZE; i++)
637 {
638 eeprom->contents[i] = eeprom->input;
639 }
640 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
641
642 eeprom->mode = Chip9346_enter_command_mode;
643 eeprom->tick = 0;
644 eeprom->input = 0;
645 }
646 break;
647
648 default:
649 break;
650 }
651 }
652
653 static int prom9346_get_wire(RTL8139State *s)
654 {
655 EEprom9346 *eeprom = &s->eeprom;
656 if (!eeprom->eecs)
657 return 0;
658
659 return eeprom->eedo;
660 }
661
662 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
663 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
664 {
665 EEprom9346 *eeprom = &s->eeprom;
666 uint8_t old_eecs = eeprom->eecs;
667 uint8_t old_eesk = eeprom->eesk;
668
669 eeprom->eecs = eecs;
670 eeprom->eesk = eesk;
671 eeprom->eedi = eedi;
672
673 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
674 eeprom->eesk, eeprom->eedi, eeprom->eedo);
675
676 if (!old_eecs && eecs)
677 {
678 /* Synchronize start */
679 eeprom->tick = 0;
680 eeprom->input = 0;
681 eeprom->output = 0;
682 eeprom->mode = Chip9346_enter_command_mode;
683
684 DPRINTF("=== eeprom: begin access, enter command mode\n");
685 }
686
687 if (!eecs)
688 {
689 DPRINTF("=== eeprom: end access\n");
690 return;
691 }
692
693 if (!old_eesk && eesk)
694 {
695 /* SK front rules */
696 prom9346_shift_clock(eeprom);
697 }
698 }
699
700 static void rtl8139_update_irq(RTL8139State *s)
701 {
702 int isr;
703 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
704
705 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
706 s->IntrMask);
707
708 qemu_set_irq(s->dev.irq[0], (isr != 0));
709 }
710
711 #define POLYNOMIAL 0x04c11db6
712
713 /* From FreeBSD */
714 /* XXX: optimize */
715 static int compute_mcast_idx(const uint8_t *ep)
716 {
717 uint32_t crc;
718 int carry, i, j;
719 uint8_t b;
720
721 crc = 0xffffffff;
722 for (i = 0; i < 6; i++) {
723 b = *ep++;
724 for (j = 0; j < 8; j++) {
725 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
726 crc <<= 1;
727 b >>= 1;
728 if (carry)
729 crc = ((crc ^ POLYNOMIAL) | carry);
730 }
731 }
732 return (crc >> 26);
733 }
734
735 static int rtl8139_RxWrap(RTL8139State *s)
736 {
737 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
738 return (s->RxConfig & (1 << 7));
739 }
740
741 static int rtl8139_receiver_enabled(RTL8139State *s)
742 {
743 return s->bChipCmdState & CmdRxEnb;
744 }
745
746 static int rtl8139_transmitter_enabled(RTL8139State *s)
747 {
748 return s->bChipCmdState & CmdTxEnb;
749 }
750
751 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
752 {
753 return s->CpCmd & CPlusRxEnb;
754 }
755
756 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
757 {
758 return s->CpCmd & CPlusTxEnb;
759 }
760
761 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
762 {
763 if (s->RxBufAddr + size > s->RxBufferSize)
764 {
765 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
766
767 /* write packet data */
768 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
769 {
770 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
771
772 if (size > wrapped)
773 {
774 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
775 buf, size-wrapped );
776 }
777
778 /* reset buffer pointer */
779 s->RxBufAddr = 0;
780
781 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
782 buf + (size-wrapped), wrapped );
783
784 s->RxBufAddr = wrapped;
785
786 return;
787 }
788 }
789
790 /* non-wrapping path or overwrapping enabled */
791 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
792
793 s->RxBufAddr += size;
794 }
795
796 #define MIN_BUF_SIZE 60
797 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
798 {
799 #if TARGET_PHYS_ADDR_BITS > 32
800 return low | ((target_phys_addr_t)high << 32);
801 #else
802 return low;
803 #endif
804 }
805
806 static int rtl8139_can_receive(VLANClientState *nc)
807 {
808 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
809 int avail;
810
811 /* Receive (drop) packets if card is disabled. */
812 if (!s->clock_enabled)
813 return 1;
814 if (!rtl8139_receiver_enabled(s))
815 return 1;
816
817 if (rtl8139_cp_receiver_enabled(s)) {
818 /* ??? Flow control not implemented in c+ mode.
819 This is a hack to work around slirp deficiencies anyway. */
820 return 1;
821 } else {
822 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
823 s->RxBufferSize);
824 return (avail == 0 || avail >= 1514);
825 }
826 }
827
828 static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
829 {
830 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
831 /* size is the length of the buffer passed to the driver */
832 int size = size_;
833 const uint8_t *dot1q_buf = NULL;
834
835 uint32_t packet_header = 0;
836
837 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
838 static const uint8_t broadcast_macaddr[6] =
839 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
840
841 DPRINTF(">>> received len=%d\n", size);
842
843 /* test if board clock is stopped */
844 if (!s->clock_enabled)
845 {
846 DPRINTF("stopped ==========================\n");
847 return -1;
848 }
849
850 /* first check if receiver is enabled */
851
852 if (!rtl8139_receiver_enabled(s))
853 {
854 DPRINTF("receiver disabled ================\n");
855 return -1;
856 }
857
858 /* XXX: check this */
859 if (s->RxConfig & AcceptAllPhys) {
860 /* promiscuous: receive all */
861 DPRINTF(">>> packet received in promiscuous mode\n");
862
863 } else {
864 if (!memcmp(buf, broadcast_macaddr, 6)) {
865 /* broadcast address */
866 if (!(s->RxConfig & AcceptBroadcast))
867 {
868 DPRINTF(">>> broadcast packet rejected\n");
869
870 /* update tally counter */
871 ++s->tally_counters.RxERR;
872
873 return size;
874 }
875
876 packet_header |= RxBroadcast;
877
878 DPRINTF(">>> broadcast packet received\n");
879
880 /* update tally counter */
881 ++s->tally_counters.RxOkBrd;
882
883 } else if (buf[0] & 0x01) {
884 /* multicast */
885 if (!(s->RxConfig & AcceptMulticast))
886 {
887 DPRINTF(">>> multicast packet rejected\n");
888
889 /* update tally counter */
890 ++s->tally_counters.RxERR;
891
892 return size;
893 }
894
895 int mcast_idx = compute_mcast_idx(buf);
896
897 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
898 {
899 DPRINTF(">>> multicast address mismatch\n");
900
901 /* update tally counter */
902 ++s->tally_counters.RxERR;
903
904 return size;
905 }
906
907 packet_header |= RxMulticast;
908
909 DPRINTF(">>> multicast packet received\n");
910
911 /* update tally counter */
912 ++s->tally_counters.RxOkMul;
913
914 } else if (s->phys[0] == buf[0] &&
915 s->phys[1] == buf[1] &&
916 s->phys[2] == buf[2] &&
917 s->phys[3] == buf[3] &&
918 s->phys[4] == buf[4] &&
919 s->phys[5] == buf[5]) {
920 /* match */
921 if (!(s->RxConfig & AcceptMyPhys))
922 {
923 DPRINTF(">>> rejecting physical address matching packet\n");
924
925 /* update tally counter */
926 ++s->tally_counters.RxERR;
927
928 return size;
929 }
930
931 packet_header |= RxPhysical;
932
933 DPRINTF(">>> physical address matching packet received\n");
934
935 /* update tally counter */
936 ++s->tally_counters.RxOkPhy;
937
938 } else {
939
940 DPRINTF(">>> unknown packet\n");
941
942 /* update tally counter */
943 ++s->tally_counters.RxERR;
944
945 return size;
946 }
947 }
948
949 /* if too small buffer, then expand it
950 * Include some tailroom in case a vlan tag is later removed. */
951 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
952 memcpy(buf1, buf, size);
953 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
954 buf = buf1;
955 if (size < MIN_BUF_SIZE) {
956 size = MIN_BUF_SIZE;
957 }
958 }
959
960 if (rtl8139_cp_receiver_enabled(s))
961 {
962 DPRINTF("in C+ Rx mode ================\n");
963
964 /* begin C+ receiver mode */
965
966 /* w0 ownership flag */
967 #define CP_RX_OWN (1<<31)
968 /* w0 end of ring flag */
969 #define CP_RX_EOR (1<<30)
970 /* w0 bits 0...12 : buffer size */
971 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
972 /* w1 tag available flag */
973 #define CP_RX_TAVA (1<<16)
974 /* w1 bits 0...15 : VLAN tag */
975 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
976 /* w2 low 32bit of Rx buffer ptr */
977 /* w3 high 32bit of Rx buffer ptr */
978
979 int descriptor = s->currCPlusRxDesc;
980 target_phys_addr_t cplus_rx_ring_desc;
981
982 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
983 cplus_rx_ring_desc += 16 * descriptor;
984
985 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
986 "%08x %08x = "TARGET_FMT_plx"\n", descriptor, s->RxRingAddrHI,
987 s->RxRingAddrLO, cplus_rx_ring_desc);
988
989 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
990
991 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
992 rxdw0 = le32_to_cpu(val);
993 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
994 rxdw1 = le32_to_cpu(val);
995 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
996 rxbufLO = le32_to_cpu(val);
997 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
998 rxbufHI = le32_to_cpu(val);
999
1000 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
1001 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
1002
1003 if (!(rxdw0 & CP_RX_OWN))
1004 {
1005 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1006 descriptor);
1007
1008 s->IntrStatus |= RxOverflow;
1009 ++s->RxMissed;
1010
1011 /* update tally counter */
1012 ++s->tally_counters.RxERR;
1013 ++s->tally_counters.MissPkt;
1014
1015 rtl8139_update_irq(s);
1016 return size_;
1017 }
1018
1019 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1020
1021 /* write VLAN info to descriptor variables. */
1022 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1023 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1024 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1025 size -= VLAN_HLEN;
1026 /* if too small buffer, use the tailroom added duing expansion */
1027 if (size < MIN_BUF_SIZE) {
1028 size = MIN_BUF_SIZE;
1029 }
1030
1031 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1032 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1033 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1034 &dot1q_buf[ETHER_TYPE_LEN]);
1035
1036 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1037 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
1038 } else {
1039 /* reset VLAN tag flag */
1040 rxdw1 &= ~CP_RX_TAVA;
1041 }
1042
1043 /* TODO: scatter the packet over available receive ring descriptors space */
1044
1045 if (size+4 > rx_space)
1046 {
1047 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1048 descriptor, rx_space, size);
1049
1050 s->IntrStatus |= RxOverflow;
1051 ++s->RxMissed;
1052
1053 /* update tally counter */
1054 ++s->tally_counters.RxERR;
1055 ++s->tally_counters.MissPkt;
1056
1057 rtl8139_update_irq(s);
1058 return size_;
1059 }
1060
1061 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1062
1063 /* receive/copy to target memory */
1064 if (dot1q_buf) {
1065 cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
1066 cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
1067 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1068 size - 2 * ETHER_ADDR_LEN);
1069 } else {
1070 cpu_physical_memory_write(rx_addr, buf, size);
1071 }
1072
1073 if (s->CpCmd & CPlusRxChkSum)
1074 {
1075 /* do some packet checksumming */
1076 }
1077
1078 /* write checksum */
1079 val = cpu_to_le32(crc32(0, buf, size_));
1080 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1081
1082 /* first segment of received packet flag */
1083 #define CP_RX_STATUS_FS (1<<29)
1084 /* last segment of received packet flag */
1085 #define CP_RX_STATUS_LS (1<<28)
1086 /* multicast packet flag */
1087 #define CP_RX_STATUS_MAR (1<<26)
1088 /* physical-matching packet flag */
1089 #define CP_RX_STATUS_PAM (1<<25)
1090 /* broadcast packet flag */
1091 #define CP_RX_STATUS_BAR (1<<24)
1092 /* runt packet flag */
1093 #define CP_RX_STATUS_RUNT (1<<19)
1094 /* crc error flag */
1095 #define CP_RX_STATUS_CRC (1<<18)
1096 /* IP checksum error flag */
1097 #define CP_RX_STATUS_IPF (1<<15)
1098 /* UDP checksum error flag */
1099 #define CP_RX_STATUS_UDPF (1<<14)
1100 /* TCP checksum error flag */
1101 #define CP_RX_STATUS_TCPF (1<<13)
1102
1103 /* transfer ownership to target */
1104 rxdw0 &= ~CP_RX_OWN;
1105
1106 /* set first segment bit */
1107 rxdw0 |= CP_RX_STATUS_FS;
1108
1109 /* set last segment bit */
1110 rxdw0 |= CP_RX_STATUS_LS;
1111
1112 /* set received packet type flags */
1113 if (packet_header & RxBroadcast)
1114 rxdw0 |= CP_RX_STATUS_BAR;
1115 if (packet_header & RxMulticast)
1116 rxdw0 |= CP_RX_STATUS_MAR;
1117 if (packet_header & RxPhysical)
1118 rxdw0 |= CP_RX_STATUS_PAM;
1119
1120 /* set received size */
1121 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1122 rxdw0 |= (size+4);
1123
1124 /* update ring data */
1125 val = cpu_to_le32(rxdw0);
1126 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1127 val = cpu_to_le32(rxdw1);
1128 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1129
1130 /* update tally counter */
1131 ++s->tally_counters.RxOk;
1132
1133 /* seek to next Rx descriptor */
1134 if (rxdw0 & CP_RX_EOR)
1135 {
1136 s->currCPlusRxDesc = 0;
1137 }
1138 else
1139 {
1140 ++s->currCPlusRxDesc;
1141 }
1142
1143 DPRINTF("done C+ Rx mode ----------------\n");
1144
1145 }
1146 else
1147 {
1148 DPRINTF("in ring Rx mode ================\n");
1149
1150 /* begin ring receiver mode */
1151 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1152
1153 /* if receiver buffer is empty then avail == 0 */
1154
1155 if (avail != 0 && size + 8 >= avail)
1156 {
1157 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1158 "read 0x%04x === available 0x%04x need 0x%04x\n",
1159 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1160
1161 s->IntrStatus |= RxOverflow;
1162 ++s->RxMissed;
1163 rtl8139_update_irq(s);
1164 return size_;
1165 }
1166
1167 packet_header |= RxStatusOK;
1168
1169 packet_header |= (((size+4) << 16) & 0xffff0000);
1170
1171 /* write header */
1172 uint32_t val = cpu_to_le32(packet_header);
1173
1174 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1175
1176 rtl8139_write_buffer(s, buf, size);
1177
1178 /* write checksum */
1179 val = cpu_to_le32(crc32(0, buf, size));
1180 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1181
1182 /* correct buffer write pointer */
1183 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1184
1185 /* now we can signal we have received something */
1186
1187 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1188 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1189 }
1190
1191 s->IntrStatus |= RxOK;
1192
1193 if (do_interrupt)
1194 {
1195 rtl8139_update_irq(s);
1196 }
1197
1198 return size_;
1199 }
1200
1201 static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
1202 {
1203 return rtl8139_do_receive(nc, buf, size, 1);
1204 }
1205
1206 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1207 {
1208 s->RxBufferSize = bufferSize;
1209 s->RxBufPtr = 0;
1210 s->RxBufAddr = 0;
1211 }
1212
1213 static void rtl8139_reset(DeviceState *d)
1214 {
1215 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
1216 int i;
1217
1218 /* restore MAC address */
1219 memcpy(s->phys, s->conf.macaddr.a, 6);
1220
1221 /* reset interrupt mask */
1222 s->IntrStatus = 0;
1223 s->IntrMask = 0;
1224
1225 rtl8139_update_irq(s);
1226
1227 /* mark all status registers as owned by host */
1228 for (i = 0; i < 4; ++i)
1229 {
1230 s->TxStatus[i] = TxHostOwns;
1231 }
1232
1233 s->currTxDesc = 0;
1234 s->currCPlusRxDesc = 0;
1235 s->currCPlusTxDesc = 0;
1236
1237 s->RxRingAddrLO = 0;
1238 s->RxRingAddrHI = 0;
1239
1240 s->RxBuf = 0;
1241
1242 rtl8139_reset_rxring(s, 8192);
1243
1244 /* ACK the reset */
1245 s->TxConfig = 0;
1246
1247 #if 0
1248 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1249 s->clock_enabled = 0;
1250 #else
1251 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1252 s->clock_enabled = 1;
1253 #endif
1254
1255 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1256
1257 /* set initial state data */
1258 s->Config0 = 0x0; /* No boot ROM */
1259 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1260 s->Config3 = 0x1; /* fast back-to-back compatible */
1261 s->Config5 = 0x0;
1262
1263 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1264
1265 s->CpCmd = 0x0; /* reset C+ mode */
1266 s->cplus_enabled = 0;
1267
1268
1269 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1270 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1271 s->BasicModeCtrl = 0x1000; // autonegotiation
1272
1273 s->BasicModeStatus = 0x7809;
1274 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1275 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1276 s->BasicModeStatus |= 0x0004; /* link is up */
1277
1278 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1279 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1280 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1281
1282 /* also reset timer and disable timer interrupt */
1283 s->TCTR = 0;
1284 s->TimerInt = 0;
1285 s->TCTR_base = 0;
1286
1287 /* reset tally counters */
1288 RTL8139TallyCounters_clear(&s->tally_counters);
1289 }
1290
1291 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1292 {
1293 counters->TxOk = 0;
1294 counters->RxOk = 0;
1295 counters->TxERR = 0;
1296 counters->RxERR = 0;
1297 counters->MissPkt = 0;
1298 counters->FAE = 0;
1299 counters->Tx1Col = 0;
1300 counters->TxMCol = 0;
1301 counters->RxOkPhy = 0;
1302 counters->RxOkBrd = 0;
1303 counters->RxOkMul = 0;
1304 counters->TxAbt = 0;
1305 counters->TxUndrn = 0;
1306 }
1307
1308 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1309 {
1310 uint16_t val16;
1311 uint32_t val32;
1312 uint64_t val64;
1313
1314 val64 = cpu_to_le64(tally_counters->TxOk);
1315 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1316
1317 val64 = cpu_to_le64(tally_counters->RxOk);
1318 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1319
1320 val64 = cpu_to_le64(tally_counters->TxERR);
1321 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1322
1323 val32 = cpu_to_le32(tally_counters->RxERR);
1324 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1325
1326 val16 = cpu_to_le16(tally_counters->MissPkt);
1327 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1328
1329 val16 = cpu_to_le16(tally_counters->FAE);
1330 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1331
1332 val32 = cpu_to_le32(tally_counters->Tx1Col);
1333 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1334
1335 val32 = cpu_to_le32(tally_counters->TxMCol);
1336 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1337
1338 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1339 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1340
1341 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1342 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1343
1344 val32 = cpu_to_le32(tally_counters->RxOkMul);
1345 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1346
1347 val16 = cpu_to_le16(tally_counters->TxAbt);
1348 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1349
1350 val16 = cpu_to_le16(tally_counters->TxUndrn);
1351 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1352 }
1353
1354 /* Loads values of tally counters from VM state file */
1355
1356 static const VMStateDescription vmstate_tally_counters = {
1357 .name = "tally_counters",
1358 .version_id = 1,
1359 .minimum_version_id = 1,
1360 .minimum_version_id_old = 1,
1361 .fields = (VMStateField []) {
1362 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1363 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1364 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1365 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1366 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1367 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1368 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1369 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1370 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1371 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1372 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1373 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1374 VMSTATE_END_OF_LIST()
1375 }
1376 };
1377
1378 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1379 {
1380 val &= 0xff;
1381
1382 DPRINTF("ChipCmd write val=0x%08x\n", val);
1383
1384 if (val & CmdReset)
1385 {
1386 DPRINTF("ChipCmd reset\n");
1387 rtl8139_reset(&s->dev.qdev);
1388 }
1389 if (val & CmdRxEnb)
1390 {
1391 DPRINTF("ChipCmd enable receiver\n");
1392
1393 s->currCPlusRxDesc = 0;
1394 }
1395 if (val & CmdTxEnb)
1396 {
1397 DPRINTF("ChipCmd enable transmitter\n");
1398
1399 s->currCPlusTxDesc = 0;
1400 }
1401
1402 /* mask unwritable bits */
1403 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1404
1405 /* Deassert reset pin before next read */
1406 val &= ~CmdReset;
1407
1408 s->bChipCmdState = val;
1409 }
1410
1411 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1412 {
1413 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1414
1415 if (unread != 0)
1416 {
1417 DPRINTF("receiver buffer data available 0x%04x\n", unread);
1418 return 0;
1419 }
1420
1421 DPRINTF("receiver buffer is empty\n");
1422
1423 return 1;
1424 }
1425
1426 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1427 {
1428 uint32_t ret = s->bChipCmdState;
1429
1430 if (rtl8139_RxBufferEmpty(s))
1431 ret |= RxBufEmpty;
1432
1433 DPRINTF("ChipCmd read val=0x%04x\n", ret);
1434
1435 return ret;
1436 }
1437
1438 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1439 {
1440 val &= 0xffff;
1441
1442 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1443
1444 s->cplus_enabled = 1;
1445
1446 /* mask unwritable bits */
1447 val = SET_MASKED(val, 0xff84, s->CpCmd);
1448
1449 s->CpCmd = val;
1450 }
1451
1452 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1453 {
1454 uint32_t ret = s->CpCmd;
1455
1456 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1457
1458 return ret;
1459 }
1460
1461 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1462 {
1463 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1464 }
1465
1466 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1467 {
1468 uint32_t ret = 0;
1469
1470 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1471
1472 return ret;
1473 }
1474
1475 static int rtl8139_config_writable(RTL8139State *s)
1476 {
1477 if (s->Cfg9346 & Cfg9346_Unlock)
1478 {
1479 return 1;
1480 }
1481
1482 DPRINTF("Configuration registers are write-protected\n");
1483
1484 return 0;
1485 }
1486
1487 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1488 {
1489 val &= 0xffff;
1490
1491 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1492
1493 /* mask unwritable bits */
1494 uint32_t mask = 0x4cff;
1495
1496 if (1 || !rtl8139_config_writable(s))
1497 {
1498 /* Speed setting and autonegotiation enable bits are read-only */
1499 mask |= 0x3000;
1500 /* Duplex mode setting is read-only */
1501 mask |= 0x0100;
1502 }
1503
1504 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1505
1506 s->BasicModeCtrl = val;
1507 }
1508
1509 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1510 {
1511 uint32_t ret = s->BasicModeCtrl;
1512
1513 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1514
1515 return ret;
1516 }
1517
1518 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1519 {
1520 val &= 0xffff;
1521
1522 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1523
1524 /* mask unwritable bits */
1525 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1526
1527 s->BasicModeStatus = val;
1528 }
1529
1530 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1531 {
1532 uint32_t ret = s->BasicModeStatus;
1533
1534 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1535
1536 return ret;
1537 }
1538
1539 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1540 {
1541 val &= 0xff;
1542
1543 DPRINTF("Cfg9346 write val=0x%02x\n", val);
1544
1545 /* mask unwritable bits */
1546 val = SET_MASKED(val, 0x31, s->Cfg9346);
1547
1548 uint32_t opmode = val & 0xc0;
1549 uint32_t eeprom_val = val & 0xf;
1550
1551 if (opmode == 0x80) {
1552 /* eeprom access */
1553 int eecs = (eeprom_val & 0x08)?1:0;
1554 int eesk = (eeprom_val & 0x04)?1:0;
1555 int eedi = (eeprom_val & 0x02)?1:0;
1556 prom9346_set_wire(s, eecs, eesk, eedi);
1557 } else if (opmode == 0x40) {
1558 /* Reset. */
1559 val = 0;
1560 rtl8139_reset(&s->dev.qdev);
1561 }
1562
1563 s->Cfg9346 = val;
1564 }
1565
1566 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1567 {
1568 uint32_t ret = s->Cfg9346;
1569
1570 uint32_t opmode = ret & 0xc0;
1571
1572 if (opmode == 0x80)
1573 {
1574 /* eeprom access */
1575 int eedo = prom9346_get_wire(s);
1576 if (eedo)
1577 {
1578 ret |= 0x01;
1579 }
1580 else
1581 {
1582 ret &= ~0x01;
1583 }
1584 }
1585
1586 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1587
1588 return ret;
1589 }
1590
1591 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1592 {
1593 val &= 0xff;
1594
1595 DPRINTF("Config0 write val=0x%02x\n", val);
1596
1597 if (!rtl8139_config_writable(s)) {
1598 return;
1599 }
1600
1601 /* mask unwritable bits */
1602 val = SET_MASKED(val, 0xf8, s->Config0);
1603
1604 s->Config0 = val;
1605 }
1606
1607 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1608 {
1609 uint32_t ret = s->Config0;
1610
1611 DPRINTF("Config0 read val=0x%02x\n", ret);
1612
1613 return ret;
1614 }
1615
1616 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1617 {
1618 val &= 0xff;
1619
1620 DPRINTF("Config1 write val=0x%02x\n", val);
1621
1622 if (!rtl8139_config_writable(s)) {
1623 return;
1624 }
1625
1626 /* mask unwritable bits */
1627 val = SET_MASKED(val, 0xC, s->Config1);
1628
1629 s->Config1 = val;
1630 }
1631
1632 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1633 {
1634 uint32_t ret = s->Config1;
1635
1636 DPRINTF("Config1 read val=0x%02x\n", ret);
1637
1638 return ret;
1639 }
1640
1641 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1642 {
1643 val &= 0xff;
1644
1645 DPRINTF("Config3 write val=0x%02x\n", val);
1646
1647 if (!rtl8139_config_writable(s)) {
1648 return;
1649 }
1650
1651 /* mask unwritable bits */
1652 val = SET_MASKED(val, 0x8F, s->Config3);
1653
1654 s->Config3 = val;
1655 }
1656
1657 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1658 {
1659 uint32_t ret = s->Config3;
1660
1661 DPRINTF("Config3 read val=0x%02x\n", ret);
1662
1663 return ret;
1664 }
1665
1666 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1667 {
1668 val &= 0xff;
1669
1670 DPRINTF("Config4 write val=0x%02x\n", val);
1671
1672 if (!rtl8139_config_writable(s)) {
1673 return;
1674 }
1675
1676 /* mask unwritable bits */
1677 val = SET_MASKED(val, 0x0a, s->Config4);
1678
1679 s->Config4 = val;
1680 }
1681
1682 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1683 {
1684 uint32_t ret = s->Config4;
1685
1686 DPRINTF("Config4 read val=0x%02x\n", ret);
1687
1688 return ret;
1689 }
1690
1691 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1692 {
1693 val &= 0xff;
1694
1695 DPRINTF("Config5 write val=0x%02x\n", val);
1696
1697 /* mask unwritable bits */
1698 val = SET_MASKED(val, 0x80, s->Config5);
1699
1700 s->Config5 = val;
1701 }
1702
1703 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1704 {
1705 uint32_t ret = s->Config5;
1706
1707 DPRINTF("Config5 read val=0x%02x\n", ret);
1708
1709 return ret;
1710 }
1711
1712 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1713 {
1714 if (!rtl8139_transmitter_enabled(s))
1715 {
1716 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1717 return;
1718 }
1719
1720 DPRINTF("TxConfig write val=0x%08x\n", val);
1721
1722 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1723
1724 s->TxConfig = val;
1725 }
1726
1727 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1728 {
1729 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1730
1731 uint32_t tc = s->TxConfig;
1732 tc &= 0xFFFFFF00;
1733 tc |= (val & 0x000000FF);
1734 rtl8139_TxConfig_write(s, tc);
1735 }
1736
1737 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1738 {
1739 uint32_t ret = s->TxConfig;
1740
1741 DPRINTF("TxConfig read val=0x%04x\n", ret);
1742
1743 return ret;
1744 }
1745
1746 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1747 {
1748 DPRINTF("RxConfig write val=0x%08x\n", val);
1749
1750 /* mask unwritable bits */
1751 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1752
1753 s->RxConfig = val;
1754
1755 /* reset buffer size and read/write pointers */
1756 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1757
1758 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1759 }
1760
1761 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1762 {
1763 uint32_t ret = s->RxConfig;
1764
1765 DPRINTF("RxConfig read val=0x%08x\n", ret);
1766
1767 return ret;
1768 }
1769
1770 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1771 int do_interrupt, const uint8_t *dot1q_buf)
1772 {
1773 struct iovec *iov = NULL;
1774
1775 if (!size)
1776 {
1777 DPRINTF("+++ empty ethernet frame\n");
1778 return;
1779 }
1780
1781 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1782 iov = (struct iovec[3]) {
1783 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1784 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1785 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1786 .iov_len = size - ETHER_ADDR_LEN * 2 },
1787 };
1788 }
1789
1790 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1791 {
1792 size_t buf2_size;
1793 uint8_t *buf2;
1794
1795 if (iov) {
1796 buf2_size = iov_size(iov, 3);
1797 buf2 = qemu_malloc(buf2_size);
1798 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1799 buf = buf2;
1800 }
1801
1802 DPRINTF("+++ transmit loopback mode\n");
1803 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
1804
1805 if (iov) {
1806 qemu_free(buf2);
1807 }
1808 }
1809 else
1810 {
1811 if (iov) {
1812 qemu_sendv_packet(&s->nic->nc, iov, 3);
1813 } else {
1814 qemu_send_packet(&s->nic->nc, buf, size);
1815 }
1816 }
1817 }
1818
1819 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1820 {
1821 if (!rtl8139_transmitter_enabled(s))
1822 {
1823 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1824 "disabled\n", descriptor);
1825 return 0;
1826 }
1827
1828 if (s->TxStatus[descriptor] & TxHostOwns)
1829 {
1830 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1831 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
1832 return 0;
1833 }
1834
1835 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1836
1837 int txsize = s->TxStatus[descriptor] & 0x1fff;
1838 uint8_t txbuffer[0x2000];
1839
1840 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1841 txsize, s->TxAddr[descriptor]);
1842
1843 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1844
1845 /* Mark descriptor as transferred */
1846 s->TxStatus[descriptor] |= TxHostOwns;
1847 s->TxStatus[descriptor] |= TxStatOK;
1848
1849 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
1850
1851 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1852 descriptor);
1853
1854 /* update interrupt */
1855 s->IntrStatus |= TxOK;
1856 rtl8139_update_irq(s);
1857
1858 return 1;
1859 }
1860
1861 /* structures and macros for task offloading */
1862 typedef struct ip_header
1863 {
1864 uint8_t ip_ver_len; /* version and header length */
1865 uint8_t ip_tos; /* type of service */
1866 uint16_t ip_len; /* total length */
1867 uint16_t ip_id; /* identification */
1868 uint16_t ip_off; /* fragment offset field */
1869 uint8_t ip_ttl; /* time to live */
1870 uint8_t ip_p; /* protocol */
1871 uint16_t ip_sum; /* checksum */
1872 uint32_t ip_src,ip_dst; /* source and dest address */
1873 } ip_header;
1874
1875 #define IP_HEADER_VERSION_4 4
1876 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1877 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1878
1879 typedef struct tcp_header
1880 {
1881 uint16_t th_sport; /* source port */
1882 uint16_t th_dport; /* destination port */
1883 uint32_t th_seq; /* sequence number */
1884 uint32_t th_ack; /* acknowledgement number */
1885 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1886 uint16_t th_win; /* window */
1887 uint16_t th_sum; /* checksum */
1888 uint16_t th_urp; /* urgent pointer */
1889 } tcp_header;
1890
1891 typedef struct udp_header
1892 {
1893 uint16_t uh_sport; /* source port */
1894 uint16_t uh_dport; /* destination port */
1895 uint16_t uh_ulen; /* udp length */
1896 uint16_t uh_sum; /* udp checksum */
1897 } udp_header;
1898
1899 typedef struct ip_pseudo_header
1900 {
1901 uint32_t ip_src;
1902 uint32_t ip_dst;
1903 uint8_t zeros;
1904 uint8_t ip_proto;
1905 uint16_t ip_payload;
1906 } ip_pseudo_header;
1907
1908 #define IP_PROTO_TCP 6
1909 #define IP_PROTO_UDP 17
1910
1911 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1912 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1913 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1914
1915 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1916
1917 #define TCP_FLAG_FIN 0x01
1918 #define TCP_FLAG_PUSH 0x08
1919
1920 /* produces ones' complement sum of data */
1921 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1922 {
1923 uint32_t result = 0;
1924
1925 for (; len > 1; data+=2, len-=2)
1926 {
1927 result += *(uint16_t*)data;
1928 }
1929
1930 /* add the remainder byte */
1931 if (len)
1932 {
1933 uint8_t odd[2] = {*data, 0};
1934 result += *(uint16_t*)odd;
1935 }
1936
1937 while (result>>16)
1938 result = (result & 0xffff) + (result >> 16);
1939
1940 return result;
1941 }
1942
1943 static uint16_t ip_checksum(void *data, size_t len)
1944 {
1945 return ~ones_complement_sum((uint8_t*)data, len);
1946 }
1947
1948 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1949 {
1950 if (!rtl8139_transmitter_enabled(s))
1951 {
1952 DPRINTF("+++ C+ mode: transmitter disabled\n");
1953 return 0;
1954 }
1955
1956 if (!rtl8139_cp_transmitter_enabled(s))
1957 {
1958 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1959 return 0 ;
1960 }
1961
1962 int descriptor = s->currCPlusTxDesc;
1963
1964 target_phys_addr_t cplus_tx_ring_desc =
1965 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1966
1967 /* Normal priority ring */
1968 cplus_tx_ring_desc += 16 * descriptor;
1969
1970 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1971 "%08x0x%08x = 0x"TARGET_FMT_plx"\n", descriptor, s->TxAddr[1],
1972 s->TxAddr[0], cplus_tx_ring_desc);
1973
1974 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1975
1976 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1977 txdw0 = le32_to_cpu(val);
1978 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1979 txdw1 = le32_to_cpu(val);
1980 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1981 txbufLO = le32_to_cpu(val);
1982 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1983 txbufHI = le32_to_cpu(val);
1984
1985 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1986 txdw0, txdw1, txbufLO, txbufHI);
1987
1988 /* w0 ownership flag */
1989 #define CP_TX_OWN (1<<31)
1990 /* w0 end of ring flag */
1991 #define CP_TX_EOR (1<<30)
1992 /* first segment of received packet flag */
1993 #define CP_TX_FS (1<<29)
1994 /* last segment of received packet flag */
1995 #define CP_TX_LS (1<<28)
1996 /* large send packet flag */
1997 #define CP_TX_LGSEN (1<<27)
1998 /* large send MSS mask, bits 16...25 */
1999 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
2000
2001 /* IP checksum offload flag */
2002 #define CP_TX_IPCS (1<<18)
2003 /* UDP checksum offload flag */
2004 #define CP_TX_UDPCS (1<<17)
2005 /* TCP checksum offload flag */
2006 #define CP_TX_TCPCS (1<<16)
2007
2008 /* w0 bits 0...15 : buffer size */
2009 #define CP_TX_BUFFER_SIZE (1<<16)
2010 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
2011 /* w1 add tag flag */
2012 #define CP_TX_TAGC (1<<17)
2013 /* w1 bits 0...15 : VLAN tag (big endian) */
2014 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2015 /* w2 low 32bit of Rx buffer ptr */
2016 /* w3 high 32bit of Rx buffer ptr */
2017
2018 /* set after transmission */
2019 /* FIFO underrun flag */
2020 #define CP_TX_STATUS_UNF (1<<25)
2021 /* transmit error summary flag, valid if set any of three below */
2022 #define CP_TX_STATUS_TES (1<<23)
2023 /* out-of-window collision flag */
2024 #define CP_TX_STATUS_OWC (1<<22)
2025 /* link failure flag */
2026 #define CP_TX_STATUS_LNKF (1<<21)
2027 /* excessive collisions flag */
2028 #define CP_TX_STATUS_EXC (1<<20)
2029
2030 if (!(txdw0 & CP_TX_OWN))
2031 {
2032 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
2033 return 0 ;
2034 }
2035
2036 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
2037
2038 if (txdw0 & CP_TX_FS)
2039 {
2040 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2041 "descriptor\n", descriptor);
2042
2043 /* reset internal buffer offset */
2044 s->cplus_txbuffer_offset = 0;
2045 }
2046
2047 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
2048 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
2049
2050 /* make sure we have enough space to assemble the packet */
2051 if (!s->cplus_txbuffer)
2052 {
2053 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2054 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
2055 s->cplus_txbuffer_offset = 0;
2056
2057 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2058 s->cplus_txbuffer_len);
2059 }
2060
2061 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2062 {
2063 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2064 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
2065
2066 DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
2067 s->cplus_txbuffer_len);
2068 }
2069
2070 if (!s->cplus_txbuffer)
2071 {
2072 /* out of memory */
2073
2074 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2075 s->cplus_txbuffer_len);
2076
2077 /* update tally counter */
2078 ++s->tally_counters.TxERR;
2079 ++s->tally_counters.TxAbt;
2080
2081 return 0;
2082 }
2083
2084 /* append more data to the packet */
2085
2086 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2087 TARGET_FMT_plx" to offset %d\n", txsize, tx_addr,
2088 s->cplus_txbuffer_offset);
2089
2090 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2091 s->cplus_txbuffer_offset += txsize;
2092
2093 /* seek to next Rx descriptor */
2094 if (txdw0 & CP_TX_EOR)
2095 {
2096 s->currCPlusTxDesc = 0;
2097 }
2098 else
2099 {
2100 ++s->currCPlusTxDesc;
2101 if (s->currCPlusTxDesc >= 64)
2102 s->currCPlusTxDesc = 0;
2103 }
2104
2105 /* transfer ownership to target */
2106 txdw0 &= ~CP_RX_OWN;
2107
2108 /* reset error indicator bits */
2109 txdw0 &= ~CP_TX_STATUS_UNF;
2110 txdw0 &= ~CP_TX_STATUS_TES;
2111 txdw0 &= ~CP_TX_STATUS_OWC;
2112 txdw0 &= ~CP_TX_STATUS_LNKF;
2113 txdw0 &= ~CP_TX_STATUS_EXC;
2114
2115 /* update ring data */
2116 val = cpu_to_le32(txdw0);
2117 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2118
2119 /* Now decide if descriptor being processed is holding the last segment of packet */
2120 if (txdw0 & CP_TX_LS)
2121 {
2122 uint8_t dot1q_buffer_space[VLAN_HLEN];
2123 uint16_t *dot1q_buffer;
2124
2125 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2126 descriptor);
2127
2128 /* can transfer fully assembled packet */
2129
2130 uint8_t *saved_buffer = s->cplus_txbuffer;
2131 int saved_size = s->cplus_txbuffer_offset;
2132 int saved_buffer_len = s->cplus_txbuffer_len;
2133
2134 /* create vlan tag */
2135 if (txdw1 & CP_TX_TAGC) {
2136 /* the vlan tag is in BE byte order in the descriptor
2137 * BE + le_to_cpu() + ~swap()~ = cpu */
2138 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2139 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
2140
2141 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2142 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2143 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2144 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2145 } else {
2146 dot1q_buffer = NULL;
2147 }
2148
2149 /* reset the card space to protect from recursive call */
2150 s->cplus_txbuffer = NULL;
2151 s->cplus_txbuffer_offset = 0;
2152 s->cplus_txbuffer_len = 0;
2153
2154 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2155 {
2156 DPRINTF("+++ C+ mode offloaded task checksum\n");
2157
2158 /* ip packet header */
2159 ip_header *ip = NULL;
2160 int hlen = 0;
2161 uint8_t ip_protocol = 0;
2162 uint16_t ip_data_len = 0;
2163
2164 uint8_t *eth_payload_data = NULL;
2165 size_t eth_payload_len = 0;
2166
2167 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2168 if (proto == ETH_P_IP)
2169 {
2170 DPRINTF("+++ C+ mode has IP packet\n");
2171
2172 /* not aligned */
2173 eth_payload_data = saved_buffer + ETH_HLEN;
2174 eth_payload_len = saved_size - ETH_HLEN;
2175
2176 ip = (ip_header*)eth_payload_data;
2177
2178 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2179 DPRINTF("+++ C+ mode packet has bad IP version %d "
2180 "expected %d\n", IP_HEADER_VERSION(ip),
2181 IP_HEADER_VERSION_4);
2182 ip = NULL;
2183 } else {
2184 hlen = IP_HEADER_LENGTH(ip);
2185 ip_protocol = ip->ip_p;
2186 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2187 }
2188 }
2189
2190 if (ip)
2191 {
2192 if (txdw0 & CP_TX_IPCS)
2193 {
2194 DPRINTF("+++ C+ mode need IP checksum\n");
2195
2196 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2197 /* bad packet header len */
2198 /* or packet too short */
2199 }
2200 else
2201 {
2202 ip->ip_sum = 0;
2203 ip->ip_sum = ip_checksum(ip, hlen);
2204 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2205 hlen, ip->ip_sum);
2206 }
2207 }
2208
2209 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2210 {
2211 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2212
2213 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2214 "frame data %d specified MSS=%d\n", ETH_MTU,
2215 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2216
2217 int tcp_send_offset = 0;
2218 int send_count = 0;
2219
2220 /* maximum IP header length is 60 bytes */
2221 uint8_t saved_ip_header[60];
2222
2223 /* save IP header template; data area is used in tcp checksum calculation */
2224 memcpy(saved_ip_header, eth_payload_data, hlen);
2225
2226 /* a placeholder for checksum calculation routine in tcp case */
2227 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2228 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2229
2230 /* pointer to TCP header */
2231 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2232
2233 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2234
2235 /* ETH_MTU = ip header len + tcp header len + payload */
2236 int tcp_data_len = ip_data_len - tcp_hlen;
2237 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2238
2239 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2240 "data len %d TCP chunk size %d\n", ip_data_len,
2241 tcp_hlen, tcp_data_len, tcp_chunk_size);
2242
2243 /* note the cycle below overwrites IP header data,
2244 but restores it from saved_ip_header before sending packet */
2245
2246 int is_last_frame = 0;
2247
2248 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2249 {
2250 uint16_t chunk_size = tcp_chunk_size;
2251
2252 /* check if this is the last frame */
2253 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2254 {
2255 is_last_frame = 1;
2256 chunk_size = tcp_data_len - tcp_send_offset;
2257 }
2258
2259 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2260 be32_to_cpu(p_tcp_hdr->th_seq));
2261
2262 /* add 4 TCP pseudoheader fields */
2263 /* copy IP source and destination fields */
2264 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2265
2266 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2267 "packet with %d bytes data\n", tcp_hlen +
2268 chunk_size);
2269
2270 if (tcp_send_offset)
2271 {
2272 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2273 }
2274
2275 /* keep PUSH and FIN flags only for the last frame */
2276 if (!is_last_frame)
2277 {
2278 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2279 }
2280
2281 /* recalculate TCP checksum */
2282 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2283 p_tcpip_hdr->zeros = 0;
2284 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2285 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2286
2287 p_tcp_hdr->th_sum = 0;
2288
2289 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2290 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2291 tcp_checksum);
2292
2293 p_tcp_hdr->th_sum = tcp_checksum;
2294
2295 /* restore IP header */
2296 memcpy(eth_payload_data, saved_ip_header, hlen);
2297
2298 /* set IP data length and recalculate IP checksum */
2299 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2300
2301 /* increment IP id for subsequent frames */
2302 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2303
2304 ip->ip_sum = 0;
2305 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2306 DPRINTF("+++ C+ mode TSO IP header len=%d "
2307 "checksum=%04x\n", hlen, ip->ip_sum);
2308
2309 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2310 DPRINTF("+++ C+ mode TSO transferring packet size "
2311 "%d\n", tso_send_size);
2312 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2313 0, (uint8_t *) dot1q_buffer);
2314
2315 /* add transferred count to TCP sequence number */
2316 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2317 ++send_count;
2318 }
2319
2320 /* Stop sending this frame */
2321 saved_size = 0;
2322 }
2323 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2324 {
2325 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2326
2327 /* maximum IP header length is 60 bytes */
2328 uint8_t saved_ip_header[60];
2329 memcpy(saved_ip_header, eth_payload_data, hlen);
2330
2331 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2332 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2333
2334 /* add 4 TCP pseudoheader fields */
2335 /* copy IP source and destination fields */
2336 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2337
2338 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2339 {
2340 DPRINTF("+++ C+ mode calculating TCP checksum for "
2341 "packet with %d bytes data\n", ip_data_len);
2342
2343 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2344 p_tcpip_hdr->zeros = 0;
2345 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2346 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2347
2348 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2349
2350 p_tcp_hdr->th_sum = 0;
2351
2352 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2353 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2354 tcp_checksum);
2355
2356 p_tcp_hdr->th_sum = tcp_checksum;
2357 }
2358 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2359 {
2360 DPRINTF("+++ C+ mode calculating UDP checksum for "
2361 "packet with %d bytes data\n", ip_data_len);
2362
2363 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2364 p_udpip_hdr->zeros = 0;
2365 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2366 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2367
2368 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2369
2370 p_udp_hdr->uh_sum = 0;
2371
2372 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2373 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2374 udp_checksum);
2375
2376 p_udp_hdr->uh_sum = udp_checksum;
2377 }
2378
2379 /* restore IP header */
2380 memcpy(eth_payload_data, saved_ip_header, hlen);
2381 }
2382 }
2383 }
2384
2385 /* update tally counter */
2386 ++s->tally_counters.TxOk;
2387
2388 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2389
2390 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2391 (uint8_t *) dot1q_buffer);
2392
2393 /* restore card space if there was no recursion and reset offset */
2394 if (!s->cplus_txbuffer)
2395 {
2396 s->cplus_txbuffer = saved_buffer;
2397 s->cplus_txbuffer_len = saved_buffer_len;
2398 s->cplus_txbuffer_offset = 0;
2399 }
2400 else
2401 {
2402 qemu_free(saved_buffer);
2403 }
2404 }
2405 else
2406 {
2407 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2408 }
2409
2410 return 1;
2411 }
2412
2413 static void rtl8139_cplus_transmit(RTL8139State *s)
2414 {
2415 int txcount = 0;
2416
2417 while (rtl8139_cplus_transmit_one(s))
2418 {
2419 ++txcount;
2420 }
2421
2422 /* Mark transfer completed */
2423 if (!txcount)
2424 {
2425 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2426 s->currCPlusTxDesc);
2427 }
2428 else
2429 {
2430 /* update interrupt status */
2431 s->IntrStatus |= TxOK;
2432 rtl8139_update_irq(s);
2433 }
2434 }
2435
2436 static void rtl8139_transmit(RTL8139State *s)
2437 {
2438 int descriptor = s->currTxDesc, txcount = 0;
2439
2440 /*while*/
2441 if (rtl8139_transmit_one(s, descriptor))
2442 {
2443 ++s->currTxDesc;
2444 s->currTxDesc %= 4;
2445 ++txcount;
2446 }
2447
2448 /* Mark transfer completed */
2449 if (!txcount)
2450 {
2451 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2452 s->currTxDesc);
2453 }
2454 }
2455
2456 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2457 {
2458
2459 int descriptor = txRegOffset/4;
2460
2461 /* handle C+ transmit mode register configuration */
2462
2463 if (s->cplus_enabled)
2464 {
2465 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2466 "descriptor=%d\n", txRegOffset, val, descriptor);
2467
2468 /* handle Dump Tally Counters command */
2469 s->TxStatus[descriptor] = val;
2470
2471 if (descriptor == 0 && (val & 0x8))
2472 {
2473 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2474
2475 /* dump tally counters to specified memory location */
2476 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2477
2478 /* mark dump completed */
2479 s->TxStatus[0] &= ~0x8;
2480 }
2481
2482 return;
2483 }
2484
2485 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2486 txRegOffset, val, descriptor);
2487
2488 /* mask only reserved bits */
2489 val &= ~0xff00c000; /* these bits are reset on write */
2490 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2491
2492 s->TxStatus[descriptor] = val;
2493
2494 /* attempt to start transmission */
2495 rtl8139_transmit(s);
2496 }
2497
2498 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2499 {
2500 uint32_t ret = s->TxStatus[txRegOffset/4];
2501
2502 DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
2503
2504 return ret;
2505 }
2506
2507 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2508 {
2509 uint16_t ret = 0;
2510
2511 /* Simulate TSAD, it is read only anyway */
2512
2513 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2514 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2515 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2516 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2517
2518 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2519 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2520 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2521 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2522
2523 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2524 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2525 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2526 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2527
2528 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2529 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2530 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2531 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2532
2533
2534 DPRINTF("TSAD read val=0x%04x\n", ret);
2535
2536 return ret;
2537 }
2538
2539 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2540 {
2541 uint16_t ret = s->CSCR;
2542
2543 DPRINTF("CSCR read val=0x%04x\n", ret);
2544
2545 return ret;
2546 }
2547
2548 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2549 {
2550 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2551
2552 s->TxAddr[txAddrOffset/4] = val;
2553 }
2554
2555 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2556 {
2557 uint32_t ret = s->TxAddr[txAddrOffset/4];
2558
2559 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2560
2561 return ret;
2562 }
2563
2564 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2565 {
2566 DPRINTF("RxBufPtr write val=0x%04x\n", val);
2567
2568 /* this value is off by 16 */
2569 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2570
2571 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2572 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2573 }
2574
2575 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2576 {
2577 /* this value is off by 16 */
2578 uint32_t ret = s->RxBufPtr - 0x10;
2579
2580 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2581
2582 return ret;
2583 }
2584
2585 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2586 {
2587 /* this value is NOT off by 16 */
2588 uint32_t ret = s->RxBufAddr;
2589
2590 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2591
2592 return ret;
2593 }
2594
2595 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2596 {
2597 DPRINTF("RxBuf write val=0x%08x\n", val);
2598
2599 s->RxBuf = val;
2600
2601 /* may need to reset rxring here */
2602 }
2603
2604 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2605 {
2606 uint32_t ret = s->RxBuf;
2607
2608 DPRINTF("RxBuf read val=0x%08x\n", ret);
2609
2610 return ret;
2611 }
2612
2613 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2614 {
2615 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2616
2617 /* mask unwritable bits */
2618 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2619
2620 s->IntrMask = val;
2621
2622 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2623 rtl8139_update_irq(s);
2624
2625 }
2626
2627 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2628 {
2629 uint32_t ret = s->IntrMask;
2630
2631 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2632
2633 return ret;
2634 }
2635
2636 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2637 {
2638 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2639
2640 #if 0
2641
2642 /* writing to ISR has no effect */
2643
2644 return;
2645
2646 #else
2647 uint16_t newStatus = s->IntrStatus & ~val;
2648
2649 /* mask unwritable bits */
2650 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2651
2652 /* writing 1 to interrupt status register bit clears it */
2653 s->IntrStatus = 0;
2654 rtl8139_update_irq(s);
2655
2656 s->IntrStatus = newStatus;
2657 /*
2658 * Computing if we miss an interrupt here is not that correct but
2659 * considered that we should have had already an interrupt
2660 * and probably emulated is slower is better to assume this resetting was
2661 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2662 */
2663 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2664 rtl8139_update_irq(s);
2665
2666 #endif
2667 }
2668
2669 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2670 {
2671 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2672
2673 uint32_t ret = s->IntrStatus;
2674
2675 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2676
2677 #if 0
2678
2679 /* reading ISR clears all interrupts */
2680 s->IntrStatus = 0;
2681
2682 rtl8139_update_irq(s);
2683
2684 #endif
2685
2686 return ret;
2687 }
2688
2689 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2690 {
2691 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2692
2693 /* mask unwritable bits */
2694 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2695
2696 s->MultiIntr = val;
2697 }
2698
2699 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2700 {
2701 uint32_t ret = s->MultiIntr;
2702
2703 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2704
2705 return ret;
2706 }
2707
2708 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2709 {
2710 RTL8139State *s = opaque;
2711
2712 addr &= 0xff;
2713
2714 switch (addr)
2715 {
2716 case MAC0 ... MAC0+5:
2717 s->phys[addr - MAC0] = val;
2718 break;
2719 case MAC0+6 ... MAC0+7:
2720 /* reserved */
2721 break;
2722 case MAR0 ... MAR0+7:
2723 s->mult[addr - MAR0] = val;
2724 break;
2725 case ChipCmd:
2726 rtl8139_ChipCmd_write(s, val);
2727 break;
2728 case Cfg9346:
2729 rtl8139_Cfg9346_write(s, val);
2730 break;
2731 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2732 rtl8139_TxConfig_writeb(s, val);
2733 break;
2734 case Config0:
2735 rtl8139_Config0_write(s, val);
2736 break;
2737 case Config1:
2738 rtl8139_Config1_write(s, val);
2739 break;
2740 case Config3:
2741 rtl8139_Config3_write(s, val);
2742 break;
2743 case Config4:
2744 rtl8139_Config4_write(s, val);
2745 break;
2746 case Config5:
2747 rtl8139_Config5_write(s, val);
2748 break;
2749 case MediaStatus:
2750 /* ignore */
2751 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2752 val);
2753 break;
2754
2755 case HltClk:
2756 DPRINTF("HltClk write val=0x%08x\n", val);
2757 if (val == 'R')
2758 {
2759 s->clock_enabled = 1;
2760 }
2761 else if (val == 'H')
2762 {
2763 s->clock_enabled = 0;
2764 }
2765 break;
2766
2767 case TxThresh:
2768 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2769 s->TxThresh = val;
2770 break;
2771
2772 case TxPoll:
2773 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2774 if (val & (1 << 7))
2775 {
2776 DPRINTF("C+ TxPoll high priority transmission (not "
2777 "implemented)\n");
2778 //rtl8139_cplus_transmit(s);
2779 }
2780 if (val & (1 << 6))
2781 {
2782 DPRINTF("C+ TxPoll normal priority transmission\n");
2783 rtl8139_cplus_transmit(s);
2784 }
2785
2786 break;
2787
2788 default:
2789 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2790 val);
2791 break;
2792 }
2793 }
2794
2795 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2796 {
2797 RTL8139State *s = opaque;
2798
2799 addr &= 0xfe;
2800
2801 switch (addr)
2802 {
2803 case IntrMask:
2804 rtl8139_IntrMask_write(s, val);
2805 break;
2806
2807 case IntrStatus:
2808 rtl8139_IntrStatus_write(s, val);
2809 break;
2810
2811 case MultiIntr:
2812 rtl8139_MultiIntr_write(s, val);
2813 break;
2814
2815 case RxBufPtr:
2816 rtl8139_RxBufPtr_write(s, val);
2817 break;
2818
2819 case BasicModeCtrl:
2820 rtl8139_BasicModeCtrl_write(s, val);
2821 break;
2822 case BasicModeStatus:
2823 rtl8139_BasicModeStatus_write(s, val);
2824 break;
2825 case NWayAdvert:
2826 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2827 s->NWayAdvert = val;
2828 break;
2829 case NWayLPAR:
2830 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2831 break;
2832 case NWayExpansion:
2833 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2834 s->NWayExpansion = val;
2835 break;
2836
2837 case CpCmd:
2838 rtl8139_CpCmd_write(s, val);
2839 break;
2840
2841 case IntrMitigate:
2842 rtl8139_IntrMitigate_write(s, val);
2843 break;
2844
2845 default:
2846 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2847 addr, val);
2848
2849 rtl8139_io_writeb(opaque, addr, val & 0xff);
2850 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2851 break;
2852 }
2853 }
2854
2855 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2856 {
2857 int64_t pci_time, next_time;
2858 uint32_t low_pci;
2859
2860 DPRINTF("entered rtl8139_set_next_tctr_time\n");
2861
2862 if (s->TimerExpire && current_time >= s->TimerExpire) {
2863 s->IntrStatus |= PCSTimeout;
2864 rtl8139_update_irq(s);
2865 }
2866
2867 /* Set QEMU timer only if needed that is
2868 * - TimerInt <> 0 (we have a timer)
2869 * - mask = 1 (we want an interrupt timer)
2870 * - irq = 0 (irq is not already active)
2871 * If any of above change we need to compute timer again
2872 * Also we must check if timer is passed without QEMU timer
2873 */
2874 s->TimerExpire = 0;
2875 if (!s->TimerInt) {
2876 return;
2877 }
2878
2879 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2880 get_ticks_per_sec());
2881 low_pci = pci_time & 0xffffffff;
2882 pci_time = pci_time - low_pci + s->TimerInt;
2883 if (low_pci >= s->TimerInt) {
2884 pci_time += 0x100000000LL;
2885 }
2886 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2887 PCI_FREQUENCY);
2888 s->TimerExpire = next_time;
2889
2890 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2891 qemu_mod_timer(s->timer, next_time);
2892 }
2893 }
2894
2895 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2896 {
2897 RTL8139State *s = opaque;
2898
2899 addr &= 0xfc;
2900
2901 switch (addr)
2902 {
2903 case RxMissed:
2904 DPRINTF("RxMissed clearing on write\n");
2905 s->RxMissed = 0;
2906 break;
2907
2908 case TxConfig:
2909 rtl8139_TxConfig_write(s, val);
2910 break;
2911
2912 case RxConfig:
2913 rtl8139_RxConfig_write(s, val);
2914 break;
2915
2916 case TxStatus0 ... TxStatus0+4*4-1:
2917 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2918 break;
2919
2920 case TxAddr0 ... TxAddr0+4*4-1:
2921 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2922 break;
2923
2924 case RxBuf:
2925 rtl8139_RxBuf_write(s, val);
2926 break;
2927
2928 case RxRingAddrLO:
2929 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2930 s->RxRingAddrLO = val;
2931 break;
2932
2933 case RxRingAddrHI:
2934 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2935 s->RxRingAddrHI = val;
2936 break;
2937
2938 case Timer:
2939 DPRINTF("TCTR Timer reset on write\n");
2940 s->TCTR_base = qemu_get_clock_ns(vm_clock);
2941 rtl8139_set_next_tctr_time(s, s->TCTR_base);
2942 break;
2943
2944 case FlashReg:
2945 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2946 if (s->TimerInt != val) {
2947 s->TimerInt = val;
2948 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2949 }
2950 break;
2951
2952 default:
2953 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2954 addr, val);
2955 rtl8139_io_writeb(opaque, addr, val & 0xff);
2956 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2957 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2958 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2959 break;
2960 }
2961 }
2962
2963 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2964 {
2965 RTL8139State *s = opaque;
2966 int ret;
2967
2968 addr &= 0xff;
2969
2970 switch (addr)
2971 {
2972 case MAC0 ... MAC0+5:
2973 ret = s->phys[addr - MAC0];
2974 break;
2975 case MAC0+6 ... MAC0+7:
2976 ret = 0;
2977 break;
2978 case MAR0 ... MAR0+7:
2979 ret = s->mult[addr - MAR0];
2980 break;
2981 case ChipCmd:
2982 ret = rtl8139_ChipCmd_read(s);
2983 break;
2984 case Cfg9346:
2985 ret = rtl8139_Cfg9346_read(s);
2986 break;
2987 case Config0:
2988 ret = rtl8139_Config0_read(s);
2989 break;
2990 case Config1:
2991 ret = rtl8139_Config1_read(s);
2992 break;
2993 case Config3:
2994 ret = rtl8139_Config3_read(s);
2995 break;
2996 case Config4:
2997 ret = rtl8139_Config4_read(s);
2998 break;
2999 case Config5:
3000 ret = rtl8139_Config5_read(s);
3001 break;
3002
3003 case MediaStatus:
3004 ret = 0xd0;
3005 DPRINTF("MediaStatus read 0x%x\n", ret);
3006 break;
3007
3008 case HltClk:
3009 ret = s->clock_enabled;
3010 DPRINTF("HltClk read 0x%x\n", ret);
3011 break;
3012
3013 case PCIRevisionID:
3014 ret = RTL8139_PCI_REVID;
3015 DPRINTF("PCI Revision ID read 0x%x\n", ret);
3016 break;
3017
3018 case TxThresh:
3019 ret = s->TxThresh;
3020 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
3021 break;
3022
3023 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3024 ret = s->TxConfig >> 24;
3025 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
3026 break;
3027
3028 default:
3029 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
3030 ret = 0;
3031 break;
3032 }
3033
3034 return ret;
3035 }
3036
3037 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3038 {
3039 RTL8139State *s = opaque;
3040 uint32_t ret;
3041
3042 addr &= 0xfe; /* mask lower bit */
3043
3044 switch (addr)
3045 {
3046 case IntrMask:
3047 ret = rtl8139_IntrMask_read(s);
3048 break;
3049
3050 case IntrStatus:
3051 ret = rtl8139_IntrStatus_read(s);
3052 break;
3053
3054 case MultiIntr:
3055 ret = rtl8139_MultiIntr_read(s);
3056 break;
3057
3058 case RxBufPtr:
3059 ret = rtl8139_RxBufPtr_read(s);
3060 break;
3061
3062 case RxBufAddr:
3063 ret = rtl8139_RxBufAddr_read(s);
3064 break;
3065
3066 case BasicModeCtrl:
3067 ret = rtl8139_BasicModeCtrl_read(s);
3068 break;
3069 case BasicModeStatus:
3070 ret = rtl8139_BasicModeStatus_read(s);
3071 break;
3072 case NWayAdvert:
3073 ret = s->NWayAdvert;
3074 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3075 break;
3076 case NWayLPAR:
3077 ret = s->NWayLPAR;
3078 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3079 break;
3080 case NWayExpansion:
3081 ret = s->NWayExpansion;
3082 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3083 break;
3084
3085 case CpCmd:
3086 ret = rtl8139_CpCmd_read(s);
3087 break;
3088
3089 case IntrMitigate:
3090 ret = rtl8139_IntrMitigate_read(s);
3091 break;
3092
3093 case TxSummary:
3094 ret = rtl8139_TSAD_read(s);
3095 break;
3096
3097 case CSCR:
3098 ret = rtl8139_CSCR_read(s);
3099 break;
3100
3101 default:
3102 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3103
3104 ret = rtl8139_io_readb(opaque, addr);
3105 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3106
3107 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3108 break;
3109 }
3110
3111 return ret;
3112 }
3113
3114 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3115 {
3116 RTL8139State *s = opaque;
3117 uint32_t ret;
3118
3119 addr &= 0xfc; /* also mask low 2 bits */
3120
3121 switch (addr)
3122 {
3123 case RxMissed:
3124 ret = s->RxMissed;
3125
3126 DPRINTF("RxMissed read val=0x%08x\n", ret);
3127 break;
3128
3129 case TxConfig:
3130 ret = rtl8139_TxConfig_read(s);
3131 break;
3132
3133 case RxConfig:
3134 ret = rtl8139_RxConfig_read(s);
3135 break;
3136
3137 case TxStatus0 ... TxStatus0+4*4-1:
3138 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3139 break;
3140
3141 case TxAddr0 ... TxAddr0+4*4-1:
3142 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3143 break;
3144
3145 case RxBuf:
3146 ret = rtl8139_RxBuf_read(s);
3147 break;
3148
3149 case RxRingAddrLO:
3150 ret = s->RxRingAddrLO;
3151 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3152 break;
3153
3154 case RxRingAddrHI:
3155 ret = s->RxRingAddrHI;
3156 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3157 break;
3158
3159 case Timer:
3160 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
3161 PCI_FREQUENCY, get_ticks_per_sec());
3162 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3163 break;
3164
3165 case FlashReg:
3166 ret = s->TimerInt;
3167 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3168 break;
3169
3170 default:
3171 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3172
3173 ret = rtl8139_io_readb(opaque, addr);
3174 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3175 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3176 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3177
3178 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3179 break;
3180 }
3181
3182 return ret;
3183 }
3184
3185 /* */
3186
3187 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3188 {
3189 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3190 }
3191
3192 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3193 {
3194 rtl8139_io_writew(opaque, addr & 0xFF, val);
3195 }
3196
3197 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3198 {
3199 rtl8139_io_writel(opaque, addr & 0xFF, val);
3200 }
3201
3202 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3203 {
3204 return rtl8139_io_readb(opaque, addr & 0xFF);
3205 }
3206
3207 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3208 {
3209 return rtl8139_io_readw(opaque, addr & 0xFF);
3210 }
3211
3212 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3213 {
3214 return rtl8139_io_readl(opaque, addr & 0xFF);
3215 }
3216
3217 /* */
3218
3219 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3220 {
3221 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3222 }
3223
3224 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3225 {
3226 rtl8139_io_writew(opaque, addr & 0xFF, val);
3227 }
3228
3229 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3230 {
3231 rtl8139_io_writel(opaque, addr & 0xFF, val);
3232 }
3233
3234 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3235 {
3236 return rtl8139_io_readb(opaque, addr & 0xFF);
3237 }
3238
3239 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3240 {
3241 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3242 return val;
3243 }
3244
3245 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3246 {
3247 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3248 return val;
3249 }
3250
3251 static int rtl8139_post_load(void *opaque, int version_id)
3252 {
3253 RTL8139State* s = opaque;
3254 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3255 if (version_id < 4) {
3256 s->cplus_enabled = s->CpCmd != 0;
3257 }
3258
3259 return 0;
3260 }
3261
3262 static bool rtl8139_hotplug_ready_needed(void *opaque)
3263 {
3264 return qdev_machine_modified();
3265 }
3266
3267 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3268 .name = "rtl8139/hotplug_ready",
3269 .version_id = 1,
3270 .minimum_version_id = 1,
3271 .minimum_version_id_old = 1,
3272 .fields = (VMStateField []) {
3273 VMSTATE_END_OF_LIST()
3274 }
3275 };
3276
3277 static void rtl8139_pre_save(void *opaque)
3278 {
3279 RTL8139State* s = opaque;
3280 int64_t current_time = qemu_get_clock_ns(vm_clock);
3281
3282 /* set IntrStatus correctly */
3283 rtl8139_set_next_tctr_time(s, current_time);
3284 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3285 get_ticks_per_sec());
3286 s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
3287 }
3288
3289 static const VMStateDescription vmstate_rtl8139 = {
3290 .name = "rtl8139",
3291 .version_id = 4,
3292 .minimum_version_id = 3,
3293 .minimum_version_id_old = 3,
3294 .post_load = rtl8139_post_load,
3295 .pre_save = rtl8139_pre_save,
3296 .fields = (VMStateField []) {
3297 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3298 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3299 VMSTATE_BUFFER(mult, RTL8139State),
3300 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3301 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3302
3303 VMSTATE_UINT32(RxBuf, RTL8139State),
3304 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3305 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3306 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3307
3308 VMSTATE_UINT16(IntrStatus, RTL8139State),
3309 VMSTATE_UINT16(IntrMask, RTL8139State),
3310
3311 VMSTATE_UINT32(TxConfig, RTL8139State),
3312 VMSTATE_UINT32(RxConfig, RTL8139State),
3313 VMSTATE_UINT32(RxMissed, RTL8139State),
3314 VMSTATE_UINT16(CSCR, RTL8139State),
3315
3316 VMSTATE_UINT8(Cfg9346, RTL8139State),
3317 VMSTATE_UINT8(Config0, RTL8139State),
3318 VMSTATE_UINT8(Config1, RTL8139State),
3319 VMSTATE_UINT8(Config3, RTL8139State),
3320 VMSTATE_UINT8(Config4, RTL8139State),
3321 VMSTATE_UINT8(Config5, RTL8139State),
3322
3323 VMSTATE_UINT8(clock_enabled, RTL8139State),
3324 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3325
3326 VMSTATE_UINT16(MultiIntr, RTL8139State),
3327
3328 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3329 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3330 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3331 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3332 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3333
3334 VMSTATE_UINT16(CpCmd, RTL8139State),
3335 VMSTATE_UINT8(TxThresh, RTL8139State),
3336
3337 VMSTATE_UNUSED(4),
3338 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3339 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3340
3341 VMSTATE_UINT32(currTxDesc, RTL8139State),
3342 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3343 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3344 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3345 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3346
3347 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3348 VMSTATE_INT32(eeprom.mode, RTL8139State),
3349 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3350 VMSTATE_UINT8(eeprom.address, RTL8139State),
3351 VMSTATE_UINT16(eeprom.input, RTL8139State),
3352 VMSTATE_UINT16(eeprom.output, RTL8139State),
3353
3354 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3355 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3356 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3357 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3358
3359 VMSTATE_UINT32(TCTR, RTL8139State),
3360 VMSTATE_UINT32(TimerInt, RTL8139State),
3361 VMSTATE_INT64(TCTR_base, RTL8139State),
3362
3363 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3364 vmstate_tally_counters, RTL8139TallyCounters),
3365
3366 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3367 VMSTATE_END_OF_LIST()
3368 },
3369 .subsections = (VMStateSubsection []) {
3370 {
3371 .vmsd = &vmstate_rtl8139_hotplug_ready,
3372 .needed = rtl8139_hotplug_ready_needed,
3373 }, {
3374 /* empty */
3375 }
3376 }
3377 };
3378
3379 /***********************************************************/
3380 /* PCI RTL8139 definitions */
3381
3382 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3383 pcibus_t addr, pcibus_t size, int type)
3384 {
3385 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
3386
3387 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3388 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3389
3390 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3391 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3392
3393 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3394 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3395 }
3396
3397 static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
3398 rtl8139_mmio_readb,
3399 rtl8139_mmio_readw,
3400 rtl8139_mmio_readl,
3401 };
3402
3403 static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
3404 rtl8139_mmio_writeb,
3405 rtl8139_mmio_writew,
3406 rtl8139_mmio_writel,
3407 };
3408
3409 static void rtl8139_timer(void *opaque)
3410 {
3411 RTL8139State *s = opaque;
3412
3413 if (!s->clock_enabled)
3414 {
3415 DPRINTF(">>> timer: clock is not running\n");
3416 return;
3417 }
3418
3419 s->IntrStatus |= PCSTimeout;
3420 rtl8139_update_irq(s);
3421 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3422 }
3423
3424 static void rtl8139_cleanup(VLANClientState *nc)
3425 {
3426 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
3427
3428 s->nic = NULL;
3429 }
3430
3431 static int pci_rtl8139_uninit(PCIDevice *dev)
3432 {
3433 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3434
3435 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
3436 if (s->cplus_txbuffer) {
3437 qemu_free(s->cplus_txbuffer);
3438 s->cplus_txbuffer = NULL;
3439 }
3440 qemu_del_timer(s->timer);
3441 qemu_free_timer(s->timer);
3442 qemu_del_vlan_client(&s->nic->nc);
3443 return 0;
3444 }
3445
3446 static NetClientInfo net_rtl8139_info = {
3447 .type = NET_CLIENT_TYPE_NIC,
3448 .size = sizeof(NICState),
3449 .can_receive = rtl8139_can_receive,
3450 .receive = rtl8139_receive,
3451 .cleanup = rtl8139_cleanup,
3452 };
3453
3454 static int pci_rtl8139_init(PCIDevice *dev)
3455 {
3456 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
3457 uint8_t *pci_conf;
3458
3459 pci_conf = s->dev.config;
3460 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3461 /* TODO: start of capability list, but no capability
3462 * list bit in status register, and offset 0xdc seems unused. */
3463 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3464
3465 /* I/O handler for memory-mapped I/O */
3466 s->rtl8139_mmio_io_addr =
3467 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
3468 DEVICE_LITTLE_ENDIAN);
3469
3470 pci_register_bar(&s->dev, 0, 0x100,
3471 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3472
3473 pci_register_bar_simple(&s->dev, 1, 0x100, 0, s->rtl8139_mmio_io_addr);
3474
3475 qemu_macaddr_default_if_unset(&s->conf.macaddr);
3476
3477 /* prepare eeprom */
3478 s->eeprom.contents[0] = 0x8129;
3479 #if 1
3480 /* PCI vendor and device ID should be mirrored here */
3481 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3482 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3483 #endif
3484 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3485 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3486 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3487
3488 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3489 dev->qdev.info->name, dev->qdev.id, s);
3490 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
3491
3492 s->cplus_txbuffer = NULL;
3493 s->cplus_txbuffer_len = 0;
3494 s->cplus_txbuffer_offset = 0;
3495
3496 s->TimerExpire = 0;
3497 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3498 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3499
3500 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3501
3502 return 0;
3503 }
3504
3505 static PCIDeviceInfo rtl8139_info = {
3506 .qdev.name = "rtl8139",
3507 .qdev.size = sizeof(RTL8139State),
3508 .qdev.reset = rtl8139_reset,
3509 .qdev.vmsd = &vmstate_rtl8139,
3510 .init = pci_rtl8139_init,
3511 .exit = pci_rtl8139_uninit,
3512 .romfile = "pxe-rtl8139.rom",
3513 .vendor_id = PCI_VENDOR_ID_REALTEK,
3514 .device_id = PCI_DEVICE_ID_REALTEK_8139,
3515 .revision = RTL8139_PCI_REVID, /* >=0x20 is for 8139C+ */
3516 .class_id = PCI_CLASS_NETWORK_ETHERNET,
3517 .qdev.props = (Property[]) {
3518 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3519 DEFINE_PROP_END_OF_LIST(),
3520 }
3521 };
3522
3523 static void rtl8139_register_devices(void)
3524 {
3525 pci_qdev_register(&rtl8139_info);
3526 }
3527
3528 device_init(rtl8139_register_devices)
Stefan Hajnoczi's patches