2 * QEMU JZ Soc emulation
4 * Copyright (c) 2009 yajin (yajin@vm-kernel.org)
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * The emulation target is pavo demo board.
28 * http://www.ingenic.cn/eng/productServ/kfyd/Hardware/pffaqQuestionContent.aspx?Category=2&Question=3
35 #include "qemu-timer.h"
36 #include "qemu-char.h"
39 #include "audio/audio.h"
45 #define DEBUG /*global debug on/off */
47 #define DEBUG_CPM (1<<0x0)
48 #define DEBUG_EMC (1<<0x1)
49 #define DEBUG_GPIO (1<<0x2)
50 #define DEBUG_RTC (1<<0x3)
51 #define DEBUG_TCU (1<<0x4)
52 #define DEBUG_LCDC (1<<0x5)
53 #define DEBUG_DMA (1<<0x6)
54 #define DEBUG_FLAG 0//DEBUG_TCU// (DEBUG_CPM|DEBUG_EMC|DEBUG_GPIO \
55 // | DEBUG_RTC | DEBUG_TCU | DEBUG_LCDC | DEBUG_DMA)
60 static void debug_init(void)
62 fp
= fopen("jz4740.txt", "w+");
65 fprintf(stderr
, "can not open jz4740.txt \n");
69 static void debug_out(uint32_t flag
, const char *format
, ...)
74 if (flag
& DEBUG_FLAG
)
77 vfprintf(fp
, format
, ap
);
84 static void debug_init(void)
87 static void debug_out(uint32_t flag
, const char *format
, ...)
92 uint32_t jz4740_badwidth_read8(void *opaque
, target_phys_addr_t addr
)
97 cpu_physical_memory_read(addr
, (void *) &ret
, 1);
101 void jz4740_badwidth_write8(void *opaque
, target_phys_addr_t addr
,
104 uint8_t val8
= value
;
107 cpu_physical_memory_write(addr
, (void *) &val8
, 1);
110 uint32_t jz4740_badwidth_read16(void *opaque
, target_phys_addr_t addr
)
113 JZ4740_16B_REG(addr
);
114 cpu_physical_memory_read(addr
, (void *) &ret
, 2);
118 void jz4740_badwidth_write16(void *opaque
, target_phys_addr_t addr
,
121 uint16_t val16
= value
;
123 JZ4740_16B_REG(addr
);
124 cpu_physical_memory_write(addr
, (void *) &val16
, 2);
127 uint32_t jz4740_badwidth_read32(void *opaque
, target_phys_addr_t addr
)
131 JZ4740_32B_REG(addr
);
132 cpu_physical_memory_read(addr
, (void *) &ret
, 4);
136 void jz4740_badwidth_write32(void *opaque
, target_phys_addr_t addr
,
139 JZ4740_32B_REG(addr
);
140 cpu_physical_memory_write(addr
, (void *) &value
, 4);
144 /*clock reset and power control*/
147 target_phys_addr_t base
;
148 struct jz_state_s
*soc
;
164 static void jz4740_dump_clocks(jz_clk parent
)
168 debug_out(DEBUG_CPM
, "clock %s rate %d \n", i
->name
, i
->rate
);
169 for (i
= i
->child1
; i
; i
= i
->sibling
)
170 jz4740_dump_clocks(i
);
173 static inline void jz4740_cpccr_update(struct jz4740_cpm_s
*s
,
176 uint32_t ldiv
, mdiv
, pdiv
, hdiv
, cdiv
, udiv
;
177 uint32_t div_table
[10] = {
178 1, 2, 3, 4, 6, 8, 12, 16, 24, 32
181 if (unlikely(new_value
== s
->cpccr
))
184 if (new_value
& CPM_CPCCR_PCS
)
185 jz_clk_setrate(jz_findclk(s
->soc
, "pll_divider"), 1, 1);
187 jz_clk_setrate(jz_findclk(s
->soc
, "pll_divider"), 2, 1);
190 ldiv
= (new_value
& CPM_CPCCR_LDIV_MASK
) >> CPM_CPCCR_LDIV_BIT
;
193 mdiv
= div_table
[(new_value
& CPM_CPCCR_MDIV_MASK
) >> CPM_CPCCR_MDIV_BIT
];
194 pdiv
= div_table
[(new_value
& CPM_CPCCR_PDIV_MASK
) >> CPM_CPCCR_PDIV_BIT
];
195 hdiv
= div_table
[(new_value
& CPM_CPCCR_HDIV_MASK
) >> CPM_CPCCR_HDIV_BIT
];
196 cdiv
= div_table
[(new_value
& CPM_CPCCR_CDIV_MASK
) >> CPM_CPCCR_CDIV_BIT
];
197 udiv
= div_table
[(new_value
& CPM_CPCCR_UDIV_MASK
) >> CPM_CPCCR_UDIV_BIT
];
199 jz_clk_setrate(jz_findclk(s
->soc
, "ldclk"), ldiv
, 1);
200 jz_clk_setrate(jz_findclk(s
->soc
, "mclk"), mdiv
, 1);
201 jz_clk_setrate(jz_findclk(s
->soc
, "pclk"), pdiv
, 1);
202 jz_clk_setrate(jz_findclk(s
->soc
, "hclk"), hdiv
, 1);
203 jz_clk_setrate(jz_findclk(s
->soc
, "cclk"), cdiv
, 1);
204 jz_clk_setrate(jz_findclk(s
->soc
, "usbclk"), udiv
, 1);
206 if (new_value
& CPM_CPCCR_UCS
)
207 jz_clk_reparent(jz_findclk(s
->soc
, "usbclk"),
208 jz_findclk(s
->soc
, "pll_divider"));
210 jz_clk_reparent(jz_findclk(s
->soc
, "usbclk"),
211 jz_findclk(s
->soc
, "osc_extal"));
213 if (new_value
& CPM_CPCCR_I2CS
)
214 jz_clk_reparent(jz_findclk(s
->soc
, "i2sclk"),
215 jz_findclk(s
->soc
, "pll_divider"));
217 jz_clk_reparent(jz_findclk(s
->soc
, "i2sclk"),
218 jz_findclk(s
->soc
, "osc_extal"));
220 s
->cpccr
= new_value
;
222 debug_out(DEBUG_CPM
, "write to cpccr 0x%x\n", new_value
);
223 jz4740_dump_clocks(jz_findclk(s
->soc
, "osc_extal"));
227 static inline void jz4740_cppcr_update(struct jz4740_cpm_s
*s
,
230 uint32_t pllm
, plln
, pllod
, pllbp
, pllen
;
236 pllen
= new_value
& CPM_CPPCR_PLLEN
;
237 pllbp
= new_value
& CPM_CPPCR_PLLBP
;
238 if ((!pllen
) || (pllen
&& pllbp
))
240 jz_clk_setrate(jz_findclk(s
->soc
, "pll_output"), 1, 1);
241 debug_out(DEBUG_CPM
, "pll is bypassed \n");
242 s
->cppcr
= new_value
| CPM_CPPCR_PLLS
;
247 pllm
= (new_value
& CPM_CPPCR_PLLM_MASK
) >> CPM_CPPCR_PLLM_BIT
;
248 plln
= (new_value
& CPM_CPPCR_PLLN_MASK
) >> CPM_CPPCR_PLLN_BIT
;
249 pllod
= (new_value
& CPM_CPPCR_PLLOD_MASK
) >> CPM_CPPCR_PLLOD_BIT
;
250 jz_clk_setrate(jz_findclk(s
->soc
, "pll_output"), (plln
+ 2) * pll0
[pllod
],
253 s
->cppcr
= new_value
;
255 debug_out(DEBUG_CPM
, "write to cppcr 0x%x\n", new_value
);
256 jz4740_dump_clocks(jz_findclk(s
->soc
, "osc_extal"));
260 static inline void jz4740_i2scdr_update(struct jz4740_cpm_s
*s
,
265 i2scdr
= new_value
& CPM_I2SCDR_I2SDIV_MASK
;
266 if (unlikely(i2scdr
== s
->i2scdr
))
270 jz_clk_setrate(jz_findclk(s
->soc
, "i2sclk"), i2scdr
+ 1, 1);
274 debug_out(DEBUG_CPM
, "write to i2scdr 0x%x\n", new_value
);
275 jz4740_dump_clocks(jz_findclk(s
->soc
, "osc_extal"));
279 static inline void jz4740_lpcdr_update(struct jz4740_cpm_s
*s
,
284 ipcdr
= new_value
& CPM_LPCDR_PIXDIV_MASK
;
289 static inline void jz4740_msccdr_update(struct jz4740_cpm_s
*s
,
294 msccdr
= new_value
& CPM_MSCCDR_MSCDIV_MASK
;
296 if (unlikely(msccdr
== s
->msccdr
))
300 jz_clk_setrate(jz_findclk(s
->soc
, "mscclk"), msccdr
+ 1, 1);
304 debug_out(DEBUG_CPM
, "write to msccdr 0x%x\n", new_value
);
305 jz4740_dump_clocks(jz_findclk(s
->soc
, "osc_extal"));
309 static inline void jz4740_uhccdr_update(struct jz4740_cpm_s
*s
,
314 uhccdr
= new_value
& 0xf;
319 static void jz4740_cpm_write(void *opaque
, target_phys_addr_t addr
,
322 struct jz4740_cpm_s
*s
= (struct jz4740_cpm_s
*) opaque
;
327 jz4740_cpccr_update(s
, value
);
330 s
->lcr
= value
& 0xff;
333 s
->clkgr
= value
& 0xffff;
336 s
->scr
= value
& 0xffff;
339 jz4740_cppcr_update(s
, value
);
342 jz4740_i2scdr_update(s
, value
);
345 jz4740_lpcdr_update(s
, value
);
348 jz4740_msccdr_update(s
, value
);
351 jz4740_uhccdr_update(s
, value
);
354 s
->uhctst
= value
& 0x3f;
357 s
->ssicdr
= value
& 0xf;
360 cpu_abort(s
->soc
->env
,
361 "jz4740_cpm_write undefined addr " JZ_FMT_plx
362 " value %x \n", addr
, value
);
368 static uint32_t jz474_cpm_read(void *opaque
, target_phys_addr_t addr
)
370 struct jz4740_cpm_s
*s
= (struct jz4740_cpm_s
*) opaque
;
397 cpu_abort(s
->soc
->env
,
398 "jz474_cpm_read undefined addr " JZ_FMT_plx
" \n", addr
);
405 static CPUReadMemoryFunc
*jz4740_cpm_readfn
[] = {
406 jz4740_badwidth_read32
, jz4740_badwidth_read32
, jz474_cpm_read
,
409 static CPUWriteMemoryFunc
*jz4740_cpm_writefn
[] = {
410 jz4740_badwidth_write32
, jz4740_badwidth_write32
, jz4740_cpm_write
,
413 static void jz4740_cpm_reset(struct jz4740_cpm_s
*s
)
415 s
->cpccr
= 0x42040000;
416 s
->cppcr
= 0x28080011;
417 s
->i2scdr
= 0x00000004;
418 s
->lpcdr
= 0x00000004;
419 s
->msccdr
= 0x00000004;
420 s
->uhccdr
= 0x00000004;
422 s
->ssicdr
= 0x00000004;
429 static struct jz4740_cpm_s
*jz4740_cpm_init(struct jz_state_s
*soc
)
432 struct jz4740_cpm_s
*s
= (struct jz4740_cpm_s
*) qemu_mallocz(sizeof(*s
));
433 s
->base
= JZ4740_PHYS_BASE(JZ4740_CPM_BASE
);
439 cpu_register_io_memory(0, jz4740_cpm_readfn
, jz4740_cpm_writefn
, s
);
440 cpu_register_physical_memory(s
->base
, 0x00001000, iomemtype
);
445 /* JZ4740 interrupt controller
446 * It issues INT2 to MIPS
452 target_phys_addr_t base
;
453 struct jz_state_s
*soc
;
462 static uint32_t jz4740_intc_read(void *opaque
, target_phys_addr_t addr
)
464 struct jz4740_intc_s
*s
= (struct jz4740_intc_s
*) opaque
;
479 cpu_abort(s
->soc
->env
,
480 "jz4740_intc_read undefined addr " JZ_FMT_plx
" \n", addr
);
486 static void jz4740_intc_write(void *opaque
, target_phys_addr_t addr
,
489 struct jz4740_intc_s
*s
= (struct jz4740_intc_s
*) opaque
;
509 cpu_abort(s
->soc
->env
,
510 "jz4740_intc_write undefined addr " JZ_FMT_plx
511 " value %x \n", addr
, value
);
516 static CPUReadMemoryFunc
*jz4740_intc_readfn
[] = {
517 jz4740_badwidth_read32
, jz4740_badwidth_read32
, jz4740_intc_read
,
520 static CPUWriteMemoryFunc
*jz4740_intc_writefn
[] = {
521 jz4740_badwidth_write32
, jz4740_badwidth_write32
, jz4740_intc_write
,
524 static void jz4740_intc_reset(struct jz4740_intc_s
*s
)
527 s
->icmr
= 0xffffffff;
531 static void jz4740_set_irq(void *opaque
, int irq
, int level
)
533 struct jz4740_intc_s
*s
= (struct jz4740_intc_s
*) opaque
;
534 uint32_t irq_mask
= 1 << irq
;
536 s
->icpr
&= ~irq_mask
;
540 //printf("s->icmr %x \n",s->icmr);
541 if (!(s
->icmr
& irq_mask
))
544 qemu_set_irq(s
->parent_irq
, 1);
548 qemu_set_irq(s
->parent_irq
, 0);
551 static qemu_irq
*jz4740_intc_init(struct jz_state_s
*soc
, qemu_irq parent_irq
)
554 struct jz4740_intc_s
*s
= (struct jz4740_intc_s
*) qemu_mallocz(sizeof(*s
));
555 s
->base
= JZ4740_PHYS_BASE(JZ4740_INTC_BASE
);
556 s
->parent_irq
= parent_irq
;
559 jz4740_intc_reset(s
);
562 cpu_register_io_memory(0, jz4740_intc_readfn
, jz4740_intc_writefn
, s
);
563 cpu_register_physical_memory(s
->base
, 0x00001000, iomemtype
);
564 return qemu_allocate_irqs(jz4740_set_irq
, s
, 32);
567 /*external memory controller*/
571 target_phys_addr_t base
;
572 struct jz_state_s
*soc
;
575 uint32_t smcr1
; /*0x13010014 */
576 uint32_t smcr2
; /*0x13010018 */
577 uint32_t smcr3
; /*0x1301001c */
578 uint32_t smcr4
; /*0x13010020 */
579 uint32_t sacr1
; /*0x13010034 */
580 uint32_t sacr2
; /*0x13010038 */
581 uint32_t sacr3
; /*0x1301003c */
582 uint32_t sacr4
; /*0x13010040 */
584 uint32_t nfcsr
; /*0x13010050 */
585 uint32_t nfeccr
; /*0x13010100 */
586 uint32_t nfecc
; /*0x13010104 */
587 uint32_t nfpar0
; /*0x13010108 */
588 uint32_t nfpar1
; /*0x1301010c */
589 uint32_t nfpar2
; /*0x13010110 */
590 uint32_t nfints
; /*0x13010114 */
591 uint32_t nfinte
; /*0x13010118 */
592 uint32_t nferr0
; /*0x1301011c */
593 uint32_t nferr1
; /*0x13010120 */
594 uint32_t nferr2
; /*0x13010124 */
595 uint32_t nferr3
; /*0x13010128 */
597 uint32_t dmcr
; /*0x13010080 */
598 uint32_t rtcsr
; /*0x13010084 */
599 uint32_t rtcnt
; /*0x13010088 */
600 uint32_t rtcor
; /*0x1301008c */
601 uint32_t dmar
; /*0x13010090 */
602 uint32_t sdmr
; /*0x1301a000 */
607 static void jz4740_emc_reset(struct jz4740_emc_s
*s
)
609 s
->smcr1
= 0xfff7700;
610 s
->smcr2
= 0xfff7700;
611 s
->smcr3
= 0xfff7700;
612 s
->smcr4
= 0xfff7700;
640 static uint32_t jz4740_emc_read8(void *opaque
, target_phys_addr_t addr
)
642 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
650 return (s
->nfpar0
>> ((addr
- 0x108) * 8)) & 0xff;
655 return (s
->nfpar1
>> ((addr
- 0x10c) * 8)) & 0xff;
660 return (s
->nfpar2
>> ((addr
- 0x110) * 8)) & 0xff;
665 return (s
->sdmr
>> ((addr
- 0xa000) * 8)) & 0xff;
667 cpu_abort(s
->soc
->env
,
668 "jz4740_emc_read8 undefined addr " JZ_FMT_plx
" \n", addr
);
675 static uint32_t jz4740_emc_read16(void *opaque
, target_phys_addr_t addr
)
677 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
683 return (s
->nfpar0
>> ((addr
- 0x108) * 8)) & 0xffff;
686 return (s
->nfpar1
>> ((addr
- 0x10c) * 8)) & 0xffff;
689 return (s
->nfpar2
>> ((addr
- 0x110) * 8)) & 0xffff;
692 return (s
->nferr0
>> ((addr
- 0x11c) * 8)) & 0xffff;
695 return (s
->nferr1
>> ((addr
- 0x120) * 8)) & 0xffff;
698 return (s
->nferr2
>> ((addr
- 0x124) * 8)) & 0xffff;
701 return (s
->nferr3
>> ((addr
- 0x128) * 8)) & 0xffff;
703 cpu_abort(s
->soc
->env
,
704 "jz4740_emc_read16 undefined addr " JZ_FMT_plx
" \n", addr
);
709 static uint32_t jz4740_emc_read32(void *opaque
, target_phys_addr_t addr
)
711 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
762 cpu_abort(s
->soc
->env
,
763 "jz4740_emc_read32 undefined addr " JZ_FMT_plx
" \n", addr
);
768 static void jz4740_emc_write8(void *opaque
, target_phys_addr_t addr
,
771 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
773 debug_out(DEBUG_EMC
, "jz4740_emc_write8 addr %x value %x\n", addr
, value
);
781 s
->nfpar0
|= (value
& 0xff) << ((addr
- 0x108) * 8);
787 s
->nfpar1
|= (value
& 0xff) << ((addr
- 0x10c) * 8);
793 s
->nfpar2
|= (value
& 0xff) << ((addr
- 0x110) * 8);
795 case 0xa000 ... 0xa3ff:
798 cpu_abort(s
->soc
->env
,
799 "jz4740_emc_write8 undefined addr " JZ_FMT_plx
800 " value %x \n", addr
, value
);
803 static void jz4740_emc_write16(void *opaque
, target_phys_addr_t addr
,
806 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
808 debug_out(DEBUG_EMC
, "jz4740_emc_write16 addr %x value %x\n", addr
, value
);
813 s
->nfpar0
|= (value
& 0xffff) << ((addr
- 0x108) * 8);
817 s
->nfpar1
|= (value
& 0xffff) << ((addr
- 0x10c) * 8);
821 s
->nfpar2
|= (value
& 0xffff) << ((addr
- 0x110) * 8);
825 s
->rtcsr
|= (value
& 0xffff) << ((addr
- 0x84) * 8);
829 s
->rtcnt
|= (value
& 0xffff) << ((addr
- 0x88) * 8);
832 s
->rtcor
|= (value
& 0xffff) << ((addr
- 0x8c) * 8);
835 cpu_abort(s
->soc
->env
,
836 "jz4740_emc_write16 undefined addr " JZ_FMT_plx
837 " value %x \n", addr
, value
);
841 static void jz4740_emc_upate_interrupt(struct jz4740_emc_s
*s
)
843 qemu_set_irq(s
->irq
, s
->nfints
& s
->nfinte
);
846 static void jz4740_emc_write32(void *opaque
, target_phys_addr_t addr
,
849 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
851 debug_out(DEBUG_EMC
, "jz4740_emc_write32 addr %x value %x\n", addr
, value
);
865 s
->smcr1
= value
& 0xfff77cf;
868 s
->smcr2
= value
& 0xfff77cf;
871 s
->smcr3
= value
& 0xfff77cf;
874 s
->smcr4
= value
& 0xfff77cf;
877 s
->sacr1
= value
& 0xffff;
880 s
->sacr2
= value
& 0xffff;
883 s
->sacr3
= value
& 0xffff;
886 s
->sacr4
= value
& 0xffff;
889 s
->nfcsr
= value
& 0xffff;
892 s
->nfeccr
= value
& 0x1f;
907 /*TODO: Real RS error correction */
910 if ((s
->nfeccr
& 0x10) && (!(s
->nfeccr
& 0x8)))
922 s
->nfpar0
= 0xffffffff; /*fake value. for debug */
923 s
->nfpar1
= 0xffffffff; /*fake value */
924 s
->nfpar2
= 0xff; /*fake value */
931 jz4740_emc_upate_interrupt(s
);
940 s
->nfpar2
= value
& 0xff;
943 s
->nfints
= value
& 0x1fffffff;
944 jz4740_emc_upate_interrupt(s
);
947 s
->nfinte
= value
& 0x1f;
948 jz4740_emc_upate_interrupt(s
);
951 s
->dmcr
= value
& 0x9fbeff7f;
954 s
->dmar
= value
& 0xffff;
957 cpu_abort(s
->soc
->env
,
958 "jz4740_emc_write32 undefined addr " JZ_FMT_plx
959 " value %x \n", addr
, value
);
965 static CPUReadMemoryFunc
*jz4740_emc_readfn
[] = {
966 jz4740_emc_read8
, jz4740_emc_read16
, jz4740_emc_read32
,
969 static CPUWriteMemoryFunc
*jz4740_emc_writefn
[] = {
970 jz4740_emc_write8
, jz4740_emc_write16
, jz4740_emc_write32
,
974 static struct jz4740_emc_s
*jz4740_emc_init(struct jz_state_s
*soc
,
978 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) qemu_mallocz(sizeof(*s
));
979 s
->base
= JZ4740_PHYS_BASE(JZ4740_EMC_BASE
);
986 cpu_register_io_memory(0, jz4740_emc_readfn
, jz4740_emc_writefn
, s
);
987 cpu_register_physical_memory(s
->base
, 0x00010000, iomemtype
);
995 target_phys_addr_t base
;
996 struct jz_state_s
*soc
;
1009 static void jz4740_gpio_reset(struct jz4740_gpio_s
*s
)
1011 memset(s
->papin
, 0x0, sizeof(s
->papin
));
1012 memset(s
->padat
, 0x0, sizeof(s
->padat
));
1013 memset(s
->paim
, 0xffffffff, sizeof(s
->paim
));
1014 memset(s
->pape
, 0x0, sizeof(s
->pape
));
1015 memset(s
->pafun
, 0x0, sizeof(s
->pafun
));
1016 memset(s
->pasel
, 0x0, sizeof(s
->pasel
));
1017 memset(s
->padir
, 0x0, sizeof(s
->padir
));
1018 memset(s
->patrg
, 0x0, sizeof(s
->patrg
));
1019 memset(s
->paflg
, 0x0, sizeof(s
->paflg
));
1022 static uint32_t jz4740_gpio_read(void *opaque
, target_phys_addr_t addr
)
1024 struct jz4740_gpio_s
*s
= (struct jz4740_gpio_s
*) opaque
;
1026 debug_out(DEBUG_GPIO
, "jz4740_gpio_read addr %x\n", addr
);
1090 JZ4740_WO_REG(addr
);
1097 group
= (addr
- 0x0) / 0x100;
1100 /*GPIO(C) PIN 30 -> NAND FLASH R/B. */
1101 /*FOR NAND FLASH.PIN 30 ----|_____|------ */
1102 s
->papin
[2] &= 0x40000000;
1104 s
->papin
[2] &= ~0x40000000;
1106 s
->papin
[2] |= 0x40000000;
1108 return s
->papin
[group
];
1113 group
= (addr
- 0x10) / 0x100;
1114 return s
->padat
[group
];
1119 group
= (addr
- 0x20) / 0x100;
1120 return s
->paim
[group
];
1125 group
= (addr
- 0x30) / 0x100;
1126 return s
->pape
[group
];
1131 group
= (addr
- 0x40) / 0x100;
1132 return s
->pafun
[group
];
1137 group
= (addr
- 0x50) / 0x100;
1138 return s
->pasel
[group
];
1143 group
= (addr
- 0x60) / 0x100;
1144 return s
->padir
[group
];
1149 group
= (addr
- 0x70) / 0x100;
1150 return s
->patrg
[group
];
1155 group
= (addr
- 0x80) / 0x100;
1156 return s
->paflg
[group
];
1158 cpu_abort(s
->soc
->env
,
1159 "jz4740_gpio_read undefined addr " JZ_FMT_plx
" \n", addr
);
1164 static void jz4740_gpio_write(void *opaque
, target_phys_addr_t addr
,
1167 struct jz4740_gpio_s
*s
= (struct jz4740_gpio_s
*) opaque
;
1170 debug_out(DEBUG_GPIO
, "jz4740_gpio_write addr %x value %x\n", addr
, value
);
1210 JZ4740_RO_REG(addr
);
1216 group
= (addr
- 0x14) / 0x100;
1217 s
->padat
[group
] = value
;
1223 group
= (addr
- 0x18) / 0x100;
1224 s
->padat
[group
] &= ~value
;
1230 group
= (addr
- 0x24) / 0x100;
1231 s
->paim
[group
] = value
;
1237 group
= (addr
- 0x28) / 0x100;
1238 s
->paim
[group
] &= ~value
;
1244 group
= (addr
- 0x34) / 0x100;
1245 s
->pape
[group
] = value
;
1251 group
= (addr
- 0x38) / 0x100;
1252 s
->pape
[group
] &= ~value
;
1258 group
= (addr
- 0x44) / 0x100;
1259 s
->pafun
[group
] = value
;
1265 group
= (addr
- 0x48) / 0x100;
1266 s
->pafun
[group
] &= ~value
;
1272 group
= (addr
- 0x54) / 0x100;
1273 s
->pasel
[group
] = value
;
1279 group
= (addr
- 0x58) / 0x100;
1280 s
->pasel
[group
] &= ~value
;
1286 group
= (addr
- 0x64) / 0x100;
1287 s
->padir
[group
] = value
;
1293 group
= (addr
- 0x68) / 0x100;
1294 s
->padir
[group
] &= ~value
;
1300 group
= (addr
- 0x74) / 0x100;
1301 s
->patrg
[group
] = value
;
1307 group
= (addr
- 0x78) / 0x100;
1308 s
->patrg
[group
] &= ~value
;
1314 group
= (addr
- 0x74) / 0x100;
1315 s
->paflg
[group
] &= ~value
;
1318 cpu_abort(s
->soc
->env
,
1319 "jz4740_gpio_write undefined addr " JZ_FMT_plx
1320 " value %x \n", addr
, value
);
1328 static CPUReadMemoryFunc
*jz4740_gpio_readfn
[] = {
1329 jz4740_badwidth_read32
, jz4740_badwidth_read32
, jz4740_gpio_read
,
1332 static CPUWriteMemoryFunc
*jz4740_gpio_writefn
[] = {
1333 jz4740_badwidth_write32
, jz4740_badwidth_write32
, jz4740_gpio_write
,
1336 static struct jz4740_gpio_s
*jz4740_gpio_init(struct jz_state_s
*soc
,
1340 struct jz4740_gpio_s
*s
= (struct jz4740_gpio_s
*) qemu_mallocz(sizeof(*s
));
1341 s
->base
= JZ4740_PHYS_BASE(JZ4740_GPIO_BASE
);
1345 jz4740_gpio_reset(s
);
1348 cpu_register_io_memory(0, jz4740_gpio_readfn
, jz4740_gpio_writefn
, s
);
1349 cpu_register_physical_memory(s
->base
, 0x00010000, iomemtype
);
1357 target_phys_addr_t base
;
1358 struct jz_state_s
*soc
;
1380 static void jz4740_rtc_update_interrupt(struct jz4740_rtc_s
*s
)
1382 if (((s
->rtcsr
& 0x40) && (s
->rtcsr
& 0x20))
1383 || ((s
->rtcsr
& 0x10) && (s
->rtcsr
& 0x8)))
1384 qemu_set_irq(s
->irq
, 1);
1386 qemu_set_irq(s
->irq
, 0);
1389 static inline void jz4740_rtc_start(struct jz4740_rtc_s
*s
)
1391 s
->next
= +qemu_get_clock(rt_clock
);
1392 qemu_mod_timer(s
->hz_tm
, s
->next
);
1395 static inline void jz4740_rtc_stop(struct jz4740_rtc_s
*s
)
1397 qemu_del_timer(s
->hz_tm
);
1398 s
->next
= -qemu_get_clock(rt_clock
);
1403 static void jz4740_rtc_hz(void *opaque
)
1405 struct jz4740_rtc_s
*s
= (struct jz4740_rtc_s
*) opaque
;
1408 qemu_mod_timer(s
->hz_tm
, s
->next
);
1415 if (s
->rtcsr
== s
->rtcsar
)
1418 jz4740_rtc_update_interrupt(s
);
1422 static void jz4740_rtc_reset(struct jz4740_rtc_s
*s
)
1428 /*Maybe rtcsr need to be saved to file */
1430 //s->sec_offset = 0;
1431 //qemu_get_timedate(&s->tm, s->sec_offset);
1432 jz4740_rtc_start(s
);
1436 static uint32_t jz4740_rtc_read(void *opaque
, target_phys_addr_t addr
)
1438 struct jz4740_rtc_s
*s
= (struct jz4740_rtc_s
*) opaque
;
1440 debug_out(DEBUG_RTC
, "jz4740_rtc_read addr %x\n", addr
);
1444 return s
->rtccr
| 0x80;
1464 cpu_abort(s
->soc
->env
,
1465 "jz4740_rtc_read undefined addr " JZ_FMT_plx
"\n", addr
);
1471 static void jz4740_rtc_write(void *opaque
, target_phys_addr_t addr
,
1474 struct jz4740_rtc_s
*s
= (struct jz4740_rtc_s
*) opaque
;
1476 debug_out(DEBUG_RTC
, "jz4740_rtc_write addr %x value %x\n", addr
, value
);
1481 s
->rtccr
= value
& 0x2d;
1488 jz4740_rtc_start(s
);
1489 jz4740_rtc_update_interrupt(s
);
1494 //s->sec_offset = qemu_timedate_diff(&s->tm);
1500 s
->rtcgr
= value
& 0x13ffffff;
1503 s
->hcr
= value
& 0x1;
1506 s
->hwfcr
= value
& 0xffe0;
1509 s
->hrcr
= value
& 0xfe0;
1512 s
->hwcr
= value
& 0x1;
1515 s
->hwrsr
= value
& 0x33;
1521 cpu_abort(s
->soc
->env
,
1522 "jz4740_rtc_write undefined addr " JZ_FMT_plx
1523 " value %x \n", addr
, value
);
1528 static CPUReadMemoryFunc
*jz4740_rtc_readfn
[] = {
1529 jz4740_badwidth_read32
, jz4740_badwidth_read32
, jz4740_rtc_read
,
1532 static CPUWriteMemoryFunc
*jz4740_rtc_writefn
[] = {
1533 jz4740_badwidth_write32
, jz4740_badwidth_write32
, jz4740_rtc_write
,
1536 static struct jz4740_rtc_s
*jz4740_rtc_init(struct jz_state_s
*soc
,
1540 struct jz4740_rtc_s
*s
= (struct jz4740_rtc_s
*) qemu_mallocz(sizeof(*s
));
1541 s
->base
= JZ4740_PHYS_BASE(JZ4740_RTC_BASE
);
1545 s
->hz_tm
= qemu_new_timer(rt_clock
, jz4740_rtc_hz
, s
);
1547 jz4740_rtc_reset(s
);
1550 cpu_register_io_memory(0, jz4740_rtc_readfn
, jz4740_rtc_writefn
, s
);
1551 cpu_register_physical_memory(s
->base
, 0x00001000, iomemtype
);
1561 target_phys_addr_t base
;
1562 struct jz_state_s
*soc
;
1565 QEMUTimer
*half_timer
[8];
1566 QEMUTimer
*full_timer
[8];
1579 uint32_t prescale
[8];
1583 static void jz4740_tcu_update_interrupt(struct jz4740_tcu_s
*s
)
1585 //printf("s->tfr %x s->tmr %x \n",s->tfr,s->tmr);
1586 if (((s
->tfr
& 0x1) & (~(s
->tmr
& 0x1)))
1587 || ((s
->tfr
& 0x10000) & (~(s
->tmr
& 0x10000))))
1589 qemu_set_irq(s
->tcu_irq0
, 1);
1592 // qemu_set_irq(s->tcu_irq0, 0);
1594 if (((s
->tfr
& 0x2) & (~(s
->tmr
& 0x2)))
1595 || ((s
->tfr
& 0x20000) & (~(s
->tmr
& 0x20000))))
1597 qemu_set_irq(s
->tcu_irq1
, 1);
1600 qemu_set_irq(s
->tcu_irq1
, 0);
1602 if (((s
->tfr
& 0xfc) & (~(s
->tmr
& 0xfc)))
1603 || ((s
->tfr
& 0xfc0000) & (~(s
->tmr
& 0xfc0000))))
1605 qemu_set_irq(s
->tcu_irq2
, 1);
1608 qemu_set_irq(s
->tcu_irq2
, 0);
1614 #include "mips_jz_glue.h"
1616 #include "mips_jz_glue.h"
1618 #include "mips_jz_glue.h"
1620 #include "mips_jz_glue.h"
1622 #include "mips_jz_glue.h"
1624 #include "mips_jz_glue.h"
1626 #include "mips_jz_glue.h"
1628 #include "mips_jz_glue.h"
1631 #define jz4740_tcu_start(s) do { \
1632 jz4740_tcu_start_half0(s); \
1633 jz4740_tcu_start_full0(s); \
1634 jz4740_tcu_start_half1(s); \
1635 jz4740_tcu_start_full1(s); \
1636 jz4740_tcu_start_half2(s); \
1637 jz4740_tcu_start_full2(s); \
1638 jz4740_tcu_start_half3(s); \
1639 jz4740_tcu_start_full3(s); \
1640 jz4740_tcu_start_half4(s); \
1641 jz4740_tcu_start_full4(s); \
1642 jz4740_tcu_start_half5(s); \
1643 jz4740_tcu_start_full5(s); \
1644 jz4740_tcu_start_half6(s); \
1645 jz4740_tcu_start_full6(s); \
1646 jz4740_tcu_start_half7(s); \
1647 jz4740_tcu_start_full7(s); \
1650 static void jz4740_tcu_if_reset(struct jz4740_tcu_s
*s
)
1658 for (i
= 0; i
< 8; i
++)
1660 s
->tdfr
[i
] = 0xffff;
1661 s
->tdhr
[i
] = 0x8000;
1664 s
->half_timer
[i
] = NULL
;
1665 s
->full_timer
[i
] = NULL
;
1669 static void jz4740_tcu_if_write8(void *opaque
, target_phys_addr_t addr
,
1672 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) opaque
;
1674 debug_out(DEBUG_TCU
, "jz4740_tcu_if_write8 addr %x value %x\n", addr
,
1680 s
->ter
|= (value
& 0xff);
1681 jz4740_tcu_start(s
);
1684 s
->ter
&= ~(value
& 0xff);
1685 jz4740_tcu_start(s
);
1688 cpu_abort(s
->soc
->env
,
1689 "jz4740_tcu_if_write8 undefined addr " JZ_FMT_plx
1690 " value %x \n", addr
, value
);
1695 static void jz4740_tcu_if_write32(void *opaque
, target_phys_addr_t addr
,
1698 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) opaque
;
1700 debug_out(DEBUG_TCU
, "jz4740_tcu_if_write32 addr %x value %x\n", addr
,
1703 fprintf(fp
, "jz4740_tcu_if_write32 addr %x value %x\n", addr
,
1708 s
->tsr
|= (value
& 0x100ff);
1709 jz4740_tcu_start(s
);
1712 s
->tsr
&= ~(value
& 0x100ff);
1713 jz4740_tcu_start(s
);
1716 s
->tfr
|= (value
& 0xff00ff);
1719 s
->tfr
&= ~(value
& 0xff00ff);
1722 s
->tmr
|= (value
& 0xff00ff);
1723 jz4740_tcu_update_interrupt(s
);
1726 s
->tmr
&= ~(value
& 0xff00ff);
1727 jz4740_tcu_update_interrupt(s
);
1730 cpu_abort(s
->soc
->env
,
1731 "jz4740_tcu_if_write32 undefined addr " JZ_FMT_plx
1732 " value %x \n", addr
, value
);
1737 static uint32_t jz4740_tcu_if_read8(void *opaque
, target_phys_addr_t addr
)
1739 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) opaque
;
1741 debug_out(DEBUG_TCU
, "jz4740_tcu_if_read8 addr %x\n", addr
);
1748 cpu_abort(s
->soc
->env
,
1749 "jz4740_tcu_if_read8 undefined addr " JZ_FMT_plx
"\n", addr
);
1754 static uint32_t jz4740_tcu_if_read32(void *opaque
, target_phys_addr_t addr
)
1756 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) opaque
;
1758 debug_out(DEBUG_TCU
, "jz4740_tcu_if_read32 addr %x\n", addr
);
1769 cpu_abort(s
->soc
->env
,
1770 "jz4740_tcu_if_read32 undefined addr " JZ_FMT_plx
"\n", addr
);
1777 static CPUReadMemoryFunc
*jz4740_tcu_if_readfn
[] = {
1778 jz4740_tcu_if_read8
, jz4740_badwidth_read32
, jz4740_tcu_if_read32
,
1781 static CPUWriteMemoryFunc
*jz4740_tcu_if_writefn
[] = {
1782 jz4740_tcu_if_write8
, jz4740_badwidth_write32
, jz4740_tcu_if_write32
,
1785 static struct jz4740_tcu_s
*jz4740_tcu_if_init(struct jz_state_s
*soc
,
1793 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) qemu_mallocz(sizeof(*s
));
1794 s
->base
= JZ4740_PHYS_BASE(JZ4740_TCU_BASE
);
1796 s
->tcu_irq0
= tcu_irq0
;
1797 s
->tcu_irq1
= tcu_irq1
;
1798 s
->tcu_irq2
= tcu_irq2
;
1800 jz4740_tcu_if_reset(s
);
1803 cpu_register_io_memory(0, jz4740_tcu_if_readfn
, jz4740_tcu_if_writefn
,
1805 cpu_register_physical_memory(s
->base
, 0x00000040, iomemtype
);
1810 static void jz4740_tcu_init(struct jz_state_s
*soc
,
1811 struct jz4740_tcu_s
*s
, int timer_index
)
1813 switch (timer_index
)
1816 jz4740_tcu_init0(soc
, s
);
1819 jz4740_tcu_init1(soc
, s
);
1822 jz4740_tcu_init2(soc
, s
);
1825 jz4740_tcu_init3(soc
, s
);
1828 jz4740_tcu_init4(soc
, s
);
1831 jz4740_tcu_init5(soc
, s
);
1834 jz4740_tcu_init6(soc
, s
);
1837 jz4740_tcu_init7(soc
, s
);
1840 cpu_abort(s
->soc
->env
,
1841 "jz4740_tcu_init undefined timer %x \n", timer_index
);
1845 typedef void (*jz4740_lcd_fn_t
) (uint8_t * d
, const uint8_t * s
, int width
,
1846 const uint16_t * pal
);
1847 struct jz_fb_descriptor
1849 uint32_t fdadr
; /* Frame descriptor address register */
1850 uint32_t fsadr
; /* Frame source address register */
1851 uint32_t fidr
; /* Frame ID register */
1852 uint32_t ldcmd
; /* Command register */
1855 struct jz4740_lcdc_s
1859 target_phys_addr_t base
;
1860 struct jz_state_s
*soc
;
1862 DisplayState
*state
;
1863 QEMUConsole
*console
;
1864 jz4740_lcd_fn_t
*line_fn_tab
;
1865 jz4740_lcd_fn_t line_fn
;
1894 uint32_t bpp
; /*bit per second */
1895 uint16_t palette
[256];
1896 uint32_t invalidate
;
1901 static const int jz4740_lcd_bpp
[0x6] = {
1902 1, 2, 4, 8, 16, 32 /*4740 uses 32 bit for 24bpp */
1905 static void jz4740_lcdc_reset(struct jz4740_lcdc_s
*s
)
1910 static uint32_t jz4740_lcdc_read(void *opaque
, target_phys_addr_t addr
)
1912 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) opaque
;
1914 debug_out(DEBUG_LCDC
, "jz4740_lcdc_read addr %x \n", addr
);
1960 cpu_abort(s
->soc
->env
,
1961 "jz4740_lcdc_read undefined addr " JZ_FMT_plx
" \n", addr
);
1967 static void jz4740_lcdc_write(void *opaque
, target_phys_addr_t addr
,
1970 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) opaque
;
1972 debug_out(DEBUG_LCDC
, "jz4740_lcdc_write addr %x value %x\n", addr
, value
);
1979 JZ4740_RO_REG(addr
);
1982 s
->lcdcfg
= value
& 0x80ffffbf;
1985 s
->lcdvsync
= value
& 0x7ff07ff;
1988 s
->lcdhsync
= value
& 0x7ff07ff;
1991 s
->lcdvat
= value
& 0x7ff07ff;
1994 s
->lcddah
= value
& 0x7ff07ff;
1995 s
->width
= (value
& 0x7ff) - ((value
>> 16) & 0x7ff);
1998 s
->height
= (value
& 0x7ff) - ((value
>> 16) & 0x7ff);
1999 s
->lcddav
= value
& 0x7ff07ff;
2002 s
->lcdps
= value
& 0x7ff07ff;
2005 s
->lcdcls
= value
& 0x7ff07ff;
2008 s
->lcdspl
= value
& 0x7ff07ff;
2011 s
->lcdrev
= value
& 0x7ff0000;
2014 s
->lcdctrl
= value
& 0x3fff3fff;
2015 s
->ena
= (value
& 0x8) >> 3;
2016 s
->dis
= (value
& 0x10) >> 4;
2017 s
->bpp
= jz4740_lcd_bpp
[value
& 0x7];
2020 fprintf(stderr
, "bpp =1 is not supported\n");
2023 s
->line_fn
= s
->line_fn_tab
[value
& 0x7];
2026 s
->lcdstate
= value
& 0xbf;
2038 cpu_abort(s
->soc
->env
,
2039 "jz4740_lcdc_write undefined addr " JZ_FMT_plx
" value %x \n",
2045 static CPUReadMemoryFunc
*jz4740_lcdc_readfn
[] = {
2046 jz4740_badwidth_read32
, jz4740_badwidth_read32
, jz4740_lcdc_read
,
2049 static CPUWriteMemoryFunc
*jz4740_lcdc_writefn
[] = {
2050 jz4740_badwidth_write32
, jz4740_badwidth_write32
, jz4740_lcdc_write
,
2053 #include "pixel_ops.h"
2054 #define JZ4740_LCD_PANEL
2056 #include "mips_jz_glue.h"
2058 #include "mips_jz_glue.h"
2060 #include "mips_jz_glue.h"
2062 #include "mips_jz_glue.h"
2064 #include "mips_jz_glue.h"
2065 #undef JZ4740_LCD_PANEL
2067 static void *jz4740_lcd_get_buffer(struct jz4740_lcdc_s
*s
,
2068 target_phys_addr_t addr
)
2072 pd
= cpu_get_physical_page_desc(addr
);
2073 if ((pd
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2075 cpu_abort(cpu_single_env
, "%s: framebuffer outside RAM!\n",
2078 return phys_ram_base
+
2079 (pd
& TARGET_PAGE_MASK
) + (addr
& ~TARGET_PAGE_MASK
);
2082 static void jz4740_lcd_update_display(void *opaque
)
2084 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) opaque
;
2086 uint8_t *src
, *dest
;
2087 struct jz_fb_descriptor
*fb_des
;
2101 fb_des
= (struct jz_fb_descriptor
*) jz4740_lcd_get_buffer(s
, s
->lcdda0
);
2102 s
->lcdda0
= fb_des
->fdadr
;
2103 s
->lcdsa0
= fb_des
->fsadr
;
2104 s
->lcdfid0
= fb_des
->fidr
;
2105 s
->lcdcmd0
= fb_des
->ldcmd
;
2107 src
= (uint8_t *) jz4740_lcd_get_buffer(s
, fb_des
->fsadr
);
2108 if (s
->lcdcmd0
& (0x1 << 28))
2111 memcpy(s
->palette
, src
, sizeof(s
->palette
));
2117 if (s
->width
!= ds_get_width(s
->state
) ||
2118 s
->height
!= ds_get_height(s
->state
))
2120 qemu_console_resize(s
->console
, s
->width
, s
->height
);
2124 step
= (s
->width
* s
->bpp
) >> 3;
2125 dest
= ds_get_data(s
->state
);
2126 linesize
= ds_get_linesize(s
->state
);
2128 //printf("s->width %d s->height %d s->bpp %d linesize %d \n",s->width,s->height ,s->bpp,linesize);
2130 for (y
= 0; y
< s
->height
; y
++)
2132 s
->line_fn(dest
, src
, s
->width
, s
->palette
);
2133 //memcpy(dest,src,step);
2139 dpy_update(s
->state
, 0, 0, s
->width
, s
->height
);
2140 s
->lcdstate
|= 0x20;
2141 if ((s
->lcdcmd0
& 0x40000000) && (!(s
->lcdctrl
& 0x2000)))
2142 qemu_set_irq(s
->irq
, 1);
2145 static inline void jz4740_lcd_invalidate_display(void *opaque
)
2147 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) opaque
;
2151 static struct jz4740_lcdc_s
*jz4740_lcdc_init(struct jz_state_s
*soc
,
2152 qemu_irq irq
, DisplayState
* ds
)
2156 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) qemu_mallocz(sizeof(*s
));
2157 s
->base
= JZ4740_PHYS_BASE(JZ4740_LCD_BASE
);
2163 jz4740_lcdc_reset(s
);
2166 cpu_register_io_memory(0, jz4740_lcdc_readfn
, jz4740_lcdc_writefn
, s
);
2167 cpu_register_physical_memory(s
->base
, 0x10000, iomemtype
);
2169 s
->console
= graphic_console_init(s
->state
, jz4740_lcd_update_display
,
2170 jz4740_lcd_invalidate_display
,
2172 switch (ds_get_bits_per_pixel(s
->state
))
2175 s
->line_fn_tab
= qemu_mallocz(sizeof(jz4740_lcd_fn_t
) * 6);
2178 s
->line_fn_tab
= jz4740_lcd_draw_fn_8
;
2181 s
->line_fn_tab
= jz4740_lcd_draw_fn_15
;
2184 s
->line_fn_tab
= jz4740_lcd_draw_fn_16
;
2187 s
->line_fn_tab
= jz4740_lcd_draw_fn_24
;
2190 s
->line_fn_tab
= jz4740_lcd_draw_fn_32
;
2193 fprintf(stderr
, "%s: Bad color depth\n", __FUNCTION__
);
2201 #define JZ4740_DMA_NUM 6
2206 target_phys_addr_t base
;
2207 struct jz_state_s
*soc
;
2214 uint32_t dsa
[JZ4740_DMA_NUM
];
2215 uint32_t dta
[JZ4740_DMA_NUM
];
2216 uint32_t dtc
[JZ4740_DMA_NUM
];
2217 uint32_t drs
[JZ4740_DMA_NUM
];
2218 uint32_t dcs
[JZ4740_DMA_NUM
];
2219 uint32_t dcm
[JZ4740_DMA_NUM
];
2220 uint32_t dda
[JZ4740_DMA_NUM
];
2224 struct jz4740_desc_s
2226 uint32_t dcmd
; /* DCMD value for the current transfer */
2227 uint32_t dsadr
; /* DSAR value for the current transfer */
2228 uint32_t dtadr
; /* DTAR value for the current transfer */
2229 uint32_t ddadr
; /* Points to the next descriptor + transfer count */
2232 static inline void jz4740_dma_transfer(struct jz4740_dma_s
*s
,
2233 target_phys_addr_t src
,
2234 target_phys_addr_t dest
, uint32_t len
)
2236 uint32_t pd_src
, pd_dest
;
2239 pd_src
= cpu_get_physical_page_desc(src
);
2240 if ((pd_src
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2242 cpu_abort(cpu_single_env
, "%s: DMA source address %x outside RAM!\n",
2245 sr
= phys_ram_base
+
2246 (pd_src
& TARGET_PAGE_MASK
) + (src
& ~TARGET_PAGE_MASK
);
2248 pd_dest
= cpu_get_physical_page_desc(dest
);
2249 if ((pd_dest
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2251 cpu_abort(cpu_single_env
,
2252 "%s: DMA destination address %x outside RAM!\n",
2253 __FUNCTION__
, dest
);
2255 de
= phys_ram_base
+
2256 (pd_dest
& TARGET_PAGE_MASK
) + (dest
& ~TARGET_PAGE_MASK
);
2258 memcpy(de
, sr
, len
);
2261 static inline uint32_t jz4740_dma_unit_size(struct jz4740_dma_s
*s
,
2264 switch ((cmd
& 0x700) >> 8)
2281 /*No-descriptor transfer*/
2282 static inline void jz4740_dma_ndrun(struct jz4740_dma_s
*s
, int channel
)
2286 len
= jz4740_dma_unit_size(s
, s
->dcs
[channel
]) * s
->dtc
[channel
];
2288 jz4740_dma_transfer(s
, s
->dsa
[channel
], s
->dta
[channel
], len
);
2290 /*finish dma transfer */
2291 s
->dtc
[channel
] = 0;
2293 s
->dirqp
|= 1 << channel
;
2295 /*some cleanup work */
2296 /*clean AR TT GLOBAL AR */
2297 s
->dcs
[channel
] &= 0xffffffe7;
2298 s
->dmac
&= 0xfffffffb;
2300 if (s
->dcm
[channel
] & 0x2)
2301 qemu_set_irq(s
->irq
, 1);
2304 /*descriptor transfer */
2305 static inline void jz4740_dma_drun(struct jz4740_dma_s
*s
, int channel
)
2307 struct jz4740_desc_s
*desc
;
2308 target_phys_addr_t desc_phy
;
2311 desc_phy
= s
->dda
[channel
];
2313 cpu_abort(s
->soc
->env
,
2314 "jz4740_dma_drun descriptor address " JZ_FMT_plx
2315 " must be 4 bytes aligned \n", desc_phy
);
2317 pd
= cpu_get_physical_page_desc(desc_phy
);
2318 if ((pd
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2319 cpu_abort(cpu_single_env
,
2320 "%s: DMA descriptor address " JZ_FMT_plx
" outside RAM!\n",
2321 __FUNCTION__
, desc_phy
);
2323 desc
= (struct jz4740_desc_s
*) (phys_ram_base
+
2324 (pd
& TARGET_PAGE_MASK
) +
2325 (desc_phy
& ~TARGET_PAGE_MASK
));
2328 cpu_abort(cpu_single_env
,
2329 "%s: DMA descriptor " JZ_FMT_plx
" is NULL!\n", __FUNCTION__
,
2334 if ((desc
->dcmd
& 0x8) && (!(desc
->dcmd
& 0x10)))
2336 /*Stop DMA and set DCSN.INV=1 */
2337 s
->dcs
[channel
] |= 1 << 6;
2340 jz4740_dma_transfer(s
, desc
->dtadr
, desc
->dsadr
,
2341 (desc
->ddadr
& 0xffffff) *
2342 jz4740_dma_unit_size(s
, desc
->dcmd
));
2344 if ((desc
->dcmd
) & (1 << 3))
2346 desc
->dcmd
&= ~(1 << 4);
2347 if (desc
->dcmd
& 0x1)
2349 s
->dcs
[channel
] |= 0x2;
2352 s
->dcs
[channel
] |= 0x8;
2354 if (desc
->dcmd
& 0x2)
2355 qemu_set_irq(s
->irq
, 1);
2357 if ((desc
->dcmd
) & 0x1)
2359 /*fetch next descriptor */
2360 desc_phy
= s
->dda
[channel
] & 0xfffff000;
2361 desc_phy
+= (desc
->dtadr
& 0xff000000) >> 24;
2362 pd
= cpu_get_physical_page_desc(desc_phy
);
2363 if ((pd
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2364 cpu_abort(cpu_single_env
,
2365 "%s: DMA descriptor address %x outside RAM!\n",
2366 __FUNCTION__
, desc_phy
);
2368 desc
= (struct jz4740_desc_s
*) (phys_ram_base
+
2369 (pd
& TARGET_PAGE_MASK
)
2372 ~TARGET_PAGE_MASK
));
2374 cpu_abort(cpu_single_env
,
2375 "%s: DMA descriptor %x is NULL!\n",
2376 __FUNCTION__
, (uint32_t) desc
);
2383 static void jz4740_dma_en_channel(struct jz4740_dma_s
*s
, int channel
)
2387 if (s
->dcs
[channel
] & (1 << 31))
2390 jz4740_dma_ndrun(s
, channel
);
2395 static inline void jz4740_dma_en_global(struct jz4740_dma_s
*s
)
2398 for (channel
= 0; channel
< JZ4740_DMA_NUM
; channel
++)
2400 jz4740_dma_en_channel(s
, channel
);
2404 static inline void jz4740_dma_en_dbn(struct jz4740_dma_s
*s
, int channel
)
2406 if ((s
->dmac
& 0x1) && (s
->dcs
[channel
] & (1 << 31)))
2408 jz4740_dma_drun(s
, channel
);
2412 static void jz4740_dma_reset(struct jz4740_dma_s
*s
)
2417 static uint32_t jz4740_dma_read(void *opaque
, target_phys_addr_t addr
)
2419 struct jz4740_dma_s
*s
= (struct jz4740_dma_s
*) opaque
;
2422 debug_out(DEBUG_DMA
, "jz4740_dma_read addr %x \n", addr
);
2437 channel
= (addr
- 0x0) / 0x20;
2438 return s
->dsa
[channel
];
2445 channel
= (addr
- 0x4) / 0x20;
2446 return s
->dta
[channel
];
2453 channel
= (addr
- 0x8) / 0x20;
2454 return s
->dtc
[channel
];
2461 channel
= (addr
- 0xc) / 0x20;
2462 return s
->drs
[channel
];
2469 channel
= (addr
- 0x10) / 0x20;
2470 return s
->dcs
[channel
];
2477 channel
= (addr
- 0x14) / 0x20;
2478 return s
->dcm
[channel
];
2485 channel
= (addr
- 0x18) / 0x20;
2486 return s
->dda
[channel
];
2488 cpu_abort(s
->soc
->env
,
2489 "jz4740_dma_read undefined addr " JZ_FMT_plx
" \n", addr
);
2494 static void jz4740_dma_write(void *opaque
, target_phys_addr_t addr
,
2497 struct jz4740_dma_s
*s
= (struct jz4740_dma_s
*) opaque
;
2500 debug_out(DEBUG_DMA
, "jz4740_dma_write addr %x value %x \n", addr
, value
);
2504 JZ4740_RO_REG(addr
);
2507 s
->dmac
= value
& 0x30d;
2509 jz4740_dma_en_global(s
);
2513 s
->ddr
= value
& 0xff;
2514 for (channel
= 0; channel
< JZ4740_DMA_NUM
; channel
++)
2516 if (s
->ddr
& (1 << channel
))
2518 jz4740_dma_en_dbn(s
, channel
);
2529 channel
= (addr
- 0x0) / 0x20;
2530 s
->dsa
[channel
] = value
;
2538 channel
= (addr
- 0x4) / 0x20;
2539 s
->dta
[channel
] = value
;
2547 channel
= (addr
- 0x8) / 0x20;
2548 s
->dtc
[channel
] = value
;
2556 channel
= (addr
- 0xc) / 0x20;
2557 s
->drs
[channel
] = value
& 0x10;
2558 if (s
->drs
[channel
] != 0x8)
2560 fprintf(stderr
, "Only auto request is supproted \n");
2569 channel
= (addr
- 0x10) / 0x20;
2570 s
->dcs
[channel
] = value
& 0x80ff005f;
2571 if (s
->dcs
[channel
] & 0x1)
2572 jz4740_dma_en_channel(s
, channel
);
2580 channel
= (addr
- 0x14) / 0x20;
2581 s
->dcm
[channel
] = value
& 0xcff79f;
2589 channel
= (addr
- 0x18) / 0x20;
2590 s
->dda
[channel
] = 0xfffffff0;
2593 cpu_abort(s
->soc
->env
,
2594 "jz4740_dma_read undefined addr " JZ_FMT_plx
" \n", addr
);
2599 static CPUReadMemoryFunc
*jz4740_dma_readfn
[] = {
2600 jz4740_badwidth_read32
, jz4740_badwidth_read32
, jz4740_dma_read
,
2603 static CPUWriteMemoryFunc
*jz4740_dma_writefn
[] = {
2604 jz4740_badwidth_write32
, jz4740_badwidth_write32
, jz4740_dma_write
,
2608 static struct jz4740_dma_s
*jz4740_dma_init(struct jz_state_s
*soc
,
2612 struct jz4740_dma_s
*s
= (struct jz4740_dma_s
*) qemu_mallocz(sizeof(*s
));
2613 s
->base
= JZ4740_PHYS_BASE(JZ4740_DMAC_BASE
);
2617 jz4740_dma_reset(s
);
2620 cpu_register_io_memory(0, jz4740_dma_readfn
, jz4740_dma_writefn
, s
);
2621 cpu_register_physical_memory(s
->base
, 0x00010000, iomemtype
);
2626 static void jz4740_cpu_reset(void *opaque
)
2628 fprintf(stderr
, "%s: UNIMPLEMENTED!", __FUNCTION__
);
2631 struct jz_state_s
*jz4740_init(unsigned long sdram_size
,
2632 uint32_t osc_extal_freq
, DisplayState
* ds
)
2634 struct jz_state_s
*s
= (struct jz_state_s
*)
2635 qemu_mallocz(sizeof(struct jz_state_s
));
2636 ram_addr_t sram_base
, sdram_base
;
2639 s
->mpu_model
= jz4740
;
2640 s
->env
= cpu_init("jz4740");
2644 fprintf(stderr
, "Unable to find CPU definition\n");
2649 qemu_register_reset(jz4740_cpu_reset
, s
->env
);
2651 s
->sdram_size
= sdram_size
;
2652 s
->sram_size
= JZ4740_SRAM_SIZE
;
2655 jz_clk_init(s
, osc_extal_freq
);
2657 /*map sram to 0x80000000 and sdram to 0x80004000 */
2658 sram_base
= qemu_ram_alloc(s
->sram_size
);
2659 cpu_register_physical_memory(0x0, s
->sram_size
, (sram_base
| IO_MEM_RAM
));
2660 sdram_base
= qemu_ram_alloc(s
->sdram_size
);
2661 cpu_register_physical_memory(JZ4740_SRAM_SIZE
, s
->sdram_size
,
2662 (sdram_base
| IO_MEM_RAM
));
2664 /* Init internal devices */
2665 cpu_mips_irq_init_cpu(s
->env
);
2666 cpu_mips_clock_init(s
->env
);
2670 jz_clk_init(s
, osc_extal_freq
);
2672 intc
= jz4740_intc_init(s
, s
->env
->irq
[2]);
2673 s
->cpm
= jz4740_cpm_init(s
);
2674 s
->emc
= jz4740_emc_init(s
, intc
[2]);
2675 s
->gpio
= jz4740_gpio_init(s
, intc
[25]);
2676 s
->rtc
= jz4740_rtc_init(s
, intc
[15]);
2677 s
->tcu
= jz4740_tcu_if_init(s
, intc
[23], intc
[22], intc
[21]);
2678 jz4740_tcu_init(s
, s
->tcu
, 0);
2679 s
->lcdc
= jz4740_lcdc_init(s
, intc
[30], ds
);
2680 s
->dma
= jz4740_dma_init(s
, intc
[20]);
2683 serial_mm_init(0x10030000, 2, intc
[9], 57600, serial_hds
[0], 1);