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merage qemu master
[qemu/qemu-JZ.git] / hw / cirrus_vga.c
blobf9ad479573bc28af7e7570c10eee31f76d059c3c
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35
36 /*
37 * TODO:
38 * - destination write mask support not complete (bits 5..7)
39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
43 //#define DEBUG_CIRRUS
44 //#define DEBUG_BITBLT
45
46 /***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
52 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
53
54 // ID
55 #define CIRRUS_ID_CLGD5422 (0x23<<2)
56 #define CIRRUS_ID_CLGD5426 (0x24<<2)
57 #define CIRRUS_ID_CLGD5424 (0x25<<2)
58 #define CIRRUS_ID_CLGD5428 (0x26<<2)
59 #define CIRRUS_ID_CLGD5430 (0x28<<2)
60 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
61 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
62 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
63
64 // sequencer 0x07
65 #define CIRRUS_SR7_BPP_VGA 0x00
66 #define CIRRUS_SR7_BPP_SVGA 0x01
67 #define CIRRUS_SR7_BPP_MASK 0x0e
68 #define CIRRUS_SR7_BPP_8 0x00
69 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
70 #define CIRRUS_SR7_BPP_24 0x04
71 #define CIRRUS_SR7_BPP_16 0x06
72 #define CIRRUS_SR7_BPP_32 0x08
73 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
74
75 // sequencer 0x0f
76 #define CIRRUS_MEMSIZE_512k 0x08
77 #define CIRRUS_MEMSIZE_1M 0x10
78 #define CIRRUS_MEMSIZE_2M 0x18
79 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
80
81 // sequencer 0x12
82 #define CIRRUS_CURSOR_SHOW 0x01
83 #define CIRRUS_CURSOR_HIDDENPEL 0x02
84 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
85
86 // sequencer 0x17
87 #define CIRRUS_BUSTYPE_VLBFAST 0x10
88 #define CIRRUS_BUSTYPE_PCI 0x20
89 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
90 #define CIRRUS_BUSTYPE_ISA 0x38
91 #define CIRRUS_MMIO_ENABLE 0x04
92 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
93 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
94
95 // control 0x0b
96 #define CIRRUS_BANKING_DUAL 0x01
97 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
98
99 // control 0x30
100 #define CIRRUS_BLTMODE_BACKWARDS 0x01
101 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
102 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
103 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
104 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
105 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
106 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
107 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
108 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
109 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
110 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
111
112 // control 0x31
113 #define CIRRUS_BLT_BUSY 0x01
114 #define CIRRUS_BLT_START 0x02
115 #define CIRRUS_BLT_RESET 0x04
116 #define CIRRUS_BLT_FIFOUSED 0x10
117 #define CIRRUS_BLT_AUTOSTART 0x80
118
119 // control 0x32
120 #define CIRRUS_ROP_0 0x00
121 #define CIRRUS_ROP_SRC_AND_DST 0x05
122 #define CIRRUS_ROP_NOP 0x06
123 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
124 #define CIRRUS_ROP_NOTDST 0x0b
125 #define CIRRUS_ROP_SRC 0x0d
126 #define CIRRUS_ROP_1 0x0e
127 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
128 #define CIRRUS_ROP_SRC_XOR_DST 0x59
129 #define CIRRUS_ROP_SRC_OR_DST 0x6d
130 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
131 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
132 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
133 #define CIRRUS_ROP_NOTSRC 0xd0
134 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
135 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
136
137 #define CIRRUS_ROP_NOP_INDEX 2
138 #define CIRRUS_ROP_SRC_INDEX 5
139
140 // control 0x33
141 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
142 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
143 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
144
145 // memory-mapped IO
146 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
147 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
148 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
149 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
150 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
151 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
152 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
153 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
154 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
155 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
156 #define CIRRUS_MMIO_BLTROP 0x1a // byte
157 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
160 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
161 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
168 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
169 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
170 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
171 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
172 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
173 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
174 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
175
176 // PCI 0x00: vendor, 0x02: device
177 #define PCI_VENDOR_CIRRUS 0x1013
178 #define PCI_DEVICE_CLGD5462 0x00d0
179 #define PCI_DEVICE_CLGD5465 0x00d6
180
181 // PCI 0x04: command(word), 0x06(word): status
182 #define PCI_COMMAND_IOACCESS 0x0001
183 #define PCI_COMMAND_MEMACCESS 0x0002
184 #define PCI_COMMAND_BUSMASTER 0x0004
185 #define PCI_COMMAND_SPECIALCYCLE 0x0008
186 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
187 #define PCI_COMMAND_PALETTESNOOPING 0x0020
188 #define PCI_COMMAND_PARITYDETECTION 0x0040
189 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
190 #define PCI_COMMAND_SERR 0x0100
191 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
192 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
193 #define PCI_CLASS_BASE_DISPLAY 0x03
194 // PCI 0x08, 0x00ff0000
195 #define PCI_CLASS_SUB_VGA 0x00
196 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
197 #define PCI_CLASS_HEADERTYPE_00h 0x00
198 // 0x10-0x3f (headertype 00h)
199 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
200 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
201 #define PCI_MAP_MEM 0x0
202 #define PCI_MAP_IO 0x1
203 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
204 #define PCI_MAP_IO_ADDR_MASK (~0x3)
205 #define PCI_MAP_MEMFLAGS_32BIT 0x0
206 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
207 #define PCI_MAP_MEMFLAGS_64BIT 0x4
208 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
209 // PCI 0x28: cardbus CIS pointer
210 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
211 // PCI 0x30: expansion ROM base address
212 #define PCI_ROMBIOS_ENABLED 0x1
213 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
214 // PCI 0x38: reserved
215 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
216
217 #define CIRRUS_PNPMMIO_SIZE 0x1000
218
219
220 /* I/O and memory hook */
221 #define CIRRUS_HOOK_NOT_HANDLED 0
222 #define CIRRUS_HOOK_HANDLED 1
223
224 #define ABS(a) ((signed)(a) > 0 ? a : -a)
225
226 #define BLTUNSAFE(s) \
227 ( \
228 ( /* check dst is within bounds */ \
229 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
230 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
231 (s)->vram_size \
232 ) || \
233 ( /* check src is within bounds */ \
234 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
235 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
236 (s)->vram_size \
237 ) \
238 )
239
240 struct CirrusVGAState;
241 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
242 uint8_t * dst, const uint8_t * src,
243 int dstpitch, int srcpitch,
244 int bltwidth, int bltheight);
245 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
246 uint8_t *dst, int dst_pitch, int width, int height);
247
248 typedef struct CirrusVGAState {
249 VGA_STATE_COMMON
250
251 int cirrus_linear_io_addr;
252 int cirrus_linear_bitblt_io_addr;
253 int cirrus_mmio_io_addr;
254 uint32_t cirrus_addr_mask;
255 uint32_t linear_mmio_mask;
256 uint8_t cirrus_shadow_gr0;
257 uint8_t cirrus_shadow_gr1;
258 uint8_t cirrus_hidden_dac_lockindex;
259 uint8_t cirrus_hidden_dac_data;
260 uint32_t cirrus_bank_base[2];
261 uint32_t cirrus_bank_limit[2];
262 uint8_t cirrus_hidden_palette[48];
263 uint32_t hw_cursor_x;
264 uint32_t hw_cursor_y;
265 int cirrus_blt_pixelwidth;
266 int cirrus_blt_width;
267 int cirrus_blt_height;
268 int cirrus_blt_dstpitch;
269 int cirrus_blt_srcpitch;
270 uint32_t cirrus_blt_fgcol;
271 uint32_t cirrus_blt_bgcol;
272 uint32_t cirrus_blt_dstaddr;
273 uint32_t cirrus_blt_srcaddr;
274 uint8_t cirrus_blt_mode;
275 uint8_t cirrus_blt_modeext;
276 cirrus_bitblt_rop_t cirrus_rop;
277 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
278 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
279 uint8_t *cirrus_srcptr;
280 uint8_t *cirrus_srcptr_end;
281 uint32_t cirrus_srccounter;
282 /* hwcursor display state */
283 int last_hw_cursor_size;
284 int last_hw_cursor_x;
285 int last_hw_cursor_y;
286 int last_hw_cursor_y_start;
287 int last_hw_cursor_y_end;
288 int real_vram_size; /* XXX: suppress that */
289 CPUWriteMemoryFunc **cirrus_linear_write;
290 int device_id;
291 int bustype;
292 } CirrusVGAState;
293
294 typedef struct PCICirrusVGAState {
295 PCIDevice dev;
296 CirrusVGAState cirrus_vga;
297 } PCICirrusVGAState;
298
299 static uint8_t rop_to_index[256];
300
301 /***************************************
302 *
303 * prototypes.
304 *
305 ***************************************/
306
307
308 static void cirrus_bitblt_reset(CirrusVGAState *s);
309 static void cirrus_update_memory_access(CirrusVGAState *s);
310
311 /***************************************
312 *
313 * raster operations
314 *
315 ***************************************/
316
317 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
318 uint8_t *dst,const uint8_t *src,
319 int dstpitch,int srcpitch,
320 int bltwidth,int bltheight)
321 {
322 }
323
324 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
325 uint8_t *dst,
326 int dstpitch, int bltwidth,int bltheight)
327 {
328 }
329
330 #define ROP_NAME 0
331 #define ROP_OP(d, s) d = 0
332 #include "cirrus_vga_rop.h"
333
334 #define ROP_NAME src_and_dst
335 #define ROP_OP(d, s) d = (s) & (d)
336 #include "cirrus_vga_rop.h"
337
338 #define ROP_NAME src_and_notdst
339 #define ROP_OP(d, s) d = (s) & (~(d))
340 #include "cirrus_vga_rop.h"
341
342 #define ROP_NAME notdst
343 #define ROP_OP(d, s) d = ~(d)
344 #include "cirrus_vga_rop.h"
345
346 #define ROP_NAME src
347 #define ROP_OP(d, s) d = s
348 #include "cirrus_vga_rop.h"
349
350 #define ROP_NAME 1
351 #define ROP_OP(d, s) d = ~0
352 #include "cirrus_vga_rop.h"
353
354 #define ROP_NAME notsrc_and_dst
355 #define ROP_OP(d, s) d = (~(s)) & (d)
356 #include "cirrus_vga_rop.h"
357
358 #define ROP_NAME src_xor_dst
359 #define ROP_OP(d, s) d = (s) ^ (d)
360 #include "cirrus_vga_rop.h"
361
362 #define ROP_NAME src_or_dst
363 #define ROP_OP(d, s) d = (s) | (d)
364 #include "cirrus_vga_rop.h"
365
366 #define ROP_NAME notsrc_or_notdst
367 #define ROP_OP(d, s) d = (~(s)) | (~(d))
368 #include "cirrus_vga_rop.h"
369
370 #define ROP_NAME src_notxor_dst
371 #define ROP_OP(d, s) d = ~((s) ^ (d))
372 #include "cirrus_vga_rop.h"
373
374 #define ROP_NAME src_or_notdst
375 #define ROP_OP(d, s) d = (s) | (~(d))
376 #include "cirrus_vga_rop.h"
377
378 #define ROP_NAME notsrc
379 #define ROP_OP(d, s) d = (~(s))
380 #include "cirrus_vga_rop.h"
381
382 #define ROP_NAME notsrc_or_dst
383 #define ROP_OP(d, s) d = (~(s)) | (d)
384 #include "cirrus_vga_rop.h"
385
386 #define ROP_NAME notsrc_and_notdst
387 #define ROP_OP(d, s) d = (~(s)) & (~(d))
388 #include "cirrus_vga_rop.h"
389
390 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
391 cirrus_bitblt_rop_fwd_0,
392 cirrus_bitblt_rop_fwd_src_and_dst,
393 cirrus_bitblt_rop_nop,
394 cirrus_bitblt_rop_fwd_src_and_notdst,
395 cirrus_bitblt_rop_fwd_notdst,
396 cirrus_bitblt_rop_fwd_src,
397 cirrus_bitblt_rop_fwd_1,
398 cirrus_bitblt_rop_fwd_notsrc_and_dst,
399 cirrus_bitblt_rop_fwd_src_xor_dst,
400 cirrus_bitblt_rop_fwd_src_or_dst,
401 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
402 cirrus_bitblt_rop_fwd_src_notxor_dst,
403 cirrus_bitblt_rop_fwd_src_or_notdst,
404 cirrus_bitblt_rop_fwd_notsrc,
405 cirrus_bitblt_rop_fwd_notsrc_or_dst,
406 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
407 };
408
409 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
410 cirrus_bitblt_rop_bkwd_0,
411 cirrus_bitblt_rop_bkwd_src_and_dst,
412 cirrus_bitblt_rop_nop,
413 cirrus_bitblt_rop_bkwd_src_and_notdst,
414 cirrus_bitblt_rop_bkwd_notdst,
415 cirrus_bitblt_rop_bkwd_src,
416 cirrus_bitblt_rop_bkwd_1,
417 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
418 cirrus_bitblt_rop_bkwd_src_xor_dst,
419 cirrus_bitblt_rop_bkwd_src_or_dst,
420 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
421 cirrus_bitblt_rop_bkwd_src_notxor_dst,
422 cirrus_bitblt_rop_bkwd_src_or_notdst,
423 cirrus_bitblt_rop_bkwd_notsrc,
424 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
425 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
426 };
427
428 #define TRANSP_ROP(name) {\
429 name ## _8,\
430 name ## _16,\
431 }
432 #define TRANSP_NOP(func) {\
433 func,\
434 func,\
435 }
436
437 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
440 TRANSP_NOP(cirrus_bitblt_rop_nop),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
454 };
455
456 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
459 TRANSP_NOP(cirrus_bitblt_rop_nop),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
473 };
474
475 #define ROP2(name) {\
476 name ## _8,\
477 name ## _16,\
478 name ## _24,\
479 name ## _32,\
480 }
481
482 #define ROP_NOP2(func) {\
483 func,\
484 func,\
485 func,\
486 func,\
487 }
488
489 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
490 ROP2(cirrus_patternfill_0),
491 ROP2(cirrus_patternfill_src_and_dst),
492 ROP_NOP2(cirrus_bitblt_rop_nop),
493 ROP2(cirrus_patternfill_src_and_notdst),
494 ROP2(cirrus_patternfill_notdst),
495 ROP2(cirrus_patternfill_src),
496 ROP2(cirrus_patternfill_1),
497 ROP2(cirrus_patternfill_notsrc_and_dst),
498 ROP2(cirrus_patternfill_src_xor_dst),
499 ROP2(cirrus_patternfill_src_or_dst),
500 ROP2(cirrus_patternfill_notsrc_or_notdst),
501 ROP2(cirrus_patternfill_src_notxor_dst),
502 ROP2(cirrus_patternfill_src_or_notdst),
503 ROP2(cirrus_patternfill_notsrc),
504 ROP2(cirrus_patternfill_notsrc_or_dst),
505 ROP2(cirrus_patternfill_notsrc_and_notdst),
506 };
507
508 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
509 ROP2(cirrus_colorexpand_transp_0),
510 ROP2(cirrus_colorexpand_transp_src_and_dst),
511 ROP_NOP2(cirrus_bitblt_rop_nop),
512 ROP2(cirrus_colorexpand_transp_src_and_notdst),
513 ROP2(cirrus_colorexpand_transp_notdst),
514 ROP2(cirrus_colorexpand_transp_src),
515 ROP2(cirrus_colorexpand_transp_1),
516 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
517 ROP2(cirrus_colorexpand_transp_src_xor_dst),
518 ROP2(cirrus_colorexpand_transp_src_or_dst),
519 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
520 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
521 ROP2(cirrus_colorexpand_transp_src_or_notdst),
522 ROP2(cirrus_colorexpand_transp_notsrc),
523 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
524 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
525 };
526
527 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
528 ROP2(cirrus_colorexpand_0),
529 ROP2(cirrus_colorexpand_src_and_dst),
530 ROP_NOP2(cirrus_bitblt_rop_nop),
531 ROP2(cirrus_colorexpand_src_and_notdst),
532 ROP2(cirrus_colorexpand_notdst),
533 ROP2(cirrus_colorexpand_src),
534 ROP2(cirrus_colorexpand_1),
535 ROP2(cirrus_colorexpand_notsrc_and_dst),
536 ROP2(cirrus_colorexpand_src_xor_dst),
537 ROP2(cirrus_colorexpand_src_or_dst),
538 ROP2(cirrus_colorexpand_notsrc_or_notdst),
539 ROP2(cirrus_colorexpand_src_notxor_dst),
540 ROP2(cirrus_colorexpand_src_or_notdst),
541 ROP2(cirrus_colorexpand_notsrc),
542 ROP2(cirrus_colorexpand_notsrc_or_dst),
543 ROP2(cirrus_colorexpand_notsrc_and_notdst),
544 };
545
546 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
547 ROP2(cirrus_colorexpand_pattern_transp_0),
548 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
549 ROP_NOP2(cirrus_bitblt_rop_nop),
550 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
551 ROP2(cirrus_colorexpand_pattern_transp_notdst),
552 ROP2(cirrus_colorexpand_pattern_transp_src),
553 ROP2(cirrus_colorexpand_pattern_transp_1),
554 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
555 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
557 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
558 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
559 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
560 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
563 };
564
565 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
566 ROP2(cirrus_colorexpand_pattern_0),
567 ROP2(cirrus_colorexpand_pattern_src_and_dst),
568 ROP_NOP2(cirrus_bitblt_rop_nop),
569 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
570 ROP2(cirrus_colorexpand_pattern_notdst),
571 ROP2(cirrus_colorexpand_pattern_src),
572 ROP2(cirrus_colorexpand_pattern_1),
573 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
574 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
575 ROP2(cirrus_colorexpand_pattern_src_or_dst),
576 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
577 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
578 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
579 ROP2(cirrus_colorexpand_pattern_notsrc),
580 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
581 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
582 };
583
584 static const cirrus_fill_t cirrus_fill[16][4] = {
585 ROP2(cirrus_fill_0),
586 ROP2(cirrus_fill_src_and_dst),
587 ROP_NOP2(cirrus_bitblt_fill_nop),
588 ROP2(cirrus_fill_src_and_notdst),
589 ROP2(cirrus_fill_notdst),
590 ROP2(cirrus_fill_src),
591 ROP2(cirrus_fill_1),
592 ROP2(cirrus_fill_notsrc_and_dst),
593 ROP2(cirrus_fill_src_xor_dst),
594 ROP2(cirrus_fill_src_or_dst),
595 ROP2(cirrus_fill_notsrc_or_notdst),
596 ROP2(cirrus_fill_src_notxor_dst),
597 ROP2(cirrus_fill_src_or_notdst),
598 ROP2(cirrus_fill_notsrc),
599 ROP2(cirrus_fill_notsrc_or_dst),
600 ROP2(cirrus_fill_notsrc_and_notdst),
601 };
602
603 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
604 {
605 unsigned int color;
606 switch (s->cirrus_blt_pixelwidth) {
607 case 1:
608 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
609 break;
610 case 2:
611 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
612 s->cirrus_blt_fgcol = le16_to_cpu(color);
613 break;
614 case 3:
615 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
616 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
617 break;
618 default:
619 case 4:
620 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
621 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
622 s->cirrus_blt_fgcol = le32_to_cpu(color);
623 break;
624 }
625 }
626
627 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
628 {
629 unsigned int color;
630 switch (s->cirrus_blt_pixelwidth) {
631 case 1:
632 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
633 break;
634 case 2:
635 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
636 s->cirrus_blt_bgcol = le16_to_cpu(color);
637 break;
638 case 3:
639 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
640 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
641 break;
642 default:
643 case 4:
644 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
645 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
646 s->cirrus_blt_bgcol = le32_to_cpu(color);
647 break;
648 }
649 }
650
651 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
652 int off_pitch, int bytesperline,
653 int lines)
654 {
655 int y;
656 int off_cur;
657 int off_cur_end;
658
659 for (y = 0; y < lines; y++) {
660 off_cur = off_begin;
661 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
662 off_cur &= TARGET_PAGE_MASK;
663 while (off_cur < off_cur_end) {
664 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
665 off_cur += TARGET_PAGE_SIZE;
666 }
667 off_begin += off_pitch;
668 }
669 }
670
671 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
672 const uint8_t * src)
673 {
674 uint8_t *dst;
675
676 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
677
678 if (BLTUNSAFE(s))
679 return 0;
680
681 (*s->cirrus_rop) (s, dst, src,
682 s->cirrus_blt_dstpitch, 0,
683 s->cirrus_blt_width, s->cirrus_blt_height);
684 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
685 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
686 s->cirrus_blt_height);
687 return 1;
688 }
689
690 /* fill */
691
692 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
693 {
694 cirrus_fill_t rop_func;
695
696 if (BLTUNSAFE(s))
697 return 0;
698 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
699 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
700 s->cirrus_blt_dstpitch,
701 s->cirrus_blt_width, s->cirrus_blt_height);
702 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
703 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
704 s->cirrus_blt_height);
705 cirrus_bitblt_reset(s);
706 return 1;
707 }
708
709 /***************************************
710 *
711 * bitblt (video-to-video)
712 *
713 ***************************************/
714
715 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
716 {
717 return cirrus_bitblt_common_patterncopy(s,
718 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
719 s->cirrus_addr_mask));
720 }
721
722 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
723 {
724 int sx, sy;
725 int dx, dy;
726 int width, height;
727 int depth;
728 int notify = 0;
729
730 depth = s->get_bpp((VGAState *)s) / 8;
731 s->get_resolution((VGAState *)s, &width, &height);
732
733 /* extra x, y */
734 sx = (src % (width * depth)) / depth;
735 sy = (src / (width * depth));
736 dx = (dst % (width *depth)) / depth;
737 dy = (dst / (width * depth));
738
739 /* normalize width */
740 w /= depth;
741
742 /* if we're doing a backward copy, we have to adjust
743 our x/y to be the upper left corner (instead of the lower
744 right corner) */
745 if (s->cirrus_blt_dstpitch < 0) {
746 sx -= (s->cirrus_blt_width / depth) - 1;
747 dx -= (s->cirrus_blt_width / depth) - 1;
748 sy -= s->cirrus_blt_height - 1;
749 dy -= s->cirrus_blt_height - 1;
750 }
751
752 /* are we in the visible portion of memory? */
753 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
754 (sx + w) <= width && (sy + h) <= height &&
755 (dx + w) <= width && (dy + h) <= height) {
756 notify = 1;
757 }
758
759 /* make to sure only copy if it's a plain copy ROP */
760 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
761 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
762 notify = 0;
763
764 /* we have to flush all pending changes so that the copy
765 is generated at the appropriate moment in time */
766 if (notify)
767 vga_hw_update();
768
769 (*s->cirrus_rop) (s, s->vram_ptr +
770 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
771 s->vram_ptr +
772 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
773 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
774 s->cirrus_blt_width, s->cirrus_blt_height);
775
776 if (notify)
777 qemu_console_copy(s->console,
778 sx, sy, dx, dy,
779 s->cirrus_blt_width / depth,
780 s->cirrus_blt_height);
781
782 /* we don't have to notify the display that this portion has
783 changed since qemu_console_copy implies this */
784
785 if (!notify)
786 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
787 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
788 s->cirrus_blt_height);
789 }
790
791 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
792 {
793 if (BLTUNSAFE(s))
794 return 0;
795
796 if (s->ds->dpy_copy) {
797 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
798 s->cirrus_blt_srcaddr - s->start_addr,
799 s->cirrus_blt_width, s->cirrus_blt_height);
800 } else {
801 (*s->cirrus_rop) (s, s->vram_ptr +
802 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
803 s->vram_ptr +
804 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
805 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
806 s->cirrus_blt_width, s->cirrus_blt_height);
807
808 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
809 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
810 s->cirrus_blt_height);
811 }
812
813 return 1;
814 }
815
816 /***************************************
817 *
818 * bitblt (cpu-to-video)
819 *
820 ***************************************/
821
822 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
823 {
824 int copy_count;
825 uint8_t *end_ptr;
826
827 if (s->cirrus_srccounter > 0) {
828 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
829 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
830 the_end:
831 s->cirrus_srccounter = 0;
832 cirrus_bitblt_reset(s);
833 } else {
834 /* at least one scan line */
835 do {
836 (*s->cirrus_rop)(s, s->vram_ptr +
837 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
838 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
839 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
840 s->cirrus_blt_width, 1);
841 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
842 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
843 if (s->cirrus_srccounter <= 0)
844 goto the_end;
845 /* more bytes than needed can be transfered because of
846 word alignment, so we keep them for the next line */
847 /* XXX: keep alignment to speed up transfer */
848 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
849 copy_count = s->cirrus_srcptr_end - end_ptr;
850 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
851 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
852 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
853 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
854 }
855 }
856 }
857
858 /***************************************
859 *
860 * bitblt wrapper
861 *
862 ***************************************/
863
864 static void cirrus_bitblt_reset(CirrusVGAState * s)
865 {
866 s->gr[0x31] &=
867 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
868 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
869 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
870 s->cirrus_srccounter = 0;
871 cirrus_update_memory_access(s);
872 }
873
874 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
875 {
876 int w;
877
878 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
879 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
880 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
881
882 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
883 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
884 s->cirrus_blt_srcpitch = 8;
885 } else {
886 /* XXX: check for 24 bpp */
887 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
888 }
889 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
890 } else {
891 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
892 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
893 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
894 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
895 else
896 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
897 } else {
898 /* always align input size to 32 bits */
899 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
900 }
901 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
902 }
903 s->cirrus_srcptr = s->cirrus_bltbuf;
904 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
905 cirrus_update_memory_access(s);
906 return 1;
907 }
908
909 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
910 {
911 /* XXX */
912 #ifdef DEBUG_BITBLT
913 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
914 #endif
915 return 0;
916 }
917
918 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
919 {
920 int ret;
921
922 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
923 ret = cirrus_bitblt_videotovideo_patterncopy(s);
924 } else {
925 ret = cirrus_bitblt_videotovideo_copy(s);
926 }
927 if (ret)
928 cirrus_bitblt_reset(s);
929 return ret;
930 }
931
932 static void cirrus_bitblt_start(CirrusVGAState * s)
933 {
934 uint8_t blt_rop;
935
936 s->gr[0x31] |= CIRRUS_BLT_BUSY;
937
938 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
939 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
940 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
941 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
942 s->cirrus_blt_dstaddr =
943 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
944 s->cirrus_blt_srcaddr =
945 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
946 s->cirrus_blt_mode = s->gr[0x30];
947 s->cirrus_blt_modeext = s->gr[0x33];
948 blt_rop = s->gr[0x32];
949
950 #ifdef DEBUG_BITBLT
951 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
952 blt_rop,
953 s->cirrus_blt_mode,
954 s->cirrus_blt_modeext,
955 s->cirrus_blt_width,
956 s->cirrus_blt_height,
957 s->cirrus_blt_dstpitch,
958 s->cirrus_blt_srcpitch,
959 s->cirrus_blt_dstaddr,
960 s->cirrus_blt_srcaddr,
961 s->gr[0x2f]);
962 #endif
963
964 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
965 case CIRRUS_BLTMODE_PIXELWIDTH8:
966 s->cirrus_blt_pixelwidth = 1;
967 break;
968 case CIRRUS_BLTMODE_PIXELWIDTH16:
969 s->cirrus_blt_pixelwidth = 2;
970 break;
971 case CIRRUS_BLTMODE_PIXELWIDTH24:
972 s->cirrus_blt_pixelwidth = 3;
973 break;
974 case CIRRUS_BLTMODE_PIXELWIDTH32:
975 s->cirrus_blt_pixelwidth = 4;
976 break;
977 default:
978 #ifdef DEBUG_BITBLT
979 printf("cirrus: bitblt - pixel width is unknown\n");
980 #endif
981 goto bitblt_ignore;
982 }
983 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
984
985 if ((s->
986 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
987 CIRRUS_BLTMODE_MEMSYSDEST))
988 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
989 #ifdef DEBUG_BITBLT
990 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
991 #endif
992 goto bitblt_ignore;
993 }
994
995 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
996 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
997 CIRRUS_BLTMODE_TRANSPARENTCOMP |
998 CIRRUS_BLTMODE_PATTERNCOPY |
999 CIRRUS_BLTMODE_COLOREXPAND)) ==
1000 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1001 cirrus_bitblt_fgcol(s);
1002 cirrus_bitblt_solidfill(s, blt_rop);
1003 } else {
1004 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1005 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1006 CIRRUS_BLTMODE_COLOREXPAND) {
1007
1008 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1009 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1010 cirrus_bitblt_bgcol(s);
1011 else
1012 cirrus_bitblt_fgcol(s);
1013 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1014 } else {
1015 cirrus_bitblt_fgcol(s);
1016 cirrus_bitblt_bgcol(s);
1017 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1018 }
1019 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1020 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1021 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1022 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1023 cirrus_bitblt_bgcol(s);
1024 else
1025 cirrus_bitblt_fgcol(s);
1026 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1027 } else {
1028 cirrus_bitblt_fgcol(s);
1029 cirrus_bitblt_bgcol(s);
1030 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1031 }
1032 } else {
1033 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1034 }
1035 } else {
1036 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1037 if (s->cirrus_blt_pixelwidth > 2) {
1038 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1039 goto bitblt_ignore;
1040 }
1041 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1042 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1043 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1044 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1045 } else {
1046 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1047 }
1048 } else {
1049 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1050 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1051 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1052 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1053 } else {
1054 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1055 }
1056 }
1057 }
1058 // setup bitblt engine.
1059 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1060 if (!cirrus_bitblt_cputovideo(s))
1061 goto bitblt_ignore;
1062 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1063 if (!cirrus_bitblt_videotocpu(s))
1064 goto bitblt_ignore;
1065 } else {
1066 if (!cirrus_bitblt_videotovideo(s))
1067 goto bitblt_ignore;
1068 }
1069 }
1070 return;
1071 bitblt_ignore:;
1072 cirrus_bitblt_reset(s);
1073 }
1074
1075 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1076 {
1077 unsigned old_value;
1078
1079 old_value = s->gr[0x31];
1080 s->gr[0x31] = reg_value;
1081
1082 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1083 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1084 cirrus_bitblt_reset(s);
1085 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1086 ((reg_value & CIRRUS_BLT_START) != 0)) {
1087 cirrus_bitblt_start(s);
1088 }
1089 }
1090
1091
1092 /***************************************
1093 *
1094 * basic parameters
1095 *
1096 ***************************************/
1097
1098 static void cirrus_get_offsets(VGAState *s1,
1099 uint32_t *pline_offset,
1100 uint32_t *pstart_addr,
1101 uint32_t *pline_compare)
1102 {
1103 CirrusVGAState * s = (CirrusVGAState *)s1;
1104 uint32_t start_addr, line_offset, line_compare;
1105
1106 line_offset = s->cr[0x13]
1107 | ((s->cr[0x1b] & 0x10) << 4);
1108 line_offset <<= 3;
1109 *pline_offset = line_offset;
1110
1111 start_addr = (s->cr[0x0c] << 8)
1112 | s->cr[0x0d]
1113 | ((s->cr[0x1b] & 0x01) << 16)
1114 | ((s->cr[0x1b] & 0x0c) << 15)
1115 | ((s->cr[0x1d] & 0x80) << 12);
1116 *pstart_addr = start_addr;
1117
1118 line_compare = s->cr[0x18] |
1119 ((s->cr[0x07] & 0x10) << 4) |
1120 ((s->cr[0x09] & 0x40) << 3);
1121 *pline_compare = line_compare;
1122 }
1123
1124 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1125 {
1126 uint32_t ret = 16;
1127
1128 switch (s->cirrus_hidden_dac_data & 0xf) {
1129 case 0:
1130 ret = 15;
1131 break; /* Sierra HiColor */
1132 case 1:
1133 ret = 16;
1134 break; /* XGA HiColor */
1135 default:
1136 #ifdef DEBUG_CIRRUS
1137 printf("cirrus: invalid DAC value %x in 16bpp\n",
1138 (s->cirrus_hidden_dac_data & 0xf));
1139 #endif
1140 ret = 15; /* XXX */
1141 break;
1142 }
1143 return ret;
1144 }
1145
1146 static int cirrus_get_bpp(VGAState *s1)
1147 {
1148 CirrusVGAState * s = (CirrusVGAState *)s1;
1149 uint32_t ret = 8;
1150
1151 if ((s->sr[0x07] & 0x01) != 0) {
1152 /* Cirrus SVGA */
1153 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1154 case CIRRUS_SR7_BPP_8:
1155 ret = 8;
1156 break;
1157 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1158 ret = cirrus_get_bpp16_depth(s);
1159 break;
1160 case CIRRUS_SR7_BPP_24:
1161 ret = 24;
1162 break;
1163 case CIRRUS_SR7_BPP_16:
1164 ret = cirrus_get_bpp16_depth(s);
1165 break;
1166 case CIRRUS_SR7_BPP_32:
1167 ret = 32;
1168 break;
1169 default:
1170 #ifdef DEBUG_CIRRUS
1171 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1172 #endif
1173 ret = 8;
1174 break;
1175 }
1176 } else {
1177 /* VGA */
1178 ret = 0;
1179 }
1180
1181 return ret;
1182 }
1183
1184 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1185 {
1186 int width, height;
1187
1188 width = (s->cr[0x01] + 1) * 8;
1189 height = s->cr[0x12] |
1190 ((s->cr[0x07] & 0x02) << 7) |
1191 ((s->cr[0x07] & 0x40) << 3);
1192 height = (height + 1);
1193 /* interlace support */
1194 if (s->cr[0x1a] & 0x01)
1195 height = height * 2;
1196 *pwidth = width;
1197 *pheight = height;
1198 }
1199
1200 /***************************************
1201 *
1202 * bank memory
1203 *
1204 ***************************************/
1205
1206 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1207 {
1208 unsigned offset;
1209 unsigned limit;
1210
1211 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1212 offset = s->gr[0x09 + bank_index];
1213 else /* single bank */
1214 offset = s->gr[0x09];
1215
1216 if ((s->gr[0x0b] & 0x20) != 0)
1217 offset <<= 14;
1218 else
1219 offset <<= 12;
1220
1221 if (s->real_vram_size <= offset)
1222 limit = 0;
1223 else
1224 limit = s->real_vram_size - offset;
1225
1226 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1227 if (limit > 0x8000) {
1228 offset += 0x8000;
1229 limit -= 0x8000;
1230 } else {
1231 limit = 0;
1232 }
1233 }
1234
1235 if (limit > 0) {
1236 /* Thinking about changing bank base? First, drop the dirty bitmap information
1237 * on the current location, otherwise we lose this pointer forever */
1238 if (s->lfb_vram_mapped) {
1239 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1240 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1241 }
1242 s->cirrus_bank_base[bank_index] = offset;
1243 s->cirrus_bank_limit[bank_index] = limit;
1244 } else {
1245 s->cirrus_bank_base[bank_index] = 0;
1246 s->cirrus_bank_limit[bank_index] = 0;
1247 }
1248 }
1249
1250 /***************************************
1251 *
1252 * I/O access between 0x3c4-0x3c5
1253 *
1254 ***************************************/
1255
1256 static int
1257 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1258 {
1259 switch (reg_index) {
1260 case 0x00: // Standard VGA
1261 case 0x01: // Standard VGA
1262 case 0x02: // Standard VGA
1263 case 0x03: // Standard VGA
1264 case 0x04: // Standard VGA
1265 return CIRRUS_HOOK_NOT_HANDLED;
1266 case 0x06: // Unlock Cirrus extensions
1267 *reg_value = s->sr[reg_index];
1268 break;
1269 case 0x10:
1270 case 0x30:
1271 case 0x50:
1272 case 0x70: // Graphics Cursor X
1273 case 0x90:
1274 case 0xb0:
1275 case 0xd0:
1276 case 0xf0: // Graphics Cursor X
1277 *reg_value = s->sr[0x10];
1278 break;
1279 case 0x11:
1280 case 0x31:
1281 case 0x51:
1282 case 0x71: // Graphics Cursor Y
1283 case 0x91:
1284 case 0xb1:
1285 case 0xd1:
1286 case 0xf1: // Graphics Cursor Y
1287 *reg_value = s->sr[0x11];
1288 break;
1289 case 0x05: // ???
1290 case 0x07: // Extended Sequencer Mode
1291 case 0x08: // EEPROM Control
1292 case 0x09: // Scratch Register 0
1293 case 0x0a: // Scratch Register 1
1294 case 0x0b: // VCLK 0
1295 case 0x0c: // VCLK 1
1296 case 0x0d: // VCLK 2
1297 case 0x0e: // VCLK 3
1298 case 0x0f: // DRAM Control
1299 case 0x12: // Graphics Cursor Attribute
1300 case 0x13: // Graphics Cursor Pattern Address
1301 case 0x14: // Scratch Register 2
1302 case 0x15: // Scratch Register 3
1303 case 0x16: // Performance Tuning Register
1304 case 0x17: // Configuration Readback and Extended Control
1305 case 0x18: // Signature Generator Control
1306 case 0x19: // Signal Generator Result
1307 case 0x1a: // Signal Generator Result
1308 case 0x1b: // VCLK 0 Denominator & Post
1309 case 0x1c: // VCLK 1 Denominator & Post
1310 case 0x1d: // VCLK 2 Denominator & Post
1311 case 0x1e: // VCLK 3 Denominator & Post
1312 case 0x1f: // BIOS Write Enable and MCLK select
1313 #ifdef DEBUG_CIRRUS
1314 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1315 #endif
1316 *reg_value = s->sr[reg_index];
1317 break;
1318 default:
1319 #ifdef DEBUG_CIRRUS
1320 printf("cirrus: inport sr_index %02x\n", reg_index);
1321 #endif
1322 *reg_value = 0xff;
1323 break;
1324 }
1325
1326 return CIRRUS_HOOK_HANDLED;
1327 }
1328
1329 static int
1330 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1331 {
1332 switch (reg_index) {
1333 case 0x00: // Standard VGA
1334 case 0x01: // Standard VGA
1335 case 0x02: // Standard VGA
1336 case 0x03: // Standard VGA
1337 case 0x04: // Standard VGA
1338 return CIRRUS_HOOK_NOT_HANDLED;
1339 case 0x06: // Unlock Cirrus extensions
1340 reg_value &= 0x17;
1341 if (reg_value == 0x12) {
1342 s->sr[reg_index] = 0x12;
1343 } else {
1344 s->sr[reg_index] = 0x0f;
1345 }
1346 break;
1347 case 0x10:
1348 case 0x30:
1349 case 0x50:
1350 case 0x70: // Graphics Cursor X
1351 case 0x90:
1352 case 0xb0:
1353 case 0xd0:
1354 case 0xf0: // Graphics Cursor X
1355 s->sr[0x10] = reg_value;
1356 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1357 break;
1358 case 0x11:
1359 case 0x31:
1360 case 0x51:
1361 case 0x71: // Graphics Cursor Y
1362 case 0x91:
1363 case 0xb1:
1364 case 0xd1:
1365 case 0xf1: // Graphics Cursor Y
1366 s->sr[0x11] = reg_value;
1367 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1368 break;
1369 case 0x07: // Extended Sequencer Mode
1370 cirrus_update_memory_access(s);
1371 case 0x08: // EEPROM Control
1372 case 0x09: // Scratch Register 0
1373 case 0x0a: // Scratch Register 1
1374 case 0x0b: // VCLK 0
1375 case 0x0c: // VCLK 1
1376 case 0x0d: // VCLK 2
1377 case 0x0e: // VCLK 3
1378 case 0x0f: // DRAM Control
1379 case 0x12: // Graphics Cursor Attribute
1380 case 0x13: // Graphics Cursor Pattern Address
1381 case 0x14: // Scratch Register 2
1382 case 0x15: // Scratch Register 3
1383 case 0x16: // Performance Tuning Register
1384 case 0x18: // Signature Generator Control
1385 case 0x19: // Signature Generator Result
1386 case 0x1a: // Signature Generator Result
1387 case 0x1b: // VCLK 0 Denominator & Post
1388 case 0x1c: // VCLK 1 Denominator & Post
1389 case 0x1d: // VCLK 2 Denominator & Post
1390 case 0x1e: // VCLK 3 Denominator & Post
1391 case 0x1f: // BIOS Write Enable and MCLK select
1392 s->sr[reg_index] = reg_value;
1393 #ifdef DEBUG_CIRRUS
1394 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1395 reg_index, reg_value);
1396 #endif
1397 break;
1398 case 0x17: // Configuration Readback and Extended Control
1399 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1400 cirrus_update_memory_access(s);
1401 break;
1402 default:
1403 #ifdef DEBUG_CIRRUS
1404 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1405 reg_value);
1406 #endif
1407 break;
1408 }
1409
1410 return CIRRUS_HOOK_HANDLED;
1411 }
1412
1413 /***************************************
1414 *
1415 * I/O access at 0x3c6
1416 *
1417 ***************************************/
1418
1419 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1420 {
1421 *reg_value = 0xff;
1422 if (++s->cirrus_hidden_dac_lockindex == 5) {
1423 *reg_value = s->cirrus_hidden_dac_data;
1424 s->cirrus_hidden_dac_lockindex = 0;
1425 }
1426 }
1427
1428 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1429 {
1430 if (s->cirrus_hidden_dac_lockindex == 4) {
1431 s->cirrus_hidden_dac_data = reg_value;
1432 #if defined(DEBUG_CIRRUS)
1433 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1434 #endif
1435 }
1436 s->cirrus_hidden_dac_lockindex = 0;
1437 }
1438
1439 /***************************************
1440 *
1441 * I/O access at 0x3c9
1442 *
1443 ***************************************/
1444
1445 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1446 {
1447 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1448 return CIRRUS_HOOK_NOT_HANDLED;
1449 *reg_value =
1450 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1451 s->dac_sub_index];
1452 if (++s->dac_sub_index == 3) {
1453 s->dac_sub_index = 0;
1454 s->dac_read_index++;
1455 }
1456 return CIRRUS_HOOK_HANDLED;
1457 }
1458
1459 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1460 {
1461 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1462 return CIRRUS_HOOK_NOT_HANDLED;
1463 s->dac_cache[s->dac_sub_index] = reg_value;
1464 if (++s->dac_sub_index == 3) {
1465 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1466 s->dac_cache, 3);
1467 /* XXX update cursor */
1468 s->dac_sub_index = 0;
1469 s->dac_write_index++;
1470 }
1471 return CIRRUS_HOOK_HANDLED;
1472 }
1473
1474 /***************************************
1475 *
1476 * I/O access between 0x3ce-0x3cf
1477 *
1478 ***************************************/
1479
1480 static int
1481 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1482 {
1483 switch (reg_index) {
1484 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1485 *reg_value = s->cirrus_shadow_gr0;
1486 return CIRRUS_HOOK_HANDLED;
1487 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1488 *reg_value = s->cirrus_shadow_gr1;
1489 return CIRRUS_HOOK_HANDLED;
1490 case 0x02: // Standard VGA
1491 case 0x03: // Standard VGA
1492 case 0x04: // Standard VGA
1493 case 0x06: // Standard VGA
1494 case 0x07: // Standard VGA
1495 case 0x08: // Standard VGA
1496 return CIRRUS_HOOK_NOT_HANDLED;
1497 case 0x05: // Standard VGA, Cirrus extended mode
1498 default:
1499 break;
1500 }
1501
1502 if (reg_index < 0x3a) {
1503 *reg_value = s->gr[reg_index];
1504 } else {
1505 #ifdef DEBUG_CIRRUS
1506 printf("cirrus: inport gr_index %02x\n", reg_index);
1507 #endif
1508 *reg_value = 0xff;
1509 }
1510
1511 return CIRRUS_HOOK_HANDLED;
1512 }
1513
1514 static int
1515 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1516 {
1517 #if defined(DEBUG_BITBLT) && 0
1518 printf("gr%02x: %02x\n", reg_index, reg_value);
1519 #endif
1520 switch (reg_index) {
1521 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1522 s->cirrus_shadow_gr0 = reg_value;
1523 return CIRRUS_HOOK_NOT_HANDLED;
1524 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1525 s->cirrus_shadow_gr1 = reg_value;
1526 return CIRRUS_HOOK_NOT_HANDLED;
1527 case 0x02: // Standard VGA
1528 case 0x03: // Standard VGA
1529 case 0x04: // Standard VGA
1530 case 0x06: // Standard VGA
1531 case 0x07: // Standard VGA
1532 case 0x08: // Standard VGA
1533 return CIRRUS_HOOK_NOT_HANDLED;
1534 case 0x05: // Standard VGA, Cirrus extended mode
1535 s->gr[reg_index] = reg_value & 0x7f;
1536 cirrus_update_memory_access(s);
1537 break;
1538 case 0x09: // bank offset #0
1539 case 0x0A: // bank offset #1
1540 s->gr[reg_index] = reg_value;
1541 cirrus_update_bank_ptr(s, 0);
1542 cirrus_update_bank_ptr(s, 1);
1543 cirrus_update_memory_access(s);
1544 break;
1545 case 0x0B:
1546 s->gr[reg_index] = reg_value;
1547 cirrus_update_bank_ptr(s, 0);
1548 cirrus_update_bank_ptr(s, 1);
1549 cirrus_update_memory_access(s);
1550 break;
1551 case 0x10: // BGCOLOR 0x0000ff00
1552 case 0x11: // FGCOLOR 0x0000ff00
1553 case 0x12: // BGCOLOR 0x00ff0000
1554 case 0x13: // FGCOLOR 0x00ff0000
1555 case 0x14: // BGCOLOR 0xff000000
1556 case 0x15: // FGCOLOR 0xff000000
1557 case 0x20: // BLT WIDTH 0x0000ff
1558 case 0x22: // BLT HEIGHT 0x0000ff
1559 case 0x24: // BLT DEST PITCH 0x0000ff
1560 case 0x26: // BLT SRC PITCH 0x0000ff
1561 case 0x28: // BLT DEST ADDR 0x0000ff
1562 case 0x29: // BLT DEST ADDR 0x00ff00
1563 case 0x2c: // BLT SRC ADDR 0x0000ff
1564 case 0x2d: // BLT SRC ADDR 0x00ff00
1565 case 0x2f: // BLT WRITEMASK
1566 case 0x30: // BLT MODE
1567 case 0x32: // RASTER OP
1568 case 0x33: // BLT MODEEXT
1569 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1570 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1571 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1572 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1573 s->gr[reg_index] = reg_value;
1574 break;
1575 case 0x21: // BLT WIDTH 0x001f00
1576 case 0x23: // BLT HEIGHT 0x001f00
1577 case 0x25: // BLT DEST PITCH 0x001f00
1578 case 0x27: // BLT SRC PITCH 0x001f00
1579 s->gr[reg_index] = reg_value & 0x1f;
1580 break;
1581 case 0x2a: // BLT DEST ADDR 0x3f0000
1582 s->gr[reg_index] = reg_value & 0x3f;
1583 /* if auto start mode, starts bit blt now */
1584 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1585 cirrus_bitblt_start(s);
1586 }
1587 break;
1588 case 0x2e: // BLT SRC ADDR 0x3f0000
1589 s->gr[reg_index] = reg_value & 0x3f;
1590 break;
1591 case 0x31: // BLT STATUS/START
1592 cirrus_write_bitblt(s, reg_value);
1593 break;
1594 default:
1595 #ifdef DEBUG_CIRRUS
1596 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1597 reg_value);
1598 #endif
1599 break;
1600 }
1601
1602 return CIRRUS_HOOK_HANDLED;
1603 }
1604
1605 /***************************************
1606 *
1607 * I/O access between 0x3d4-0x3d5
1608 *
1609 ***************************************/
1610
1611 static int
1612 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1613 {
1614 switch (reg_index) {
1615 case 0x00: // Standard VGA
1616 case 0x01: // Standard VGA
1617 case 0x02: // Standard VGA
1618 case 0x03: // Standard VGA
1619 case 0x04: // Standard VGA
1620 case 0x05: // Standard VGA
1621 case 0x06: // Standard VGA
1622 case 0x07: // Standard VGA
1623 case 0x08: // Standard VGA
1624 case 0x09: // Standard VGA
1625 case 0x0a: // Standard VGA
1626 case 0x0b: // Standard VGA
1627 case 0x0c: // Standard VGA
1628 case 0x0d: // Standard VGA
1629 case 0x0e: // Standard VGA
1630 case 0x0f: // Standard VGA
1631 case 0x10: // Standard VGA
1632 case 0x11: // Standard VGA
1633 case 0x12: // Standard VGA
1634 case 0x13: // Standard VGA
1635 case 0x14: // Standard VGA
1636 case 0x15: // Standard VGA
1637 case 0x16: // Standard VGA
1638 case 0x17: // Standard VGA
1639 case 0x18: // Standard VGA
1640 return CIRRUS_HOOK_NOT_HANDLED;
1641 case 0x24: // Attribute Controller Toggle Readback (R)
1642 *reg_value = (s->ar_flip_flop << 7);
1643 break;
1644 case 0x19: // Interlace End
1645 case 0x1a: // Miscellaneous Control
1646 case 0x1b: // Extended Display Control
1647 case 0x1c: // Sync Adjust and Genlock
1648 case 0x1d: // Overlay Extended Control
1649 case 0x22: // Graphics Data Latches Readback (R)
1650 case 0x25: // Part Status
1651 case 0x27: // Part ID (R)
1652 *reg_value = s->cr[reg_index];
1653 break;
1654 case 0x26: // Attribute Controller Index Readback (R)
1655 *reg_value = s->ar_index & 0x3f;
1656 break;
1657 default:
1658 #ifdef DEBUG_CIRRUS
1659 printf("cirrus: inport cr_index %02x\n", reg_index);
1660 *reg_value = 0xff;
1661 #endif
1662 break;
1663 }
1664
1665 return CIRRUS_HOOK_HANDLED;
1666 }
1667
1668 static int
1669 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1670 {
1671 switch (reg_index) {
1672 case 0x00: // Standard VGA
1673 case 0x01: // Standard VGA
1674 case 0x02: // Standard VGA
1675 case 0x03: // Standard VGA
1676 case 0x04: // Standard VGA
1677 case 0x05: // Standard VGA
1678 case 0x06: // Standard VGA
1679 case 0x07: // Standard VGA
1680 case 0x08: // Standard VGA
1681 case 0x09: // Standard VGA
1682 case 0x0a: // Standard VGA
1683 case 0x0b: // Standard VGA
1684 case 0x0c: // Standard VGA
1685 case 0x0d: // Standard VGA
1686 case 0x0e: // Standard VGA
1687 case 0x0f: // Standard VGA
1688 case 0x10: // Standard VGA
1689 case 0x11: // Standard VGA
1690 case 0x12: // Standard VGA
1691 case 0x13: // Standard VGA
1692 case 0x14: // Standard VGA
1693 case 0x15: // Standard VGA
1694 case 0x16: // Standard VGA
1695 case 0x17: // Standard VGA
1696 case 0x18: // Standard VGA
1697 return CIRRUS_HOOK_NOT_HANDLED;
1698 case 0x19: // Interlace End
1699 case 0x1a: // Miscellaneous Control
1700 case 0x1b: // Extended Display Control
1701 case 0x1c: // Sync Adjust and Genlock
1702 case 0x1d: // Overlay Extended Control
1703 s->cr[reg_index] = reg_value;
1704 #ifdef DEBUG_CIRRUS
1705 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1706 reg_index, reg_value);
1707 #endif
1708 break;
1709 case 0x22: // Graphics Data Latches Readback (R)
1710 case 0x24: // Attribute Controller Toggle Readback (R)
1711 case 0x26: // Attribute Controller Index Readback (R)
1712 case 0x27: // Part ID (R)
1713 break;
1714 case 0x25: // Part Status
1715 default:
1716 #ifdef DEBUG_CIRRUS
1717 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1718 reg_value);
1719 #endif
1720 break;
1721 }
1722
1723 return CIRRUS_HOOK_HANDLED;
1724 }
1725
1726 /***************************************
1727 *
1728 * memory-mapped I/O (bitblt)
1729 *
1730 ***************************************/
1731
1732 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1733 {
1734 int value = 0xff;
1735
1736 switch (address) {
1737 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1738 cirrus_hook_read_gr(s, 0x00, &value);
1739 break;
1740 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1741 cirrus_hook_read_gr(s, 0x10, &value);
1742 break;
1743 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1744 cirrus_hook_read_gr(s, 0x12, &value);
1745 break;
1746 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1747 cirrus_hook_read_gr(s, 0x14, &value);
1748 break;
1749 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1750 cirrus_hook_read_gr(s, 0x01, &value);
1751 break;
1752 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1753 cirrus_hook_read_gr(s, 0x11, &value);
1754 break;
1755 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1756 cirrus_hook_read_gr(s, 0x13, &value);
1757 break;
1758 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1759 cirrus_hook_read_gr(s, 0x15, &value);
1760 break;
1761 case (CIRRUS_MMIO_BLTWIDTH + 0):
1762 cirrus_hook_read_gr(s, 0x20, &value);
1763 break;
1764 case (CIRRUS_MMIO_BLTWIDTH + 1):
1765 cirrus_hook_read_gr(s, 0x21, &value);
1766 break;
1767 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1768 cirrus_hook_read_gr(s, 0x22, &value);
1769 break;
1770 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1771 cirrus_hook_read_gr(s, 0x23, &value);
1772 break;
1773 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1774 cirrus_hook_read_gr(s, 0x24, &value);
1775 break;
1776 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1777 cirrus_hook_read_gr(s, 0x25, &value);
1778 break;
1779 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1780 cirrus_hook_read_gr(s, 0x26, &value);
1781 break;
1782 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1783 cirrus_hook_read_gr(s, 0x27, &value);
1784 break;
1785 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1786 cirrus_hook_read_gr(s, 0x28, &value);
1787 break;
1788 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1789 cirrus_hook_read_gr(s, 0x29, &value);
1790 break;
1791 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1792 cirrus_hook_read_gr(s, 0x2a, &value);
1793 break;
1794 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1795 cirrus_hook_read_gr(s, 0x2c, &value);
1796 break;
1797 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1798 cirrus_hook_read_gr(s, 0x2d, &value);
1799 break;
1800 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1801 cirrus_hook_read_gr(s, 0x2e, &value);
1802 break;
1803 case CIRRUS_MMIO_BLTWRITEMASK:
1804 cirrus_hook_read_gr(s, 0x2f, &value);
1805 break;
1806 case CIRRUS_MMIO_BLTMODE:
1807 cirrus_hook_read_gr(s, 0x30, &value);
1808 break;
1809 case CIRRUS_MMIO_BLTROP:
1810 cirrus_hook_read_gr(s, 0x32, &value);
1811 break;
1812 case CIRRUS_MMIO_BLTMODEEXT:
1813 cirrus_hook_read_gr(s, 0x33, &value);
1814 break;
1815 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1816 cirrus_hook_read_gr(s, 0x34, &value);
1817 break;
1818 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1819 cirrus_hook_read_gr(s, 0x35, &value);
1820 break;
1821 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1822 cirrus_hook_read_gr(s, 0x38, &value);
1823 break;
1824 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1825 cirrus_hook_read_gr(s, 0x39, &value);
1826 break;
1827 case CIRRUS_MMIO_BLTSTATUS:
1828 cirrus_hook_read_gr(s, 0x31, &value);
1829 break;
1830 default:
1831 #ifdef DEBUG_CIRRUS
1832 printf("cirrus: mmio read - address 0x%04x\n", address);
1833 #endif
1834 break;
1835 }
1836
1837 return (uint8_t) value;
1838 }
1839
1840 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1841 uint8_t value)
1842 {
1843 switch (address) {
1844 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1845 cirrus_hook_write_gr(s, 0x00, value);
1846 break;
1847 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1848 cirrus_hook_write_gr(s, 0x10, value);
1849 break;
1850 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1851 cirrus_hook_write_gr(s, 0x12, value);
1852 break;
1853 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1854 cirrus_hook_write_gr(s, 0x14, value);
1855 break;
1856 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1857 cirrus_hook_write_gr(s, 0x01, value);
1858 break;
1859 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1860 cirrus_hook_write_gr(s, 0x11, value);
1861 break;
1862 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1863 cirrus_hook_write_gr(s, 0x13, value);
1864 break;
1865 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1866 cirrus_hook_write_gr(s, 0x15, value);
1867 break;
1868 case (CIRRUS_MMIO_BLTWIDTH + 0):
1869 cirrus_hook_write_gr(s, 0x20, value);
1870 break;
1871 case (CIRRUS_MMIO_BLTWIDTH + 1):
1872 cirrus_hook_write_gr(s, 0x21, value);
1873 break;
1874 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1875 cirrus_hook_write_gr(s, 0x22, value);
1876 break;
1877 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1878 cirrus_hook_write_gr(s, 0x23, value);
1879 break;
1880 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1881 cirrus_hook_write_gr(s, 0x24, value);
1882 break;
1883 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1884 cirrus_hook_write_gr(s, 0x25, value);
1885 break;
1886 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1887 cirrus_hook_write_gr(s, 0x26, value);
1888 break;
1889 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1890 cirrus_hook_write_gr(s, 0x27, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1893 cirrus_hook_write_gr(s, 0x28, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1896 cirrus_hook_write_gr(s, 0x29, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1899 cirrus_hook_write_gr(s, 0x2a, value);
1900 break;
1901 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1902 /* ignored */
1903 break;
1904 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1905 cirrus_hook_write_gr(s, 0x2c, value);
1906 break;
1907 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1908 cirrus_hook_write_gr(s, 0x2d, value);
1909 break;
1910 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1911 cirrus_hook_write_gr(s, 0x2e, value);
1912 break;
1913 case CIRRUS_MMIO_BLTWRITEMASK:
1914 cirrus_hook_write_gr(s, 0x2f, value);
1915 break;
1916 case CIRRUS_MMIO_BLTMODE:
1917 cirrus_hook_write_gr(s, 0x30, value);
1918 break;
1919 case CIRRUS_MMIO_BLTROP:
1920 cirrus_hook_write_gr(s, 0x32, value);
1921 break;
1922 case CIRRUS_MMIO_BLTMODEEXT:
1923 cirrus_hook_write_gr(s, 0x33, value);
1924 break;
1925 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1926 cirrus_hook_write_gr(s, 0x34, value);
1927 break;
1928 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1929 cirrus_hook_write_gr(s, 0x35, value);
1930 break;
1931 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1932 cirrus_hook_write_gr(s, 0x38, value);
1933 break;
1934 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1935 cirrus_hook_write_gr(s, 0x39, value);
1936 break;
1937 case CIRRUS_MMIO_BLTSTATUS:
1938 cirrus_hook_write_gr(s, 0x31, value);
1939 break;
1940 default:
1941 #ifdef DEBUG_CIRRUS
1942 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1943 address, value);
1944 #endif
1945 break;
1946 }
1947 }
1948
1949 /***************************************
1950 *
1951 * write mode 4/5
1952 *
1953 * assume TARGET_PAGE_SIZE >= 16
1954 *
1955 ***************************************/
1956
1957 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1958 unsigned mode,
1959 unsigned offset,
1960 uint32_t mem_value)
1961 {
1962 int x;
1963 unsigned val = mem_value;
1964 uint8_t *dst;
1965
1966 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1967 for (x = 0; x < 8; x++) {
1968 if (val & 0x80) {
1969 *dst = s->cirrus_shadow_gr1;
1970 } else if (mode == 5) {
1971 *dst = s->cirrus_shadow_gr0;
1972 }
1973 val <<= 1;
1974 dst++;
1975 }
1976 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1977 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1978 }
1979
1980 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1981 unsigned mode,
1982 unsigned offset,
1983 uint32_t mem_value)
1984 {
1985 int x;
1986 unsigned val = mem_value;
1987 uint8_t *dst;
1988
1989 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1990 for (x = 0; x < 8; x++) {
1991 if (val & 0x80) {
1992 *dst = s->cirrus_shadow_gr1;
1993 *(dst + 1) = s->gr[0x11];
1994 } else if (mode == 5) {
1995 *dst = s->cirrus_shadow_gr0;
1996 *(dst + 1) = s->gr[0x10];
1997 }
1998 val <<= 1;
1999 dst += 2;
2000 }
2001 cpu_physical_memory_set_dirty(s->vram_offset + offset);
2002 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
2003 }
2004
2005 /***************************************
2006 *
2007 * memory access between 0xa0000-0xbffff
2008 *
2009 ***************************************/
2010
2011 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2012 {
2013 CirrusVGAState *s = opaque;
2014 unsigned bank_index;
2015 unsigned bank_offset;
2016 uint32_t val;
2017
2018 if ((s->sr[0x07] & 0x01) == 0) {
2019 return vga_mem_readb(s, addr);
2020 }
2021
2022 addr &= 0x1ffff;
2023
2024 if (addr < 0x10000) {
2025 /* XXX handle bitblt */
2026 /* video memory */
2027 bank_index = addr >> 15;
2028 bank_offset = addr & 0x7fff;
2029 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2030 bank_offset += s->cirrus_bank_base[bank_index];
2031 if ((s->gr[0x0B] & 0x14) == 0x14) {
2032 bank_offset <<= 4;
2033 } else if (s->gr[0x0B] & 0x02) {
2034 bank_offset <<= 3;
2035 }
2036 bank_offset &= s->cirrus_addr_mask;
2037 val = *(s->vram_ptr + bank_offset);
2038 } else
2039 val = 0xff;
2040 } else if (addr >= 0x18000 && addr < 0x18100) {
2041 /* memory-mapped I/O */
2042 val = 0xff;
2043 if ((s->sr[0x17] & 0x44) == 0x04) {
2044 val = cirrus_mmio_blt_read(s, addr & 0xff);
2045 }
2046 } else {
2047 val = 0xff;
2048 #ifdef DEBUG_CIRRUS
2049 printf("cirrus: mem_readb %06x\n", addr);
2050 #endif
2051 }
2052 return val;
2053 }
2054
2055 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2056 {
2057 uint32_t v;
2058 #ifdef TARGET_WORDS_BIGENDIAN
2059 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2060 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2061 #else
2062 v = cirrus_vga_mem_readb(opaque, addr);
2063 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2064 #endif
2065 return v;
2066 }
2067
2068 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2069 {
2070 uint32_t v;
2071 #ifdef TARGET_WORDS_BIGENDIAN
2072 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2073 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2074 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2075 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2076 #else
2077 v = cirrus_vga_mem_readb(opaque, addr);
2078 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2079 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2080 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2081 #endif
2082 return v;
2083 }
2084
2085 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2086 uint32_t mem_value)
2087 {
2088 CirrusVGAState *s = opaque;
2089 unsigned bank_index;
2090 unsigned bank_offset;
2091 unsigned mode;
2092
2093 if ((s->sr[0x07] & 0x01) == 0) {
2094 vga_mem_writeb(s, addr, mem_value);
2095 return;
2096 }
2097
2098 addr &= 0x1ffff;
2099
2100 if (addr < 0x10000) {
2101 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2102 /* bitblt */
2103 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2104 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2105 cirrus_bitblt_cputovideo_next(s);
2106 }
2107 } else {
2108 /* video memory */
2109 bank_index = addr >> 15;
2110 bank_offset = addr & 0x7fff;
2111 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2112 bank_offset += s->cirrus_bank_base[bank_index];
2113 if ((s->gr[0x0B] & 0x14) == 0x14) {
2114 bank_offset <<= 4;
2115 } else if (s->gr[0x0B] & 0x02) {
2116 bank_offset <<= 3;
2117 }
2118 bank_offset &= s->cirrus_addr_mask;
2119 mode = s->gr[0x05] & 0x7;
2120 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2121 *(s->vram_ptr + bank_offset) = mem_value;
2122 cpu_physical_memory_set_dirty(s->vram_offset +
2123 bank_offset);
2124 } else {
2125 if ((s->gr[0x0B] & 0x14) != 0x14) {
2126 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2127 bank_offset,
2128 mem_value);
2129 } else {
2130 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2131 bank_offset,
2132 mem_value);
2133 }
2134 }
2135 }
2136 }
2137 } else if (addr >= 0x18000 && addr < 0x18100) {
2138 /* memory-mapped I/O */
2139 if ((s->sr[0x17] & 0x44) == 0x04) {
2140 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2141 }
2142 } else {
2143 #ifdef DEBUG_CIRRUS
2144 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2145 #endif
2146 }
2147 }
2148
2149 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2150 {
2151 #ifdef TARGET_WORDS_BIGENDIAN
2152 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2153 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2154 #else
2155 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2156 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2157 #endif
2158 }
2159
2160 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2161 {
2162 #ifdef TARGET_WORDS_BIGENDIAN
2163 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2164 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2165 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2166 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2167 #else
2168 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2169 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2170 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2171 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2172 #endif
2173 }
2174
2175 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2176 cirrus_vga_mem_readb,
2177 cirrus_vga_mem_readw,
2178 cirrus_vga_mem_readl,
2179 };
2180
2181 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2182 cirrus_vga_mem_writeb,
2183 cirrus_vga_mem_writew,
2184 cirrus_vga_mem_writel,
2185 };
2186
2187 /***************************************
2188 *
2189 * hardware cursor
2190 *
2191 ***************************************/
2192
2193 static inline void invalidate_cursor1(CirrusVGAState *s)
2194 {
2195 if (s->last_hw_cursor_size) {
2196 vga_invalidate_scanlines((VGAState *)s,
2197 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2198 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2199 }
2200 }
2201
2202 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2203 {
2204 const uint8_t *src;
2205 uint32_t content;
2206 int y, y_min, y_max;
2207
2208 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2209 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2210 src += (s->sr[0x13] & 0x3c) * 256;
2211 y_min = 64;
2212 y_max = -1;
2213 for(y = 0; y < 64; y++) {
2214 content = ((uint32_t *)src)[0] |
2215 ((uint32_t *)src)[1] |
2216 ((uint32_t *)src)[2] |
2217 ((uint32_t *)src)[3];
2218 if (content) {
2219 if (y < y_min)
2220 y_min = y;
2221 if (y > y_max)
2222 y_max = y;
2223 }
2224 src += 16;
2225 }
2226 } else {
2227 src += (s->sr[0x13] & 0x3f) * 256;
2228 y_min = 32;
2229 y_max = -1;
2230 for(y = 0; y < 32; y++) {
2231 content = ((uint32_t *)src)[0] |
2232 ((uint32_t *)(src + 128))[0];
2233 if (content) {
2234 if (y < y_min)
2235 y_min = y;
2236 if (y > y_max)
2237 y_max = y;
2238 }
2239 src += 4;
2240 }
2241 }
2242 if (y_min > y_max) {
2243 s->last_hw_cursor_y_start = 0;
2244 s->last_hw_cursor_y_end = 0;
2245 } else {
2246 s->last_hw_cursor_y_start = y_min;
2247 s->last_hw_cursor_y_end = y_max + 1;
2248 }
2249 }
2250
2251 /* NOTE: we do not currently handle the cursor bitmap change, so we
2252 update the cursor only if it moves. */
2253 static void cirrus_cursor_invalidate(VGAState *s1)
2254 {
2255 CirrusVGAState *s = (CirrusVGAState *)s1;
2256 int size;
2257
2258 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2259 size = 0;
2260 } else {
2261 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2262 size = 64;
2263 else
2264 size = 32;
2265 }
2266 /* invalidate last cursor and new cursor if any change */
2267 if (s->last_hw_cursor_size != size ||
2268 s->last_hw_cursor_x != s->hw_cursor_x ||
2269 s->last_hw_cursor_y != s->hw_cursor_y) {
2270
2271 invalidate_cursor1(s);
2272
2273 s->last_hw_cursor_size = size;
2274 s->last_hw_cursor_x = s->hw_cursor_x;
2275 s->last_hw_cursor_y = s->hw_cursor_y;
2276 /* compute the real cursor min and max y */
2277 cirrus_cursor_compute_yrange(s);
2278 invalidate_cursor1(s);
2279 }
2280 }
2281
2282 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2283 {
2284 CirrusVGAState *s = (CirrusVGAState *)s1;
2285 int w, h, bpp, x1, x2, poffset;
2286 unsigned int color0, color1;
2287 const uint8_t *palette, *src;
2288 uint32_t content;
2289
2290 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2291 return;
2292 /* fast test to see if the cursor intersects with the scan line */
2293 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2294 h = 64;
2295 } else {
2296 h = 32;
2297 }
2298 if (scr_y < s->hw_cursor_y ||
2299 scr_y >= (s->hw_cursor_y + h))
2300 return;
2301
2302 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2303 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2304 src += (s->sr[0x13] & 0x3c) * 256;
2305 src += (scr_y - s->hw_cursor_y) * 16;
2306 poffset = 8;
2307 content = ((uint32_t *)src)[0] |
2308 ((uint32_t *)src)[1] |
2309 ((uint32_t *)src)[2] |
2310 ((uint32_t *)src)[3];
2311 } else {
2312 src += (s->sr[0x13] & 0x3f) * 256;
2313 src += (scr_y - s->hw_cursor_y) * 4;
2314 poffset = 128;
2315 content = ((uint32_t *)src)[0] |
2316 ((uint32_t *)(src + 128))[0];
2317 }
2318 /* if nothing to draw, no need to continue */
2319 if (!content)
2320 return;
2321 w = h;
2322
2323 x1 = s->hw_cursor_x;
2324 if (x1 >= s->last_scr_width)
2325 return;
2326 x2 = s->hw_cursor_x + w;
2327 if (x2 > s->last_scr_width)
2328 x2 = s->last_scr_width;
2329 w = x2 - x1;
2330 palette = s->cirrus_hidden_palette;
2331 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2332 c6_to_8(palette[0x0 * 3 + 1]),
2333 c6_to_8(palette[0x0 * 3 + 2]));
2334 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2335 c6_to_8(palette[0xf * 3 + 1]),
2336 c6_to_8(palette[0xf * 3 + 2]));
2337 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2338 d1 += x1 * bpp;
2339 switch(ds_get_bits_per_pixel(s->ds)) {
2340 default:
2341 break;
2342 case 8:
2343 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2344 break;
2345 case 15:
2346 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2347 break;
2348 case 16:
2349 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2350 break;
2351 case 32:
2352 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2353 break;
2354 }
2355 }
2356
2357 /***************************************
2358 *
2359 * LFB memory access
2360 *
2361 ***************************************/
2362
2363 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2364 {
2365 CirrusVGAState *s = (CirrusVGAState *) opaque;
2366 uint32_t ret;
2367
2368 addr &= s->cirrus_addr_mask;
2369
2370 if (((s->sr[0x17] & 0x44) == 0x44) &&
2371 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2372 /* memory-mapped I/O */
2373 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2374 } else if (0) {
2375 /* XXX handle bitblt */
2376 ret = 0xff;
2377 } else {
2378 /* video memory */
2379 if ((s->gr[0x0B] & 0x14) == 0x14) {
2380 addr <<= 4;
2381 } else if (s->gr[0x0B] & 0x02) {
2382 addr <<= 3;
2383 }
2384 addr &= s->cirrus_addr_mask;
2385 ret = *(s->vram_ptr + addr);
2386 }
2387
2388 return ret;
2389 }
2390
2391 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2392 {
2393 uint32_t v;
2394 #ifdef TARGET_WORDS_BIGENDIAN
2395 v = cirrus_linear_readb(opaque, addr) << 8;
2396 v |= cirrus_linear_readb(opaque, addr + 1);
2397 #else
2398 v = cirrus_linear_readb(opaque, addr);
2399 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2400 #endif
2401 return v;
2402 }
2403
2404 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2405 {
2406 uint32_t v;
2407 #ifdef TARGET_WORDS_BIGENDIAN
2408 v = cirrus_linear_readb(opaque, addr) << 24;
2409 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2410 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2411 v |= cirrus_linear_readb(opaque, addr + 3);
2412 #else
2413 v = cirrus_linear_readb(opaque, addr);
2414 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2415 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2416 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2417 #endif
2418 return v;
2419 }
2420
2421 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2422 uint32_t val)
2423 {
2424 CirrusVGAState *s = (CirrusVGAState *) opaque;
2425 unsigned mode;
2426
2427 addr &= s->cirrus_addr_mask;
2428
2429 if (((s->sr[0x17] & 0x44) == 0x44) &&
2430 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2431 /* memory-mapped I/O */
2432 cirrus_mmio_blt_write(s, addr & 0xff, val);
2433 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2434 /* bitblt */
2435 *s->cirrus_srcptr++ = (uint8_t) val;
2436 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2437 cirrus_bitblt_cputovideo_next(s);
2438 }
2439 } else {
2440 /* video memory */
2441 if ((s->gr[0x0B] & 0x14) == 0x14) {
2442 addr <<= 4;
2443 } else if (s->gr[0x0B] & 0x02) {
2444 addr <<= 3;
2445 }
2446 addr &= s->cirrus_addr_mask;
2447
2448 mode = s->gr[0x05] & 0x7;
2449 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2450 *(s->vram_ptr + addr) = (uint8_t) val;
2451 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2452 } else {
2453 if ((s->gr[0x0B] & 0x14) != 0x14) {
2454 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2455 } else {
2456 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2457 }
2458 }
2459 }
2460 }
2461
2462 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2463 uint32_t val)
2464 {
2465 #ifdef TARGET_WORDS_BIGENDIAN
2466 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2467 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2468 #else
2469 cirrus_linear_writeb(opaque, addr, val & 0xff);
2470 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2471 #endif
2472 }
2473
2474 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2475 uint32_t val)
2476 {
2477 #ifdef TARGET_WORDS_BIGENDIAN
2478 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2479 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2480 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2481 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2482 #else
2483 cirrus_linear_writeb(opaque, addr, val & 0xff);
2484 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2485 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2486 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2487 #endif
2488 }
2489
2490
2491 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2492 cirrus_linear_readb,
2493 cirrus_linear_readw,
2494 cirrus_linear_readl,
2495 };
2496
2497 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2498 cirrus_linear_writeb,
2499 cirrus_linear_writew,
2500 cirrus_linear_writel,
2501 };
2502
2503 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2504 uint32_t val)
2505 {
2506 CirrusVGAState *s = (CirrusVGAState *) opaque;
2507
2508 addr &= s->cirrus_addr_mask;
2509 *(s->vram_ptr + addr) = val;
2510 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2511 }
2512
2513 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2514 uint32_t val)
2515 {
2516 CirrusVGAState *s = (CirrusVGAState *) opaque;
2517
2518 addr &= s->cirrus_addr_mask;
2519 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2520 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2521 }
2522
2523 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2524 uint32_t val)
2525 {
2526 CirrusVGAState *s = (CirrusVGAState *) opaque;
2527
2528 addr &= s->cirrus_addr_mask;
2529 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2530 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2531 }
2532
2533 /***************************************
2534 *
2535 * system to screen memory access
2536 *
2537 ***************************************/
2538
2539
2540 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2541 {
2542 uint32_t ret;
2543
2544 /* XXX handle bitblt */
2545 ret = 0xff;
2546 return ret;
2547 }
2548
2549 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2550 {
2551 uint32_t v;
2552 #ifdef TARGET_WORDS_BIGENDIAN
2553 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2554 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2555 #else
2556 v = cirrus_linear_bitblt_readb(opaque, addr);
2557 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2558 #endif
2559 return v;
2560 }
2561
2562 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2563 {
2564 uint32_t v;
2565 #ifdef TARGET_WORDS_BIGENDIAN
2566 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2567 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2568 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2569 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2570 #else
2571 v = cirrus_linear_bitblt_readb(opaque, addr);
2572 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2573 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2574 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2575 #endif
2576 return v;
2577 }
2578
2579 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2580 uint32_t val)
2581 {
2582 CirrusVGAState *s = (CirrusVGAState *) opaque;
2583
2584 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2585 /* bitblt */
2586 *s->cirrus_srcptr++ = (uint8_t) val;
2587 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2588 cirrus_bitblt_cputovideo_next(s);
2589 }
2590 }
2591 }
2592
2593 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2594 uint32_t val)
2595 {
2596 #ifdef TARGET_WORDS_BIGENDIAN
2597 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2598 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2599 #else
2600 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2601 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2602 #endif
2603 }
2604
2605 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2606 uint32_t val)
2607 {
2608 #ifdef TARGET_WORDS_BIGENDIAN
2609 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2610 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2611 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2612 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2613 #else
2614 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2615 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2616 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2617 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2618 #endif
2619 }
2620
2621
2622 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2623 cirrus_linear_bitblt_readb,
2624 cirrus_linear_bitblt_readw,
2625 cirrus_linear_bitblt_readl,
2626 };
2627
2628 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2629 cirrus_linear_bitblt_writeb,
2630 cirrus_linear_bitblt_writew,
2631 cirrus_linear_bitblt_writel,
2632 };
2633
2634 static void map_linear_vram(CirrusVGAState *s)
2635 {
2636
2637 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2638 s->map_addr = s->lfb_addr;
2639 s->map_end = s->lfb_end;
2640 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2641 vga_dirty_log_start((VGAState *)s);
2642 }
2643
2644 if (!s->map_addr)
2645 return;
2646
2647 s->lfb_vram_mapped = 0;
2648
2649 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2650 && !((s->sr[0x07] & 0x01) == 0)
2651 && !((s->gr[0x0B] & 0x14) == 0x14)
2652 && !(s->gr[0x0B] & 0x02)) {
2653
2654 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2655 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2656 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2657 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2658
2659 s->lfb_vram_mapped = 1;
2660 vga_dirty_log_start((VGAState *)s);
2661 }
2662 else {
2663 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, s->vga_io_memory);
2664 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, s->vga_io_memory);
2665 }
2666
2667 }
2668
2669 static void unmap_linear_vram(CirrusVGAState *s)
2670 {
2671 if (s->map_addr && s->lfb_addr && s->lfb_end) {
2672 vga_dirty_log_stop((VGAState *)s);
2673 s->map_addr = s->map_end = 0;
2674 }
2675
2676 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2677 s->vga_io_memory);
2678 }
2679
2680 /* Compute the memory access functions */
2681 static void cirrus_update_memory_access(CirrusVGAState *s)
2682 {
2683 unsigned mode;
2684
2685 if ((s->sr[0x17] & 0x44) == 0x44) {
2686 goto generic_io;
2687 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2688 goto generic_io;
2689 } else {
2690 if ((s->gr[0x0B] & 0x14) == 0x14) {
2691 goto generic_io;
2692 } else if (s->gr[0x0B] & 0x02) {
2693 goto generic_io;
2694 }
2695
2696 mode = s->gr[0x05] & 0x7;
2697 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2698 map_linear_vram(s);
2699 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2700 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2701 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2702 } else {
2703 generic_io:
2704 unmap_linear_vram(s);
2705 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2706 s->cirrus_linear_write[1] = cirrus_linear_writew;
2707 s->cirrus_linear_write[2] = cirrus_linear_writel;
2708 }
2709 }
2710 }
2711
2712
2713 /* I/O ports */
2714
2715 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2716 {
2717 CirrusVGAState *s = opaque;
2718 int val, index;
2719
2720 /* check port range access depending on color/monochrome mode */
2721 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2722 || (addr >= 0x3d0 && addr <= 0x3df
2723 && !(s->msr & MSR_COLOR_EMULATION))) {
2724 val = 0xff;
2725 } else {
2726 switch (addr) {
2727 case 0x3c0:
2728 if (s->ar_flip_flop == 0) {
2729 val = s->ar_index;
2730 } else {
2731 val = 0;
2732 }
2733 break;
2734 case 0x3c1:
2735 index = s->ar_index & 0x1f;
2736 if (index < 21)
2737 val = s->ar[index];
2738 else
2739 val = 0;
2740 break;
2741 case 0x3c2:
2742 val = s->st00;
2743 break;
2744 case 0x3c4:
2745 val = s->sr_index;
2746 break;
2747 case 0x3c5:
2748 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2749 break;
2750 val = s->sr[s->sr_index];
2751 #ifdef DEBUG_VGA_REG
2752 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2753 #endif
2754 break;
2755 case 0x3c6:
2756 cirrus_read_hidden_dac(s, &val);
2757 break;
2758 case 0x3c7:
2759 val = s->dac_state;
2760 break;
2761 case 0x3c8:
2762 val = s->dac_write_index;
2763 s->cirrus_hidden_dac_lockindex = 0;
2764 break;
2765 case 0x3c9:
2766 if (cirrus_hook_read_palette(s, &val))
2767 break;
2768 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2769 if (++s->dac_sub_index == 3) {
2770 s->dac_sub_index = 0;
2771 s->dac_read_index++;
2772 }
2773 break;
2774 case 0x3ca:
2775 val = s->fcr;
2776 break;
2777 case 0x3cc:
2778 val = s->msr;
2779 break;
2780 case 0x3ce:
2781 val = s->gr_index;
2782 break;
2783 case 0x3cf:
2784 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2785 break;
2786 val = s->gr[s->gr_index];
2787 #ifdef DEBUG_VGA_REG
2788 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2789 #endif
2790 break;
2791 case 0x3b4:
2792 case 0x3d4:
2793 val = s->cr_index;
2794 break;
2795 case 0x3b5:
2796 case 0x3d5:
2797 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2798 break;
2799 val = s->cr[s->cr_index];
2800 #ifdef DEBUG_VGA_REG
2801 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2802 #endif
2803 break;
2804 case 0x3ba:
2805 case 0x3da:
2806 /* just toggle to fool polling */
2807 val = s->st01 = s->retrace((VGAState *) s);
2808 s->ar_flip_flop = 0;
2809 break;
2810 default:
2811 val = 0x00;
2812 break;
2813 }
2814 }
2815 #if defined(DEBUG_VGA)
2816 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2817 #endif
2818 return val;
2819 }
2820
2821 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2822 {
2823 CirrusVGAState *s = opaque;
2824 int index;
2825
2826 /* check port range access depending on color/monochrome mode */
2827 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2828 || (addr >= 0x3d0 && addr <= 0x3df
2829 && !(s->msr & MSR_COLOR_EMULATION)))
2830 return;
2831
2832 #ifdef DEBUG_VGA
2833 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2834 #endif
2835
2836 switch (addr) {
2837 case 0x3c0:
2838 if (s->ar_flip_flop == 0) {
2839 val &= 0x3f;
2840 s->ar_index = val;
2841 } else {
2842 index = s->ar_index & 0x1f;
2843 switch (index) {
2844 case 0x00 ... 0x0f:
2845 s->ar[index] = val & 0x3f;
2846 break;
2847 case 0x10:
2848 s->ar[index] = val & ~0x10;
2849 break;
2850 case 0x11:
2851 s->ar[index] = val;
2852 break;
2853 case 0x12:
2854 s->ar[index] = val & ~0xc0;
2855 break;
2856 case 0x13:
2857 s->ar[index] = val & ~0xf0;
2858 break;
2859 case 0x14:
2860 s->ar[index] = val & ~0xf0;
2861 break;
2862 default:
2863 break;
2864 }
2865 }
2866 s->ar_flip_flop ^= 1;
2867 break;
2868 case 0x3c2:
2869 s->msr = val & ~0x10;
2870 s->update_retrace_info((VGAState *) s);
2871 break;
2872 case 0x3c4:
2873 s->sr_index = val;
2874 break;
2875 case 0x3c5:
2876 if (cirrus_hook_write_sr(s, s->sr_index, val))
2877 break;
2878 #ifdef DEBUG_VGA_REG
2879 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2880 #endif
2881 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2882 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2883 break;
2884 case 0x3c6:
2885 cirrus_write_hidden_dac(s, val);
2886 break;
2887 case 0x3c7:
2888 s->dac_read_index = val;
2889 s->dac_sub_index = 0;
2890 s->dac_state = 3;
2891 break;
2892 case 0x3c8:
2893 s->dac_write_index = val;
2894 s->dac_sub_index = 0;
2895 s->dac_state = 0;
2896 break;
2897 case 0x3c9:
2898 if (cirrus_hook_write_palette(s, val))
2899 break;
2900 s->dac_cache[s->dac_sub_index] = val;
2901 if (++s->dac_sub_index == 3) {
2902 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2903 s->dac_sub_index = 0;
2904 s->dac_write_index++;
2905 }
2906 break;
2907 case 0x3ce:
2908 s->gr_index = val;
2909 break;
2910 case 0x3cf:
2911 if (cirrus_hook_write_gr(s, s->gr_index, val))
2912 break;
2913 #ifdef DEBUG_VGA_REG
2914 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2915 #endif
2916 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2917 break;
2918 case 0x3b4:
2919 case 0x3d4:
2920 s->cr_index = val;
2921 break;
2922 case 0x3b5:
2923 case 0x3d5:
2924 if (cirrus_hook_write_cr(s, s->cr_index, val))
2925 break;
2926 #ifdef DEBUG_VGA_REG
2927 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2928 #endif
2929 /* handle CR0-7 protection */
2930 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2931 /* can always write bit 4 of CR7 */
2932 if (s->cr_index == 7)
2933 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2934 return;
2935 }
2936 switch (s->cr_index) {
2937 case 0x01: /* horizontal display end */
2938 case 0x07:
2939 case 0x09:
2940 case 0x0c:
2941 case 0x0d:
2942 case 0x12: /* vertical display end */
2943 s->cr[s->cr_index] = val;
2944 break;
2945
2946 default:
2947 s->cr[s->cr_index] = val;
2948 break;
2949 }
2950
2951 switch(s->cr_index) {
2952 case 0x00:
2953 case 0x04:
2954 case 0x05:
2955 case 0x06:
2956 case 0x07:
2957 case 0x11:
2958 case 0x17:
2959 s->update_retrace_info((VGAState *) s);
2960 break;
2961 }
2962 break;
2963 case 0x3ba:
2964 case 0x3da:
2965 s->fcr = val & 0x10;
2966 break;
2967 }
2968 }
2969
2970 /***************************************
2971 *
2972 * memory-mapped I/O access
2973 *
2974 ***************************************/
2975
2976 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2977 {
2978 CirrusVGAState *s = (CirrusVGAState *) opaque;
2979
2980 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2981
2982 if (addr >= 0x100) {
2983 return cirrus_mmio_blt_read(s, addr - 0x100);
2984 } else {
2985 return vga_ioport_read(s, addr + 0x3c0);
2986 }
2987 }
2988
2989 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2990 {
2991 uint32_t v;
2992 #ifdef TARGET_WORDS_BIGENDIAN
2993 v = cirrus_mmio_readb(opaque, addr) << 8;
2994 v |= cirrus_mmio_readb(opaque, addr + 1);
2995 #else
2996 v = cirrus_mmio_readb(opaque, addr);
2997 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2998 #endif
2999 return v;
3000 }
3001
3002 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3003 {
3004 uint32_t v;
3005 #ifdef TARGET_WORDS_BIGENDIAN
3006 v = cirrus_mmio_readb(opaque, addr) << 24;
3007 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3008 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3009 v |= cirrus_mmio_readb(opaque, addr + 3);
3010 #else
3011 v = cirrus_mmio_readb(opaque, addr);
3012 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3013 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3014 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3015 #endif
3016 return v;
3017 }
3018
3019 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3020 uint32_t val)
3021 {
3022 CirrusVGAState *s = (CirrusVGAState *) opaque;
3023
3024 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3025
3026 if (addr >= 0x100) {
3027 cirrus_mmio_blt_write(s, addr - 0x100, val);
3028 } else {
3029 vga_ioport_write(s, addr + 0x3c0, val);
3030 }
3031 }
3032
3033 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3034 uint32_t val)
3035 {
3036 #ifdef TARGET_WORDS_BIGENDIAN
3037 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3038 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3039 #else
3040 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3041 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3042 #endif
3043 }
3044
3045 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3046 uint32_t val)
3047 {
3048 #ifdef TARGET_WORDS_BIGENDIAN
3049 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3050 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3051 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3052 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3053 #else
3054 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3055 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3056 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3057 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3058 #endif
3059 }
3060
3061
3062 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3063 cirrus_mmio_readb,
3064 cirrus_mmio_readw,
3065 cirrus_mmio_readl,
3066 };
3067
3068 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3069 cirrus_mmio_writeb,
3070 cirrus_mmio_writew,
3071 cirrus_mmio_writel,
3072 };
3073
3074 /* load/save state */
3075
3076 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3077 {
3078 CirrusVGAState *s = opaque;
3079
3080 if (s->pci_dev)
3081 pci_device_save(s->pci_dev, f);
3082
3083 qemu_put_be32s(f, &s->latch);
3084 qemu_put_8s(f, &s->sr_index);
3085 qemu_put_buffer(f, s->sr, 256);
3086 qemu_put_8s(f, &s->gr_index);
3087 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3088 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3089 qemu_put_buffer(f, s->gr + 2, 254);
3090 qemu_put_8s(f, &s->ar_index);
3091 qemu_put_buffer(f, s->ar, 21);
3092 qemu_put_be32(f, s->ar_flip_flop);
3093 qemu_put_8s(f, &s->cr_index);
3094 qemu_put_buffer(f, s->cr, 256);
3095 qemu_put_8s(f, &s->msr);
3096 qemu_put_8s(f, &s->fcr);
3097 qemu_put_8s(f, &s->st00);
3098 qemu_put_8s(f, &s->st01);
3099
3100 qemu_put_8s(f, &s->dac_state);
3101 qemu_put_8s(f, &s->dac_sub_index);
3102 qemu_put_8s(f, &s->dac_read_index);
3103 qemu_put_8s(f, &s->dac_write_index);
3104 qemu_put_buffer(f, s->dac_cache, 3);
3105 qemu_put_buffer(f, s->palette, 768);
3106
3107 qemu_put_be32(f, s->bank_offset);
3108
3109 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3110 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3111
3112 qemu_put_be32s(f, &s->hw_cursor_x);
3113 qemu_put_be32s(f, &s->hw_cursor_y);
3114 /* XXX: we do not save the bitblt state - we assume we do not save
3115 the state when the blitter is active */
3116 }
3117
3118 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3119 {
3120 CirrusVGAState *s = opaque;
3121 int ret;
3122
3123 if (version_id > 2)
3124 return -EINVAL;
3125
3126 if (s->pci_dev && version_id >= 2) {
3127 ret = pci_device_load(s->pci_dev, f);
3128 if (ret < 0)
3129 return ret;
3130 }
3131
3132 qemu_get_be32s(f, &s->latch);
3133 qemu_get_8s(f, &s->sr_index);
3134 qemu_get_buffer(f, s->sr, 256);
3135 qemu_get_8s(f, &s->gr_index);
3136 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3137 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3138 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3139 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3140 qemu_get_buffer(f, s->gr + 2, 254);
3141 qemu_get_8s(f, &s->ar_index);
3142 qemu_get_buffer(f, s->ar, 21);
3143 s->ar_flip_flop=qemu_get_be32(f);
3144 qemu_get_8s(f, &s->cr_index);
3145 qemu_get_buffer(f, s->cr, 256);
3146 qemu_get_8s(f, &s->msr);
3147 qemu_get_8s(f, &s->fcr);
3148 qemu_get_8s(f, &s->st00);
3149 qemu_get_8s(f, &s->st01);
3150
3151 qemu_get_8s(f, &s->dac_state);
3152 qemu_get_8s(f, &s->dac_sub_index);
3153 qemu_get_8s(f, &s->dac_read_index);
3154 qemu_get_8s(f, &s->dac_write_index);
3155 qemu_get_buffer(f, s->dac_cache, 3);
3156 qemu_get_buffer(f, s->palette, 768);
3157
3158 s->bank_offset=qemu_get_be32(f);
3159
3160 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3161 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3162
3163 qemu_get_be32s(f, &s->hw_cursor_x);
3164 qemu_get_be32s(f, &s->hw_cursor_y);
3165
3166 cirrus_update_memory_access(s);
3167 /* force refresh */
3168 s->graphic_mode = -1;
3169 cirrus_update_bank_ptr(s, 0);
3170 cirrus_update_bank_ptr(s, 1);
3171 return 0;
3172 }
3173
3174 /***************************************
3175 *
3176 * initialize
3177 *
3178 ***************************************/
3179
3180 static void cirrus_reset(void *opaque)
3181 {
3182 CirrusVGAState *s = opaque;
3183
3184 vga_reset(s);
3185 s->sr[0x06] = 0x0f;
3186 if (s->device_id == CIRRUS_ID_CLGD5446) {
3187 /* 4MB 64 bit memory config, always PCI */
3188 s->sr[0x1F] = 0x2d; // MemClock
3189 s->gr[0x18] = 0x0f; // fastest memory configuration
3190 #if 1
3191 s->sr[0x0f] = 0x98;
3192 s->sr[0x17] = 0x20;
3193 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3194 s->real_vram_size = 4096 * 1024;
3195 #else
3196 s->sr[0x0f] = 0x18;
3197 s->sr[0x17] = 0x20;
3198 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3199 s->real_vram_size = 2048 * 1024;
3200 #endif
3201 } else {
3202 s->sr[0x1F] = 0x22; // MemClock
3203 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3204 s->sr[0x17] = s->bustype;
3205 s->real_vram_size = 2048 * 1024;
3206 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3207 }
3208 s->cr[0x27] = s->device_id;
3209
3210 /* Win2K seems to assume that the pattern buffer is at 0xff
3211 initially ! */
3212 memset(s->vram_ptr, 0xff, s->real_vram_size);
3213
3214 s->cirrus_hidden_dac_lockindex = 5;
3215 s->cirrus_hidden_dac_data = 0;
3216
3217 /* I/O handler for LFB */
3218 s->cirrus_linear_io_addr =
3219 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3220 s);
3221 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3222
3223 /* I/O handler for LFB */
3224 s->cirrus_linear_bitblt_io_addr =
3225 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3226 s);
3227
3228 /* I/O handler for memory-mapped I/O */
3229 s->cirrus_mmio_io_addr =
3230 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3231
3232 /* XXX: s->vram_size must be a power of two */
3233 s->cirrus_addr_mask = s->real_vram_size - 1;
3234 s->linear_mmio_mask = s->real_vram_size - 256;
3235
3236 s->get_bpp = cirrus_get_bpp;
3237 s->get_offsets = cirrus_get_offsets;
3238 s->get_resolution = cirrus_get_resolution;
3239 s->cursor_invalidate = cirrus_cursor_invalidate;
3240 s->cursor_draw_line = cirrus_cursor_draw_line;
3241 }
3242
3243 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3244 {
3245 int i;
3246 static int inited;
3247
3248 if (!inited) {
3249 inited = 1;
3250 for(i = 0;i < 256; i++)
3251 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3252 rop_to_index[CIRRUS_ROP_0] = 0;
3253 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3254 rop_to_index[CIRRUS_ROP_NOP] = 2;
3255 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3256 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3257 rop_to_index[CIRRUS_ROP_SRC] = 5;
3258 rop_to_index[CIRRUS_ROP_1] = 6;
3259 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3260 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3261 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3262 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3263 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3264 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3265 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3266 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3267 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3268 s->device_id = device_id;
3269 if (is_pci)
3270 s->bustype = CIRRUS_BUSTYPE_PCI;
3271 else
3272 s->bustype = CIRRUS_BUSTYPE_ISA;
3273 }
3274
3275 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3276
3277 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3278 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3279 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3280 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3281
3282 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3283
3284 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3285 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3286 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3287 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3288
3289 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3290 cirrus_vga_mem_write, s);
3291 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3292 s->vga_io_memory);
3293 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3294
3295 qemu_register_reset(cirrus_reset, s);
3296 cirrus_reset(s);
3297 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3298 }
3299
3300 /***************************************
3301 *
3302 * ISA bus support
3303 *
3304 ***************************************/
3305
3306 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3307 ram_addr_t vga_ram_offset, int vga_ram_size)
3308 {
3309 CirrusVGAState *s;
3310
3311 s = qemu_mallocz(sizeof(CirrusVGAState));
3312
3313 vga_common_init((VGAState *)s,
3314 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3315 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3316 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3317 s->screen_dump, s->text_update, s);
3318 /* XXX ISA-LFB support */
3319 }
3320
3321 /***************************************
3322 *
3323 * PCI bus support
3324 *
3325 ***************************************/
3326
3327 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3328 uint32_t addr, uint32_t size, int type)
3329 {
3330 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3331
3332 /* XXX: add byte swapping apertures */
3333 cpu_register_physical_memory(addr, s->vram_size,
3334 s->cirrus_linear_io_addr);
3335 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3336 s->cirrus_linear_bitblt_io_addr);
3337
3338 s->map_addr = s->map_end = 0;
3339 s->lfb_addr = addr & TARGET_PAGE_MASK;
3340 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3341 /* account for overflow */
3342 if (s->lfb_end < addr + VGA_RAM_SIZE)
3343 s->lfb_end = addr + VGA_RAM_SIZE;
3344 }
3345
3346 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3347 uint32_t addr, uint32_t size, int type)
3348 {
3349 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3350
3351 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3352 s->cirrus_mmio_io_addr);
3353 }
3354
3355 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3356 ram_addr_t vga_ram_offset, int vga_ram_size)
3357 {
3358 PCICirrusVGAState *d;
3359 uint8_t *pci_conf;
3360 CirrusVGAState *s;
3361 int device_id;
3362
3363 device_id = CIRRUS_ID_CLGD5446;
3364
3365 /* setup PCI configuration registers */
3366 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3367 sizeof(PCICirrusVGAState),
3368 -1, NULL, NULL);
3369 pci_conf = d->dev.config;
3370 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3371 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3372 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3373 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3374 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3375 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3376 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3377 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3378
3379 /* setup VGA */
3380 s = &d->cirrus_vga;
3381 vga_common_init((VGAState *)s,
3382 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3383 cirrus_init_common(s, device_id, 1);
3384
3385 s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3386 s->screen_dump, s->text_update, s);
3387
3388 s->pci_dev = (PCIDevice *)d;
3389
3390 /* setup memory space */
3391 /* memory #0 LFB */
3392 /* memory #1 memory-mapped I/O */
3393 /* XXX: s->vram_size must be a power of two */
3394 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3395 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3396 if (device_id == CIRRUS_ID_CLGD5446) {
3397 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3398 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3399 }
3400 /* XXX: ROM BIOS */
3401 }
jz4740 based target emulation