?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
fix spell error. pvao->pavo
[qemu/qemu-JZ.git] / hw / sun4m.c
blobe6a538a9f358c3233f9b9bb6b88a16d632a4e810
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38
39 //#define DEBUG_IRQ
40
41 /*
42 * Sun4m architecture was used in the following machines:
43 *
44 * SPARCserver 6xxMP/xx
45 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
46 * SPARCclassic X (4/10)
47 * SPARCstation LX/ZX (4/30)
48 * SPARCstation Voyager
49 * SPARCstation 10/xx, SPARCserver 10/xx
50 * SPARCstation 5, SPARCserver 5
51 * SPARCstation 20/xx, SPARCserver 20
52 * SPARCstation 4
53 *
54 * Sun4d architecture was used in the following machines:
55 *
56 * SPARCcenter 2000
57 * SPARCserver 1000
58 *
59 * Sun4c architecture was used in the following machines:
60 * SPARCstation 1/1+, SPARCserver 1/1+
61 * SPARCstation SLC
62 * SPARCstation IPC
63 * SPARCstation ELC
64 * SPARCstation IPX
65 *
66 * See for example: http://www.sunhelp.org/faq/sunref1.html
67 */
68
69 #ifdef DEBUG_IRQ
70 #define DPRINTF(fmt, args...) \
71 do { printf("CPUIRQ: " fmt , ##args); } while (0)
72 #else
73 #define DPRINTF(fmt, args...)
74 #endif
75
76 #define KERNEL_LOAD_ADDR 0x00004000
77 #define CMDLINE_ADDR 0x007ff000
78 #define INITRD_LOAD_ADDR 0x00800000
79 #define PROM_SIZE_MAX (1024 * 1024)
80 #define PROM_VADDR 0xffd00000
81 #define PROM_FILENAME "openbios-sparc32"
82 #define CFG_ADDR 0xd00000510ULL
83 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
84
85 // Control plane, 8-bit and 24-bit planes
86 #define TCX_SIZE (9 * 1024 * 1024)
87
88 #define MAX_CPUS 16
89 #define MAX_PILS 16
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int nvram_boot_set(void *opaque, const char *boot_device)
175 {
176 unsigned int i;
177 uint8_t image[sizeof(ohwcfg_v3_t)];
178 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
179 m48t59_t *nvram = (m48t59_t *)opaque;
180
181 for (i = 0; i < sizeof(image); i++)
182 image[i] = m48t59_read(nvram, i) & 0xff;
183
184 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
185 boot_device);
186 header->nboot_devices = strlen(boot_device) & 0xff;
187 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
188
189 for (i = 0; i < sizeof(image); i++)
190 m48t59_write(nvram, i, image[i]);
191
192 return 0;
193 }
194
195 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
196 const char *boot_devices, ram_addr_t RAM_size,
197 uint32_t kernel_size,
198 int width, int height, int depth,
199 int nvram_machine_id, const char *arch)
200 {
201 unsigned int i;
202 uint32_t start, end;
203 uint8_t image[0x1ff0];
204 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
205 struct sparc_arch_cfg *sparc_header;
206 struct OpenBIOS_nvpart_v1 *part_header;
207
208 memset(image, '\0', sizeof(image));
209
210 // Try to match PPC NVRAM
211 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
212 "QEMU_BIOS");
213 header->struct_version = cpu_to_be32(3); /* structure v3 */
214
215 header->nvram_size = cpu_to_be16(0x2000);
216 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
217 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
218 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
219 header->nb_cpus = smp_cpus & 0xff;
220 header->RAM0_base = 0;
221 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
222 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
223 boot_devices);
224 header->nboot_devices = strlen(boot_devices) & 0xff;
225 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
226 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
227 if (cmdline) {
228 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
229 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
230 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
231 }
232 // XXX add initrd_image, initrd_size
233 header->width = cpu_to_be16(width);
234 header->height = cpu_to_be16(height);
235 header->depth = cpu_to_be16(depth);
236 if (nographic)
237 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
238
239 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
240
241 // Architecture specific header
242 start = sizeof(ohwcfg_v3_t);
243 sparc_header = (struct sparc_arch_cfg *)&image[start];
244 sparc_header->valid = 0;
245 start += sizeof(struct sparc_arch_cfg);
246
247 // OpenBIOS nvram variables
248 // Variable partition
249 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
250 part_header->signature = OPENBIOS_PART_SYSTEM;
251 pstrcpy(part_header->name, sizeof(part_header->name), "system");
252
253 end = start + sizeof(struct OpenBIOS_nvpart_v1);
254 for (i = 0; i < nb_prom_envs; i++)
255 end = OpenBIOS_set_var(image, end, prom_envs[i]);
256
257 // End marker
258 image[end++] = '\0';
259
260 end = start + ((end - start + 15) & ~15);
261 OpenBIOS_finish_partition(part_header, end - start);
262
263 // free partition
264 start = end;
265 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
266 part_header->signature = OPENBIOS_PART_FREE;
267 pstrcpy(part_header->name, sizeof(part_header->name), "free");
268
269 end = 0x1fd0;
270 OpenBIOS_finish_partition(part_header, end - start);
271
272 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
273 nvram_machine_id);
274
275 for (i = 0; i < sizeof(image); i++)
276 m48t59_write(nvram, i, image[i]);
277
278 qemu_register_boot_set(nvram_boot_set, nvram);
279 }
280
281 static void *slavio_intctl;
282
283 void pic_info(void)
284 {
285 if (slavio_intctl)
286 slavio_pic_info(slavio_intctl);
287 }
288
289 void irq_info(void)
290 {
291 if (slavio_intctl)
292 slavio_irq_info(slavio_intctl);
293 }
294
295 void cpu_check_irqs(CPUState *env)
296 {
297 if (env->pil_in && (env->interrupt_index == 0 ||
298 (env->interrupt_index & ~15) == TT_EXTINT)) {
299 unsigned int i;
300
301 for (i = 15; i > 0; i--) {
302 if (env->pil_in & (1 << i)) {
303 int old_interrupt = env->interrupt_index;
304
305 env->interrupt_index = TT_EXTINT | i;
306 if (old_interrupt != env->interrupt_index) {
307 DPRINTF("Set CPU IRQ %d\n", i);
308 cpu_interrupt(env, CPU_INTERRUPT_HARD);
309 }
310 break;
311 }
312 }
313 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
314 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
315 env->interrupt_index = 0;
316 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
317 }
318 }
319
320 static void cpu_set_irq(void *opaque, int irq, int level)
321 {
322 CPUState *env = opaque;
323
324 if (level) {
325 DPRINTF("Raise CPU IRQ %d\n", irq);
326 env->halted = 0;
327 env->pil_in |= 1 << irq;
328 cpu_check_irqs(env);
329 } else {
330 DPRINTF("Lower CPU IRQ %d\n", irq);
331 env->pil_in &= ~(1 << irq);
332 cpu_check_irqs(env);
333 }
334 }
335
336 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
337 {
338 }
339
340 static void *slavio_misc;
341
342 void qemu_system_powerdown(void)
343 {
344 slavio_set_power_fail(slavio_misc, 1);
345 }
346
347 static void main_cpu_reset(void *opaque)
348 {
349 CPUState *env = opaque;
350
351 cpu_reset(env);
352 env->halted = 0;
353 }
354
355 static void secondary_cpu_reset(void *opaque)
356 {
357 CPUState *env = opaque;
358
359 cpu_reset(env);
360 env->halted = 1;
361 }
362
363 static void cpu_halt_signal(void *opaque, int irq, int level)
364 {
365 if (level && cpu_single_env)
366 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
367 }
368
369 static unsigned long sun4m_load_kernel(const char *kernel_filename,
370 const char *initrd_filename,
371 ram_addr_t RAM_size)
372 {
373 int linux_boot;
374 unsigned int i;
375 long initrd_size, kernel_size;
376
377 linux_boot = (kernel_filename != NULL);
378
379 kernel_size = 0;
380 if (linux_boot) {
381 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
382 NULL);
383 if (kernel_size < 0)
384 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
385 RAM_size - KERNEL_LOAD_ADDR);
386 if (kernel_size < 0)
387 kernel_size = load_image_targphys(kernel_filename,
388 KERNEL_LOAD_ADDR,
389 RAM_size - KERNEL_LOAD_ADDR);
390 if (kernel_size < 0) {
391 fprintf(stderr, "qemu: could not load kernel '%s'\n",
392 kernel_filename);
393 exit(1);
394 }
395
396 /* load initrd */
397 initrd_size = 0;
398 if (initrd_filename) {
399 initrd_size = load_image_targphys(initrd_filename,
400 INITRD_LOAD_ADDR,
401 RAM_size - INITRD_LOAD_ADDR);
402 if (initrd_size < 0) {
403 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
404 initrd_filename);
405 exit(1);
406 }
407 }
408 if (initrd_size > 0) {
409 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
410 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
411 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
412 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
413 break;
414 }
415 }
416 }
417 }
418 return kernel_size;
419 }
420
421 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
422 const char *boot_device,
423 DisplayState *ds, const char *kernel_filename,
424 const char *kernel_cmdline,
425 const char *initrd_filename, const char *cpu_model)
426
427 {
428 CPUState *env, *envs[MAX_CPUS];
429 unsigned int i;
430 void *iommu, *espdma, *ledma, *main_esp, *nvram;
431 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
432 *espdma_irq, *ledma_irq;
433 qemu_irq *esp_reset, *le_reset;
434 qemu_irq *fdc_tc;
435 qemu_irq *cpu_halt;
436 ram_addr_t ram_offset, prom_offset, tcx_offset, idreg_offset;
437 unsigned long kernel_size;
438 int ret;
439 char buf[1024];
440 BlockDriverState *fd[MAX_FD];
441 int drive_index;
442 void *fw_cfg;
443
444 /* init CPUs */
445 if (!cpu_model)
446 cpu_model = hwdef->default_cpu_model;
447
448 for(i = 0; i < smp_cpus; i++) {
449 env = cpu_init(cpu_model);
450 if (!env) {
451 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
452 exit(1);
453 }
454 cpu_sparc_set_id(env, i);
455 envs[i] = env;
456 if (i == 0) {
457 qemu_register_reset(main_cpu_reset, env);
458 } else {
459 qemu_register_reset(secondary_cpu_reset, env);
460 env->halted = 1;
461 }
462 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
463 env->prom_addr = hwdef->slavio_base;
464 }
465
466 for (i = smp_cpus; i < MAX_CPUS; i++)
467 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
468
469
470 /* allocate RAM */
471 if ((uint64_t)RAM_size > hwdef->max_mem) {
472 fprintf(stderr,
473 "qemu: Too much memory for this machine: %d, maximum %d\n",
474 (unsigned int)(RAM_size / (1024 * 1024)),
475 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
476 exit(1);
477 }
478 ram_offset = qemu_ram_alloc(RAM_size);
479 cpu_register_physical_memory(0, RAM_size, ram_offset);
480
481 /* load boot prom */
482 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
483 cpu_register_physical_memory(hwdef->slavio_base,
484 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
485 TARGET_PAGE_MASK,
486 prom_offset | IO_MEM_ROM);
487
488 if (bios_name == NULL)
489 bios_name = PROM_FILENAME;
490 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
491 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
492 if (ret < 0 || ret > PROM_SIZE_MAX)
493 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
494 if (ret < 0 || ret > PROM_SIZE_MAX) {
495 fprintf(stderr, "qemu: could not load prom '%s'\n",
496 buf);
497 exit(1);
498 }
499
500 /* set up devices */
501 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
502 hwdef->intctl_base + 0x10000ULL,
503 &hwdef->intbit_to_level[0],
504 &slavio_irq, &slavio_cpu_irq,
505 cpu_irqs,
506 hwdef->clock_irq);
507
508 if (hwdef->idreg_base) {
509 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
510
511 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
512 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
513 idreg_offset | IO_MEM_ROM);
514 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
515 sizeof(idreg_data));
516 }
517
518 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
519 slavio_irq[hwdef->me_irq]);
520
521 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
522 iommu, &espdma_irq, &esp_reset);
523
524 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
525 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
526 &le_reset);
527
528 if (graphic_depth != 8 && graphic_depth != 24) {
529 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
530 exit (1);
531 }
532 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
533 tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
534 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
535
536 if (nd_table[0].model == NULL
537 || strcmp(nd_table[0].model, "lance") == 0) {
538 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
539 } else if (strcmp(nd_table[0].model, "?") == 0) {
540 fprintf(stderr, "qemu: Supported NICs: lance\n");
541 exit (1);
542 } else {
543 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
544 exit (1);
545 }
546
547 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
548 hwdef->nvram_size, 8);
549
550 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
551 slavio_cpu_irq, smp_cpus);
552
553 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
554 nographic);
555 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
556 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
557 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
558 serial_hds[1], serial_hds[0]);
559
560 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
561 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
562 hwdef->aux1_base, hwdef->aux2_base,
563 slavio_irq[hwdef->me_irq], cpu_halt[0],
564 &fdc_tc);
565
566 if (hwdef->fd_base) {
567 /* there is zero or one floppy drive */
568 memset(fd, 0, sizeof(fd));
569 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
570 if (drive_index != -1)
571 fd[0] = drives_table[drive_index].bdrv;
572
573 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
574 fdc_tc);
575 }
576
577 if (drive_get_max_bus(IF_SCSI) > 0) {
578 fprintf(stderr, "qemu: too many SCSI bus\n");
579 exit(1);
580 }
581
582 main_esp = esp_init(hwdef->esp_base, 2,
583 espdma_memory_read, espdma_memory_write,
584 espdma, *espdma_irq, esp_reset);
585
586 for (i = 0; i < ESP_MAX_DEVS; i++) {
587 drive_index = drive_get_index(IF_SCSI, 0, i);
588 if (drive_index == -1)
589 continue;
590 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
591 }
592
593 if (hwdef->cs_base)
594 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
595
596 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
597 RAM_size);
598
599 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
600 boot_device, RAM_size, kernel_size, graphic_width,
601 graphic_height, graphic_depth, hwdef->nvram_machine_id,
602 "Sun4m");
603
604 if (hwdef->ecc_base)
605 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
606 hwdef->ecc_version);
607
608 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
609 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
610 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
611 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
612 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
613 }
614
615 enum {
616 ss2_id = 0,
617 ss5_id = 32,
618 vger_id,
619 lx_id,
620 ss4_id,
621 scls_id,
622 sbook_id,
623 ss10_id = 64,
624 ss20_id,
625 ss600mp_id,
626 ss1000_id = 96,
627 ss2000_id,
628 };
629
630 static const struct sun4m_hwdef sun4m_hwdefs[] = {
631 /* SS-5 */
632 {
633 .iommu_base = 0x10000000,
634 .tcx_base = 0x50000000,
635 .cs_base = 0x6c000000,
636 .slavio_base = 0x70000000,
637 .ms_kb_base = 0x71000000,
638 .serial_base = 0x71100000,
639 .nvram_base = 0x71200000,
640 .fd_base = 0x71400000,
641 .counter_base = 0x71d00000,
642 .intctl_base = 0x71e00000,
643 .idreg_base = 0x78000000,
644 .dma_base = 0x78400000,
645 .esp_base = 0x78800000,
646 .le_base = 0x78c00000,
647 .apc_base = 0x6a000000,
648 .aux1_base = 0x71900000,
649 .aux2_base = 0x71910000,
650 .vram_size = 0x00100000,
651 .nvram_size = 0x2000,
652 .esp_irq = 18,
653 .le_irq = 16,
654 .clock_irq = 7,
655 .clock1_irq = 19,
656 .ms_kb_irq = 14,
657 .ser_irq = 15,
658 .fd_irq = 22,
659 .me_irq = 30,
660 .cs_irq = 5,
661 .nvram_machine_id = 0x80,
662 .machine_id = ss5_id,
663 .iommu_version = 0x05000000,
664 .intbit_to_level = {
665 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
666 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
667 },
668 .max_mem = 0x10000000,
669 .default_cpu_model = "Fujitsu MB86904",
670 },
671 /* SS-10 */
672 {
673 .iommu_base = 0xfe0000000ULL,
674 .tcx_base = 0xe20000000ULL,
675 .slavio_base = 0xff0000000ULL,
676 .ms_kb_base = 0xff1000000ULL,
677 .serial_base = 0xff1100000ULL,
678 .nvram_base = 0xff1200000ULL,
679 .fd_base = 0xff1700000ULL,
680 .counter_base = 0xff1300000ULL,
681 .intctl_base = 0xff1400000ULL,
682 .idreg_base = 0xef0000000ULL,
683 .dma_base = 0xef0400000ULL,
684 .esp_base = 0xef0800000ULL,
685 .le_base = 0xef0c00000ULL,
686 .apc_base = 0xefa000000ULL, // XXX should not exist
687 .aux1_base = 0xff1800000ULL,
688 .aux2_base = 0xff1a01000ULL,
689 .ecc_base = 0xf00000000ULL,
690 .ecc_version = 0x10000000, // version 0, implementation 1
691 .vram_size = 0x00100000,
692 .nvram_size = 0x2000,
693 .esp_irq = 18,
694 .le_irq = 16,
695 .clock_irq = 7,
696 .clock1_irq = 19,
697 .ms_kb_irq = 14,
698 .ser_irq = 15,
699 .fd_irq = 22,
700 .me_irq = 30,
701 .ecc_irq = 28,
702 .nvram_machine_id = 0x72,
703 .machine_id = ss10_id,
704 .iommu_version = 0x03000000,
705 .intbit_to_level = {
706 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
707 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
708 },
709 .max_mem = 0xf00000000ULL,
710 .default_cpu_model = "TI SuperSparc II",
711 },
712 /* SS-600MP */
713 {
714 .iommu_base = 0xfe0000000ULL,
715 .tcx_base = 0xe20000000ULL,
716 .slavio_base = 0xff0000000ULL,
717 .ms_kb_base = 0xff1000000ULL,
718 .serial_base = 0xff1100000ULL,
719 .nvram_base = 0xff1200000ULL,
720 .counter_base = 0xff1300000ULL,
721 .intctl_base = 0xff1400000ULL,
722 .dma_base = 0xef0081000ULL,
723 .esp_base = 0xef0080000ULL,
724 .le_base = 0xef0060000ULL,
725 .apc_base = 0xefa000000ULL, // XXX should not exist
726 .aux1_base = 0xff1800000ULL,
727 .aux2_base = 0xff1a01000ULL, // XXX should not exist
728 .ecc_base = 0xf00000000ULL,
729 .ecc_version = 0x00000000, // version 0, implementation 0
730 .vram_size = 0x00100000,
731 .nvram_size = 0x2000,
732 .esp_irq = 18,
733 .le_irq = 16,
734 .clock_irq = 7,
735 .clock1_irq = 19,
736 .ms_kb_irq = 14,
737 .ser_irq = 15,
738 .fd_irq = 22,
739 .me_irq = 30,
740 .ecc_irq = 28,
741 .nvram_machine_id = 0x71,
742 .machine_id = ss600mp_id,
743 .iommu_version = 0x01000000,
744 .intbit_to_level = {
745 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
746 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
747 },
748 .max_mem = 0xf00000000ULL,
749 .default_cpu_model = "TI SuperSparc II",
750 },
751 /* SS-20 */
752 {
753 .iommu_base = 0xfe0000000ULL,
754 .tcx_base = 0xe20000000ULL,
755 .slavio_base = 0xff0000000ULL,
756 .ms_kb_base = 0xff1000000ULL,
757 .serial_base = 0xff1100000ULL,
758 .nvram_base = 0xff1200000ULL,
759 .fd_base = 0xff1700000ULL,
760 .counter_base = 0xff1300000ULL,
761 .intctl_base = 0xff1400000ULL,
762 .idreg_base = 0xef0000000ULL,
763 .dma_base = 0xef0400000ULL,
764 .esp_base = 0xef0800000ULL,
765 .le_base = 0xef0c00000ULL,
766 .apc_base = 0xefa000000ULL, // XXX should not exist
767 .aux1_base = 0xff1800000ULL,
768 .aux2_base = 0xff1a01000ULL,
769 .ecc_base = 0xf00000000ULL,
770 .ecc_version = 0x20000000, // version 0, implementation 2
771 .vram_size = 0x00100000,
772 .nvram_size = 0x2000,
773 .esp_irq = 18,
774 .le_irq = 16,
775 .clock_irq = 7,
776 .clock1_irq = 19,
777 .ms_kb_irq = 14,
778 .ser_irq = 15,
779 .fd_irq = 22,
780 .me_irq = 30,
781 .ecc_irq = 28,
782 .nvram_machine_id = 0x72,
783 .machine_id = ss20_id,
784 .iommu_version = 0x13000000,
785 .intbit_to_level = {
786 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
787 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
788 },
789 .max_mem = 0xf00000000ULL,
790 .default_cpu_model = "TI SuperSparc II",
791 },
792 /* Voyager */
793 {
794 .iommu_base = 0x10000000,
795 .tcx_base = 0x50000000,
796 .slavio_base = 0x70000000,
797 .ms_kb_base = 0x71000000,
798 .serial_base = 0x71100000,
799 .nvram_base = 0x71200000,
800 .fd_base = 0x71400000,
801 .counter_base = 0x71d00000,
802 .intctl_base = 0x71e00000,
803 .idreg_base = 0x78000000,
804 .dma_base = 0x78400000,
805 .esp_base = 0x78800000,
806 .le_base = 0x78c00000,
807 .apc_base = 0x71300000, // pmc
808 .aux1_base = 0x71900000,
809 .aux2_base = 0x71910000,
810 .vram_size = 0x00100000,
811 .nvram_size = 0x2000,
812 .esp_irq = 18,
813 .le_irq = 16,
814 .clock_irq = 7,
815 .clock1_irq = 19,
816 .ms_kb_irq = 14,
817 .ser_irq = 15,
818 .fd_irq = 22,
819 .me_irq = 30,
820 .nvram_machine_id = 0x80,
821 .machine_id = vger_id,
822 .iommu_version = 0x05000000,
823 .intbit_to_level = {
824 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
825 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
826 },
827 .max_mem = 0x10000000,
828 .default_cpu_model = "Fujitsu MB86904",
829 },
830 /* LX */
831 {
832 .iommu_base = 0x10000000,
833 .tcx_base = 0x50000000,
834 .slavio_base = 0x70000000,
835 .ms_kb_base = 0x71000000,
836 .serial_base = 0x71100000,
837 .nvram_base = 0x71200000,
838 .fd_base = 0x71400000,
839 .counter_base = 0x71d00000,
840 .intctl_base = 0x71e00000,
841 .idreg_base = 0x78000000,
842 .dma_base = 0x78400000,
843 .esp_base = 0x78800000,
844 .le_base = 0x78c00000,
845 .aux1_base = 0x71900000,
846 .aux2_base = 0x71910000,
847 .vram_size = 0x00100000,
848 .nvram_size = 0x2000,
849 .esp_irq = 18,
850 .le_irq = 16,
851 .clock_irq = 7,
852 .clock1_irq = 19,
853 .ms_kb_irq = 14,
854 .ser_irq = 15,
855 .fd_irq = 22,
856 .me_irq = 30,
857 .nvram_machine_id = 0x80,
858 .machine_id = lx_id,
859 .iommu_version = 0x04000000,
860 .intbit_to_level = {
861 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
862 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
863 },
864 .max_mem = 0x10000000,
865 .default_cpu_model = "TI MicroSparc I",
866 },
867 /* SS-4 */
868 {
869 .iommu_base = 0x10000000,
870 .tcx_base = 0x50000000,
871 .cs_base = 0x6c000000,
872 .slavio_base = 0x70000000,
873 .ms_kb_base = 0x71000000,
874 .serial_base = 0x71100000,
875 .nvram_base = 0x71200000,
876 .fd_base = 0x71400000,
877 .counter_base = 0x71d00000,
878 .intctl_base = 0x71e00000,
879 .idreg_base = 0x78000000,
880 .dma_base = 0x78400000,
881 .esp_base = 0x78800000,
882 .le_base = 0x78c00000,
883 .apc_base = 0x6a000000,
884 .aux1_base = 0x71900000,
885 .aux2_base = 0x71910000,
886 .vram_size = 0x00100000,
887 .nvram_size = 0x2000,
888 .esp_irq = 18,
889 .le_irq = 16,
890 .clock_irq = 7,
891 .clock1_irq = 19,
892 .ms_kb_irq = 14,
893 .ser_irq = 15,
894 .fd_irq = 22,
895 .me_irq = 30,
896 .cs_irq = 5,
897 .nvram_machine_id = 0x80,
898 .machine_id = ss4_id,
899 .iommu_version = 0x05000000,
900 .intbit_to_level = {
901 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
902 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
903 },
904 .max_mem = 0x10000000,
905 .default_cpu_model = "Fujitsu MB86904",
906 },
907 /* SPARCClassic */
908 {
909 .iommu_base = 0x10000000,
910 .tcx_base = 0x50000000,
911 .slavio_base = 0x70000000,
912 .ms_kb_base = 0x71000000,
913 .serial_base = 0x71100000,
914 .nvram_base = 0x71200000,
915 .fd_base = 0x71400000,
916 .counter_base = 0x71d00000,
917 .intctl_base = 0x71e00000,
918 .idreg_base = 0x78000000,
919 .dma_base = 0x78400000,
920 .esp_base = 0x78800000,
921 .le_base = 0x78c00000,
922 .apc_base = 0x6a000000,
923 .aux1_base = 0x71900000,
924 .aux2_base = 0x71910000,
925 .vram_size = 0x00100000,
926 .nvram_size = 0x2000,
927 .esp_irq = 18,
928 .le_irq = 16,
929 .clock_irq = 7,
930 .clock1_irq = 19,
931 .ms_kb_irq = 14,
932 .ser_irq = 15,
933 .fd_irq = 22,
934 .me_irq = 30,
935 .nvram_machine_id = 0x80,
936 .machine_id = scls_id,
937 .iommu_version = 0x05000000,
938 .intbit_to_level = {
939 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
940 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
941 },
942 .max_mem = 0x10000000,
943 .default_cpu_model = "TI MicroSparc I",
944 },
945 /* SPARCbook */
946 {
947 .iommu_base = 0x10000000,
948 .tcx_base = 0x50000000, // XXX
949 .slavio_base = 0x70000000,
950 .ms_kb_base = 0x71000000,
951 .serial_base = 0x71100000,
952 .nvram_base = 0x71200000,
953 .fd_base = 0x71400000,
954 .counter_base = 0x71d00000,
955 .intctl_base = 0x71e00000,
956 .idreg_base = 0x78000000,
957 .dma_base = 0x78400000,
958 .esp_base = 0x78800000,
959 .le_base = 0x78c00000,
960 .apc_base = 0x6a000000,
961 .aux1_base = 0x71900000,
962 .aux2_base = 0x71910000,
963 .vram_size = 0x00100000,
964 .nvram_size = 0x2000,
965 .esp_irq = 18,
966 .le_irq = 16,
967 .clock_irq = 7,
968 .clock1_irq = 19,
969 .ms_kb_irq = 14,
970 .ser_irq = 15,
971 .fd_irq = 22,
972 .me_irq = 30,
973 .nvram_machine_id = 0x80,
974 .machine_id = sbook_id,
975 .iommu_version = 0x05000000,
976 .intbit_to_level = {
977 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
978 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
979 },
980 .max_mem = 0x10000000,
981 .default_cpu_model = "TI MicroSparc I",
982 },
983 };
984
985 /* SPARCstation 5 hardware initialisation */
986 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
987 const char *boot_device, DisplayState *ds,
988 const char *kernel_filename, const char *kernel_cmdline,
989 const char *initrd_filename, const char *cpu_model)
990 {
991 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
992 kernel_cmdline, initrd_filename, cpu_model);
993 }
994
995 /* SPARCstation 10 hardware initialisation */
996 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
997 const char *boot_device, DisplayState *ds,
998 const char *kernel_filename, const char *kernel_cmdline,
999 const char *initrd_filename, const char *cpu_model)
1000 {
1001 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1002 kernel_cmdline, initrd_filename, cpu_model);
1003 }
1004
1005 /* SPARCserver 600MP hardware initialisation */
1006 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1007 const char *boot_device, DisplayState *ds,
1008 const char *kernel_filename,
1009 const char *kernel_cmdline,
1010 const char *initrd_filename, const char *cpu_model)
1011 {
1012 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1013 kernel_cmdline, initrd_filename, cpu_model);
1014 }
1015
1016 /* SPARCstation 20 hardware initialisation */
1017 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1018 const char *boot_device, DisplayState *ds,
1019 const char *kernel_filename, const char *kernel_cmdline,
1020 const char *initrd_filename, const char *cpu_model)
1021 {
1022 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1023 kernel_cmdline, initrd_filename, cpu_model);
1024 }
1025
1026 /* SPARCstation Voyager hardware initialisation */
1027 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1028 const char *boot_device, DisplayState *ds,
1029 const char *kernel_filename, const char *kernel_cmdline,
1030 const char *initrd_filename, const char *cpu_model)
1031 {
1032 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1033 kernel_cmdline, initrd_filename, cpu_model);
1034 }
1035
1036 /* SPARCstation LX hardware initialisation */
1037 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1038 const char *boot_device, DisplayState *ds,
1039 const char *kernel_filename, const char *kernel_cmdline,
1040 const char *initrd_filename, const char *cpu_model)
1041 {
1042 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1043 kernel_cmdline, initrd_filename, cpu_model);
1044 }
1045
1046 /* SPARCstation 4 hardware initialisation */
1047 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1048 const char *boot_device, DisplayState *ds,
1049 const char *kernel_filename, const char *kernel_cmdline,
1050 const char *initrd_filename, const char *cpu_model)
1051 {
1052 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1053 kernel_cmdline, initrd_filename, cpu_model);
1054 }
1055
1056 /* SPARCClassic hardware initialisation */
1057 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1058 const char *boot_device, DisplayState *ds,
1059 const char *kernel_filename, const char *kernel_cmdline,
1060 const char *initrd_filename, const char *cpu_model)
1061 {
1062 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1063 kernel_cmdline, initrd_filename, cpu_model);
1064 }
1065
1066 /* SPARCbook hardware initialisation */
1067 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1068 const char *boot_device, DisplayState *ds,
1069 const char *kernel_filename, const char *kernel_cmdline,
1070 const char *initrd_filename, const char *cpu_model)
1071 {
1072 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1073 kernel_cmdline, initrd_filename, cpu_model);
1074 }
1075
1076 QEMUMachine ss5_machine = {
1077 .name = "SS-5",
1078 .desc = "Sun4m platform, SPARCstation 5",
1079 .init = ss5_init,
1080 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1081 .nodisk_ok = 1,
1082 .use_scsi = 1,
1083 };
1084
1085 QEMUMachine ss10_machine = {
1086 .name = "SS-10",
1087 .desc = "Sun4m platform, SPARCstation 10",
1088 .init = ss10_init,
1089 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1090 .nodisk_ok = 1,
1091 .use_scsi = 1,
1092 .max_cpus = 4,
1093 };
1094
1095 QEMUMachine ss600mp_machine = {
1096 .name = "SS-600MP",
1097 .desc = "Sun4m platform, SPARCserver 600MP",
1098 .init = ss600mp_init,
1099 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1100 .nodisk_ok = 1,
1101 .use_scsi = 1,
1102 .max_cpus = 4,
1103 };
1104
1105 QEMUMachine ss20_machine = {
1106 .name = "SS-20",
1107 .desc = "Sun4m platform, SPARCstation 20",
1108 .init = ss20_init,
1109 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1110 .nodisk_ok = 1,
1111 .use_scsi = 1,
1112 .max_cpus = 4,
1113 };
1114
1115 QEMUMachine voyager_machine = {
1116 .name = "Voyager",
1117 .desc = "Sun4m platform, SPARCstation Voyager",
1118 .init = vger_init,
1119 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1120 .nodisk_ok = 1,
1121 .use_scsi = 1,
1122 };
1123
1124 QEMUMachine ss_lx_machine = {
1125 .name = "LX",
1126 .desc = "Sun4m platform, SPARCstation LX",
1127 .init = ss_lx_init,
1128 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1129 .nodisk_ok = 1,
1130 .use_scsi = 1,
1131 };
1132
1133 QEMUMachine ss4_machine = {
1134 .name = "SS-4",
1135 .desc = "Sun4m platform, SPARCstation 4",
1136 .init = ss4_init,
1137 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1138 .nodisk_ok = 1,
1139 .use_scsi = 1,
1140 };
1141
1142 QEMUMachine scls_machine = {
1143 .name = "SPARCClassic",
1144 .desc = "Sun4m platform, SPARCClassic",
1145 .init = scls_init,
1146 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1147 .nodisk_ok = 1,
1148 .use_scsi = 1,
1149 };
1150
1151 QEMUMachine sbook_machine = {
1152 .name = "SPARCbook",
1153 .desc = "Sun4m platform, SPARCbook",
1154 .init = sbook_init,
1155 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1156 .nodisk_ok = 1,
1157 .use_scsi = 1,
1158 };
1159
1160 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1161 /* SS-1000 */
1162 {
1163 .iounit_bases = {
1164 0xfe0200000ULL,
1165 0xfe1200000ULL,
1166 0xfe2200000ULL,
1167 0xfe3200000ULL,
1168 -1,
1169 },
1170 .tcx_base = 0x820000000ULL,
1171 .slavio_base = 0xf00000000ULL,
1172 .ms_kb_base = 0xf00240000ULL,
1173 .serial_base = 0xf00200000ULL,
1174 .nvram_base = 0xf00280000ULL,
1175 .counter_base = 0xf00300000ULL,
1176 .espdma_base = 0x800081000ULL,
1177 .esp_base = 0x800080000ULL,
1178 .ledma_base = 0x800040000ULL,
1179 .le_base = 0x800060000ULL,
1180 .sbi_base = 0xf02800000ULL,
1181 .vram_size = 0x00100000,
1182 .nvram_size = 0x2000,
1183 .esp_irq = 3,
1184 .le_irq = 4,
1185 .clock_irq = 14,
1186 .clock1_irq = 10,
1187 .ms_kb_irq = 12,
1188 .ser_irq = 12,
1189 .nvram_machine_id = 0x80,
1190 .machine_id = ss1000_id,
1191 .iounit_version = 0x03000000,
1192 .max_mem = 0xf00000000ULL,
1193 .default_cpu_model = "TI SuperSparc II",
1194 },
1195 /* SS-2000 */
1196 {
1197 .iounit_bases = {
1198 0xfe0200000ULL,
1199 0xfe1200000ULL,
1200 0xfe2200000ULL,
1201 0xfe3200000ULL,
1202 0xfe4200000ULL,
1203 },
1204 .tcx_base = 0x820000000ULL,
1205 .slavio_base = 0xf00000000ULL,
1206 .ms_kb_base = 0xf00240000ULL,
1207 .serial_base = 0xf00200000ULL,
1208 .nvram_base = 0xf00280000ULL,
1209 .counter_base = 0xf00300000ULL,
1210 .espdma_base = 0x800081000ULL,
1211 .esp_base = 0x800080000ULL,
1212 .ledma_base = 0x800040000ULL,
1213 .le_base = 0x800060000ULL,
1214 .sbi_base = 0xf02800000ULL,
1215 .vram_size = 0x00100000,
1216 .nvram_size = 0x2000,
1217 .esp_irq = 3,
1218 .le_irq = 4,
1219 .clock_irq = 14,
1220 .clock1_irq = 10,
1221 .ms_kb_irq = 12,
1222 .ser_irq = 12,
1223 .nvram_machine_id = 0x80,
1224 .machine_id = ss2000_id,
1225 .iounit_version = 0x03000000,
1226 .max_mem = 0xf00000000ULL,
1227 .default_cpu_model = "TI SuperSparc II",
1228 },
1229 };
1230
1231 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1232 const char *boot_device,
1233 DisplayState *ds, const char *kernel_filename,
1234 const char *kernel_cmdline,
1235 const char *initrd_filename, const char *cpu_model)
1236 {
1237 CPUState *env, *envs[MAX_CPUS];
1238 unsigned int i;
1239 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1240 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1241 *espdma_irq, *ledma_irq;
1242 qemu_irq *esp_reset, *le_reset;
1243 ram_addr_t ram_offset, prom_offset, tcx_offset;
1244 unsigned long kernel_size;
1245 int ret;
1246 char buf[1024];
1247 int drive_index;
1248 void *fw_cfg;
1249
1250 /* init CPUs */
1251 if (!cpu_model)
1252 cpu_model = hwdef->default_cpu_model;
1253
1254 for (i = 0; i < smp_cpus; i++) {
1255 env = cpu_init(cpu_model);
1256 if (!env) {
1257 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1258 exit(1);
1259 }
1260 cpu_sparc_set_id(env, i);
1261 envs[i] = env;
1262 if (i == 0) {
1263 qemu_register_reset(main_cpu_reset, env);
1264 } else {
1265 qemu_register_reset(secondary_cpu_reset, env);
1266 env->halted = 1;
1267 }
1268 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1269 env->prom_addr = hwdef->slavio_base;
1270 }
1271
1272 for (i = smp_cpus; i < MAX_CPUS; i++)
1273 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1274
1275 /* allocate RAM */
1276 if ((uint64_t)RAM_size > hwdef->max_mem) {
1277 fprintf(stderr,
1278 "qemu: Too much memory for this machine: %d, maximum %d\n",
1279 (unsigned int)(RAM_size / (1024 * 1024)),
1280 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1281 exit(1);
1282 }
1283 ram_offset = qemu_ram_alloc(RAM_size);
1284 cpu_register_physical_memory(0, RAM_size, ram_offset);
1285
1286 /* load boot prom */
1287 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1288 cpu_register_physical_memory(hwdef->slavio_base,
1289 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1290 TARGET_PAGE_MASK,
1291 prom_offset | IO_MEM_ROM);
1292
1293 if (bios_name == NULL)
1294 bios_name = PROM_FILENAME;
1295 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1296 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1297 if (ret < 0 || ret > PROM_SIZE_MAX)
1298 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1299 if (ret < 0 || ret > PROM_SIZE_MAX) {
1300 fprintf(stderr, "qemu: could not load prom '%s'\n",
1301 buf);
1302 exit(1);
1303 }
1304
1305 /* set up devices */
1306 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1307
1308 for (i = 0; i < MAX_IOUNITS; i++)
1309 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1310 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1311 hwdef->iounit_version,
1312 sbi_irq[hwdef->me_irq]);
1313
1314 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1315 iounits[0], &espdma_irq, &esp_reset);
1316
1317 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1318 iounits[0], &ledma_irq, &le_reset);
1319
1320 if (graphic_depth != 8 && graphic_depth != 24) {
1321 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1322 exit (1);
1323 }
1324 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
1325 tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
1326 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1327
1328 if (nd_table[0].model == NULL
1329 || strcmp(nd_table[0].model, "lance") == 0) {
1330 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1331 } else if (strcmp(nd_table[0].model, "?") == 0) {
1332 fprintf(stderr, "qemu: Supported NICs: lance\n");
1333 exit (1);
1334 } else {
1335 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1336 exit (1);
1337 }
1338
1339 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1340 hwdef->nvram_size, 8);
1341
1342 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1343 sbi_cpu_irq, smp_cpus);
1344
1345 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1346 nographic);
1347 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1348 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1349 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1350 serial_hds[1], serial_hds[0]);
1351
1352 if (drive_get_max_bus(IF_SCSI) > 0) {
1353 fprintf(stderr, "qemu: too many SCSI bus\n");
1354 exit(1);
1355 }
1356
1357 main_esp = esp_init(hwdef->esp_base, 2,
1358 espdma_memory_read, espdma_memory_write,
1359 espdma, *espdma_irq, esp_reset);
1360
1361 for (i = 0; i < ESP_MAX_DEVS; i++) {
1362 drive_index = drive_get_index(IF_SCSI, 0, i);
1363 if (drive_index == -1)
1364 continue;
1365 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1366 }
1367
1368 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1369 RAM_size);
1370
1371 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1372 boot_device, RAM_size, kernel_size, graphic_width,
1373 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1374 "Sun4d");
1375
1376 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1377 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1378 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1379 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1380 }
1381
1382 /* SPARCserver 1000 hardware initialisation */
1383 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1384 const char *boot_device, DisplayState *ds,
1385 const char *kernel_filename, const char *kernel_cmdline,
1386 const char *initrd_filename, const char *cpu_model)
1387 {
1388 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1389 kernel_cmdline, initrd_filename, cpu_model);
1390 }
1391
1392 /* SPARCcenter 2000 hardware initialisation */
1393 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1394 const char *boot_device, DisplayState *ds,
1395 const char *kernel_filename, const char *kernel_cmdline,
1396 const char *initrd_filename, const char *cpu_model)
1397 {
1398 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1399 kernel_cmdline, initrd_filename, cpu_model);
1400 }
1401
1402 QEMUMachine ss1000_machine = {
1403 .name = "SS-1000",
1404 .desc = "Sun4d platform, SPARCserver 1000",
1405 .init = ss1000_init,
1406 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1407 .nodisk_ok = 1,
1408 .use_scsi = 1,
1409 .max_cpus = 8,
1410 };
1411
1412 QEMUMachine ss2000_machine = {
1413 .name = "SS-2000",
1414 .desc = "Sun4d platform, SPARCcenter 2000",
1415 .init = ss2000_init,
1416 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1417 .nodisk_ok = 1,
1418 .use_scsi = 1,
1419 .max_cpus = 20,
1420 };
1421
1422 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1423 /* SS-2 */
1424 {
1425 .iommu_base = 0xf8000000,
1426 .tcx_base = 0xfe000000,
1427 .slavio_base = 0xf6000000,
1428 .intctl_base = 0xf5000000,
1429 .counter_base = 0xf3000000,
1430 .ms_kb_base = 0xf0000000,
1431 .serial_base = 0xf1000000,
1432 .nvram_base = 0xf2000000,
1433 .fd_base = 0xf7200000,
1434 .dma_base = 0xf8400000,
1435 .esp_base = 0xf8800000,
1436 .le_base = 0xf8c00000,
1437 .aux1_base = 0xf7400003,
1438 .vram_size = 0x00100000,
1439 .nvram_size = 0x800,
1440 .esp_irq = 2,
1441 .le_irq = 3,
1442 .clock_irq = 5,
1443 .clock1_irq = 7,
1444 .ms_kb_irq = 1,
1445 .ser_irq = 1,
1446 .fd_irq = 1,
1447 .me_irq = 1,
1448 .nvram_machine_id = 0x55,
1449 .machine_id = ss2_id,
1450 .max_mem = 0x10000000,
1451 .default_cpu_model = "Cypress CY7C601",
1452 },
1453 };
1454
1455 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1456 const char *boot_device,
1457 DisplayState *ds, const char *kernel_filename,
1458 const char *kernel_cmdline,
1459 const char *initrd_filename, const char *cpu_model)
1460 {
1461 CPUState *env;
1462 unsigned int i;
1463 void *iommu, *espdma, *ledma, *main_esp, *nvram;
1464 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1465 qemu_irq *esp_reset, *le_reset;
1466 qemu_irq *fdc_tc;
1467 ram_addr_t ram_offset, prom_offset, tcx_offset;
1468 unsigned long kernel_size;
1469 int ret;
1470 char buf[1024];
1471 BlockDriverState *fd[MAX_FD];
1472 int drive_index;
1473 void *fw_cfg;
1474
1475 /* init CPU */
1476 if (!cpu_model)
1477 cpu_model = hwdef->default_cpu_model;
1478
1479 env = cpu_init(cpu_model);
1480 if (!env) {
1481 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1482 exit(1);
1483 }
1484
1485 cpu_sparc_set_id(env, 0);
1486
1487 qemu_register_reset(main_cpu_reset, env);
1488 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1489 env->prom_addr = hwdef->slavio_base;
1490
1491 /* allocate RAM */
1492 if ((uint64_t)RAM_size > hwdef->max_mem) {
1493 fprintf(stderr,
1494 "qemu: Too much memory for this machine: %d, maximum %d\n",
1495 (unsigned int)(RAM_size / (1024 * 1024)),
1496 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1497 exit(1);
1498 }
1499 ram_offset = qemu_ram_alloc(RAM_size);
1500 cpu_register_physical_memory(0, RAM_size, ram_offset);
1501
1502 /* load boot prom */
1503 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1504 cpu_register_physical_memory(hwdef->slavio_base,
1505 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1506 TARGET_PAGE_MASK,
1507 prom_offset | IO_MEM_ROM);
1508
1509 if (bios_name == NULL)
1510 bios_name = PROM_FILENAME;
1511 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1512 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1513 if (ret < 0 || ret > PROM_SIZE_MAX)
1514 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1515 if (ret < 0 || ret > PROM_SIZE_MAX) {
1516 fprintf(stderr, "qemu: could not load prom '%s'\n",
1517 buf);
1518 exit(1);
1519 }
1520
1521 /* set up devices */
1522 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1523 &slavio_irq, cpu_irqs);
1524
1525 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1526 slavio_irq[hwdef->me_irq]);
1527
1528 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1529 iommu, &espdma_irq, &esp_reset);
1530
1531 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1532 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1533 &le_reset);
1534
1535 if (graphic_depth != 8 && graphic_depth != 24) {
1536 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1537 exit (1);
1538 }
1539 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
1540 tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
1541 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1542
1543 if (nd_table[0].model == NULL
1544 || strcmp(nd_table[0].model, "lance") == 0) {
1545 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1546 } else if (strcmp(nd_table[0].model, "?") == 0) {
1547 fprintf(stderr, "qemu: Supported NICs: lance\n");
1548 exit (1);
1549 } else {
1550 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1551 exit (1);
1552 }
1553
1554 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1555 hwdef->nvram_size, 2);
1556
1557 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1558 nographic);
1559 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1560 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1561 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1562 serial_hds[1], serial_hds[0]);
1563
1564 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1565 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1566
1567 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1568 /* there is zero or one floppy drive */
1569 memset(fd, 0, sizeof(fd));
1570 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1571 if (drive_index != -1)
1572 fd[0] = drives_table[drive_index].bdrv;
1573
1574 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1575 fdc_tc);
1576 }
1577
1578 if (drive_get_max_bus(IF_SCSI) > 0) {
1579 fprintf(stderr, "qemu: too many SCSI bus\n");
1580 exit(1);
1581 }
1582
1583 main_esp = esp_init(hwdef->esp_base, 2,
1584 espdma_memory_read, espdma_memory_write,
1585 espdma, *espdma_irq, esp_reset);
1586
1587 for (i = 0; i < ESP_MAX_DEVS; i++) {
1588 drive_index = drive_get_index(IF_SCSI, 0, i);
1589 if (drive_index == -1)
1590 continue;
1591 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1592 }
1593
1594 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1595 RAM_size);
1596
1597 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1598 boot_device, RAM_size, kernel_size, graphic_width,
1599 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1600 "Sun4c");
1601
1602 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1603 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1604 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1605 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1606 }
1607
1608 /* SPARCstation 2 hardware initialisation */
1609 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1610 const char *boot_device, DisplayState *ds,
1611 const char *kernel_filename, const char *kernel_cmdline,
1612 const char *initrd_filename, const char *cpu_model)
1613 {
1614 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1615 kernel_cmdline, initrd_filename, cpu_model);
1616 }
1617
1618 QEMUMachine ss2_machine = {
1619 .name = "SS-2",
1620 .desc = "Sun4c platform, SPARCstation 2",
1621 .init = ss2_init,
1622 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1623 .nodisk_ok = 1,
1624 .use_scsi = 1,
1625 };
jz4740 based target emulation