target-mips/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3
   4 #include "exec-all.h"
   5
   6 void register_machines(void)
   7 {
   8     qemu_register_machine(&mips_malta_machine);
   9     qemu_register_machine(&mips_magnum_machine);
  10     qemu_register_machine(&mips_pica61_machine);
  11     qemu_register_machine(&mips_mipssim_machine);
  12     qemu_register_machine(&mips_pavo_machine);
  13     qemu_register_machine(&mips_machine);
  14 }
  15
  16 static void save_tc(QEMUFile *f, TCState *tc)
  17 {
  18     int i;
  19
  20     /* Save active TC */
  21     for(i = 0; i < 32; i++)
  22         qemu_put_betls(f, &tc->gpr[i]);
  23     qemu_put_betls(f, &tc->PC);
  24     for(i = 0; i < MIPS_DSP_ACC; i++)
  25         qemu_put_betls(f, &tc->HI[i]);
  26     for(i = 0; i < MIPS_DSP_ACC; i++)
  27         qemu_put_betls(f, &tc->LO[i]);
  28     for(i = 0; i < MIPS_DSP_ACC; i++)
  29         qemu_put_betls(f, &tc->ACX[i]);
  30     qemu_put_betls(f, &tc->DSPControl);
  31     qemu_put_sbe32s(f, &tc->CP0_TCStatus);
  32     qemu_put_sbe32s(f, &tc->CP0_TCBind);
  33     qemu_put_betls(f, &tc->CP0_TCHalt);
  34     qemu_put_betls(f, &tc->CP0_TCContext);
  35     qemu_put_betls(f, &tc->CP0_TCSchedule);
  36     qemu_put_betls(f, &tc->CP0_TCScheFBack);
  37     qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
  38 }
  39
  40 static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
  41 {
  42     int i;
  43
  44     for(i = 0; i < 32; i++)
  45         qemu_put_be64s(f, &fpu->fpr[i].d);
  46     qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess);
  47     qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode);
  48     qemu_put_s8s(f, &fpu->fp_status.float_exception_flags);
  49     qemu_put_be32s(f, &fpu->fcr0);
  50     qemu_put_be32s(f, &fpu->fcr31);
  51 }
  52
  53 void cpu_save(QEMUFile *f, void *opaque)
  54 {
  55     CPUState *env = opaque;
  56     int i;
  57
  58     /* Save active TC */
  59     save_tc(f, &env->active_tc);
  60
  61     /* Save active FPU */
  62     save_fpu(f, &env->active_fpu);
  63
  64     /* Save MVP */
  65     qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
  66     qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
  67     qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
  68
  69     /* Save TLB */
  70     qemu_put_be32s(f, &env->tlb->nb_tlb);
  71     qemu_put_be32s(f, &env->tlb->tlb_in_use);
  72     for(i = 0; i < MIPS_TLB_MAX; i++) {
  73         uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
  74                           (env->tlb->mmu.r4k.tlb[i].C0 << 7) |
  75                           (env->tlb->mmu.r4k.tlb[i].C1 << 4) |
  76                           (env->tlb->mmu.r4k.tlb[i].V0 << 3) |
  77                           (env->tlb->mmu.r4k.tlb[i].V1 << 2) |
  78                           (env->tlb->mmu.r4k.tlb[i].D0 << 1) |
  79                           (env->tlb->mmu.r4k.tlb[i].D1 << 0));
  80
  81         qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
  82         qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
  83         qemu_put_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID);
  84         qemu_put_be16s(f, &flags);
  85         qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
  86         qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
  87     }
  88
  89     /* Save CPU metastate */
  90     qemu_put_be32s(f, &env->current_tc);
  91     qemu_put_be32s(f, &env->current_fpu);
  92     qemu_put_sbe32s(f, &env->error_code);
  93     qemu_put_be32s(f, &env->hflags);
  94     qemu_put_betls(f, &env->btarget);
  95     qemu_put_sbe32s(f, &env->bcond);
  96
  97     /* Save remaining CP1 registers */
  98     qemu_put_sbe32s(f, &env->CP0_Index);
  99     qemu_put_sbe32s(f, &env->CP0_Random);
 100     qemu_put_sbe32s(f, &env->CP0_VPEControl);
 101     qemu_put_sbe32s(f, &env->CP0_VPEConf0);
 102     qemu_put_sbe32s(f, &env->CP0_VPEConf1);
 103     qemu_put_betls(f, &env->CP0_YQMask);
 104     qemu_put_betls(f, &env->CP0_VPESchedule);
 105     qemu_put_betls(f, &env->CP0_VPEScheFBack);
 106     qemu_put_sbe32s(f, &env->CP0_VPEOpt);
 107     qemu_put_betls(f, &env->CP0_EntryLo0);
 108     qemu_put_betls(f, &env->CP0_EntryLo1);
 109     qemu_put_betls(f, &env->CP0_Context);
 110     qemu_put_sbe32s(f, &env->CP0_PageMask);
 111     qemu_put_sbe32s(f, &env->CP0_PageGrain);
 112     qemu_put_sbe32s(f, &env->CP0_Wired);
 113     qemu_put_sbe32s(f, &env->CP0_SRSConf0);
 114     qemu_put_sbe32s(f, &env->CP0_SRSConf1);
 115     qemu_put_sbe32s(f, &env->CP0_SRSConf2);
 116     qemu_put_sbe32s(f, &env->CP0_SRSConf3);
 117     qemu_put_sbe32s(f, &env->CP0_SRSConf4);
 118     qemu_put_sbe32s(f, &env->CP0_HWREna);
 119     qemu_put_betls(f, &env->CP0_BadVAddr);
 120     qemu_put_sbe32s(f, &env->CP0_Count);
 121     qemu_put_betls(f, &env->CP0_EntryHi);
 122     qemu_put_sbe32s(f, &env->CP0_Compare);
 123     qemu_put_sbe32s(f, &env->CP0_Status);
 124     qemu_put_sbe32s(f, &env->CP0_IntCtl);
 125     qemu_put_sbe32s(f, &env->CP0_SRSCtl);
 126     qemu_put_sbe32s(f, &env->CP0_SRSMap);
 127     qemu_put_sbe32s(f, &env->CP0_Cause);
 128     qemu_put_betls(f, &env->CP0_EPC);
 129     qemu_put_sbe32s(f, &env->CP0_PRid);
 130     qemu_put_sbe32s(f, &env->CP0_EBase);
 131     qemu_put_sbe32s(f, &env->CP0_Config0);
 132     qemu_put_sbe32s(f, &env->CP0_Config1);
 133     qemu_put_sbe32s(f, &env->CP0_Config2);
 134     qemu_put_sbe32s(f, &env->CP0_Config3);
 135     qemu_put_sbe32s(f, &env->CP0_Config6);
 136     qemu_put_sbe32s(f, &env->CP0_Config7);
 137     qemu_put_betls(f, &env->CP0_LLAddr);
 138     for(i = 0; i < 8; i++)
 139         qemu_put_betls(f, &env->CP0_WatchLo[i]);
 140     for(i = 0; i < 8; i++)
 141         qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
 142     qemu_put_betls(f, &env->CP0_XContext);
 143     qemu_put_sbe32s(f, &env->CP0_Framemask);
 144     qemu_put_sbe32s(f, &env->CP0_Debug);
 145     qemu_put_betls(f, &env->CP0_DEPC);
 146     qemu_put_sbe32s(f, &env->CP0_Performance0);
 147     qemu_put_sbe32s(f, &env->CP0_TagLo);
 148     qemu_put_sbe32s(f, &env->CP0_DataLo);
 149     qemu_put_sbe32s(f, &env->CP0_TagHi);
 150     qemu_put_sbe32s(f, &env->CP0_DataHi);
 151     qemu_put_betls(f, &env->CP0_ErrorEPC);
 152     qemu_put_sbe32s(f, &env->CP0_DESAVE);
 153
 154     /* Save inactive TC state */
 155     for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
 156         save_tc(f, &env->tcs[i]);
 157     for (i = 0; i < MIPS_FPU_MAX; i++)
 158         save_fpu(f, &env->fpus[i]);
 159 }
 160
 161 static void load_tc(QEMUFile *f, TCState *tc)
 162 {
 163     int i;
 164
 165     /* Save active TC */
 166     for(i = 0; i < 32; i++)
 167         qemu_get_betls(f, &tc->gpr[i]);
 168     qemu_get_betls(f, &tc->PC);
 169     for(i = 0; i < MIPS_DSP_ACC; i++)
 170         qemu_get_betls(f, &tc->HI[i]);
 171     for(i = 0; i < MIPS_DSP_ACC; i++)
 172         qemu_get_betls(f, &tc->LO[i]);
 173     for(i = 0; i < MIPS_DSP_ACC; i++)
 174         qemu_get_betls(f, &tc->ACX[i]);
 175     qemu_get_betls(f, &tc->DSPControl);
 176     qemu_get_sbe32s(f, &tc->CP0_TCStatus);
 177     qemu_get_sbe32s(f, &tc->CP0_TCBind);
 178     qemu_get_betls(f, &tc->CP0_TCHalt);
 179     qemu_get_betls(f, &tc->CP0_TCContext);
 180     qemu_get_betls(f, &tc->CP0_TCSchedule);
 181     qemu_get_betls(f, &tc->CP0_TCScheFBack);
 182     qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
 183 }
 184
 185 static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
 186 {
 187     int i;
 188
 189     for(i = 0; i < 32; i++)
 190         qemu_get_be64s(f, &fpu->fpr[i].d);
 191     qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess);
 192     qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode);
 193     qemu_get_s8s(f, &fpu->fp_status.float_exception_flags);
 194     qemu_get_be32s(f, &fpu->fcr0);
 195     qemu_get_be32s(f, &fpu->fcr31);
 196 }
 197
 198 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 199 {
 200     CPUState *env = opaque;
 201     int i;
 202
 203     if (version_id != 3)
 204         return -EINVAL;
 205
 206     /* Load active TC */
 207     load_tc(f, &env->active_tc);
 208
 209     /* Load active FPU */
 210     load_fpu(f, &env->active_fpu);
 211
 212     /* Load MVP */
 213     qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
 214     qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
 215     qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
 216
 217     /* Load TLB */
 218     qemu_get_be32s(f, &env->tlb->nb_tlb);
 219     qemu_get_be32s(f, &env->tlb->tlb_in_use);
 220     for(i = 0; i < MIPS_TLB_MAX; i++) {
 221         uint16_t flags;
 222
 223         qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
 224         qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
 225         qemu_get_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID);
 226         qemu_get_be16s(f, &flags);
 227         env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
 228         env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
 229         env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
 230         env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
 231         env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
 232         env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
 233         env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
 234         qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
 235         qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
 236     }
 237
 238     /* Load CPU metastate */
 239     qemu_get_be32s(f, &env->current_tc);
 240     qemu_get_be32s(f, &env->current_fpu);
 241     qemu_get_sbe32s(f, &env->error_code);
 242     qemu_get_be32s(f, &env->hflags);
 243     qemu_get_betls(f, &env->btarget);
 244     qemu_get_sbe32s(f, &env->bcond);
 245
 246     /* Load remaining CP1 registers */
 247     qemu_get_sbe32s(f, &env->CP0_Index);
 248     qemu_get_sbe32s(f, &env->CP0_Random);
 249     qemu_get_sbe32s(f, &env->CP0_VPEControl);
 250     qemu_get_sbe32s(f, &env->CP0_VPEConf0);
 251     qemu_get_sbe32s(f, &env->CP0_VPEConf1);
 252     qemu_get_betls(f, &env->CP0_YQMask);
 253     qemu_get_betls(f, &env->CP0_VPESchedule);
 254     qemu_get_betls(f, &env->CP0_VPEScheFBack);
 255     qemu_get_sbe32s(f, &env->CP0_VPEOpt);
 256     qemu_get_betls(f, &env->CP0_EntryLo0);
 257     qemu_get_betls(f, &env->CP0_EntryLo1);
 258     qemu_get_betls(f, &env->CP0_Context);
 259     qemu_get_sbe32s(f, &env->CP0_PageMask);
 260     qemu_get_sbe32s(f, &env->CP0_PageGrain);
 261     qemu_get_sbe32s(f, &env->CP0_Wired);
 262     qemu_get_sbe32s(f, &env->CP0_SRSConf0);
 263     qemu_get_sbe32s(f, &env->CP0_SRSConf1);
 264     qemu_get_sbe32s(f, &env->CP0_SRSConf2);
 265     qemu_get_sbe32s(f, &env->CP0_SRSConf3);
 266     qemu_get_sbe32s(f, &env->CP0_SRSConf4);
 267     qemu_get_sbe32s(f, &env->CP0_HWREna);
 268     qemu_get_betls(f, &env->CP0_BadVAddr);
 269     qemu_get_sbe32s(f, &env->CP0_Count);
 270     qemu_get_betls(f, &env->CP0_EntryHi);
 271     qemu_get_sbe32s(f, &env->CP0_Compare);
 272     qemu_get_sbe32s(f, &env->CP0_Status);
 273     qemu_get_sbe32s(f, &env->CP0_IntCtl);
 274     qemu_get_sbe32s(f, &env->CP0_SRSCtl);
 275     qemu_get_sbe32s(f, &env->CP0_SRSMap);
 276     qemu_get_sbe32s(f, &env->CP0_Cause);
 277     qemu_get_betls(f, &env->CP0_EPC);
 278     qemu_get_sbe32s(f, &env->CP0_PRid);
 279     qemu_get_sbe32s(f, &env->CP0_EBase);
 280     qemu_get_sbe32s(f, &env->CP0_Config0);
 281     qemu_get_sbe32s(f, &env->CP0_Config1);
 282     qemu_get_sbe32s(f, &env->CP0_Config2);
 283     qemu_get_sbe32s(f, &env->CP0_Config3);
 284     qemu_get_sbe32s(f, &env->CP0_Config6);
 285     qemu_get_sbe32s(f, &env->CP0_Config7);
 286     qemu_get_betls(f, &env->CP0_LLAddr);
 287     for(i = 0; i < 8; i++)
 288         qemu_get_betls(f, &env->CP0_WatchLo[i]);
 289     for(i = 0; i < 8; i++)
 290         qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
 291     qemu_get_betls(f, &env->CP0_XContext);
 292     qemu_get_sbe32s(f, &env->CP0_Framemask);
 293     qemu_get_sbe32s(f, &env->CP0_Debug);
 294     qemu_get_betls(f, &env->CP0_DEPC);
 295     qemu_get_sbe32s(f, &env->CP0_Performance0);
 296     qemu_get_sbe32s(f, &env->CP0_TagLo);
 297     qemu_get_sbe32s(f, &env->CP0_DataLo);
 298     qemu_get_sbe32s(f, &env->CP0_TagHi);
 299     qemu_get_sbe32s(f, &env->CP0_DataHi);
 300     qemu_get_betls(f, &env->CP0_ErrorEPC);
 301     qemu_get_sbe32s(f, &env->CP0_DESAVE);
 302
 303     /* Load inactive TC state */
 304     for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
 305         load_tc(f, &env->tcs[i]);
 306     for (i = 0; i < MIPS_FPU_MAX; i++)
 307         load_fpu(f, &env->fpus[i]);
 308
 309     /* XXX: ensure compatiblity for halted bit ? */
 310     tlb_flush(env, 1);
 311     return 0;
 312 }