hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "nvram.h"
  29 #include "pc.h"
  30 #include "sysemu.h"
  31 #include "net.h"
  32 #include "isa.h"
  33 #include "pci.h"
  34 #include "boards.h"
  35 #include "fw_cfg.h"
  36 #include "escc.h"
  37
  38 #define MAX_IDE_BUS 2
  39 #define VGA_BIOS_SIZE 65536
  40 #define CFG_ADDR 0xf0000510
  41
  42 /* temporary frame buffer OSI calls for the video.x driver. The right
  43    solution is to modify the driver to use VGA PCI I/Os */
  44 /* XXX: to be removed. This is no way related to emulation */
  45 static int vga_osi_call (CPUState *env)
  46 {
  47     static int vga_vbl_enabled;
  48     int linesize;
  49
  50     //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
  51
  52     /* same handler as PearPC, coming from the original MOL video
  53        driver. */
  54     switch(env->gpr[5]) {
  55     case 4:
  56         break;
  57     case 28: /* set_vmode */
  58         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  59             env->gpr[3] = 1;
  60         else
  61             env->gpr[3] = 0;
  62         break;
  63     case 29: /* get_vmode_info */
  64         if (env->gpr[6] != 0) {
  65             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  66                 env->gpr[3] = 1;
  67                 break;
  68             }
  69         }
  70         env->gpr[3] = 0;
  71         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  72         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  73         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  74         env->gpr[7] = 85 << 16; /* refresh rate */
  75         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  76         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  77         linesize = (linesize + 3) & ~3;
  78         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  79         break;
  80     case 31: /* set_video power */
  81         env->gpr[3] = 0;
  82         break;
  83     case 39: /* video_ctrl */
  84         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  85             vga_vbl_enabled = env->gpr[6];
  86         env->gpr[3] = 0;
  87         break;
  88     case 47:
  89         break;
  90     case 59: /* set_color */
  91         /* R6 = index, R7 = RGB */
  92         env->gpr[3] = 0;
  93         break;
  94     case 64: /* get color */
  95         /* R6 = index */
  96         env->gpr[3] = 0;
  97         break;
  98     case 116: /* set hwcursor */
  99         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 100         break;
 101     default:
 102         fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
 103                 ppc_dump_gpr(env, 5));
 104         break;
 105     }
 106
 107     return 1; /* osi_call handled */
 108 }
 109
 110 static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
 111                                const char *boot_device, DisplayState *ds,
 112                                const char *kernel_filename,
 113                                const char *kernel_cmdline,
 114                                const char *initrd_filename,
 115                                const char *cpu_model)
 116 {
 117     CPUState *env = NULL, *envs[MAX_CPUS];
 118     char buf[1024];
 119     qemu_irq *pic, **heathrow_irqs;
 120     nvram_t nvram;
 121     m48t59_t *m48t59;
 122     int linux_boot, i;
 123     ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
 124     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 125     PCIBus *pci_bus;
 126     MacIONVRAMState *nvr;
 127     int vga_bios_size, bios_size;
 128     qemu_irq *dummy_irq;
 129     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 130     int escc_mem_index, ide_mem_index[2];
 131     int ppc_boot_device;
 132     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 133     int index;
 134     void *fw_cfg;
 135
 136     linux_boot = (kernel_filename != NULL);
 137
 138     /* init CPUs */
 139     if (cpu_model == NULL)
 140         cpu_model = "G3";
 141     for (i = 0; i < smp_cpus; i++) {
 142         env = cpu_init(cpu_model);
 143         if (!env) {
 144             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 145             exit(1);
 146         }
 147         /* Set time-base frequency to 16.6 Mhz */
 148         cpu_ppc_tb_init(env,  16600000UL);
 149         env->osi_call = vga_osi_call;
 150         qemu_register_reset(&cpu_ppc_reset, env);
 151         envs[i] = env;
 152     }
 153     if (env->nip < 0xFFF80000) {
 154         /* Special test for PowerPC 601:
 155          * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
 156          * But the NVRAM is located at 0xFFF04000...
 157          */
 158         cpu_abort(env, "G3 Beige Mac hardware can not handle 1 MB BIOS\n");
 159     }
 160
 161     /* allocate RAM */
 162     if (ram_size > (2047 << 20)) {
 163         fprintf(stderr,
 164                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 165                 ((unsigned int)ram_size / (1 << 20)));
 166         exit(1);
 167     }
 168
 169     ram_offset = qemu_ram_alloc(ram_size);
 170     cpu_register_physical_memory(0, ram_size, ram_offset);
 171
 172     /* allocate VGA RAM */
 173     vga_ram_offset = qemu_ram_alloc(vga_ram_size);
 174
 175     /* allocate and load BIOS */
 176     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 177     if (bios_name == NULL)
 178         bios_name = PROM_FILENAME;
 179     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 180     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 181
 182     /* Load OpenBIOS (ELF) */
 183     bios_size = load_elf(buf, 0, NULL, NULL, NULL);
 184     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 185         cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
 186         exit(1);
 187     }
 188
 189     /* allocate and load VGA BIOS */
 190     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 191     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 192     vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
 193     if (vga_bios_size < 0) {
 194         /* if no bios is present, we can still work */
 195         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
 196         vga_bios_size = 0;
 197     } else {
 198         /* set a specific header (XXX: find real Apple format for NDRV
 199            drivers) */
 200         phys_ram_base[vga_bios_offset] = 'N';
 201         phys_ram_base[vga_bios_offset + 1] = 'D';
 202         phys_ram_base[vga_bios_offset + 2] = 'R';
 203         phys_ram_base[vga_bios_offset + 3] = 'V';
 204         cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
 205                      vga_bios_size);
 206         vga_bios_size += 8;
 207     }
 208
 209     if (linux_boot) {
 210         kernel_base = KERNEL_LOAD_ADDR;
 211         /* now we can load the kernel */
 212         kernel_size = load_elf(kernel_filename, kernel_base - 0xc0000000ULL,
 213                                NULL, NULL, NULL);
 214         if (kernel_size < 0)
 215             kernel_size = load_aout(kernel_filename, kernel_base,
 216                                     ram_size - kernel_base);
 217         if (kernel_size < 0)
 218             kernel_size = load_image_targphys(kernel_filename,
 219                                               kernel_base,
 220                                               ram_size - kernel_base);
 221         if (kernel_size < 0) {
 222             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 223                       kernel_filename);
 224             exit(1);
 225         }
 226         /* load initrd */
 227         if (initrd_filename) {
 228             initrd_base = INITRD_LOAD_ADDR;
 229             initrd_size = load_image(initrd_filename,
 230                                      phys_ram_base + initrd_base);
 231             if (initrd_size < 0) {
 232                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 233                           initrd_filename);
 234                 exit(1);
 235             }
 236         } else {
 237             initrd_base = 0;
 238             initrd_size = 0;
 239         }
 240         ppc_boot_device = 'm';
 241     } else {
 242         kernel_base = 0;
 243         kernel_size = 0;
 244         initrd_base = 0;
 245         initrd_size = 0;
 246         ppc_boot_device = '\0';
 247         for (i = 0; boot_device[i] != '\0'; i++) {
 248             /* TOFIX: for now, the second IDE channel is not properly
 249              *        used by OHW. The Mac floppy disk are not emulated.
 250              *        For now, OHW cannot boot from the network.
 251              */
 252 #if 0
 253             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 254                 ppc_boot_device = boot_device[i];
 255                 break;
 256             }
 257 #else
 258             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 259                 ppc_boot_device = boot_device[i];
 260                 break;
 261             }
 262 #endif
 263         }
 264         if (ppc_boot_device == '\0') {
 265             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 266             exit(1);
 267         }
 268     }
 269
 270     isa_mem_base = 0x80000000;
 271
 272     /* Register 2 MB of ISA IO space */
 273     isa_mmio_init(0xfe000000, 0x00200000);
 274
 275     /* XXX: we register only 1 output pin for heathrow PIC */
 276     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 277     heathrow_irqs[0] =
 278         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 279     /* Connect the heathrow PIC outputs to the 6xx bus */
 280     for (i = 0; i < smp_cpus; i++) {
 281         switch (PPC_INPUT(env)) {
 282         case PPC_FLAGS_INPUT_6xx:
 283             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 284             heathrow_irqs[i][0] =
 285                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 286             break;
 287         default:
 288             cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
 289             exit(1);
 290         }
 291     }
 292
 293     /* init basic PC hardware */
 294     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 295         cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
 296         exit(1);
 297     }
 298     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 299     pci_bus = pci_grackle_init(0xfec00000, pic);
 300     pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
 301                  vga_ram_offset, vga_ram_size,
 302                  vga_bios_offset, vga_bios_size);
 303
 304     /* XXX: suppress that */
 305     dummy_irq = i8259_init(NULL);
 306
 307     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 308                                serial_hds[1], ESCC_CLOCK, 4);
 309
 310     for(i = 0; i < nb_nics; i++)
 311         pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
 312
 313     /* First IDE channel is a CMD646 on the PCI bus */
 314
 315     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 316         fprintf(stderr, "qemu: too many IDE bus\n");
 317         exit(1);
 318     }
 319     index = drive_get_index(IF_IDE, 0, 0);
 320     if (index == -1)
 321         hd[0] = NULL;
 322     else
 323         hd[0] =  drives_table[index].bdrv;
 324     index = drive_get_index(IF_IDE, 0, 1);
 325     if (index == -1)
 326         hd[1] = NULL;
 327     else
 328         hd[1] =  drives_table[index].bdrv;
 329     hd[3] = hd[2] = NULL;
 330     pci_cmd646_ide_init(pci_bus, hd, 0);
 331
 332     /* Second IDE channel is a MAC IDE on the MacIO bus */
 333     index = drive_get_index(IF_IDE, 1, 0);
 334     if (index == -1)
 335         hd[0] = NULL;
 336     else
 337         hd[0] =  drives_table[index].bdrv;
 338     index = drive_get_index(IF_IDE, 1, 1);
 339     if (index == -1)
 340         hd[1] = NULL;
 341     else
 342         hd[1] =  drives_table[index].bdrv;
 343     ide_mem_index[0] = -1;
 344     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);
 345
 346     /* cuda also initialize ADB */
 347     cuda_init(&cuda_mem_index, pic[0x12]);
 348
 349     adb_kbd_init(&adb_bus);
 350     adb_mouse_init(&adb_bus);
 351
 352     nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
 353     pmac_format_nvram_partition(nvr, 0x2000);
 354
 355     dbdma_init(&dbdma_mem_index);
 356
 357     macio_init(pci_bus, 0x0010, 1, pic_mem_index, dbdma_mem_index,
 358                cuda_mem_index, nvr, 2, ide_mem_index, escc_mem_index);
 359
 360     if (usb_enabled) {
 361         usb_ohci_init_pci(pci_bus, 3, -1);
 362     }
 363
 364     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 365         graphic_depth = 15;
 366
 367     m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
 368     nvram.opaque = m48t59;
 369     nvram.read_fn = &m48t59_read;
 370     nvram.write_fn = &m48t59_write;
 371     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
 372                          ppc_boot_device, kernel_base, kernel_size,
 373                          kernel_cmdline,
 374                          initrd_base, initrd_size,
 375                          /* XXX: need an option to load a NVRAM image */
 376                          0,
 377                          graphic_width, graphic_height, graphic_depth);
 378     /* No PCI init: the BIOS will do it */
 379
 380     /* Special port to get debug messages from Open-Firmware */
 381     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 382
 383     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 384     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 385     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 386     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 387 }
 388
 389 QEMUMachine heathrow_machine = {
 390     .name = "g3beige",
 391     .desc = "Heathrow based PowerMAC",
 392     .init = ppc_heathrow_init,
 393     .ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE,
 394     .max_cpus = MAX_CPUS,
 395 };