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change pavo nand flash size from 128M to 1G bytes
[qemu/qemu-JZ.git] / hw / fdc.c
blobb1b4bc7d07fd50a33ab5073cd2454370eb91c92f
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29 #include "hw.h"
30 #include "fdc.h"
31 #include "block.h"
32 #include "qemu-timer.h"
33 #include "isa.h"
34
35 /********************************************************/
36 /* debug Floppy devices */
37 //#define DEBUG_FLOPPY
38
39 #ifdef DEBUG_FLOPPY
40 #define FLOPPY_DPRINTF(fmt, args...) \
41 do { printf("FLOPPY: " fmt , ##args); } while (0)
42 #else
43 #define FLOPPY_DPRINTF(fmt, args...)
44 #endif
45
46 #define FLOPPY_ERROR(fmt, args...) \
47 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0)
48
49 /********************************************************/
50 /* Floppy drive emulation */
51
52 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
53 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
54
55 /* Will always be a fixed parameter for us */
56 #define FD_SECTOR_LEN 512
57 #define FD_SECTOR_SC 2 /* Sector size code */
58
59 /* Floppy disk drive emulation */
60 typedef enum fdisk_type_t {
61 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
62 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
63 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
64 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
65 FDRIVE_DISK_NONE = 0x05, /* No disk */
66 } fdisk_type_t;
67
68 typedef enum fdrive_type_t {
69 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
70 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
71 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
72 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
73 } fdrive_type_t;
74
75 typedef enum fdisk_flags_t {
76 FDISK_DBL_SIDES = 0x01,
77 } fdisk_flags_t;
78
79 typedef struct fdrive_t {
80 BlockDriverState *bs;
81 /* Drive status */
82 fdrive_type_t drive;
83 uint8_t perpendicular; /* 2.88 MB access mode */
84 /* Position */
85 uint8_t head;
86 uint8_t track;
87 uint8_t sect;
88 /* Media */
89 fdisk_flags_t flags;
90 uint8_t last_sect; /* Nb sector per track */
91 uint8_t max_track; /* Nb of tracks */
92 uint16_t bps; /* Bytes per sector */
93 uint8_t ro; /* Is read-only */
94 } fdrive_t;
95
96 static void fd_init (fdrive_t *drv, BlockDriverState *bs)
97 {
98 /* Drive */
99 drv->bs = bs;
100 drv->drive = FDRIVE_DRV_NONE;
101 drv->perpendicular = 0;
102 /* Disk */
103 drv->last_sect = 0;
104 drv->max_track = 0;
105 }
106
107 static int _fd_sector (uint8_t head, uint8_t track,
108 uint8_t sect, uint8_t last_sect)
109 {
110 return (((track * 2) + head) * last_sect) + sect - 1;
111 }
112
113 /* Returns current position, in sectors, for given drive */
114 static int fd_sector (fdrive_t *drv)
115 {
116 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
117 }
118
119 /* Seek to a new position:
120 * returns 0 if already on right track
121 * returns 1 if track changed
122 * returns 2 if track is invalid
123 * returns 3 if sector is invalid
124 * returns 4 if seek is disabled
125 */
126 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
127 int enable_seek)
128 {
129 uint32_t sector;
130 int ret;
131
132 if (track > drv->max_track ||
133 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
134 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
135 head, track, sect, 1,
136 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
137 drv->max_track, drv->last_sect);
138 return 2;
139 }
140 if (sect > drv->last_sect) {
141 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
142 head, track, sect, 1,
143 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
144 drv->max_track, drv->last_sect);
145 return 3;
146 }
147 sector = _fd_sector(head, track, sect, drv->last_sect);
148 ret = 0;
149 if (sector != fd_sector(drv)) {
150 #if 0
151 if (!enable_seek) {
152 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
153 head, track, sect, 1, drv->max_track, drv->last_sect);
154 return 4;
155 }
156 #endif
157 drv->head = head;
158 if (drv->track != track)
159 ret = 1;
160 drv->track = track;
161 drv->sect = sect;
162 }
163
164 return ret;
165 }
166
167 /* Set drive back to track 0 */
168 static void fd_recalibrate (fdrive_t *drv)
169 {
170 FLOPPY_DPRINTF("recalibrate\n");
171 drv->head = 0;
172 drv->track = 0;
173 drv->sect = 1;
174 }
175
176 /* Recognize floppy formats */
177 typedef struct fd_format_t {
178 fdrive_type_t drive;
179 fdisk_type_t disk;
180 uint8_t last_sect;
181 uint8_t max_track;
182 uint8_t max_head;
183 const char *str;
184 } fd_format_t;
185
186 static const fd_format_t fd_formats[] = {
187 /* First entry is default format */
188 /* 1.44 MB 3"1/2 floppy disks */
189 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
190 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
191 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
192 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
197 /* 2.88 MB 3"1/2 floppy disks */
198 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
199 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
200 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
201 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
202 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
203 /* 720 kB 3"1/2 floppy disks */
204 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
205 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
206 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
207 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
208 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
210 /* 1.2 MB 5"1/4 floppy disks */
211 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
212 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
213 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
214 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
216 /* 720 kB 5"1/4 floppy disks */
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
219 /* 360 kB 5"1/4 floppy disks */
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
221 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
224 /* 320 kB 5"1/4 floppy disks */
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
227 /* 360 kB must match 5"1/4 better than 3"1/2... */
228 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
229 /* end */
230 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
231 };
232
233 /* Revalidate a disk drive after a disk change */
234 static void fd_revalidate (fdrive_t *drv)
235 {
236 const fd_format_t *parse;
237 uint64_t nb_sectors, size;
238 int i, first_match, match;
239 int nb_heads, max_track, last_sect, ro;
240
241 FLOPPY_DPRINTF("revalidate\n");
242 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
243 ro = bdrv_is_read_only(drv->bs);
244 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
245 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
246 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
247 nb_heads - 1, max_track, last_sect);
248 } else {
249 bdrv_get_geometry(drv->bs, &nb_sectors);
250 match = -1;
251 first_match = -1;
252 for (i = 0;; i++) {
253 parse = &fd_formats[i];
254 if (parse->drive == FDRIVE_DRV_NONE)
255 break;
256 if (drv->drive == parse->drive ||
257 drv->drive == FDRIVE_DRV_NONE) {
258 size = (parse->max_head + 1) * parse->max_track *
259 parse->last_sect;
260 if (nb_sectors == size) {
261 match = i;
262 break;
263 }
264 if (first_match == -1)
265 first_match = i;
266 }
267 }
268 if (match == -1) {
269 if (first_match == -1)
270 match = 1;
271 else
272 match = first_match;
273 parse = &fd_formats[match];
274 }
275 nb_heads = parse->max_head + 1;
276 max_track = parse->max_track;
277 last_sect = parse->last_sect;
278 drv->drive = parse->drive;
279 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
280 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
281 }
282 if (nb_heads == 1) {
283 drv->flags &= ~FDISK_DBL_SIDES;
284 } else {
285 drv->flags |= FDISK_DBL_SIDES;
286 }
287 drv->max_track = max_track;
288 drv->last_sect = last_sect;
289 drv->ro = ro;
290 } else {
291 FLOPPY_DPRINTF("No disk in drive\n");
292 drv->last_sect = 0;
293 drv->max_track = 0;
294 drv->flags &= ~FDISK_DBL_SIDES;
295 }
296 }
297
298 /********************************************************/
299 /* Intel 82078 floppy disk controller emulation */
300
301 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
302 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
303 static int fdctrl_transfer_handler (void *opaque, int nchan,
304 int dma_pos, int dma_len);
305 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
306
307 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
308 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
309 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
310 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
311 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
312 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
313 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
314 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
315 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
316 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
317 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
318
319 enum {
320 FD_DIR_WRITE = 0,
321 FD_DIR_READ = 1,
322 FD_DIR_SCANE = 2,
323 FD_DIR_SCANL = 3,
324 FD_DIR_SCANH = 4,
325 };
326
327 enum {
328 FD_STATE_MULTI = 0x01, /* multi track flag */
329 FD_STATE_FORMAT = 0x02, /* format flag */
330 FD_STATE_SEEK = 0x04, /* seek flag */
331 };
332
333 enum {
334 FD_REG_SRA = 0x00,
335 FD_REG_SRB = 0x01,
336 FD_REG_DOR = 0x02,
337 FD_REG_TDR = 0x03,
338 FD_REG_MSR = 0x04,
339 FD_REG_DSR = 0x04,
340 FD_REG_FIFO = 0x05,
341 FD_REG_DIR = 0x07,
342 };
343
344 enum {
345 FD_CMD_READ_TRACK = 0x02,
346 FD_CMD_SPECIFY = 0x03,
347 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
348 FD_CMD_WRITE = 0x05,
349 FD_CMD_READ = 0x06,
350 FD_CMD_RECALIBRATE = 0x07,
351 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
352 FD_CMD_WRITE_DELETED = 0x09,
353 FD_CMD_READ_ID = 0x0a,
354 FD_CMD_READ_DELETED = 0x0c,
355 FD_CMD_FORMAT_TRACK = 0x0d,
356 FD_CMD_DUMPREG = 0x0e,
357 FD_CMD_SEEK = 0x0f,
358 FD_CMD_VERSION = 0x10,
359 FD_CMD_SCAN_EQUAL = 0x11,
360 FD_CMD_PERPENDICULAR_MODE = 0x12,
361 FD_CMD_CONFIGURE = 0x13,
362 FD_CMD_LOCK = 0x14,
363 FD_CMD_VERIFY = 0x16,
364 FD_CMD_POWERDOWN_MODE = 0x17,
365 FD_CMD_PART_ID = 0x18,
366 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
367 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
368 FD_CMD_SAVE = 0x2c,
369 FD_CMD_OPTION = 0x33,
370 FD_CMD_RESTORE = 0x4c,
371 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
372 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
373 FD_CMD_FORMAT_AND_WRITE = 0xcd,
374 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
375 };
376
377 enum {
378 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
379 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
380 FD_CONFIG_POLL = 0x10, /* Poll enabled */
381 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
382 FD_CONFIG_EIS = 0x40, /* No implied seeks */
383 };
384
385 enum {
386 FD_SR0_EQPMT = 0x10,
387 FD_SR0_SEEK = 0x20,
388 FD_SR0_ABNTERM = 0x40,
389 FD_SR0_INVCMD = 0x80,
390 FD_SR0_RDYCHG = 0xc0,
391 };
392
393 enum {
394 FD_SR1_EC = 0x80, /* End of cylinder */
395 };
396
397 enum {
398 FD_SR2_SNS = 0x04, /* Scan not satisfied */
399 FD_SR2_SEH = 0x08, /* Scan equal hit */
400 };
401
402 enum {
403 FD_SRA_DIR = 0x01,
404 FD_SRA_nWP = 0x02,
405 FD_SRA_nINDX = 0x04,
406 FD_SRA_HDSEL = 0x08,
407 FD_SRA_nTRK0 = 0x10,
408 FD_SRA_STEP = 0x20,
409 FD_SRA_nDRV2 = 0x40,
410 FD_SRA_INTPEND = 0x80,
411 };
412
413 enum {
414 FD_SRB_MTR0 = 0x01,
415 FD_SRB_MTR1 = 0x02,
416 FD_SRB_WGATE = 0x04,
417 FD_SRB_RDATA = 0x08,
418 FD_SRB_WDATA = 0x10,
419 FD_SRB_DR0 = 0x20,
420 };
421
422 enum {
423 #if MAX_FD == 4
424 FD_DOR_SELMASK = 0x03,
425 #else
426 FD_DOR_SELMASK = 0x01,
427 #endif
428 FD_DOR_nRESET = 0x04,
429 FD_DOR_DMAEN = 0x08,
430 FD_DOR_MOTEN0 = 0x10,
431 FD_DOR_MOTEN1 = 0x20,
432 FD_DOR_MOTEN2 = 0x40,
433 FD_DOR_MOTEN3 = 0x80,
434 };
435
436 enum {
437 #if MAX_FD == 4
438 FD_TDR_BOOTSEL = 0x0c,
439 #else
440 FD_TDR_BOOTSEL = 0x04,
441 #endif
442 };
443
444 enum {
445 FD_DSR_DRATEMASK= 0x03,
446 FD_DSR_PWRDOWN = 0x40,
447 FD_DSR_SWRESET = 0x80,
448 };
449
450 enum {
451 FD_MSR_DRV0BUSY = 0x01,
452 FD_MSR_DRV1BUSY = 0x02,
453 FD_MSR_DRV2BUSY = 0x04,
454 FD_MSR_DRV3BUSY = 0x08,
455 FD_MSR_CMDBUSY = 0x10,
456 FD_MSR_NONDMA = 0x20,
457 FD_MSR_DIO = 0x40,
458 FD_MSR_RQM = 0x80,
459 };
460
461 enum {
462 FD_DIR_DSKCHG = 0x80,
463 };
464
465 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
466 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
467 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
468
469 struct fdctrl_t {
470 /* Controller's identification */
471 uint8_t version;
472 /* HW */
473 qemu_irq irq;
474 int dma_chann;
475 target_phys_addr_t io_base;
476 /* Controller state */
477 QEMUTimer *result_timer;
478 uint8_t sra;
479 uint8_t srb;
480 uint8_t dor;
481 uint8_t tdr;
482 uint8_t dsr;
483 uint8_t msr;
484 uint8_t cur_drv;
485 uint8_t status0;
486 uint8_t status1;
487 uint8_t status2;
488 /* Command FIFO */
489 uint8_t *fifo;
490 uint32_t data_pos;
491 uint32_t data_len;
492 uint8_t data_state;
493 uint8_t data_dir;
494 uint8_t eot; /* last wanted sector */
495 /* States kept only to be returned back */
496 /* Timers state */
497 uint8_t timer0;
498 uint8_t timer1;
499 /* precompensation */
500 uint8_t precomp_trk;
501 uint8_t config;
502 uint8_t lock;
503 /* Power down config (also with status regB access mode */
504 uint8_t pwrd;
505 /* Sun4m quirks? */
506 int sun4m;
507 /* Floppy drives */
508 fdrive_t drives[MAX_FD];
509 };
510
511 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
512 {
513 fdctrl_t *fdctrl = opaque;
514 uint32_t retval;
515
516 switch (reg) {
517 case FD_REG_SRA:
518 retval = fdctrl_read_statusA(fdctrl);
519 break;
520 case FD_REG_SRB:
521 retval = fdctrl_read_statusB(fdctrl);
522 break;
523 case FD_REG_DOR:
524 retval = fdctrl_read_dor(fdctrl);
525 break;
526 case FD_REG_TDR:
527 retval = fdctrl_read_tape(fdctrl);
528 break;
529 case FD_REG_MSR:
530 retval = fdctrl_read_main_status(fdctrl);
531 break;
532 case FD_REG_FIFO:
533 retval = fdctrl_read_data(fdctrl);
534 break;
535 case FD_REG_DIR:
536 retval = fdctrl_read_dir(fdctrl);
537 break;
538 default:
539 retval = (uint32_t)(-1);
540 break;
541 }
542 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
543
544 return retval;
545 }
546
547 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
548 {
549 fdctrl_t *fdctrl = opaque;
550
551 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
552
553 switch (reg) {
554 case FD_REG_DOR:
555 fdctrl_write_dor(fdctrl, value);
556 break;
557 case FD_REG_TDR:
558 fdctrl_write_tape(fdctrl, value);
559 break;
560 case FD_REG_DSR:
561 fdctrl_write_rate(fdctrl, value);
562 break;
563 case FD_REG_FIFO:
564 fdctrl_write_data(fdctrl, value);
565 break;
566 default:
567 break;
568 }
569 }
570
571 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
572 {
573 return fdctrl_read(opaque, reg & 7);
574 }
575
576 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
577 {
578 fdctrl_write(opaque, reg & 7, value);
579 }
580
581 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
582 {
583 return fdctrl_read(opaque, (uint32_t)reg);
584 }
585
586 static void fdctrl_write_mem (void *opaque,
587 target_phys_addr_t reg, uint32_t value)
588 {
589 fdctrl_write(opaque, (uint32_t)reg, value);
590 }
591
592 static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
593 fdctrl_read_mem,
594 fdctrl_read_mem,
595 fdctrl_read_mem,
596 };
597
598 static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
599 fdctrl_write_mem,
600 fdctrl_write_mem,
601 fdctrl_write_mem,
602 };
603
604 static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
605 fdctrl_read_mem,
606 NULL,
607 NULL,
608 };
609
610 static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
611 fdctrl_write_mem,
612 NULL,
613 NULL,
614 };
615
616 static void fd_save (QEMUFile *f, fdrive_t *fd)
617 {
618 qemu_put_8s(f, &fd->head);
619 qemu_put_8s(f, &fd->track);
620 qemu_put_8s(f, &fd->sect);
621 }
622
623 static void fdc_save (QEMUFile *f, void *opaque)
624 {
625 fdctrl_t *s = opaque;
626 uint8_t tmp;
627 int i;
628 uint8_t dor = s->dor | GET_CUR_DRV(s);
629
630 /* Controller state */
631 qemu_put_8s(f, &s->sra);
632 qemu_put_8s(f, &s->srb);
633 qemu_put_8s(f, &dor);
634 qemu_put_8s(f, &s->tdr);
635 qemu_put_8s(f, &s->dsr);
636 qemu_put_8s(f, &s->msr);
637 qemu_put_8s(f, &s->status0);
638 qemu_put_8s(f, &s->status1);
639 qemu_put_8s(f, &s->status2);
640 /* Command FIFO */
641 qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
642 qemu_put_be32s(f, &s->data_pos);
643 qemu_put_be32s(f, &s->data_len);
644 qemu_put_8s(f, &s->data_state);
645 qemu_put_8s(f, &s->data_dir);
646 qemu_put_8s(f, &s->eot);
647 /* States kept only to be returned back */
648 qemu_put_8s(f, &s->timer0);
649 qemu_put_8s(f, &s->timer1);
650 qemu_put_8s(f, &s->precomp_trk);
651 qemu_put_8s(f, &s->config);
652 qemu_put_8s(f, &s->lock);
653 qemu_put_8s(f, &s->pwrd);
654
655 tmp = MAX_FD;
656 qemu_put_8s(f, &tmp);
657 for (i = 0; i < MAX_FD; i++)
658 fd_save(f, &s->drives[i]);
659 }
660
661 static int fd_load (QEMUFile *f, fdrive_t *fd)
662 {
663 qemu_get_8s(f, &fd->head);
664 qemu_get_8s(f, &fd->track);
665 qemu_get_8s(f, &fd->sect);
666
667 return 0;
668 }
669
670 static int fdc_load (QEMUFile *f, void *opaque, int version_id)
671 {
672 fdctrl_t *s = opaque;
673 int i, ret = 0;
674 uint8_t n;
675
676 if (version_id != 2)
677 return -EINVAL;
678
679 /* Controller state */
680 qemu_get_8s(f, &s->sra);
681 qemu_get_8s(f, &s->srb);
682 qemu_get_8s(f, &s->dor);
683 SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK);
684 s->dor &= ~FD_DOR_SELMASK;
685 qemu_get_8s(f, &s->tdr);
686 qemu_get_8s(f, &s->dsr);
687 qemu_get_8s(f, &s->msr);
688 qemu_get_8s(f, &s->status0);
689 qemu_get_8s(f, &s->status1);
690 qemu_get_8s(f, &s->status2);
691 /* Command FIFO */
692 qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
693 qemu_get_be32s(f, &s->data_pos);
694 qemu_get_be32s(f, &s->data_len);
695 qemu_get_8s(f, &s->data_state);
696 qemu_get_8s(f, &s->data_dir);
697 qemu_get_8s(f, &s->eot);
698 /* States kept only to be returned back */
699 qemu_get_8s(f, &s->timer0);
700 qemu_get_8s(f, &s->timer1);
701 qemu_get_8s(f, &s->precomp_trk);
702 qemu_get_8s(f, &s->config);
703 qemu_get_8s(f, &s->lock);
704 qemu_get_8s(f, &s->pwrd);
705 qemu_get_8s(f, &n);
706
707 if (n > MAX_FD)
708 return -EINVAL;
709
710 for (i = 0; i < n; i++) {
711 ret = fd_load(f, &s->drives[i]);
712 if (ret != 0)
713 break;
714 }
715
716 return ret;
717 }
718
719 static void fdctrl_external_reset(void *opaque)
720 {
721 fdctrl_t *s = opaque;
722
723 fdctrl_reset(s, 0);
724 }
725
726 static void fdctrl_handle_tc(void *opaque, int irq, int level)
727 {
728 //fdctrl_t *s = opaque;
729
730 if (level) {
731 // XXX
732 FLOPPY_DPRINTF("TC pulsed\n");
733 }
734 }
735
736 /* XXX: may change if moved to bdrv */
737 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
738 {
739 return fdctrl->drives[drive_num].drive;
740 }
741
742 /* Change IRQ state */
743 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
744 {
745 if (!(fdctrl->sra & FD_SRA_INTPEND))
746 return;
747 FLOPPY_DPRINTF("Reset interrupt\n");
748 qemu_set_irq(fdctrl->irq, 0);
749 fdctrl->sra &= ~FD_SRA_INTPEND;
750 }
751
752 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
753 {
754 /* Sparc mutation */
755 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
756 /* XXX: not sure */
757 fdctrl->msr &= ~FD_MSR_CMDBUSY;
758 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
759 fdctrl->status0 = status0;
760 return;
761 }
762 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
763 qemu_set_irq(fdctrl->irq, 1);
764 fdctrl->sra |= FD_SRA_INTPEND;
765 }
766 fdctrl->status0 = status0;
767 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
768 }
769
770 /* Reset controller */
771 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
772 {
773 int i;
774
775 FLOPPY_DPRINTF("reset controller\n");
776 fdctrl_reset_irq(fdctrl);
777 /* Initialise controller */
778 fdctrl->sra = 0;
779 fdctrl->srb = 0xc0;
780 if (!fdctrl->drives[1].bs)
781 fdctrl->sra |= FD_SRA_nDRV2;
782 fdctrl->cur_drv = 0;
783 fdctrl->dor = FD_DOR_nRESET;
784 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
785 fdctrl->msr = FD_MSR_RQM;
786 /* FIFO state */
787 fdctrl->data_pos = 0;
788 fdctrl->data_len = 0;
789 fdctrl->data_state = 0;
790 fdctrl->data_dir = FD_DIR_WRITE;
791 for (i = 0; i < MAX_FD; i++)
792 fd_recalibrate(&fdctrl->drives[i]);
793 fdctrl_reset_fifo(fdctrl);
794 if (do_irq) {
795 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
796 }
797 }
798
799 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
800 {
801 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
802 }
803
804 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
805 {
806 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
807 return &fdctrl->drives[1];
808 else
809 return &fdctrl->drives[0];
810 }
811
812 #if MAX_FD == 4
813 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
814 {
815 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
816 return &fdctrl->drives[2];
817 else
818 return &fdctrl->drives[1];
819 }
820
821 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
822 {
823 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
824 return &fdctrl->drives[3];
825 else
826 return &fdctrl->drives[2];
827 }
828 #endif
829
830 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
831 {
832 switch (fdctrl->cur_drv) {
833 case 0: return drv0(fdctrl);
834 case 1: return drv1(fdctrl);
835 #if MAX_FD == 4
836 case 2: return drv2(fdctrl);
837 case 3: return drv3(fdctrl);
838 #endif
839 default: return NULL;
840 }
841 }
842
843 /* Status A register : 0x00 (read-only) */
844 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
845 {
846 uint32_t retval = fdctrl->sra;
847
848 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
849
850 return retval;
851 }
852
853 /* Status B register : 0x01 (read-only) */
854 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
855 {
856 uint32_t retval = fdctrl->srb;
857
858 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
859
860 return retval;
861 }
862
863 /* Digital output register : 0x02 */
864 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
865 {
866 uint32_t retval = fdctrl->dor;
867
868 /* Selected drive */
869 retval |= fdctrl->cur_drv;
870 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
871
872 return retval;
873 }
874
875 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
876 {
877 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
878
879 /* Motors */
880 if (value & FD_DOR_MOTEN0)
881 fdctrl->srb |= FD_SRB_MTR0;
882 else
883 fdctrl->srb &= ~FD_SRB_MTR0;
884 if (value & FD_DOR_MOTEN1)
885 fdctrl->srb |= FD_SRB_MTR1;
886 else
887 fdctrl->srb &= ~FD_SRB_MTR1;
888
889 /* Drive */
890 if (value & 1)
891 fdctrl->srb |= FD_SRB_DR0;
892 else
893 fdctrl->srb &= ~FD_SRB_DR0;
894
895 /* Reset */
896 if (!(value & FD_DOR_nRESET)) {
897 if (fdctrl->dor & FD_DOR_nRESET) {
898 FLOPPY_DPRINTF("controller enter RESET state\n");
899 }
900 } else {
901 if (!(fdctrl->dor & FD_DOR_nRESET)) {
902 FLOPPY_DPRINTF("controller out of RESET state\n");
903 fdctrl_reset(fdctrl, 1);
904 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
905 }
906 }
907 /* Selected drive */
908 fdctrl->cur_drv = value & FD_DOR_SELMASK;
909
910 fdctrl->dor = value;
911 }
912
913 /* Tape drive register : 0x03 */
914 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
915 {
916 uint32_t retval = fdctrl->tdr;
917
918 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
919
920 return retval;
921 }
922
923 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
924 {
925 /* Reset mode */
926 if (!(fdctrl->dor & FD_DOR_nRESET)) {
927 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
928 return;
929 }
930 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
931 /* Disk boot selection indicator */
932 fdctrl->tdr = value & FD_TDR_BOOTSEL;
933 /* Tape indicators: never allow */
934 }
935
936 /* Main status register : 0x04 (read) */
937 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
938 {
939 uint32_t retval = fdctrl->msr;
940
941 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
942 fdctrl->dor |= FD_DOR_nRESET;
943
944 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
945
946 return retval;
947 }
948
949 /* Data select rate register : 0x04 (write) */
950 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
951 {
952 /* Reset mode */
953 if (!(fdctrl->dor & FD_DOR_nRESET)) {
954 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
955 return;
956 }
957 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
958 /* Reset: autoclear */
959 if (value & FD_DSR_SWRESET) {
960 fdctrl->dor &= ~FD_DOR_nRESET;
961 fdctrl_reset(fdctrl, 1);
962 fdctrl->dor |= FD_DOR_nRESET;
963 }
964 if (value & FD_DSR_PWRDOWN) {
965 fdctrl_reset(fdctrl, 1);
966 }
967 fdctrl->dsr = value;
968 }
969
970 static int fdctrl_media_changed(fdrive_t *drv)
971 {
972 int ret;
973
974 if (!drv->bs)
975 return 0;
976 ret = bdrv_media_changed(drv->bs);
977 if (ret) {
978 fd_revalidate(drv);
979 }
980 return ret;
981 }
982
983 /* Digital input register : 0x07 (read-only) */
984 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
985 {
986 uint32_t retval = 0;
987
988 if (fdctrl_media_changed(drv0(fdctrl))
989 || fdctrl_media_changed(drv1(fdctrl))
990 #if MAX_FD == 4
991 || fdctrl_media_changed(drv2(fdctrl))
992 || fdctrl_media_changed(drv3(fdctrl))
993 #endif
994 )
995 retval |= FD_DIR_DSKCHG;
996 if (retval != 0)
997 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
998
999 return retval;
1000 }
1001
1002 /* FIFO state control */
1003 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1004 {
1005 fdctrl->data_dir = FD_DIR_WRITE;
1006 fdctrl->data_pos = 0;
1007 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1008 }
1009
1010 /* Set FIFO status for the host to read */
1011 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1012 {
1013 fdctrl->data_dir = FD_DIR_READ;
1014 fdctrl->data_len = fifo_len;
1015 fdctrl->data_pos = 0;
1016 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1017 if (do_irq)
1018 fdctrl_raise_irq(fdctrl, 0x00);
1019 }
1020
1021 /* Set an error: unimplemented/unknown command */
1022 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1023 {
1024 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1025 fdctrl->fifo[0] = FD_SR0_INVCMD;
1026 fdctrl_set_fifo(fdctrl, 1, 0);
1027 }
1028
1029 /* Seek to next sector */
1030 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1031 {
1032 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1033 cur_drv->head, cur_drv->track, cur_drv->sect,
1034 fd_sector(cur_drv));
1035 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1036 error in fact */
1037 if (cur_drv->sect >= cur_drv->last_sect ||
1038 cur_drv->sect == fdctrl->eot) {
1039 cur_drv->sect = 1;
1040 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1041 if (cur_drv->head == 0 &&
1042 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1043 cur_drv->head = 1;
1044 } else {
1045 cur_drv->head = 0;
1046 cur_drv->track++;
1047 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1048 return 0;
1049 }
1050 } else {
1051 cur_drv->track++;
1052 return 0;
1053 }
1054 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1055 cur_drv->head, cur_drv->track,
1056 cur_drv->sect, fd_sector(cur_drv));
1057 } else {
1058 cur_drv->sect++;
1059 }
1060 return 1;
1061 }
1062
1063 /* Callback for transfer end (stop or abort) */
1064 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1065 uint8_t status1, uint8_t status2)
1066 {
1067 fdrive_t *cur_drv;
1068
1069 cur_drv = get_cur_drv(fdctrl);
1070 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1071 status0, status1, status2,
1072 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1073 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1074 fdctrl->fifo[1] = status1;
1075 fdctrl->fifo[2] = status2;
1076 fdctrl->fifo[3] = cur_drv->track;
1077 fdctrl->fifo[4] = cur_drv->head;
1078 fdctrl->fifo[5] = cur_drv->sect;
1079 fdctrl->fifo[6] = FD_SECTOR_SC;
1080 fdctrl->data_dir = FD_DIR_READ;
1081 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1082 DMA_release_DREQ(fdctrl->dma_chann);
1083 }
1084 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1085 fdctrl->msr &= ~FD_MSR_NONDMA;
1086 fdctrl_set_fifo(fdctrl, 7, 1);
1087 }
1088
1089 /* Prepare a data transfer (either DMA or FIFO) */
1090 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1091 {
1092 fdrive_t *cur_drv;
1093 uint8_t kh, kt, ks;
1094 int did_seek = 0;
1095
1096 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1097 cur_drv = get_cur_drv(fdctrl);
1098 kt = fdctrl->fifo[2];
1099 kh = fdctrl->fifo[3];
1100 ks = fdctrl->fifo[4];
1101 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1102 GET_CUR_DRV(fdctrl), kh, kt, ks,
1103 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1104 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1105 case 2:
1106 /* sect too big */
1107 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1108 fdctrl->fifo[3] = kt;
1109 fdctrl->fifo[4] = kh;
1110 fdctrl->fifo[5] = ks;
1111 return;
1112 case 3:
1113 /* track too big */
1114 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1115 fdctrl->fifo[3] = kt;
1116 fdctrl->fifo[4] = kh;
1117 fdctrl->fifo[5] = ks;
1118 return;
1119 case 4:
1120 /* No seek enabled */
1121 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1122 fdctrl->fifo[3] = kt;
1123 fdctrl->fifo[4] = kh;
1124 fdctrl->fifo[5] = ks;
1125 return;
1126 case 1:
1127 did_seek = 1;
1128 break;
1129 default:
1130 break;
1131 }
1132
1133 /* Set the FIFO state */
1134 fdctrl->data_dir = direction;
1135 fdctrl->data_pos = 0;
1136 fdctrl->msr |= FD_MSR_CMDBUSY;
1137 if (fdctrl->fifo[0] & 0x80)
1138 fdctrl->data_state |= FD_STATE_MULTI;
1139 else
1140 fdctrl->data_state &= ~FD_STATE_MULTI;
1141 if (did_seek)
1142 fdctrl->data_state |= FD_STATE_SEEK;
1143 else
1144 fdctrl->data_state &= ~FD_STATE_SEEK;
1145 if (fdctrl->fifo[5] == 00) {
1146 fdctrl->data_len = fdctrl->fifo[8];
1147 } else {
1148 int tmp;
1149 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1150 tmp = (fdctrl->fifo[6] - ks + 1);
1151 if (fdctrl->fifo[0] & 0x80)
1152 tmp += fdctrl->fifo[6];
1153 fdctrl->data_len *= tmp;
1154 }
1155 fdctrl->eot = fdctrl->fifo[6];
1156 if (fdctrl->dor & FD_DOR_DMAEN) {
1157 int dma_mode;
1158 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1159 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1160 dma_mode = (dma_mode >> 2) & 3;
1161 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1162 dma_mode, direction,
1163 (128 << fdctrl->fifo[5]) *
1164 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1165 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1166 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1167 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1168 (direction == FD_DIR_READ && dma_mode == 1)) {
1169 /* No access is allowed until DMA transfer has completed */
1170 fdctrl->msr &= ~FD_MSR_RQM;
1171 /* Now, we just have to wait for the DMA controller to
1172 * recall us...
1173 */
1174 DMA_hold_DREQ(fdctrl->dma_chann);
1175 DMA_schedule(fdctrl->dma_chann);
1176 return;
1177 } else {
1178 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1179 }
1180 }
1181 FLOPPY_DPRINTF("start non-DMA transfer\n");
1182 fdctrl->msr |= FD_MSR_NONDMA;
1183 if (direction != FD_DIR_WRITE)
1184 fdctrl->msr |= FD_MSR_DIO;
1185 /* IO based transfer: calculate len */
1186 fdctrl_raise_irq(fdctrl, 0x00);
1187
1188 return;
1189 }
1190
1191 /* Prepare a transfer of deleted data */
1192 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1193 {
1194 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1195
1196 /* We don't handle deleted data,
1197 * so we don't return *ANYTHING*
1198 */
1199 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1200 }
1201
1202 /* handlers for DMA transfers */
1203 static int fdctrl_transfer_handler (void *opaque, int nchan,
1204 int dma_pos, int dma_len)
1205 {
1206 fdctrl_t *fdctrl;
1207 fdrive_t *cur_drv;
1208 int len, start_pos, rel_pos;
1209 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1210
1211 fdctrl = opaque;
1212 if (fdctrl->msr & FD_MSR_RQM) {
1213 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1214 return 0;
1215 }
1216 cur_drv = get_cur_drv(fdctrl);
1217 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1218 fdctrl->data_dir == FD_DIR_SCANH)
1219 status2 = FD_SR2_SNS;
1220 if (dma_len > fdctrl->data_len)
1221 dma_len = fdctrl->data_len;
1222 if (cur_drv->bs == NULL) {
1223 if (fdctrl->data_dir == FD_DIR_WRITE)
1224 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1225 else
1226 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1227 len = 0;
1228 goto transfer_error;
1229 }
1230 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1231 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1232 len = dma_len - fdctrl->data_pos;
1233 if (len + rel_pos > FD_SECTOR_LEN)
1234 len = FD_SECTOR_LEN - rel_pos;
1235 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1236 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1237 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1238 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1239 fd_sector(cur_drv) * FD_SECTOR_LEN);
1240 if (fdctrl->data_dir != FD_DIR_WRITE ||
1241 len < FD_SECTOR_LEN || rel_pos != 0) {
1242 /* READ & SCAN commands and realign to a sector for WRITE */
1243 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1244 fdctrl->fifo, 1) < 0) {
1245 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1246 fd_sector(cur_drv));
1247 /* Sure, image size is too small... */
1248 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1249 }
1250 }
1251 switch (fdctrl->data_dir) {
1252 case FD_DIR_READ:
1253 /* READ commands */
1254 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1255 fdctrl->data_pos, len);
1256 break;
1257 case FD_DIR_WRITE:
1258 /* WRITE commands */
1259 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1260 fdctrl->data_pos, len);
1261 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1262 fdctrl->fifo, 1) < 0) {
1263 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1264 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1265 goto transfer_error;
1266 }
1267 break;
1268 default:
1269 /* SCAN commands */
1270 {
1271 uint8_t tmpbuf[FD_SECTOR_LEN];
1272 int ret;
1273 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1274 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1275 if (ret == 0) {
1276 status2 = FD_SR2_SEH;
1277 goto end_transfer;
1278 }
1279 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1280 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1281 status2 = 0x00;
1282 goto end_transfer;
1283 }
1284 }
1285 break;
1286 }
1287 fdctrl->data_pos += len;
1288 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1289 if (rel_pos == 0) {
1290 /* Seek to next sector */
1291 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1292 break;
1293 }
1294 }
1295 end_transfer:
1296 len = fdctrl->data_pos - start_pos;
1297 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1298 fdctrl->data_pos, len, fdctrl->data_len);
1299 if (fdctrl->data_dir == FD_DIR_SCANE ||
1300 fdctrl->data_dir == FD_DIR_SCANL ||
1301 fdctrl->data_dir == FD_DIR_SCANH)
1302 status2 = FD_SR2_SEH;
1303 if (FD_DID_SEEK(fdctrl->data_state))
1304 status0 |= FD_SR0_SEEK;
1305 fdctrl->data_len -= len;
1306 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1307 transfer_error:
1308
1309 return len;
1310 }
1311
1312 /* Data register : 0x05 */
1313 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1314 {
1315 fdrive_t *cur_drv;
1316 uint32_t retval = 0;
1317 int pos;
1318
1319 cur_drv = get_cur_drv(fdctrl);
1320 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1321 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1322 FLOPPY_ERROR("controller not ready for reading\n");
1323 return 0;
1324 }
1325 pos = fdctrl->data_pos;
1326 if (fdctrl->msr & FD_MSR_NONDMA) {
1327 pos %= FD_SECTOR_LEN;
1328 if (pos == 0) {
1329 if (fdctrl->data_pos != 0)
1330 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1331 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1332 fd_sector(cur_drv));
1333 return 0;
1334 }
1335 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1336 FLOPPY_DPRINTF("error getting sector %d\n",
1337 fd_sector(cur_drv));
1338 /* Sure, image size is too small... */
1339 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1340 }
1341 }
1342 }
1343 retval = fdctrl->fifo[pos];
1344 if (++fdctrl->data_pos == fdctrl->data_len) {
1345 fdctrl->data_pos = 0;
1346 /* Switch from transfer mode to status mode
1347 * then from status mode to command mode
1348 */
1349 if (fdctrl->msr & FD_MSR_NONDMA) {
1350 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1351 } else {
1352 fdctrl_reset_fifo(fdctrl);
1353 fdctrl_reset_irq(fdctrl);
1354 }
1355 }
1356 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1357
1358 return retval;
1359 }
1360
1361 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1362 {
1363 fdrive_t *cur_drv;
1364 uint8_t kh, kt, ks;
1365
1366 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1367 cur_drv = get_cur_drv(fdctrl);
1368 kt = fdctrl->fifo[6];
1369 kh = fdctrl->fifo[7];
1370 ks = fdctrl->fifo[8];
1371 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1372 GET_CUR_DRV(fdctrl), kh, kt, ks,
1373 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1374 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1375 case 2:
1376 /* sect too big */
1377 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1378 fdctrl->fifo[3] = kt;
1379 fdctrl->fifo[4] = kh;
1380 fdctrl->fifo[5] = ks;
1381 return;
1382 case 3:
1383 /* track too big */
1384 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1385 fdctrl->fifo[3] = kt;
1386 fdctrl->fifo[4] = kh;
1387 fdctrl->fifo[5] = ks;
1388 return;
1389 case 4:
1390 /* No seek enabled */
1391 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1392 fdctrl->fifo[3] = kt;
1393 fdctrl->fifo[4] = kh;
1394 fdctrl->fifo[5] = ks;
1395 return;
1396 case 1:
1397 fdctrl->data_state |= FD_STATE_SEEK;
1398 break;
1399 default:
1400 break;
1401 }
1402 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1403 if (cur_drv->bs == NULL ||
1404 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1405 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1406 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1407 } else {
1408 if (cur_drv->sect == cur_drv->last_sect) {
1409 fdctrl->data_state &= ~FD_STATE_FORMAT;
1410 /* Last sector done */
1411 if (FD_DID_SEEK(fdctrl->data_state))
1412 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1413 else
1414 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1415 } else {
1416 /* More to do */
1417 fdctrl->data_pos = 0;
1418 fdctrl->data_len = 4;
1419 }
1420 }
1421 }
1422
1423 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1424 {
1425 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1426 fdctrl->fifo[0] = fdctrl->lock << 4;
1427 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1428 }
1429
1430 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1431 {
1432 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1433
1434 /* Drives position */
1435 fdctrl->fifo[0] = drv0(fdctrl)->track;
1436 fdctrl->fifo[1] = drv1(fdctrl)->track;
1437 #if MAX_FD == 4
1438 fdctrl->fifo[2] = drv2(fdctrl)->track;
1439 fdctrl->fifo[3] = drv3(fdctrl)->track;
1440 #else
1441 fdctrl->fifo[2] = 0;
1442 fdctrl->fifo[3] = 0;
1443 #endif
1444 /* timers */
1445 fdctrl->fifo[4] = fdctrl->timer0;
1446 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1447 fdctrl->fifo[6] = cur_drv->last_sect;
1448 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1449 (cur_drv->perpendicular << 2);
1450 fdctrl->fifo[8] = fdctrl->config;
1451 fdctrl->fifo[9] = fdctrl->precomp_trk;
1452 fdctrl_set_fifo(fdctrl, 10, 0);
1453 }
1454
1455 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1456 {
1457 /* Controller's version */
1458 fdctrl->fifo[0] = fdctrl->version;
1459 fdctrl_set_fifo(fdctrl, 1, 1);
1460 }
1461
1462 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1463 {
1464 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1465 fdctrl_set_fifo(fdctrl, 1, 0);
1466 }
1467
1468 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1469 {
1470 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1471
1472 /* Drives position */
1473 drv0(fdctrl)->track = fdctrl->fifo[3];
1474 drv1(fdctrl)->track = fdctrl->fifo[4];
1475 #if MAX_FD == 4
1476 drv2(fdctrl)->track = fdctrl->fifo[5];
1477 drv3(fdctrl)->track = fdctrl->fifo[6];
1478 #endif
1479 /* timers */
1480 fdctrl->timer0 = fdctrl->fifo[7];
1481 fdctrl->timer1 = fdctrl->fifo[8];
1482 cur_drv->last_sect = fdctrl->fifo[9];
1483 fdctrl->lock = fdctrl->fifo[10] >> 7;
1484 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1485 fdctrl->config = fdctrl->fifo[11];
1486 fdctrl->precomp_trk = fdctrl->fifo[12];
1487 fdctrl->pwrd = fdctrl->fifo[13];
1488 fdctrl_reset_fifo(fdctrl);
1489 }
1490
1491 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1492 {
1493 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1494
1495 fdctrl->fifo[0] = 0;
1496 fdctrl->fifo[1] = 0;
1497 /* Drives position */
1498 fdctrl->fifo[2] = drv0(fdctrl)->track;
1499 fdctrl->fifo[3] = drv1(fdctrl)->track;
1500 #if MAX_FD == 4
1501 fdctrl->fifo[4] = drv2(fdctrl)->track;
1502 fdctrl->fifo[5] = drv3(fdctrl)->track;
1503 #else
1504 fdctrl->fifo[4] = 0;
1505 fdctrl->fifo[5] = 0;
1506 #endif
1507 /* timers */
1508 fdctrl->fifo[6] = fdctrl->timer0;
1509 fdctrl->fifo[7] = fdctrl->timer1;
1510 fdctrl->fifo[8] = cur_drv->last_sect;
1511 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1512 (cur_drv->perpendicular << 2);
1513 fdctrl->fifo[10] = fdctrl->config;
1514 fdctrl->fifo[11] = fdctrl->precomp_trk;
1515 fdctrl->fifo[12] = fdctrl->pwrd;
1516 fdctrl->fifo[13] = 0;
1517 fdctrl->fifo[14] = 0;
1518 fdctrl_set_fifo(fdctrl, 15, 1);
1519 }
1520
1521 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1522 {
1523 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1524
1525 /* XXX: should set main status register to busy */
1526 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1527 qemu_mod_timer(fdctrl->result_timer,
1528 qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1529 }
1530
1531 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1532 {
1533 fdrive_t *cur_drv;
1534
1535 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1536 cur_drv = get_cur_drv(fdctrl);
1537 fdctrl->data_state |= FD_STATE_FORMAT;
1538 if (fdctrl->fifo[0] & 0x80)
1539 fdctrl->data_state |= FD_STATE_MULTI;
1540 else
1541 fdctrl->data_state &= ~FD_STATE_MULTI;
1542 fdctrl->data_state &= ~FD_STATE_SEEK;
1543 cur_drv->bps =
1544 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1545 #if 0
1546 cur_drv->last_sect =
1547 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1548 fdctrl->fifo[3] / 2;
1549 #else
1550 cur_drv->last_sect = fdctrl->fifo[3];
1551 #endif
1552 /* TODO: implement format using DMA expected by the Bochs BIOS
1553 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1554 * the sector with the specified fill byte
1555 */
1556 fdctrl->data_state &= ~FD_STATE_FORMAT;
1557 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1558 }
1559
1560 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1561 {
1562 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1563 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1564 if (fdctrl->fifo[2] & 1)
1565 fdctrl->dor &= ~FD_DOR_DMAEN;
1566 else
1567 fdctrl->dor |= FD_DOR_DMAEN;
1568 /* No result back */
1569 fdctrl_reset_fifo(fdctrl);
1570 }
1571
1572 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1573 {
1574 fdrive_t *cur_drv;
1575
1576 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1577 cur_drv = get_cur_drv(fdctrl);
1578 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1579 /* 1 Byte status back */
1580 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1581 (cur_drv->track == 0 ? 0x10 : 0x00) |
1582 (cur_drv->head << 2) |
1583 GET_CUR_DRV(fdctrl) |
1584 0x28;
1585 fdctrl_set_fifo(fdctrl, 1, 0);
1586 }
1587
1588 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1589 {
1590 fdrive_t *cur_drv;
1591
1592 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1593 cur_drv = get_cur_drv(fdctrl);
1594 fd_recalibrate(cur_drv);
1595 fdctrl_reset_fifo(fdctrl);
1596 /* Raise Interrupt */
1597 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1598 }
1599
1600 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1601 {
1602 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1603
1604 #if 0
1605 fdctrl->fifo[0] =
1606 fdctrl->status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1607 #else
1608 /* XXX: status0 handling is broken for read/write
1609 commands, so we do this hack. It should be suppressed
1610 ASAP */
1611 fdctrl->fifo[0] =
1612 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1613 #endif
1614 fdctrl->fifo[1] = cur_drv->track;
1615 fdctrl_set_fifo(fdctrl, 2, 0);
1616 fdctrl_reset_irq(fdctrl);
1617 fdctrl->status0 = FD_SR0_RDYCHG;
1618 }
1619
1620 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1621 {
1622 fdrive_t *cur_drv;
1623
1624 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1625 cur_drv = get_cur_drv(fdctrl);
1626 fdctrl_reset_fifo(fdctrl);
1627 if (fdctrl->fifo[2] > cur_drv->max_track) {
1628 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1629 } else {
1630 cur_drv->track = fdctrl->fifo[2];
1631 /* Raise Interrupt */
1632 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1633 }
1634 }
1635
1636 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1637 {
1638 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1639
1640 if (fdctrl->fifo[1] & 0x80)
1641 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1642 /* No result back */
1643 fdctrl_reset_fifo(fdctrl);
1644 }
1645
1646 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1647 {
1648 fdctrl->config = fdctrl->fifo[2];
1649 fdctrl->precomp_trk = fdctrl->fifo[3];
1650 /* No result back */
1651 fdctrl_reset_fifo(fdctrl);
1652 }
1653
1654 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1655 {
1656 fdctrl->pwrd = fdctrl->fifo[1];
1657 fdctrl->fifo[0] = fdctrl->fifo[1];
1658 fdctrl_set_fifo(fdctrl, 1, 1);
1659 }
1660
1661 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1662 {
1663 /* No result back */
1664 fdctrl_reset_fifo(fdctrl);
1665 }
1666
1667 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1668 {
1669 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1670
1671 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1672 /* Command parameters done */
1673 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1674 fdctrl->fifo[0] = fdctrl->fifo[1];
1675 fdctrl->fifo[2] = 0;
1676 fdctrl->fifo[3] = 0;
1677 fdctrl_set_fifo(fdctrl, 4, 1);
1678 } else {
1679 fdctrl_reset_fifo(fdctrl);
1680 }
1681 } else if (fdctrl->data_len > 7) {
1682 /* ERROR */
1683 fdctrl->fifo[0] = 0x80 |
1684 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1685 fdctrl_set_fifo(fdctrl, 1, 1);
1686 }
1687 }
1688
1689 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1690 {
1691 fdrive_t *cur_drv;
1692
1693 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1694 cur_drv = get_cur_drv(fdctrl);
1695 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1696 cur_drv->track = cur_drv->max_track - 1;
1697 } else {
1698 cur_drv->track += fdctrl->fifo[2];
1699 }
1700 fdctrl_reset_fifo(fdctrl);
1701 /* Raise Interrupt */
1702 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1703 }
1704
1705 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1706 {
1707 fdrive_t *cur_drv;
1708
1709 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1710 cur_drv = get_cur_drv(fdctrl);
1711 if (fdctrl->fifo[2] > cur_drv->track) {
1712 cur_drv->track = 0;
1713 } else {
1714 cur_drv->track -= fdctrl->fifo[2];
1715 }
1716 fdctrl_reset_fifo(fdctrl);
1717 /* Raise Interrupt */
1718 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1719 }
1720
1721 static const struct {
1722 uint8_t value;
1723 uint8_t mask;
1724 const char* name;
1725 int parameters;
1726 void (*handler)(fdctrl_t *fdctrl, int direction);
1727 int direction;
1728 } handlers[] = {
1729 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1730 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1731 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1732 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1733 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1734 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1735 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1736 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1737 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1738 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1739 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1740 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1741 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1742 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1743 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1744 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1745 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1746 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1747 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1748 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1749 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1750 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1751 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1752 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1753 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1754 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1755 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1756 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1757 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1758 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1759 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1760 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1761 };
1762 /* Associate command to an index in the 'handlers' array */
1763 static uint8_t command_to_handler[256];
1764
1765 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1766 {
1767 fdrive_t *cur_drv;
1768 int pos;
1769
1770 /* Reset mode */
1771 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1772 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1773 return;
1774 }
1775 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1776 FLOPPY_ERROR("controller not ready for writing\n");
1777 return;
1778 }
1779 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1780 /* Is it write command time ? */
1781 if (fdctrl->msr & FD_MSR_NONDMA) {
1782 /* FIFO data write */
1783 pos = fdctrl->data_pos++;
1784 pos %= FD_SECTOR_LEN;
1785 fdctrl->fifo[pos] = value;
1786 if (pos == FD_SECTOR_LEN - 1 ||
1787 fdctrl->data_pos == fdctrl->data_len) {
1788 cur_drv = get_cur_drv(fdctrl);
1789 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1790 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1791 return;
1792 }
1793 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1794 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1795 fd_sector(cur_drv));
1796 return;
1797 }
1798 }
1799 /* Switch from transfer mode to status mode
1800 * then from status mode to command mode
1801 */
1802 if (fdctrl->data_pos == fdctrl->data_len)
1803 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1804 return;
1805 }
1806 if (fdctrl->data_pos == 0) {
1807 /* Command */
1808 pos = command_to_handler[value & 0xff];
1809 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1810 fdctrl->data_len = handlers[pos].parameters + 1;
1811 }
1812
1813 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1814 fdctrl->fifo[fdctrl->data_pos++] = value;
1815 if (fdctrl->data_pos == fdctrl->data_len) {
1816 /* We now have all parameters
1817 * and will be able to treat the command
1818 */
1819 if (fdctrl->data_state & FD_STATE_FORMAT) {
1820 fdctrl_format_sector(fdctrl);
1821 return;
1822 }
1823
1824 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1825 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1826 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1827 }
1828 }
1829
1830 static void fdctrl_result_timer(void *opaque)
1831 {
1832 fdctrl_t *fdctrl = opaque;
1833 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1834
1835 /* Pretend we are spinning.
1836 * This is needed for Coherent, which uses READ ID to check for
1837 * sector interleaving.
1838 */
1839 if (cur_drv->last_sect != 0) {
1840 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1841 }
1842 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1843 }
1844
1845 /* Init functions */
1846 static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
1847 target_phys_addr_t io_base,
1848 BlockDriverState **fds)
1849 {
1850 fdctrl_t *fdctrl;
1851 int i, j;
1852
1853 /* Fill 'command_to_handler' lookup table */
1854 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1855 for (j = 0; j < sizeof(command_to_handler); j++) {
1856 if ((j & handlers[i].mask) == handlers[i].value)
1857 command_to_handler[j] = i;
1858 }
1859 }
1860
1861 FLOPPY_DPRINTF("init controller\n");
1862 fdctrl = qemu_mallocz(sizeof(fdctrl_t));
1863 if (!fdctrl)
1864 return NULL;
1865 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1866 if (fdctrl->fifo == NULL) {
1867 qemu_free(fdctrl);
1868 return NULL;
1869 }
1870 fdctrl->result_timer = qemu_new_timer(vm_clock,
1871 fdctrl_result_timer, fdctrl);
1872
1873 fdctrl->version = 0x90; /* Intel 82078 controller */
1874 fdctrl->irq = irq;
1875 fdctrl->dma_chann = dma_chann;
1876 fdctrl->io_base = io_base;
1877 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1878 if (fdctrl->dma_chann != -1) {
1879 DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1880 }
1881 for (i = 0; i < MAX_FD; i++) {
1882 fd_init(&fdctrl->drives[i], fds[i]);
1883 }
1884 fdctrl_external_reset(fdctrl);
1885 register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1886 qemu_register_reset(fdctrl_external_reset, fdctrl);
1887 for (i = 0; i < MAX_FD; i++) {
1888 fd_revalidate(&fdctrl->drives[i]);
1889 }
1890
1891 return fdctrl;
1892 }
1893
1894 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1895 target_phys_addr_t io_base,
1896 BlockDriverState **fds)
1897 {
1898 fdctrl_t *fdctrl;
1899 int io_mem;
1900
1901 fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
1902
1903 fdctrl->sun4m = 0;
1904 if (mem_mapped) {
1905 io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
1906 fdctrl);
1907 cpu_register_physical_memory(io_base, 0x08, io_mem);
1908 } else {
1909 register_ioport_read((uint32_t)io_base + 0x01, 5, 1,
1910 &fdctrl_read_port, fdctrl);
1911 register_ioport_read((uint32_t)io_base + 0x07, 1, 1,
1912 &fdctrl_read_port, fdctrl);
1913 register_ioport_write((uint32_t)io_base + 0x01, 5, 1,
1914 &fdctrl_write_port, fdctrl);
1915 register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
1916 &fdctrl_write_port, fdctrl);
1917 }
1918
1919 return fdctrl;
1920 }
1921
1922 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1923 BlockDriverState **fds, qemu_irq *fdc_tc)
1924 {
1925 fdctrl_t *fdctrl;
1926 int io_mem;
1927
1928 fdctrl = fdctrl_init_common(irq, -1, io_base, fds);
1929 fdctrl->sun4m = 1;
1930 io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
1931 fdctrl_mem_write_strict,
1932 fdctrl);
1933 cpu_register_physical_memory(io_base, 0x08, io_mem);
1934 *fdc_tc = *qemu_allocate_irqs(fdctrl_handle_tc, fdctrl, 1);
1935
1936 return fdctrl;
1937 }
jz4740 based target emulation