2 * QEMU JZ Soc emulation
4 * Copyright (c) 2009 yajin (yajin@vm-kernel.org)
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * The emulation target is pavo demo board.
28 * http://www.ingenic.cn/eng/productServ/kfyd/Hardware/pffaqQuestionContent.aspx?Category=2&Question=3
35 #include "qemu-timer.h"
36 #include "qemu-char.h"
39 #include "audio/audio.h"
45 #define DEBUG /*global debug on/off */
47 #define DEBUG_CPM (1<<0x0)
48 #define DEBUG_EMC (1<<0x1)
49 #define DEBUG_GPIO (1<<0x2)
50 #define DEBUG_RTC (1<<0x3)
51 #define DEBUG_TCU (1<<0x4)
52 #define DEBUG_LCDC (1<<0x5)
53 #define DEBUG_DMA (1<<0x6)
54 #define DEBUG_SADC (1<<0x7)
55 #define DEBUG_FLAG 0 //(DEBUG_CPM|DEBUG_EMC|DEBUG_GPIO
56 // | DEBUG_RTC | DEBUG_TCU | DEBUG_LCDC | DEBUG_DMA)
57 //DEBUG_TCU// (DEBUG_CPM|DEBUG_EMC|DEBUG_GPIO
58 // | DEBUG_RTC | DEBUG_TCU | DEBUG_LCDC | DEBUG_DMA)
63 static void debug_init(void)
65 fp
= fopen("jz4740.txt", "w+");
68 fprintf(stderr
, "can not open jz4740.txt \n");
72 static void debug_out(uint32_t flag
, const char *format
, ...)
77 if (flag
& DEBUG_FLAG
)
80 vfprintf(fp
, format
, ap
);
87 static void debug_init(void)
90 static void debug_out(uint32_t flag
, const char *format
, ...)
95 uint32_t jz4740_badwidth_read8(void *opaque
, target_phys_addr_t addr
)
100 cpu_physical_memory_read(addr
, (void *) &ret
, 1);
104 void jz4740_badwidth_write8(void *opaque
, target_phys_addr_t addr
,
107 uint8_t val8
= value
;
110 cpu_physical_memory_write(addr
, (void *) &val8
, 1);
113 uint32_t jz4740_badwidth_read16(void *opaque
, target_phys_addr_t addr
)
116 JZ4740_16B_REG(addr
);
117 cpu_physical_memory_read(addr
, (void *) &ret
, 2);
121 void jz4740_badwidth_write16(void *opaque
, target_phys_addr_t addr
,
124 uint16_t val16
= value
;
126 JZ4740_16B_REG(addr
);
127 cpu_physical_memory_write(addr
, (void *) &val16
, 2);
130 uint32_t jz4740_badwidth_read32(void *opaque
, target_phys_addr_t addr
)
134 JZ4740_32B_REG(addr
);
135 cpu_physical_memory_read(addr
, (void *) &ret
, 4);
139 void jz4740_badwidth_write32(void *opaque
, target_phys_addr_t addr
,
142 JZ4740_32B_REG(addr
);
143 cpu_physical_memory_write(addr
, (void *) &value
, 4);
147 /*clock reset and power control*/
150 target_phys_addr_t base
;
151 struct jz_state_s
*soc
;
167 static void jz4740_dump_clocks(jz_clk parent
)
171 debug_out(DEBUG_CPM
, "clock %s rate %d \n", i
->name
, i
->rate
);
172 for (i
= i
->child1
; i
; i
= i
->sibling
)
173 jz4740_dump_clocks(i
);
176 static inline void jz4740_cpccr_update(struct jz4740_cpm_s
*s
,
179 uint32_t ldiv
, mdiv
, pdiv
, hdiv
, cdiv
, udiv
;
180 uint32_t div_table
[10] = {
181 1, 2, 3, 4, 6, 8, 12, 16, 24, 32
184 if (unlikely(new_value
== s
->cpccr
))
187 if (new_value
& CPM_CPCCR_PCS
)
188 jz_clk_setrate(jz_findclk(s
->soc
, "pll_divider"), 1, 1);
190 jz_clk_setrate(jz_findclk(s
->soc
, "pll_divider"), 2, 1);
193 ldiv
= (new_value
& CPM_CPCCR_LDIV_MASK
) >> CPM_CPCCR_LDIV_BIT
;
196 mdiv
= div_table
[(new_value
& CPM_CPCCR_MDIV_MASK
) >> CPM_CPCCR_MDIV_BIT
];
197 pdiv
= div_table
[(new_value
& CPM_CPCCR_PDIV_MASK
) >> CPM_CPCCR_PDIV_BIT
];
198 hdiv
= div_table
[(new_value
& CPM_CPCCR_HDIV_MASK
) >> CPM_CPCCR_HDIV_BIT
];
199 cdiv
= div_table
[(new_value
& CPM_CPCCR_CDIV_MASK
) >> CPM_CPCCR_CDIV_BIT
];
200 udiv
= div_table
[(new_value
& CPM_CPCCR_UDIV_MASK
) >> CPM_CPCCR_UDIV_BIT
];
202 jz_clk_setrate(jz_findclk(s
->soc
, "ldclk"), ldiv
, 1);
203 jz_clk_setrate(jz_findclk(s
->soc
, "mclk"), mdiv
, 1);
204 jz_clk_setrate(jz_findclk(s
->soc
, "pclk"), pdiv
, 1);
205 jz_clk_setrate(jz_findclk(s
->soc
, "hclk"), hdiv
, 1);
206 jz_clk_setrate(jz_findclk(s
->soc
, "cclk"), cdiv
, 1);
207 jz_clk_setrate(jz_findclk(s
->soc
, "usbclk"), udiv
, 1);
209 if (new_value
& CPM_CPCCR_UCS
)
210 jz_clk_reparent(jz_findclk(s
->soc
, "usbclk"),
211 jz_findclk(s
->soc
, "pll_divider"));
213 jz_clk_reparent(jz_findclk(s
->soc
, "usbclk"),
214 jz_findclk(s
->soc
, "osc_extal"));
216 if (new_value
& CPM_CPCCR_I2CS
)
217 jz_clk_reparent(jz_findclk(s
->soc
, "i2sclk"),
218 jz_findclk(s
->soc
, "pll_divider"));
220 jz_clk_reparent(jz_findclk(s
->soc
, "i2sclk"),
221 jz_findclk(s
->soc
, "osc_extal"));
223 s
->cpccr
= new_value
;
225 debug_out(DEBUG_CPM
, "write to cpccr 0x%x\n", new_value
);
227 jz4740_dump_clocks(jz_findclk(s
->soc
, "osc_extal"));
231 static inline void jz4740_cppcr_update(struct jz4740_cpm_s
*s
,
234 uint32_t pllm
, plln
, pllod
, pllbp
, pllen
;
240 pllen
= new_value
& CPM_CPPCR_PLLEN
;
241 pllbp
= new_value
& CPM_CPPCR_PLLBP
;
242 if ((!pllen
) || (pllen
&& pllbp
))
244 jz_clk_setrate(jz_findclk(s
->soc
, "pll_output"), 1, 1);
245 debug_out(DEBUG_CPM
, "pll is bypassed \n");
246 s
->cppcr
= new_value
| CPM_CPPCR_PLLS
;
251 pllm
= (new_value
& CPM_CPPCR_PLLM_MASK
) >> CPM_CPPCR_PLLM_BIT
;
252 plln
= (new_value
& CPM_CPPCR_PLLN_MASK
) >> CPM_CPPCR_PLLN_BIT
;
253 pllod
= (new_value
& CPM_CPPCR_PLLOD_MASK
) >> CPM_CPPCR_PLLOD_BIT
;
254 jz_clk_setrate(jz_findclk(s
->soc
, "pll_output"), (plln
+ 2) * pll0
[pllod
],
257 s
->cppcr
= new_value
;
259 debug_out(DEBUG_CPM
, "write to cppcr 0x%x\n", new_value
);
260 jz4740_dump_clocks(jz_findclk(s
->soc
, "osc_extal"));
264 static inline void jz4740_i2scdr_update(struct jz4740_cpm_s
*s
,
269 i2scdr
= new_value
& CPM_I2SCDR_I2SDIV_MASK
;
270 if (unlikely(i2scdr
== s
->i2scdr
))
274 jz_clk_setrate(jz_findclk(s
->soc
, "i2sclk"), i2scdr
+ 1, 1);
278 debug_out(DEBUG_CPM
, "write to i2scdr 0x%x\n", new_value
);
279 jz4740_dump_clocks(jz_findclk(s
->soc
, "osc_extal"));
283 static inline void jz4740_lpcdr_update(struct jz4740_cpm_s
*s
,
288 ipcdr
= new_value
& CPM_LPCDR_PIXDIV_MASK
;
293 static inline void jz4740_msccdr_update(struct jz4740_cpm_s
*s
,
298 msccdr
= new_value
& CPM_MSCCDR_MSCDIV_MASK
;
300 if (unlikely(msccdr
== s
->msccdr
))
304 jz_clk_setrate(jz_findclk(s
->soc
, "mscclk"), msccdr
+ 1, 1);
308 debug_out(DEBUG_CPM
, "write to msccdr 0x%x\n", new_value
);
309 jz4740_dump_clocks(jz_findclk(s
->soc
, "osc_extal"));
313 static inline void jz4740_uhccdr_update(struct jz4740_cpm_s
*s
,
318 uhccdr
= new_value
& 0xf;
323 static void jz4740_cpm_write(void *opaque
, target_phys_addr_t addr
,
326 struct jz4740_cpm_s
*s
= (struct jz4740_cpm_s
*) opaque
;
328 debug_out(DEBUG_CPM
, "write to cpm addr %x value 0x%x\n", addr
, value
);
333 jz4740_cpccr_update(s
, value
);
336 s
->lcr
= value
& 0xff;
339 s
->clkgr
= value
& 0xffff;
342 s
->scr
= value
& 0xffff;
345 jz4740_cppcr_update(s
, value
);
348 jz4740_i2scdr_update(s
, value
);
351 jz4740_lpcdr_update(s
, value
);
354 jz4740_msccdr_update(s
, value
);
357 jz4740_uhccdr_update(s
, value
);
360 s
->uhctst
= value
& 0x3f;
363 s
->ssicdr
= value
& 0xf;
366 cpu_abort(s
->soc
->env
,
367 "jz4740_cpm_write undefined addr " JZ_FMT_plx
368 " value %x \n", addr
, value
);
374 static uint32_t jz474_cpm_read(void *opaque
, target_phys_addr_t addr
)
376 struct jz4740_cpm_s
*s
= (struct jz4740_cpm_s
*) opaque
;
403 cpu_abort(s
->soc
->env
,
404 "jz474_cpm_read undefined addr " JZ_FMT_plx
" \n", addr
);
411 static CPUReadMemoryFunc
*jz4740_cpm_readfn
[] = {
412 jz4740_badwidth_read32
,
413 jz4740_badwidth_read32
,
417 static CPUWriteMemoryFunc
*jz4740_cpm_writefn
[] = {
418 jz4740_badwidth_write32
,
419 jz4740_badwidth_write32
,
423 static void jz4740_cpm_reset(struct jz4740_cpm_s
*s
)
425 s
->cpccr
= 0x42040000;
426 s
->cppcr
= 0x28080011;
427 s
->i2scdr
= 0x00000004;
428 s
->lpcdr
= 0x00000004;
429 s
->msccdr
= 0x00000004;
430 s
->uhccdr
= 0x00000004;
432 s
->ssicdr
= 0x00000004;
439 static struct jz4740_cpm_s
*jz4740_cpm_init(struct jz_state_s
*soc
)
442 struct jz4740_cpm_s
*s
= (struct jz4740_cpm_s
*) qemu_mallocz(sizeof(*s
));
443 s
->base
= JZ4740_PHYS_BASE(JZ4740_CPM_BASE
);
449 cpu_register_io_memory(0, jz4740_cpm_readfn
, jz4740_cpm_writefn
, s
);
450 cpu_register_physical_memory(s
->base
, 0x00001000, iomemtype
);
455 /* JZ4740 interrupt controller
456 * It issues INT2 to MIPS
462 target_phys_addr_t base
;
463 struct jz_state_s
*soc
;
472 static uint32_t jz4740_intc_read(void *opaque
, target_phys_addr_t addr
)
474 struct jz4740_intc_s
*s
= (struct jz4740_intc_s
*) opaque
;
489 cpu_abort(s
->soc
->env
,
490 "jz4740_intc_read undefined addr " JZ_FMT_plx
" \n", addr
);
496 static void jz4740_intc_write(void *opaque
, target_phys_addr_t addr
,
499 struct jz4740_intc_s
*s
= (struct jz4740_intc_s
*) opaque
;
517 qemu_set_irq(s
->parent_irq
, 0);
520 cpu_abort(s
->soc
->env
,
521 "jz4740_intc_write undefined addr " JZ_FMT_plx
522 " value %x \n", addr
, value
);
527 static CPUReadMemoryFunc
*jz4740_intc_readfn
[] = {
528 jz4740_badwidth_read32
,
529 jz4740_badwidth_read32
,
533 static CPUWriteMemoryFunc
*jz4740_intc_writefn
[] = {
534 jz4740_badwidth_write32
,
535 jz4740_badwidth_write32
,
539 static void jz4740_intc_reset(struct jz4740_intc_s
*s
)
542 s
->icmr
= 0xffffffff;
546 static void jz4740_set_irq(void *opaque
, int irq
, int level
)
548 struct jz4740_intc_s
*s
= (struct jz4740_intc_s
*) opaque
;
549 uint32_t irq_mask
= 1 << irq
;
555 s
->icpr
&= ~irq_mask
;
556 if (!(s
->icmr
& irq_mask
))
559 qemu_set_irq(s
->parent_irq
, 1);
565 static qemu_irq
*jz4740_intc_init(struct jz_state_s
*soc
, qemu_irq parent_irq
)
568 struct jz4740_intc_s
*s
= (struct jz4740_intc_s
*) qemu_mallocz(sizeof(*s
));
569 s
->base
= JZ4740_PHYS_BASE(JZ4740_INTC_BASE
);
570 s
->parent_irq
= parent_irq
;
573 jz4740_intc_reset(s
);
576 cpu_register_io_memory(0, jz4740_intc_readfn
, jz4740_intc_writefn
, s
);
577 cpu_register_physical_memory(s
->base
, 0x00001000, iomemtype
);
578 return qemu_allocate_irqs(jz4740_set_irq
, s
, 32);
581 /*external memory controller*/
585 target_phys_addr_t base
;
586 struct jz_state_s
*soc
;
589 uint32_t smcr1
; /*0x13010014 */
590 uint32_t smcr2
; /*0x13010018 */
591 uint32_t smcr3
; /*0x1301001c */
592 uint32_t smcr4
; /*0x13010020 */
593 uint32_t sacr1
; /*0x13010034 */
594 uint32_t sacr2
; /*0x13010038 */
595 uint32_t sacr3
; /*0x1301003c */
596 uint32_t sacr4
; /*0x13010040 */
598 uint32_t nfcsr
; /*0x13010050 */
599 uint32_t nfeccr
; /*0x13010100 */
600 uint32_t nfecc
; /*0x13010104 */
601 uint32_t nfpar0
; /*0x13010108 */
602 uint32_t nfpar1
; /*0x1301010c */
603 uint32_t nfpar2
; /*0x13010110 */
604 uint32_t nfints
; /*0x13010114 */
605 uint32_t nfinte
; /*0x13010118 */
606 uint32_t nferr0
; /*0x1301011c */
607 uint32_t nferr1
; /*0x13010120 */
608 uint32_t nferr2
; /*0x13010124 */
609 uint32_t nferr3
; /*0x13010128 */
611 uint32_t dmcr
; /*0x13010080 */
612 uint32_t rtcsr
; /*0x13010084 */
613 uint32_t rtcnt
; /*0x13010088 */
614 uint32_t rtcor
; /*0x1301008c */
615 uint32_t dmar
; /*0x13010090 */
616 uint32_t sdmr
; /*0x1301a000 */
621 static void jz4740_emc_reset(struct jz4740_emc_s
*s
)
623 s
->smcr1
= 0xfff7700;
624 s
->smcr2
= 0xfff7700;
625 s
->smcr3
= 0xfff7700;
626 s
->smcr4
= 0xfff7700;
654 static uint32_t jz4740_emc_read8(void *opaque
, target_phys_addr_t addr
)
656 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
664 return (s
->nfpar0
>> ((addr
- 0x108) * 8)) & 0xff;
669 return (s
->nfpar1
>> ((addr
- 0x10c) * 8)) & 0xff;
674 return (s
->nfpar2
>> ((addr
- 0x110) * 8)) & 0xff;
679 return (s
->sdmr
>> ((addr
- 0xa000) * 8)) & 0xff;
681 cpu_abort(s
->soc
->env
,
682 "jz4740_emc_read8 undefined addr " JZ_FMT_plx
" \n", addr
);
689 static uint32_t jz4740_emc_read16(void *opaque
, target_phys_addr_t addr
)
691 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
697 return (s
->nfpar0
>> ((addr
- 0x108) * 8)) & 0xffff;
700 return (s
->nfpar1
>> ((addr
- 0x10c) * 8)) & 0xffff;
703 return (s
->nfpar2
>> ((addr
- 0x110) * 8)) & 0xffff;
706 return (s
->nferr0
>> ((addr
- 0x11c) * 8)) & 0xffff;
709 return (s
->nferr1
>> ((addr
- 0x120) * 8)) & 0xffff;
712 return (s
->nferr2
>> ((addr
- 0x124) * 8)) & 0xffff;
715 return (s
->nferr3
>> ((addr
- 0x128) * 8)) & 0xffff;
717 cpu_abort(s
->soc
->env
,
718 "jz4740_emc_read16 undefined addr " JZ_FMT_plx
" \n", addr
);
723 static uint32_t jz4740_emc_read32(void *opaque
, target_phys_addr_t addr
)
725 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
776 cpu_abort(s
->soc
->env
,
777 "jz4740_emc_read32 undefined addr " JZ_FMT_plx
" \n", addr
);
782 static void jz4740_emc_write8(void *opaque
, target_phys_addr_t addr
,
785 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
787 debug_out(DEBUG_EMC
, "jz4740_emc_write8 addr %x value %x\n", addr
, value
);
795 s
->nfpar0
|= (value
& 0xff) << ((addr
- 0x108) * 8);
801 s
->nfpar1
|= (value
& 0xff) << ((addr
- 0x10c) * 8);
807 s
->nfpar2
|= (value
& 0xff) << ((addr
- 0x110) * 8);
809 case 0xa000 ... 0xa3ff:
812 cpu_abort(s
->soc
->env
,
813 "jz4740_emc_write8 undefined addr " JZ_FMT_plx
814 " value %x \n", addr
, value
);
817 static void jz4740_emc_write16(void *opaque
, target_phys_addr_t addr
,
820 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
822 debug_out(DEBUG_EMC
, "jz4740_emc_write16 addr %x value %x\n", addr
, value
);
827 s
->nfpar0
|= (value
& 0xffff) << ((addr
- 0x108) * 8);
831 s
->nfpar1
|= (value
& 0xffff) << ((addr
- 0x10c) * 8);
835 s
->nfpar2
|= (value
& 0xffff) << ((addr
- 0x110) * 8);
839 s
->rtcsr
|= (value
& 0xffff) << ((addr
- 0x84) * 8);
843 s
->rtcnt
|= (value
& 0xffff) << ((addr
- 0x88) * 8);
846 s
->rtcor
|= (value
& 0xffff) << ((addr
- 0x8c) * 8);
849 cpu_abort(s
->soc
->env
,
850 "jz4740_emc_write16 undefined addr " JZ_FMT_plx
851 " value %x \n", addr
, value
);
855 static void jz4740_emc_upate_interrupt(struct jz4740_emc_s
*s
)
857 qemu_set_irq(s
->irq
, s
->nfints
& s
->nfinte
);
860 static void jz4740_emc_write32(void *opaque
, target_phys_addr_t addr
,
863 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) opaque
;
865 debug_out(DEBUG_EMC
, "jz4740_emc_write32 addr %x value %x\n", addr
, value
);
879 s
->smcr1
= value
& 0xfff77cf;
882 s
->smcr2
= value
& 0xfff77cf;
885 s
->smcr3
= value
& 0xfff77cf;
888 s
->smcr4
= value
& 0xfff77cf;
891 s
->sacr1
= value
& 0xffff;
894 s
->sacr2
= value
& 0xffff;
897 s
->sacr3
= value
& 0xffff;
900 s
->sacr4
= value
& 0xffff;
903 s
->nfcsr
= value
& 0xffff;
906 s
->nfeccr
= value
& 0x1f;
921 /*TODO: Real RS error correction */
924 if ((s
->nfeccr
& 0x10) && (!(s
->nfeccr
& 0x8)))
936 s
->nfpar0
= 0xffffffff; /*fake value. for debug */
937 s
->nfpar1
= 0xffffffff; /*fake value */
938 s
->nfpar2
= 0xff; /*fake value */
945 jz4740_emc_upate_interrupt(s
);
954 s
->nfpar2
= value
& 0xff;
957 s
->nfints
= value
& 0x1fffffff;
958 jz4740_emc_upate_interrupt(s
);
961 s
->nfinte
= value
& 0x1f;
962 jz4740_emc_upate_interrupt(s
);
965 s
->dmcr
= value
& 0x9fbeff7f;
968 s
->dmar
= value
& 0xffff;
971 cpu_abort(s
->soc
->env
,
972 "jz4740_emc_write32 undefined addr " JZ_FMT_plx
973 " value %x \n", addr
, value
);
979 static CPUReadMemoryFunc
*jz4740_emc_readfn
[] = {
985 static CPUWriteMemoryFunc
*jz4740_emc_writefn
[] = {
992 static struct jz4740_emc_s
*jz4740_emc_init(struct jz_state_s
*soc
,
996 struct jz4740_emc_s
*s
= (struct jz4740_emc_s
*) qemu_mallocz(sizeof(*s
));
997 s
->base
= JZ4740_PHYS_BASE(JZ4740_EMC_BASE
);
1001 jz4740_emc_reset(s
);
1004 cpu_register_io_memory(0, jz4740_emc_readfn
, jz4740_emc_writefn
, s
);
1005 cpu_register_physical_memory(s
->base
, 0x00010000, iomemtype
);
1010 struct jz4740_gpio_s
1013 target_phys_addr_t base
;
1014 struct jz_state_s
*soc
;
1027 static void jz4740_gpio_reset(struct jz4740_gpio_s
*s
)
1029 memset(s
->papin
, 0x0, sizeof(s
->papin
));
1030 memset(s
->padat
, 0x0, sizeof(s
->padat
));
1031 memset(s
->paim
, 0xffffffff, sizeof(s
->paim
));
1032 memset(s
->pape
, 0x0, sizeof(s
->pape
));
1033 memset(s
->pafun
, 0x0, sizeof(s
->pafun
));
1034 memset(s
->pasel
, 0x0, sizeof(s
->pasel
));
1035 memset(s
->padir
, 0x0, sizeof(s
->padir
));
1036 memset(s
->patrg
, 0x0, sizeof(s
->patrg
));
1037 memset(s
->paflg
, 0x0, sizeof(s
->paflg
));
1040 static uint32_t jz4740_gpio_read(void *opaque
, target_phys_addr_t addr
)
1042 struct jz4740_gpio_s
*s
= (struct jz4740_gpio_s
*) opaque
;
1044 debug_out(DEBUG_GPIO
, "jz4740_gpio_read addr %x\n", addr
);
1108 JZ4740_WO_REG(addr
);
1115 group
= (addr
- 0x0) / 0x100;
1118 /*GPIO(C) PIN 30 -> NAND FLASH R/B. */
1119 /*FOR NAND FLASH.PIN 30 ----|_____|------ */
1120 s
->papin
[2] &= 0x40000000;
1122 s
->papin
[2] &= ~0x40000000;
1124 s
->papin
[2] |= 0x40000000;
1126 return s
->papin
[group
];
1131 group
= (addr
- 0x10) / 0x100;
1132 return s
->padat
[group
];
1137 group
= (addr
- 0x20) / 0x100;
1138 return s
->paim
[group
];
1143 group
= (addr
- 0x30) / 0x100;
1144 return s
->pape
[group
];
1149 group
= (addr
- 0x40) / 0x100;
1150 return s
->pafun
[group
];
1155 group
= (addr
- 0x50) / 0x100;
1156 return s
->pasel
[group
];
1161 group
= (addr
- 0x60) / 0x100;
1162 return s
->padir
[group
];
1167 group
= (addr
- 0x70) / 0x100;
1168 return s
->patrg
[group
];
1173 group
= (addr
- 0x80) / 0x100;
1174 return s
->paflg
[group
];
1176 cpu_abort(s
->soc
->env
,
1177 "jz4740_gpio_read undefined addr " JZ_FMT_plx
" \n", addr
);
1182 static void jz4740_gpio_write(void *opaque
, target_phys_addr_t addr
,
1185 struct jz4740_gpio_s
*s
= (struct jz4740_gpio_s
*) opaque
;
1188 debug_out(DEBUG_GPIO
, "jz4740_gpio_write addr %x value %x\n", addr
, value
);
1228 JZ4740_RO_REG(addr
);
1234 group
= (addr
- 0x14) / 0x100;
1235 s
->padat
[group
] = value
;
1241 group
= (addr
- 0x18) / 0x100;
1242 s
->padat
[group
] &= ~value
;
1248 group
= (addr
- 0x24) / 0x100;
1249 s
->paim
[group
] = value
;
1255 group
= (addr
- 0x28) / 0x100;
1256 s
->paim
[group
] &= ~value
;
1262 group
= (addr
- 0x34) / 0x100;
1263 s
->pape
[group
] = value
;
1269 group
= (addr
- 0x38) / 0x100;
1270 s
->pape
[group
] &= ~value
;
1276 group
= (addr
- 0x44) / 0x100;
1277 s
->pafun
[group
] = value
;
1283 group
= (addr
- 0x48) / 0x100;
1284 s
->pafun
[group
] &= ~value
;
1290 group
= (addr
- 0x54) / 0x100;
1291 s
->pasel
[group
] = value
;
1297 group
= (addr
- 0x58) / 0x100;
1298 s
->pasel
[group
] &= ~value
;
1304 group
= (addr
- 0x64) / 0x100;
1305 s
->padir
[group
] = value
;
1311 group
= (addr
- 0x68) / 0x100;
1312 s
->padir
[group
] &= ~value
;
1318 group
= (addr
- 0x74) / 0x100;
1319 s
->patrg
[group
] = value
;
1325 group
= (addr
- 0x78) / 0x100;
1326 s
->patrg
[group
] &= ~value
;
1332 group
= (addr
- 0x74) / 0x100;
1333 s
->paflg
[group
] &= ~value
;
1336 cpu_abort(s
->soc
->env
,
1337 "jz4740_gpio_write undefined addr " JZ_FMT_plx
1338 " value %x \n", addr
, value
);
1346 static CPUReadMemoryFunc
*jz4740_gpio_readfn
[] = {
1347 jz4740_badwidth_read32
,
1348 jz4740_badwidth_read32
,
1352 static CPUWriteMemoryFunc
*jz4740_gpio_writefn
[] = {
1353 jz4740_badwidth_write32
,
1354 jz4740_badwidth_write32
,
1358 static struct jz4740_gpio_s
*jz4740_gpio_init(struct jz_state_s
*soc
,
1362 struct jz4740_gpio_s
*s
= (struct jz4740_gpio_s
*) qemu_mallocz(sizeof(*s
));
1363 s
->base
= JZ4740_PHYS_BASE(JZ4740_GPIO_BASE
);
1367 jz4740_gpio_reset(s
);
1370 cpu_register_io_memory(0, jz4740_gpio_readfn
, jz4740_gpio_writefn
, s
);
1371 cpu_register_physical_memory(s
->base
, 0x00010000, iomemtype
);
1379 target_phys_addr_t base
;
1380 struct jz_state_s
*soc
;
1402 static void jz4740_rtc_update_interrupt(struct jz4740_rtc_s
*s
)
1407 if (((s
->rtccr
& 0x40) && (s
->rtccr
& 0x20))
1408 || ((s
->rtccr
& 0x10) && (s
->rtccr
& 0x8)))
1410 debug_out(DEBUG_RTC
,"s->rtccr %x \n",s
->rtcsr
);
1411 qemu_set_irq(s
->irq
, 1);
1417 static inline void jz4740_rtc_start(struct jz4740_rtc_s
*s
)
1419 s
->next
= +qemu_get_clock(rt_clock
);
1420 qemu_mod_timer(s
->hz_tm
, s
->next
);
1423 static inline void jz4740_rtc_stop(struct jz4740_rtc_s
*s
)
1425 qemu_del_timer(s
->hz_tm
);
1426 s
->next
= -qemu_get_clock(rt_clock
);
1431 static void jz4740_rtc_hz(void *opaque
)
1433 struct jz4740_rtc_s
*s
= (struct jz4740_rtc_s
*) opaque
;
1436 qemu_mod_timer(s
->hz_tm
, s
->next
);
1443 if (s
->rtcsr
== s
->rtcsar
)
1446 jz4740_rtc_update_interrupt(s
);
1450 static void jz4740_rtc_reset(struct jz4740_rtc_s
*s
)
1456 /*Maybe rtcsr need to be saved to file */
1457 s
->rtcsr
= time(NULL
);
1458 jz4740_rtc_start(s
);
1462 static uint32_t jz4740_rtc_read(void *opaque
, target_phys_addr_t addr
)
1464 struct jz4740_rtc_s
*s
= (struct jz4740_rtc_s
*) opaque
;
1466 debug_out(DEBUG_RTC
, "jz4740_rtc_read addr %x\n", addr
);
1470 return s
->rtccr
| 0x80;
1490 cpu_abort(s
->soc
->env
,
1491 "jz4740_rtc_read undefined addr " JZ_FMT_plx
"\n", addr
);
1497 static void jz4740_rtc_write(void *opaque
, target_phys_addr_t addr
,
1500 struct jz4740_rtc_s
*s
= (struct jz4740_rtc_s
*) opaque
;
1502 debug_out(DEBUG_RTC
, "jz4740_rtc_write addr %x value %x\n", addr
, value
);
1507 s
->rtccr
= value
& 0x7d;
1514 jz4740_rtc_start(s
);
1526 s
->rtcgr
= value
& 0x13ffffff;
1529 s
->hcr
= value
& 0x1;
1532 s
->hwfcr
= value
& 0xffe0;
1535 s
->hrcr
= value
& 0xfe0;
1538 s
->hwcr
= value
& 0x1;
1541 s
->hwrsr
= value
& 0x33;
1547 cpu_abort(s
->soc
->env
,
1548 "jz4740_rtc_write undefined addr " JZ_FMT_plx
1549 " value %x \n", addr
, value
);
1554 static CPUReadMemoryFunc
*jz4740_rtc_readfn
[] = {
1555 jz4740_badwidth_read32
,
1556 jz4740_badwidth_read32
,
1560 static CPUWriteMemoryFunc
*jz4740_rtc_writefn
[] = {
1561 jz4740_badwidth_write32
,
1562 jz4740_badwidth_write32
,
1566 static struct jz4740_rtc_s
*jz4740_rtc_init(struct jz_state_s
*soc
,
1570 struct jz4740_rtc_s
*s
= (struct jz4740_rtc_s
*) qemu_mallocz(sizeof(*s
));
1571 s
->base
= JZ4740_PHYS_BASE(JZ4740_RTC_BASE
);
1575 s
->hz_tm
= qemu_new_timer(rt_clock
, jz4740_rtc_hz
, s
);
1577 jz4740_rtc_reset(s
);
1580 cpu_register_io_memory(0, jz4740_rtc_readfn
, jz4740_rtc_writefn
, s
);
1581 cpu_register_physical_memory(s
->base
, 0x00001000, iomemtype
);
1591 target_phys_addr_t base
;
1592 struct jz_state_s
*soc
;
1595 QEMUTimer
*half_timer
[8];
1596 QEMUTimer
*full_timer
[8];
1609 uint32_t prescale
[8];
1613 static void jz4740_tcu_update_interrupt(struct jz4740_tcu_s
*s
)
1615 //printf("s->tfr %x s->tmr %x \n",s->tfr,s->tmr);
1616 if (((s
->tfr
& 0x1) & (~(s
->tmr
& 0x1)))
1617 || ((s
->tfr
& 0x10000) & (~(s
->tmr
& 0x10000))))
1619 qemu_set_irq(s
->tcu_irq0
, 1);
1622 qemu_set_irq(s
->tcu_irq0
, 0);
1624 if (((s
->tfr
& 0x2) & (~(s
->tmr
& 0x2)))
1625 || ((s
->tfr
& 0x20000) & (~(s
->tmr
& 0x20000))))
1627 qemu_set_irq(s
->tcu_irq1
, 1);
1630 qemu_set_irq(s
->tcu_irq1
, 0);
1632 if (((s
->tfr
& 0xfc) & (~(s
->tmr
& 0xfc)))
1633 || ((s
->tfr
& 0xfc0000) & (~(s
->tmr
& 0xfc0000))))
1635 qemu_set_irq(s
->tcu_irq2
, 1);
1638 qemu_set_irq(s
->tcu_irq2
, 0);
1644 #include "mips_jz_glue.h"
1646 #include "mips_jz_glue.h"
1648 #include "mips_jz_glue.h"
1650 #include "mips_jz_glue.h"
1652 #include "mips_jz_glue.h"
1654 #include "mips_jz_glue.h"
1656 #include "mips_jz_glue.h"
1658 #include "mips_jz_glue.h"
1661 #define jz4740_tcu_start(s) do { \
1662 jz4740_tcu_start_half0(s); \
1663 jz4740_tcu_start_full0(s); \
1664 jz4740_tcu_start_half1(s); \
1665 jz4740_tcu_start_full1(s); \
1666 jz4740_tcu_start_half2(s); \
1667 jz4740_tcu_start_full2(s); \
1668 jz4740_tcu_start_half3(s); \
1669 jz4740_tcu_start_full3(s); \
1670 jz4740_tcu_start_half4(s); \
1671 jz4740_tcu_start_full4(s); \
1672 jz4740_tcu_start_half5(s); \
1673 jz4740_tcu_start_full5(s); \
1674 jz4740_tcu_start_half6(s); \
1675 jz4740_tcu_start_full6(s); \
1676 jz4740_tcu_start_half7(s); \
1677 jz4740_tcu_start_full7(s); \
1680 static void jz4740_tcu_if_reset(struct jz4740_tcu_s
*s
)
1688 for (i
= 0; i
< 8; i
++)
1690 s
->tdfr
[i
] = 0xffff;
1691 s
->tdhr
[i
] = 0x8000;
1694 s
->half_timer
[i
] = NULL
;
1695 s
->full_timer
[i
] = NULL
;
1699 static void jz4740_tcu_if_write8(void *opaque
, target_phys_addr_t addr
,
1702 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) opaque
;
1704 debug_out(DEBUG_TCU
, "jz4740_tcu_if_write8 addr %x value %x\n", addr
,
1710 s
->ter
|= (value
& 0xff);
1711 jz4740_tcu_start(s
);
1714 s
->ter
&= ~(value
& 0xff);
1715 jz4740_tcu_start(s
);
1718 cpu_abort(s
->soc
->env
,
1719 "jz4740_tcu_if_write8 undefined addr " JZ_FMT_plx
1720 " value %x \n", addr
, value
);
1725 static void jz4740_tcu_if_write32(void *opaque
, target_phys_addr_t addr
,
1728 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) opaque
;
1730 debug_out(DEBUG_TCU
, "jz4740_tcu_if_write32 addr %x value %x\n", addr
,
1736 s
->tsr
|= (value
& 0x100ff);
1737 jz4740_tcu_start(s
);
1740 s
->tsr
&= ~(value
& 0x100ff);
1741 jz4740_tcu_start(s
);
1744 s
->tfr
|= (value
& 0xff00ff);
1747 s
->tfr
&= ~(value
& 0xff00ff);
1750 s
->tmr
|= (value
& 0xff00ff);
1751 jz4740_tcu_update_interrupt(s
);
1754 s
->tmr
&= ~(value
& 0xff00ff);
1755 jz4740_tcu_update_interrupt(s
);
1758 cpu_abort(s
->soc
->env
,
1759 "jz4740_tcu_if_write32 undefined addr " JZ_FMT_plx
1760 " value %x \n", addr
, value
);
1765 static uint32_t jz4740_tcu_if_read8(void *opaque
, target_phys_addr_t addr
)
1767 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) opaque
;
1769 debug_out(DEBUG_TCU
, "jz4740_tcu_if_read8 addr %x\n", addr
);
1776 cpu_abort(s
->soc
->env
,
1777 "jz4740_tcu_if_read8 undefined addr " JZ_FMT_plx
"\n", addr
);
1782 static uint32_t jz4740_tcu_if_read32(void *opaque
, target_phys_addr_t addr
)
1784 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) opaque
;
1786 debug_out(DEBUG_TCU
, "jz4740_tcu_if_read32 addr %x\n", addr
);
1797 cpu_abort(s
->soc
->env
,
1798 "jz4740_tcu_if_read32 undefined addr " JZ_FMT_plx
"\n", addr
);
1805 static CPUReadMemoryFunc
*jz4740_tcu_if_readfn
[] = {
1806 jz4740_tcu_if_read8
,
1807 jz4740_badwidth_read32
,
1808 jz4740_tcu_if_read32
,
1811 static CPUWriteMemoryFunc
*jz4740_tcu_if_writefn
[] = {
1812 jz4740_tcu_if_write8
,
1813 jz4740_badwidth_write32
,
1814 jz4740_tcu_if_write32
,
1817 static struct jz4740_tcu_s
*jz4740_tcu_if_init(struct jz_state_s
*soc
,
1825 struct jz4740_tcu_s
*s
= (struct jz4740_tcu_s
*) qemu_mallocz(sizeof(*s
));
1826 s
->base
= JZ4740_PHYS_BASE(JZ4740_TCU_BASE
);
1828 s
->tcu_irq0
= tcu_irq0
;
1829 s
->tcu_irq1
= tcu_irq1
;
1830 s
->tcu_irq2
= tcu_irq2
;
1832 jz4740_tcu_if_reset(s
);
1835 cpu_register_io_memory(0, jz4740_tcu_if_readfn
, jz4740_tcu_if_writefn
,
1837 cpu_register_physical_memory(s
->base
, 0x00000040, iomemtype
);
1842 static void jz4740_tcu_init(struct jz_state_s
*soc
,
1843 struct jz4740_tcu_s
*s
, int timer_index
)
1845 switch (timer_index
)
1848 jz4740_tcu_init0(soc
, s
);
1851 jz4740_tcu_init1(soc
, s
);
1854 jz4740_tcu_init2(soc
, s
);
1857 jz4740_tcu_init3(soc
, s
);
1860 jz4740_tcu_init4(soc
, s
);
1863 jz4740_tcu_init5(soc
, s
);
1866 jz4740_tcu_init6(soc
, s
);
1869 jz4740_tcu_init7(soc
, s
);
1872 cpu_abort(s
->soc
->env
,
1873 "jz4740_tcu_init undefined timer %x \n", timer_index
);
1877 typedef void (*jz4740_lcd_fn_t
) (uint8_t * d
, const uint8_t * s
, int width
,
1878 const uint16_t * pal
);
1879 struct jz_fb_descriptor
1881 uint32_t fdadr
; /* Frame descriptor address register */
1882 uint32_t fsadr
; /* Frame source address register */
1883 uint32_t fidr
; /* Frame ID register */
1884 uint32_t ldcmd
; /* Command register */
1887 struct jz4740_lcdc_s
1891 target_phys_addr_t base
;
1892 struct jz_state_s
*soc
;
1894 DisplayState
*state
;
1895 QEMUConsole
*console
;
1896 jz4740_lcd_fn_t
*line_fn_tab
;
1897 jz4740_lcd_fn_t line_fn
;
1926 uint32_t bpp
; /*bit per second */
1927 uint16_t palette
[256];
1928 uint32_t invalidate
;
1933 static const int jz4740_lcd_bpp
[0x6] = {
1934 1, 2, 4, 8, 16, 32 /*4740 uses 32 bit for 24bpp */
1937 static void jz4740_lcdc_reset(struct jz4740_lcdc_s
*s
)
1942 static uint32_t jz4740_lcdc_read(void *opaque
, target_phys_addr_t addr
)
1944 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) opaque
;
1946 debug_out(DEBUG_LCDC
, "jz4740_lcdc_read addr %x \n", addr
);
1992 cpu_abort(s
->soc
->env
,
1993 "jz4740_lcdc_read undefined addr " JZ_FMT_plx
" \n", addr
);
1999 static void jz4740_lcdc_write(void *opaque
, target_phys_addr_t addr
,
2002 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) opaque
;
2004 debug_out(DEBUG_LCDC
, "jz4740_lcdc_write addr %x value %x\n", addr
, value
);
2011 JZ4740_RO_REG(addr
);
2014 s
->lcdcfg
= value
& 0x80ffffbf;
2017 s
->lcdvsync
= value
& 0x7ff07ff;
2020 s
->lcdhsync
= value
& 0x7ff07ff;
2023 s
->lcdvat
= value
& 0x7ff07ff;
2026 s
->lcddah
= value
& 0x7ff07ff;
2027 s
->width
= (value
& 0x7ff) - ((value
>> 16) & 0x7ff);
2030 s
->height
= (value
& 0x7ff) - ((value
>> 16) & 0x7ff);
2031 s
->lcddav
= value
& 0x7ff07ff;
2034 s
->lcdps
= value
& 0x7ff07ff;
2037 s
->lcdcls
= value
& 0x7ff07ff;
2040 s
->lcdspl
= value
& 0x7ff07ff;
2043 s
->lcdrev
= value
& 0x7ff0000;
2046 s
->lcdctrl
= value
& 0x3fff3fff;
2047 s
->ena
= (value
& 0x8) >> 3;
2048 s
->dis
= (value
& 0x10) >> 4;
2049 s
->bpp
= jz4740_lcd_bpp
[value
& 0x7];
2052 fprintf(stderr
, "bpp =1 is not supported\n");
2055 s
->line_fn
= s
->line_fn_tab
[value
& 0x7];
2058 s
->lcdstate
= value
& 0xbf;
2070 cpu_abort(s
->soc
->env
,
2071 "jz4740_lcdc_write undefined addr " JZ_FMT_plx
" value %x \n",
2077 static CPUReadMemoryFunc
*jz4740_lcdc_readfn
[] = {
2078 jz4740_badwidth_read32
,
2079 jz4740_badwidth_read32
,
2083 static CPUWriteMemoryFunc
*jz4740_lcdc_writefn
[] = {
2084 jz4740_badwidth_write32
,
2085 jz4740_badwidth_write32
,
2089 #include "pixel_ops.h"
2090 #define JZ4740_LCD_PANEL
2092 #include "mips_jz_glue.h"
2094 #include "mips_jz_glue.h"
2096 #include "mips_jz_glue.h"
2098 #include "mips_jz_glue.h"
2100 #include "mips_jz_glue.h"
2101 #undef JZ4740_LCD_PANEL
2103 static void *jz4740_lcd_get_buffer(struct jz4740_lcdc_s
*s
,
2104 target_phys_addr_t addr
)
2108 pd
= cpu_get_physical_page_desc(addr
);
2109 if ((pd
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2111 cpu_abort(cpu_single_env
, "%s: framebuffer outside RAM!\n",
2114 return phys_ram_base
+
2115 (pd
& TARGET_PAGE_MASK
) + (addr
& ~TARGET_PAGE_MASK
);
2118 static void jz4740_lcd_update_display(void *opaque
)
2120 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) opaque
;
2122 uint8_t *src
, *dest
;
2123 struct jz_fb_descriptor
*fb_des
;
2137 fb_des
= (struct jz_fb_descriptor
*) jz4740_lcd_get_buffer(s
, s
->lcdda0
);
2138 s
->lcdda0
= fb_des
->fdadr
;
2139 s
->lcdsa0
= fb_des
->fsadr
;
2140 s
->lcdfid0
= fb_des
->fidr
;
2141 s
->lcdcmd0
= fb_des
->ldcmd
;
2143 src
= (uint8_t *) jz4740_lcd_get_buffer(s
, fb_des
->fsadr
);
2144 if (s
->lcdcmd0
& (0x1 << 28))
2147 memcpy(s
->palette
, src
, sizeof(s
->palette
));
2153 if (s
->width
!= ds_get_width(s
->state
) ||
2154 s
->height
!= ds_get_height(s
->state
))
2156 qemu_console_resize(s
->console
, s
->width
, s
->height
);
2160 step
= (s
->width
* s
->bpp
) >> 3;
2161 dest
= ds_get_data(s
->state
);
2162 linesize
= ds_get_linesize(s
->state
);
2164 //printf("s->width %d s->height %d s->bpp %d linesize %d \n",s->width,s->height ,s->bpp,linesize);
2166 for (y
= 0; y
< s
->height
; y
++)
2168 s
->line_fn(dest
, src
, s
->width
, s
->palette
);
2169 //memcpy(dest,src,step);
2175 dpy_update(s
->state
, 0, 0, s
->width
, s
->height
);
2176 s
->lcdstate
|= 0x20;
2177 if ((s
->lcdcmd0
& 0x40000000) && (!(s
->lcdctrl
& 0x2000)))
2178 qemu_set_irq(s
->irq
, 1);
2181 static inline void jz4740_lcd_invalidate_display(void *opaque
)
2183 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) opaque
;
2187 static struct jz4740_lcdc_s
*jz4740_lcdc_init(struct jz_state_s
*soc
,
2188 qemu_irq irq
, DisplayState
* ds
)
2192 struct jz4740_lcdc_s
*s
= (struct jz4740_lcdc_s
*) qemu_mallocz(sizeof(*s
));
2193 s
->base
= JZ4740_PHYS_BASE(JZ4740_LCD_BASE
);
2199 jz4740_lcdc_reset(s
);
2202 cpu_register_io_memory(0, jz4740_lcdc_readfn
, jz4740_lcdc_writefn
, s
);
2203 cpu_register_physical_memory(s
->base
, 0x10000, iomemtype
);
2205 s
->console
= graphic_console_init(s
->state
, jz4740_lcd_update_display
,
2206 jz4740_lcd_invalidate_display
,
2208 switch (ds_get_bits_per_pixel(s
->state
))
2211 s
->line_fn_tab
= qemu_mallocz(sizeof(jz4740_lcd_fn_t
) * 6);
2214 s
->line_fn_tab
= jz4740_lcd_draw_fn_8
;
2217 s
->line_fn_tab
= jz4740_lcd_draw_fn_15
;
2220 s
->line_fn_tab
= jz4740_lcd_draw_fn_16
;
2223 s
->line_fn_tab
= jz4740_lcd_draw_fn_24
;
2226 s
->line_fn_tab
= jz4740_lcd_draw_fn_32
;
2229 fprintf(stderr
, "%s: Bad color depth\n", __FUNCTION__
);
2237 #define JZ4740_DMA_NUM 6
2242 target_phys_addr_t base
;
2243 struct jz_state_s
*soc
;
2250 uint32_t dsa
[JZ4740_DMA_NUM
];
2251 uint32_t dta
[JZ4740_DMA_NUM
];
2252 uint32_t dtc
[JZ4740_DMA_NUM
];
2253 uint32_t drs
[JZ4740_DMA_NUM
];
2254 uint32_t dcs
[JZ4740_DMA_NUM
];
2255 uint32_t dcm
[JZ4740_DMA_NUM
];
2256 uint32_t dda
[JZ4740_DMA_NUM
];
2260 struct jz4740_desc_s
2262 uint32_t dcmd
; /* DCMD value for the current transfer */
2263 uint32_t dsadr
; /* DSAR value for the current transfer */
2264 uint32_t dtadr
; /* DTAR value for the current transfer */
2265 uint32_t ddadr
; /* Points to the next descriptor + transfer count */
2268 static inline void jz4740_dma_transfer(struct jz4740_dma_s
*s
,
2269 target_phys_addr_t src
,
2270 target_phys_addr_t dest
, uint32_t len
)
2272 uint32_t pd_src
, pd_dest
;
2275 pd_src
= cpu_get_physical_page_desc(src
);
2276 if ((pd_src
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2278 cpu_abort(cpu_single_env
, "%s: DMA source address %x outside RAM!\n",
2281 sr
= phys_ram_base
+
2282 (pd_src
& TARGET_PAGE_MASK
) + (src
& ~TARGET_PAGE_MASK
);
2284 pd_dest
= cpu_get_physical_page_desc(dest
);
2285 if ((pd_dest
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2287 cpu_abort(cpu_single_env
,
2288 "%s: DMA destination address %x outside RAM!\n",
2289 __FUNCTION__
, dest
);
2291 de
= phys_ram_base
+
2292 (pd_dest
& TARGET_PAGE_MASK
) + (dest
& ~TARGET_PAGE_MASK
);
2294 memcpy(de
, sr
, len
);
2297 static inline uint32_t jz4740_dma_unit_size(struct jz4740_dma_s
*s
,
2300 switch ((cmd
& 0x700) >> 8)
2317 /*No-descriptor transfer*/
2318 static inline void jz4740_dma_ndrun(struct jz4740_dma_s
*s
, int channel
)
2322 len
= jz4740_dma_unit_size(s
, s
->dcs
[channel
]) * s
->dtc
[channel
];
2324 jz4740_dma_transfer(s
, s
->dsa
[channel
], s
->dta
[channel
], len
);
2326 /*finish dma transfer */
2327 s
->dtc
[channel
] = 0;
2329 s
->dirqp
|= 1 << channel
;
2331 /*some cleanup work */
2332 /*clean AR TT GLOBAL AR */
2333 s
->dcs
[channel
] &= 0xffffffe7;
2334 s
->dmac
&= 0xfffffffb;
2336 if (s
->dcm
[channel
] & 0x2)
2337 qemu_set_irq(s
->irq
, 1);
2340 /*descriptor transfer */
2341 static inline void jz4740_dma_drun(struct jz4740_dma_s
*s
, int channel
)
2343 struct jz4740_desc_s
*desc
;
2344 target_phys_addr_t desc_phy
;
2347 desc_phy
= s
->dda
[channel
];
2349 cpu_abort(s
->soc
->env
,
2350 "jz4740_dma_drun descriptor address " JZ_FMT_plx
2351 " must be 4 bytes aligned \n", desc_phy
);
2353 pd
= cpu_get_physical_page_desc(desc_phy
);
2354 if ((pd
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2355 cpu_abort(cpu_single_env
,
2356 "%s: DMA descriptor address " JZ_FMT_plx
" outside RAM!\n",
2357 __FUNCTION__
, desc_phy
);
2359 desc
= (struct jz4740_desc_s
*) (phys_ram_base
+
2360 (pd
& TARGET_PAGE_MASK
) +
2361 (desc_phy
& ~TARGET_PAGE_MASK
));
2364 cpu_abort(cpu_single_env
,
2365 "%s: DMA descriptor " JZ_FMT_plx
" is NULL!\n", __FUNCTION__
,
2370 if ((desc
->dcmd
& 0x8) && (!(desc
->dcmd
& 0x10)))
2372 /*Stop DMA and set DCSN.INV=1 */
2373 s
->dcs
[channel
] |= 1 << 6;
2376 jz4740_dma_transfer(s
, desc
->dtadr
, desc
->dsadr
,
2377 (desc
->ddadr
& 0xffffff) *
2378 jz4740_dma_unit_size(s
, desc
->dcmd
));
2380 if ((desc
->dcmd
) & (1 << 3))
2382 desc
->dcmd
&= ~(1 << 4);
2383 if (desc
->dcmd
& 0x1)
2385 s
->dcs
[channel
] |= 0x2;
2388 s
->dcs
[channel
] |= 0x8;
2390 if (desc
->dcmd
& 0x2)
2391 qemu_set_irq(s
->irq
, 1);
2393 if ((desc
->dcmd
) & 0x1)
2395 /*fetch next descriptor */
2396 desc_phy
= s
->dda
[channel
] & 0xfffff000;
2397 desc_phy
+= (desc
->dtadr
& 0xff000000) >> 24;
2398 pd
= cpu_get_physical_page_desc(desc_phy
);
2399 if ((pd
& ~TARGET_PAGE_MASK
) != IO_MEM_RAM
)
2400 cpu_abort(cpu_single_env
,
2401 "%s: DMA descriptor address %x outside RAM!\n",
2402 __FUNCTION__
, desc_phy
);
2404 desc
= (struct jz4740_desc_s
*) (phys_ram_base
+
2405 (pd
& TARGET_PAGE_MASK
)
2408 ~TARGET_PAGE_MASK
));
2410 cpu_abort(cpu_single_env
,
2411 "%s: DMA descriptor %x is NULL!\n",
2412 __FUNCTION__
, (uint32_t) desc
);
2419 static void jz4740_dma_en_channel(struct jz4740_dma_s
*s
, int channel
)
2423 if (s
->dcs
[channel
] & (1 << 31))
2426 jz4740_dma_ndrun(s
, channel
);
2431 static inline void jz4740_dma_en_global(struct jz4740_dma_s
*s
)
2434 for (channel
= 0; channel
< JZ4740_DMA_NUM
; channel
++)
2436 jz4740_dma_en_channel(s
, channel
);
2440 static inline void jz4740_dma_en_dbn(struct jz4740_dma_s
*s
, int channel
)
2442 if ((s
->dmac
& 0x1) && (s
->dcs
[channel
] & (1 << 31)))
2444 jz4740_dma_drun(s
, channel
);
2448 static void jz4740_dma_reset(struct jz4740_dma_s
*s
)
2453 static uint32_t jz4740_dma_read(void *opaque
, target_phys_addr_t addr
)
2455 struct jz4740_dma_s
*s
= (struct jz4740_dma_s
*) opaque
;
2458 debug_out(DEBUG_DMA
, "jz4740_dma_read addr %x \n", addr
);
2473 channel
= (addr
- 0x0) / 0x20;
2474 return s
->dsa
[channel
];
2481 channel
= (addr
- 0x4) / 0x20;
2482 return s
->dta
[channel
];
2489 channel
= (addr
- 0x8) / 0x20;
2490 return s
->dtc
[channel
];
2497 channel
= (addr
- 0xc) / 0x20;
2498 return s
->drs
[channel
];
2505 channel
= (addr
- 0x10) / 0x20;
2506 return s
->dcs
[channel
];
2513 channel
= (addr
- 0x14) / 0x20;
2514 return s
->dcm
[channel
];
2521 channel
= (addr
- 0x18) / 0x20;
2522 return s
->dda
[channel
];
2524 cpu_abort(s
->soc
->env
,
2525 "jz4740_dma_read undefined addr " JZ_FMT_plx
" \n", addr
);
2530 static void jz4740_dma_write(void *opaque
, target_phys_addr_t addr
,
2533 struct jz4740_dma_s
*s
= (struct jz4740_dma_s
*) opaque
;
2536 debug_out(DEBUG_DMA
, "jz4740_dma_write addr %x value %x \n", addr
, value
);
2540 JZ4740_RO_REG(addr
);
2543 s
->dmac
= value
& 0x30d;
2545 jz4740_dma_en_global(s
);
2549 s
->ddr
= value
& 0xff;
2550 for (channel
= 0; channel
< JZ4740_DMA_NUM
; channel
++)
2552 if (s
->ddr
& (1 << channel
))
2554 jz4740_dma_en_dbn(s
, channel
);
2565 channel
= (addr
- 0x0) / 0x20;
2566 s
->dsa
[channel
] = value
;
2574 channel
= (addr
- 0x4) / 0x20;
2575 s
->dta
[channel
] = value
;
2583 channel
= (addr
- 0x8) / 0x20;
2584 s
->dtc
[channel
] = value
;
2592 channel
= (addr
- 0xc) / 0x20;
2593 s
->drs
[channel
] = value
& 0x10;
2594 if (s
->drs
[channel
] != 0x8)
2596 fprintf(stderr
, "Only auto request is supproted \n");
2605 channel
= (addr
- 0x10) / 0x20;
2606 s
->dcs
[channel
] = value
& 0x80ff005f;
2607 if (s
->dcs
[channel
] & 0x1)
2608 jz4740_dma_en_channel(s
, channel
);
2616 channel
= (addr
- 0x14) / 0x20;
2617 s
->dcm
[channel
] = value
& 0xcff79f;
2625 channel
= (addr
- 0x18) / 0x20;
2626 s
->dda
[channel
] = 0xfffffff0;
2629 cpu_abort(s
->soc
->env
,
2630 "jz4740_dma_read undefined addr " JZ_FMT_plx
" \n", addr
);
2635 static CPUReadMemoryFunc
*jz4740_dma_readfn
[] = {
2636 jz4740_badwidth_read32
,
2637 jz4740_badwidth_read32
,
2641 static CPUWriteMemoryFunc
*jz4740_dma_writefn
[] = {
2642 jz4740_badwidth_write32
,
2643 jz4740_badwidth_write32
,
2648 static struct jz4740_dma_s
*jz4740_dma_init(struct jz_state_s
*soc
,
2652 struct jz4740_dma_s
*s
= (struct jz4740_dma_s
*) qemu_mallocz(sizeof(*s
));
2653 s
->base
= JZ4740_PHYS_BASE(JZ4740_DMAC_BASE
);
2657 jz4740_dma_reset(s
);
2660 cpu_register_io_memory(0, jz4740_dma_readfn
, jz4740_dma_writefn
, s
);
2661 cpu_register_physical_memory(s
->base
, 0x00010000, iomemtype
);
2668 struct jz4740_sadc_s
2672 target_phys_addr_t base
;
2673 struct jz_state_s
*soc
;
2700 static void jz4740_touchscreen_interrupt(struct jz4740_sadc_s
*s
)
2705 if ((s
->adctrl
)&(s
->adstate
))
2707 debug_out(DEBUG_SADC
,"irq s->adctrl %x s->adstate %x \n",s
->adctrl
,s
->adstate
);
2708 qemu_set_irq(s
->irq
,1);
2713 static void jz4740_touchscreen_event(void *opaque
,
2714 int x
, int y
, int z
, int buttons_state
)
2716 struct jz4740_sadc_s
*s
= opaque
;
2721 s
->x
= (x
*4096)/0x7FFF;
2722 s
->y
= (y
*4096)/0x7FFF;
2724 if ((s
->pen_state
== PEN_UP
)&&(buttons_state
==PEN_DOWN
))
2727 jz4740_touchscreen_interrupt(s
);
2729 else if ((s
->pen_state
== PEN_DOWN
)&&(buttons_state
==PEN_UP
))
2732 jz4740_touchscreen_interrupt(s
);
2734 s
->pen_state
= buttons_state
;
2738 static uint32_t jz4740_sadc_read8(void *opaque
, target_phys_addr_t addr
)
2740 struct jz4740_sadc_s
*s
= (struct jz4740_sadc_s
*) opaque
;
2751 cpu_abort(s
->soc
->env
,
2752 "jz4740_sadc_read8 undefined addr " JZ_FMT_plx
" \n", addr
);
2757 static uint32_t jz4740_sdac_read16(void *opaque
, target_phys_addr_t addr
)
2759 struct jz4740_sadc_s
*s
= (struct jz4740_sadc_s
*) opaque
;
2772 cpu_abort(s
->soc
->env
,
2773 "jz4740_sdac_read16 undefined addr " JZ_FMT_plx
" \n", addr
);
2778 static uint32_t jz4740_sdac_read32(void *opaque
, target_phys_addr_t addr
)
2780 struct jz4740_sadc_s
*s
= (struct jz4740_sadc_s
*) opaque
;
2786 /*TODO: Other type format*/
2787 if (s
->read_index
==0)
2790 return (((s
->x
) & 0x7fff) | ((s
->y
& 0x7ffff) << 16));
2798 cpu_abort(s
->soc
->env
,
2799 "jz4740_sdac_read32 undefined addr " JZ_FMT_plx
" \n", addr
);
2804 static void jz4740_sadc_write8(void *opaque
, target_phys_addr_t addr
,
2807 struct jz4740_sadc_s
*s
= (struct jz4740_sadc_s
*) opaque
;
2809 debug_out(DEBUG_SADC
, "jz4740_sadc_write8 addr %x value %x\n", addr
, value
);
2814 s
->adena
= value
& 0x7;
2815 s
->tchen
= value
& 0x4;
2818 s
->adctrl
= value
& 0x1f;
2821 s
->adstate
&= ~(value
& 0x1f);
2824 cpu_abort(s
->soc
->env
,
2825 "jz4740_sadc_write8 undefined addr " JZ_FMT_plx
" value %x \n", addr
,value
);
2829 static void jz4740_sadc_write16(void *opaque
, target_phys_addr_t addr
,
2832 struct jz4740_sadc_s
*s
= (struct jz4740_sadc_s
*) opaque
;
2834 debug_out(DEBUG_SADC
, "jz4740_sadc_write16 addr %x value %x\n", addr
, value
);
2839 s
->adsame
= value
& 0xffff;
2842 s
->adsdat
= value
& 0xffff;
2849 cpu_abort(s
->soc
->env
,
2850 "jz4740_sadc_write16 undefined addr " JZ_FMT_plx
" value %x \n", addr
,value
);
2854 static void jz4740_sadc_write32(void *opaque
, target_phys_addr_t addr
,
2857 struct jz4740_sadc_s
*s
= (struct jz4740_sadc_s
*) opaque
;
2860 debug_out(DEBUG_SADC
, "jz4740_sadc_write32 addr %x value %x\n", addr
, value
);
2865 s
->adcfg
= value
& 0xc007ffff;
2866 s
->ex_in
= (value
& 0x40000000)>>30;
2867 s
->xyz
= (value
& 0x6fff)>>13;
2868 s
->snum
= ((value
& 0x1cff)>>10)+1;
2871 s
->adtch
= value
& 0x8fff8fff;
2874 cpu_abort(s
->soc
->env
,
2875 "jz4740_sadc_write32 undefined addr " JZ_FMT_plx
" value %x \n", addr
,value
);
2879 static void jz4740_sadc_reset(struct jz4740_sadc_s
*s
)
2881 s
->adcfg
= 0x0002002c;
2888 static CPUReadMemoryFunc
*jz4740_sadc_readfn
[] = {
2894 static CPUWriteMemoryFunc
*jz4740_sadc_writefn
[] = {
2896 jz4740_sadc_write16
,
2897 jz4740_sadc_write32
,
2900 static struct jz4740_sadc_s
*jz4740_sadc_init(struct jz_state_s
*soc
,
2904 struct jz4740_sadc_s
*s
;
2906 s
= (struct jz4740_sadc_s
*)
2907 qemu_mallocz(sizeof(struct jz4740_sadc_s
));
2908 s
->base
= JZ4740_PHYS_BASE(JZ4740_SADC_BASE
);
2912 qemu_add_mouse_event_handler(jz4740_touchscreen_event
, s
, 1,
2913 "QEMU JZ4740 Touchscreen");
2915 jz4740_sadc_reset(s
);
2918 cpu_register_io_memory(0, jz4740_sadc_readfn
, jz4740_sadc_writefn
, s
);
2919 cpu_register_physical_memory(s
->base
, 0x00001000, iomemtype
);
2923 static void jz4740_cpu_reset(void *opaque
)
2925 fprintf(stderr
, "%s: UNIMPLEMENTED!", __FUNCTION__
);
2928 struct jz_state_s
*jz4740_init(unsigned long sdram_size
,
2929 uint32_t osc_extal_freq
, DisplayState
* ds
)
2931 struct jz_state_s
*s
= (struct jz_state_s
*)
2932 qemu_mallocz(sizeof(struct jz_state_s
));
2933 ram_addr_t sram_base
, sdram_base
;
2936 s
->mpu_model
= jz4740
;
2937 s
->env
= cpu_init("jz4740");
2941 fprintf(stderr
, "Unable to find CPU definition\n");
2946 qemu_register_reset(jz4740_cpu_reset
, s
->env
);
2948 s
->sdram_size
= sdram_size
;
2949 s
->sram_size
= JZ4740_SRAM_SIZE
;
2952 jz_clk_init(s
, osc_extal_freq
);
2954 /*map sram to 0x80000000 and sdram to 0x80004000 */
2955 sram_base
= qemu_ram_alloc(s
->sram_size
);
2956 cpu_register_physical_memory(0x0, s
->sram_size
, (sram_base
| IO_MEM_RAM
));
2957 sdram_base
= qemu_ram_alloc(s
->sdram_size
);
2958 cpu_register_physical_memory(JZ4740_SRAM_SIZE
, s
->sdram_size
,
2959 (sdram_base
| IO_MEM_RAM
));
2961 /* Init internal devices */
2962 cpu_mips_irq_init_cpu(s
->env
);
2963 cpu_mips_clock_init(s
->env
);
2967 jz_clk_init(s
, osc_extal_freq
);
2969 intc
= jz4740_intc_init(s
, s
->env
->irq
[2]);
2970 s
->cpm
= jz4740_cpm_init(s
);
2971 s
->emc
= jz4740_emc_init(s
, intc
[2]);
2972 s
->gpio
= jz4740_gpio_init(s
, intc
[25]);
2973 s
->rtc
= jz4740_rtc_init(s
, intc
[15]);
2974 s
->tcu
= jz4740_tcu_if_init(s
, intc
[23], intc
[22], intc
[21]);
2975 jz4740_tcu_init(s
, s
->tcu
, 0);
2976 s
->lcdc
= jz4740_lcdc_init(s
, intc
[30], ds
);
2977 s
->dma
= jz4740_dma_init(s
, intc
[20]);
2978 s
->sadc
= jz4740_sadc_init(s
,intc
[12]);
2981 serial_mm_init(0x10030000, 2, intc
[9], 57600, serial_hds
[0], 1);