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target-ppc: add comments about constants introduced in revision 6046
[qemu/qemu-JZ.git] / target-ppc / op_helper.c
blob4c384266835b3653bde7ad47303113aa5b3ce29f
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21 #include "host-utils.h"
22 #include "helper.h"
23
24 #include "helper_regs.h"
25
26 //#define DEBUG_OP
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
29
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
32
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
34 {
35 #if 0
36 printf("Raise exception %3x code : %d\n", exception, error_code);
37 #endif
38 env->exception_index = exception;
39 env->error_code = error_code;
40 cpu_loop_exit();
41 }
42
43 void helper_raise_exception (uint32_t exception)
44 {
45 helper_raise_exception_err(exception, 0);
46 }
47
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong helper_load_cr (void)
51 {
52 return (env->crf[0] << 28) |
53 (env->crf[1] << 24) |
54 (env->crf[2] << 20) |
55 (env->crf[3] << 16) |
56 (env->crf[4] << 12) |
57 (env->crf[5] << 8) |
58 (env->crf[6] << 4) |
59 (env->crf[7] << 0);
60 }
61
62 void helper_store_cr (target_ulong val, uint32_t mask)
63 {
64 int i, sh;
65
66 for (i = 0, sh = 7; i < 8; i++, sh--) {
67 if (mask & (1 << sh))
68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
69 }
70 }
71
72 /*****************************************************************************/
73 /* SPR accesses */
74 void helper_load_dump_spr (uint32_t sprn)
75 {
76 if (loglevel != 0) {
77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
79 }
80 }
81
82 void helper_store_dump_spr (uint32_t sprn)
83 {
84 if (loglevel != 0) {
85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
87 }
88 }
89
90 target_ulong helper_load_tbl (void)
91 {
92 return cpu_ppc_load_tbl(env);
93 }
94
95 target_ulong helper_load_tbu (void)
96 {
97 return cpu_ppc_load_tbu(env);
98 }
99
100 target_ulong helper_load_atbl (void)
101 {
102 return cpu_ppc_load_atbl(env);
103 }
104
105 target_ulong helper_load_atbu (void)
106 {
107 return cpu_ppc_load_atbu(env);
108 }
109
110 target_ulong helper_load_601_rtcl (void)
111 {
112 return cpu_ppc601_load_rtcl(env);
113 }
114
115 target_ulong helper_load_601_rtcu (void)
116 {
117 return cpu_ppc601_load_rtcu(env);
118 }
119
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val)
123 {
124 ppc_store_asr(env, val);
125 }
126 #endif
127
128 void helper_store_sdr1 (target_ulong val)
129 {
130 ppc_store_sdr1(env, val);
131 }
132
133 void helper_store_tbl (target_ulong val)
134 {
135 cpu_ppc_store_tbl(env, val);
136 }
137
138 void helper_store_tbu (target_ulong val)
139 {
140 cpu_ppc_store_tbu(env, val);
141 }
142
143 void helper_store_atbl (target_ulong val)
144 {
145 cpu_ppc_store_atbl(env, val);
146 }
147
148 void helper_store_atbu (target_ulong val)
149 {
150 cpu_ppc_store_atbu(env, val);
151 }
152
153 void helper_store_601_rtcl (target_ulong val)
154 {
155 cpu_ppc601_store_rtcl(env, val);
156 }
157
158 void helper_store_601_rtcu (target_ulong val)
159 {
160 cpu_ppc601_store_rtcu(env, val);
161 }
162
163 target_ulong helper_load_decr (void)
164 {
165 return cpu_ppc_load_decr(env);
166 }
167
168 void helper_store_decr (target_ulong val)
169 {
170 cpu_ppc_store_decr(env, val);
171 }
172
173 void helper_store_hid0_601 (target_ulong val)
174 {
175 target_ulong hid0;
176
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
184 if (loglevel != 0) {
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
187 }
188 }
189 env->spr[SPR_HID0] = (uint32_t)val;
190 }
191
192 void helper_store_403_pbr (uint32_t num, target_ulong value)
193 {
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
197 tlb_flush(env, 1);
198 }
199 }
200
201 target_ulong helper_load_40x_pit (void)
202 {
203 return load_40x_pit(env);
204 }
205
206 void helper_store_40x_pit (target_ulong val)
207 {
208 store_40x_pit(env, val);
209 }
210
211 void helper_store_40x_dbcr0 (target_ulong val)
212 {
213 store_40x_dbcr0(env, val);
214 }
215
216 void helper_store_40x_sler (target_ulong val)
217 {
218 store_40x_sler(env, val);
219 }
220
221 void helper_store_booke_tcr (target_ulong val)
222 {
223 store_booke_tcr(env, val);
224 }
225
226 void helper_store_booke_tsr (target_ulong val)
227 {
228 store_booke_tsr(env, val);
229 }
230
231 void helper_store_ibatu (uint32_t nr, target_ulong val)
232 {
233 ppc_store_ibatu(env, nr, val);
234 }
235
236 void helper_store_ibatl (uint32_t nr, target_ulong val)
237 {
238 ppc_store_ibatl(env, nr, val);
239 }
240
241 void helper_store_dbatu (uint32_t nr, target_ulong val)
242 {
243 ppc_store_dbatu(env, nr, val);
244 }
245
246 void helper_store_dbatl (uint32_t nr, target_ulong val)
247 {
248 ppc_store_dbatl(env, nr, val);
249 }
250
251 void helper_store_601_batl (uint32_t nr, target_ulong val)
252 {
253 ppc_store_ibatl_601(env, nr, val);
254 }
255
256 void helper_store_601_batu (uint32_t nr, target_ulong val)
257 {
258 ppc_store_ibatu_601(env, nr, val);
259 }
260 #endif
261
262 /*****************************************************************************/
263 /* Memory load and stores */
264
265 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
266 {
267 #if defined(TARGET_PPC64)
268 if (!msr_sf)
269 return (uint32_t)(addr + arg);
270 else
271 #endif
272 return addr + arg;
273 }
274
275 void helper_lmw (target_ulong addr, uint32_t reg)
276 {
277 for (; reg < 32; reg++) {
278 if (msr_le)
279 env->gpr[reg] = bswap32(ldl(addr));
280 else
281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
283 }
284 }
285
286 void helper_stmw (target_ulong addr, uint32_t reg)
287 {
288 for (; reg < 32; reg++) {
289 if (msr_le)
290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
291 else
292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
294 }
295 }
296
297 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
298 {
299 int sh;
300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
302 reg = (reg + 1) % 32;
303 addr = addr_add(addr, 4);
304 }
305 if (unlikely(nb > 0)) {
306 env->gpr[reg] = 0;
307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
310 }
311 }
312 }
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
317 */
318 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
319 {
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
324 POWERPC_EXCP_INVAL |
325 POWERPC_EXCP_INVAL_LSWX);
326 } else {
327 helper_lsw(addr, xer_bc, reg);
328 }
329 }
330 }
331
332 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
333 {
334 int sh;
335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
337 reg = (reg + 1) % 32;
338 addr = addr_add(addr, 4);
339 }
340 if (unlikely(nb > 0)) {
341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
344 }
345 }
346
347 static void do_dcbz(target_ulong addr, int dcache_line_size)
348 {
349 addr &= ~(dcache_line_size - 1);
350 int i;
351 for (i = 0 ; i < dcache_line_size ; i += 4) {
352 stl(addr + i , 0);
353 }
354 if (env->reserve == addr)
355 env->reserve = (target_ulong)-1ULL;
356 }
357
358 void helper_dcbz(target_ulong addr)
359 {
360 do_dcbz(addr, env->dcache_line_size);
361 }
362
363 void helper_dcbz_970(target_ulong addr)
364 {
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
366 do_dcbz(addr, 32);
367 else
368 do_dcbz(addr, env->dcache_line_size);
369 }
370
371 void helper_icbi(target_ulong addr)
372 {
373 uint32_t tmp;
374
375 addr &= ~(env->dcache_line_size - 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
380 */
381 tmp = ldl(addr);
382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
383 }
384
385 // XXX: to be tested
386 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
387 {
388 int i, c, d;
389 d = 24;
390 for (i = 0; i < xer_bc; i++) {
391 c = ldub(addr);
392 addr = addr_add(addr, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
396 }
397 if (unlikely(c == xer_cmp))
398 break;
399 if (likely(d != 0)) {
400 d -= 8;
401 } else {
402 d = 24;
403 reg++;
404 reg = reg & 0x1F;
405 }
406 }
407 return i;
408 }
409
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
413
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
416 {
417 uint64_t tl, th;
418
419 muls64(&tl, &th, arg1, arg2);
420 return th;
421 }
422
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
425 {
426 uint64_t tl, th;
427
428 mulu64(&tl, &th, arg1, arg2);
429 return th;
430 }
431
432 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
433 {
434 int64_t th;
435 uint64_t tl;
436
437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th + 1) <= 1)) {
440 env->xer &= ~(1 << XER_OV);
441 } else {
442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
443 }
444 return (int64_t)tl;
445 }
446 #endif
447
448 target_ulong helper_cntlzw (target_ulong t)
449 {
450 return clz32(t);
451 }
452
453 #if defined(TARGET_PPC64)
454 target_ulong helper_cntlzd (target_ulong t)
455 {
456 return clz64(t);
457 }
458 #endif
459
460 /* shift right arithmetic helper */
461 target_ulong helper_sraw (target_ulong value, target_ulong shift)
462 {
463 int32_t ret;
464
465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
467 shift &= 0x1f;
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
470 env->xer &= ~(1 << XER_CA);
471 } else {
472 env->xer |= (1 << XER_CA);
473 }
474 } else {
475 ret = (int32_t)value;
476 env->xer &= ~(1 << XER_CA);
477 }
478 } else {
479 ret = (int32_t)value >> 31;
480 if (ret) {
481 env->xer |= (1 << XER_CA);
482 } else {
483 env->xer &= ~(1 << XER_CA);
484 }
485 }
486 return (target_long)ret;
487 }
488
489 #if defined(TARGET_PPC64)
490 target_ulong helper_srad (target_ulong value, target_ulong shift)
491 {
492 int64_t ret;
493
494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
496 shift &= 0x3f;
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
499 env->xer &= ~(1 << XER_CA);
500 } else {
501 env->xer |= (1 << XER_CA);
502 }
503 } else {
504 ret = (int64_t)value;
505 env->xer &= ~(1 << XER_CA);
506 }
507 } else {
508 ret = (int64_t)value >> 63;
509 if (ret) {
510 env->xer |= (1 << XER_CA);
511 } else {
512 env->xer &= ~(1 << XER_CA);
513 }
514 }
515 return ret;
516 }
517 #endif
518
519 target_ulong helper_popcntb (target_ulong val)
520 {
521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
524 return val;
525 }
526
527 #if defined(TARGET_PPC64)
528 target_ulong helper_popcntb_64 (target_ulong val)
529 {
530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
533 return val;
534 }
535 #endif
536
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg)
540 {
541 CPU_FloatU f;
542 CPU_DoubleU d;
543 f.l = arg;
544 d.d = float32_to_float64(f.f, &env->fp_status);
545 return d.ll;
546 }
547
548 uint32_t helper_float64_to_float32(uint64_t arg)
549 {
550 CPU_FloatU f;
551 CPU_DoubleU d;
552 d.ll = arg;
553 f.f = float64_to_float32(d.d, &env->fp_status);
554 return f.l;
555 }
556
557 static always_inline int isden (float64 d)
558 {
559 CPU_DoubleU u;
560
561 u.d = d;
562
563 return ((u.ll >> 52) & 0x7FF) == 0;
564 }
565
566 #ifdef CONFIG_SOFTFLOAT
567 static always_inline int isnormal (float64 d)
568 {
569 CPU_DoubleU u;
570
571 u.d = d;
572
573 uint32_t exp = (u.ll >> 52) & 0x7FF;
574 return ((0 < exp) && (exp < 0x7FF));
575 }
576 #endif
577
578 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
579 {
580 CPU_DoubleU farg;
581 int isneg;
582 int ret;
583 farg.ll = arg;
584 isneg = float64_is_neg(farg.d);
585 if (unlikely(float64_is_nan(farg.d))) {
586 if (float64_is_signaling_nan(farg.d)) {
587 /* Signaling NaN: flags are undefined */
588 ret = 0x00;
589 } else {
590 /* Quiet NaN */
591 ret = 0x11;
592 }
593 } else if (unlikely(float64_is_infinity(farg.d))) {
594 /* +/- infinity */
595 if (isneg)
596 ret = 0x09;
597 else
598 ret = 0x05;
599 } else {
600 if (float64_is_zero(farg.d)) {
601 /* +/- zero */
602 if (isneg)
603 ret = 0x12;
604 else
605 ret = 0x02;
606 } else {
607 if (isden(farg.d)) {
608 /* Denormalized numbers */
609 ret = 0x10;
610 } else {
611 /* Normalized numbers */
612 ret = 0x00;
613 }
614 if (isneg) {
615 ret |= 0x08;
616 } else {
617 ret |= 0x04;
618 }
619 }
620 }
621 if (set_fprf) {
622 /* We update FPSCR_FPRF */
623 env->fpscr &= ~(0x1F << FPSCR_FPRF);
624 env->fpscr |= ret << FPSCR_FPRF;
625 }
626 /* We just need fpcc to update Rc1 */
627 return ret & 0xF;
628 }
629
630 /* Floating-point invalid operations exception */
631 static always_inline uint64_t fload_invalid_op_excp (int op)
632 {
633 uint64_t ret = 0;
634 int ve;
635
636 ve = fpscr_ve;
637 switch (op) {
638 case POWERPC_EXCP_FP_VXSNAN:
639 env->fpscr |= 1 << FPSCR_VXSNAN;
640 break;
641 case POWERPC_EXCP_FP_VXSOFT:
642 env->fpscr |= 1 << FPSCR_VXSOFT;
643 break;
644 case POWERPC_EXCP_FP_VXISI:
645 /* Magnitude subtraction of infinities */
646 env->fpscr |= 1 << FPSCR_VXISI;
647 goto update_arith;
648 case POWERPC_EXCP_FP_VXIDI:
649 /* Division of infinity by infinity */
650 env->fpscr |= 1 << FPSCR_VXIDI;
651 goto update_arith;
652 case POWERPC_EXCP_FP_VXZDZ:
653 /* Division of zero by zero */
654 env->fpscr |= 1 << FPSCR_VXZDZ;
655 goto update_arith;
656 case POWERPC_EXCP_FP_VXIMZ:
657 /* Multiplication of zero by infinity */
658 env->fpscr |= 1 << FPSCR_VXIMZ;
659 goto update_arith;
660 case POWERPC_EXCP_FP_VXVC:
661 /* Ordered comparison of NaN */
662 env->fpscr |= 1 << FPSCR_VXVC;
663 env->fpscr &= ~(0xF << FPSCR_FPCC);
664 env->fpscr |= 0x11 << FPSCR_FPCC;
665 /* We must update the target FPR before raising the exception */
666 if (ve != 0) {
667 env->exception_index = POWERPC_EXCP_PROGRAM;
668 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
669 /* Update the floating-point enabled exception summary */
670 env->fpscr |= 1 << FPSCR_FEX;
671 /* Exception is differed */
672 ve = 0;
673 }
674 break;
675 case POWERPC_EXCP_FP_VXSQRT:
676 /* Square root of a negative number */
677 env->fpscr |= 1 << FPSCR_VXSQRT;
678 update_arith:
679 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
680 if (ve == 0) {
681 /* Set the result to quiet NaN */
682 ret = 0xFFF8000000000000ULL;
683 env->fpscr &= ~(0xF << FPSCR_FPCC);
684 env->fpscr |= 0x11 << FPSCR_FPCC;
685 }
686 break;
687 case POWERPC_EXCP_FP_VXCVI:
688 /* Invalid conversion */
689 env->fpscr |= 1 << FPSCR_VXCVI;
690 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
691 if (ve == 0) {
692 /* Set the result to quiet NaN */
693 ret = 0xFFF8000000000000ULL;
694 env->fpscr &= ~(0xF << FPSCR_FPCC);
695 env->fpscr |= 0x11 << FPSCR_FPCC;
696 }
697 break;
698 }
699 /* Update the floating-point invalid operation summary */
700 env->fpscr |= 1 << FPSCR_VX;
701 /* Update the floating-point exception summary */
702 env->fpscr |= 1 << FPSCR_FX;
703 if (ve != 0) {
704 /* Update the floating-point enabled exception summary */
705 env->fpscr |= 1 << FPSCR_FEX;
706 if (msr_fe0 != 0 || msr_fe1 != 0)
707 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
708 }
709 return ret;
710 }
711
712 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
713 {
714 env->fpscr |= 1 << FPSCR_ZX;
715 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
716 /* Update the floating-point exception summary */
717 env->fpscr |= 1 << FPSCR_FX;
718 if (fpscr_ze != 0) {
719 /* Update the floating-point enabled exception summary */
720 env->fpscr |= 1 << FPSCR_FEX;
721 if (msr_fe0 != 0 || msr_fe1 != 0) {
722 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
723 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
724 }
725 } else {
726 /* Set the result to infinity */
727 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
728 arg1 |= 0x7FFULL << 52;
729 }
730 return arg1;
731 }
732
733 static always_inline void float_overflow_excp (void)
734 {
735 env->fpscr |= 1 << FPSCR_OX;
736 /* Update the floating-point exception summary */
737 env->fpscr |= 1 << FPSCR_FX;
738 if (fpscr_oe != 0) {
739 /* XXX: should adjust the result */
740 /* Update the floating-point enabled exception summary */
741 env->fpscr |= 1 << FPSCR_FEX;
742 /* We must update the target FPR before raising the exception */
743 env->exception_index = POWERPC_EXCP_PROGRAM;
744 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
745 } else {
746 env->fpscr |= 1 << FPSCR_XX;
747 env->fpscr |= 1 << FPSCR_FI;
748 }
749 }
750
751 static always_inline void float_underflow_excp (void)
752 {
753 env->fpscr |= 1 << FPSCR_UX;
754 /* Update the floating-point exception summary */
755 env->fpscr |= 1 << FPSCR_FX;
756 if (fpscr_ue != 0) {
757 /* XXX: should adjust the result */
758 /* Update the floating-point enabled exception summary */
759 env->fpscr |= 1 << FPSCR_FEX;
760 /* We must update the target FPR before raising the exception */
761 env->exception_index = POWERPC_EXCP_PROGRAM;
762 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
763 }
764 }
765
766 static always_inline void float_inexact_excp (void)
767 {
768 env->fpscr |= 1 << FPSCR_XX;
769 /* Update the floating-point exception summary */
770 env->fpscr |= 1 << FPSCR_FX;
771 if (fpscr_xe != 0) {
772 /* Update the floating-point enabled exception summary */
773 env->fpscr |= 1 << FPSCR_FEX;
774 /* We must update the target FPR before raising the exception */
775 env->exception_index = POWERPC_EXCP_PROGRAM;
776 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
777 }
778 }
779
780 static always_inline void fpscr_set_rounding_mode (void)
781 {
782 int rnd_type;
783
784 /* Set rounding mode */
785 switch (fpscr_rn) {
786 case 0:
787 /* Best approximation (round to nearest) */
788 rnd_type = float_round_nearest_even;
789 break;
790 case 1:
791 /* Smaller magnitude (round toward zero) */
792 rnd_type = float_round_to_zero;
793 break;
794 case 2:
795 /* Round toward +infinite */
796 rnd_type = float_round_up;
797 break;
798 default:
799 case 3:
800 /* Round toward -infinite */
801 rnd_type = float_round_down;
802 break;
803 }
804 set_float_rounding_mode(rnd_type, &env->fp_status);
805 }
806
807 void helper_fpscr_clrbit (uint32_t bit)
808 {
809 int prev;
810
811 prev = (env->fpscr >> bit) & 1;
812 env->fpscr &= ~(1 << bit);
813 if (prev == 1) {
814 switch (bit) {
815 case FPSCR_RN1:
816 case FPSCR_RN:
817 fpscr_set_rounding_mode();
818 break;
819 default:
820 break;
821 }
822 }
823 }
824
825 void helper_fpscr_setbit (uint32_t bit)
826 {
827 int prev;
828
829 prev = (env->fpscr >> bit) & 1;
830 env->fpscr |= 1 << bit;
831 if (prev == 0) {
832 switch (bit) {
833 case FPSCR_VX:
834 env->fpscr |= 1 << FPSCR_FX;
835 if (fpscr_ve)
836 goto raise_ve;
837 case FPSCR_OX:
838 env->fpscr |= 1 << FPSCR_FX;
839 if (fpscr_oe)
840 goto raise_oe;
841 break;
842 case FPSCR_UX:
843 env->fpscr |= 1 << FPSCR_FX;
844 if (fpscr_ue)
845 goto raise_ue;
846 break;
847 case FPSCR_ZX:
848 env->fpscr |= 1 << FPSCR_FX;
849 if (fpscr_ze)
850 goto raise_ze;
851 break;
852 case FPSCR_XX:
853 env->fpscr |= 1 << FPSCR_FX;
854 if (fpscr_xe)
855 goto raise_xe;
856 break;
857 case FPSCR_VXSNAN:
858 case FPSCR_VXISI:
859 case FPSCR_VXIDI:
860 case FPSCR_VXZDZ:
861 case FPSCR_VXIMZ:
862 case FPSCR_VXVC:
863 case FPSCR_VXSOFT:
864 case FPSCR_VXSQRT:
865 case FPSCR_VXCVI:
866 env->fpscr |= 1 << FPSCR_VX;
867 env->fpscr |= 1 << FPSCR_FX;
868 if (fpscr_ve != 0)
869 goto raise_ve;
870 break;
871 case FPSCR_VE:
872 if (fpscr_vx != 0) {
873 raise_ve:
874 env->error_code = POWERPC_EXCP_FP;
875 if (fpscr_vxsnan)
876 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
877 if (fpscr_vxisi)
878 env->error_code |= POWERPC_EXCP_FP_VXISI;
879 if (fpscr_vxidi)
880 env->error_code |= POWERPC_EXCP_FP_VXIDI;
881 if (fpscr_vxzdz)
882 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
883 if (fpscr_vximz)
884 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
885 if (fpscr_vxvc)
886 env->error_code |= POWERPC_EXCP_FP_VXVC;
887 if (fpscr_vxsoft)
888 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
889 if (fpscr_vxsqrt)
890 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
891 if (fpscr_vxcvi)
892 env->error_code |= POWERPC_EXCP_FP_VXCVI;
893 goto raise_excp;
894 }
895 break;
896 case FPSCR_OE:
897 if (fpscr_ox != 0) {
898 raise_oe:
899 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
900 goto raise_excp;
901 }
902 break;
903 case FPSCR_UE:
904 if (fpscr_ux != 0) {
905 raise_ue:
906 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
907 goto raise_excp;
908 }
909 break;
910 case FPSCR_ZE:
911 if (fpscr_zx != 0) {
912 raise_ze:
913 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
914 goto raise_excp;
915 }
916 break;
917 case FPSCR_XE:
918 if (fpscr_xx != 0) {
919 raise_xe:
920 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
921 goto raise_excp;
922 }
923 break;
924 case FPSCR_RN1:
925 case FPSCR_RN:
926 fpscr_set_rounding_mode();
927 break;
928 default:
929 break;
930 raise_excp:
931 /* Update the floating-point enabled exception summary */
932 env->fpscr |= 1 << FPSCR_FEX;
933 /* We have to update Rc1 before raising the exception */
934 env->exception_index = POWERPC_EXCP_PROGRAM;
935 break;
936 }
937 }
938 }
939
940 void helper_store_fpscr (uint64_t arg, uint32_t mask)
941 {
942 /*
943 * We use only the 32 LSB of the incoming fpr
944 */
945 uint32_t prev, new;
946 int i;
947
948 prev = env->fpscr;
949 new = (uint32_t)arg;
950 new &= ~0x60000000;
951 new |= prev & 0x60000000;
952 for (i = 0; i < 8; i++) {
953 if (mask & (1 << i)) {
954 env->fpscr &= ~(0xF << (4 * i));
955 env->fpscr |= new & (0xF << (4 * i));
956 }
957 }
958 /* Update VX and FEX */
959 if (fpscr_ix != 0)
960 env->fpscr |= 1 << FPSCR_VX;
961 else
962 env->fpscr &= ~(1 << FPSCR_VX);
963 if ((fpscr_ex & fpscr_eex) != 0) {
964 env->fpscr |= 1 << FPSCR_FEX;
965 env->exception_index = POWERPC_EXCP_PROGRAM;
966 /* XXX: we should compute it properly */
967 env->error_code = POWERPC_EXCP_FP;
968 }
969 else
970 env->fpscr &= ~(1 << FPSCR_FEX);
971 fpscr_set_rounding_mode();
972 }
973
974 void helper_float_check_status (void)
975 {
976 #ifdef CONFIG_SOFTFLOAT
977 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
978 (env->error_code & POWERPC_EXCP_FP)) {
979 /* Differred floating-point exception after target FPR update */
980 if (msr_fe0 != 0 || msr_fe1 != 0)
981 helper_raise_exception_err(env->exception_index, env->error_code);
982 } else {
983 int status = get_float_exception_flags(&env->fp_status);
984 if (status & float_flag_overflow) {
985 float_overflow_excp();
986 } else if (status & float_flag_underflow) {
987 float_underflow_excp();
988 } else if (status & float_flag_inexact) {
989 float_inexact_excp();
990 }
991 }
992 #else
993 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
994 (env->error_code & POWERPC_EXCP_FP)) {
995 /* Differred floating-point exception after target FPR update */
996 if (msr_fe0 != 0 || msr_fe1 != 0)
997 helper_raise_exception_err(env->exception_index, env->error_code);
998 }
999 #endif
1000 }
1001
1002 #ifdef CONFIG_SOFTFLOAT
1003 void helper_reset_fpstatus (void)
1004 {
1005 set_float_exception_flags(0, &env->fp_status);
1006 }
1007 #endif
1008
1009 /* fadd - fadd. */
1010 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1011 {
1012 CPU_DoubleU farg1, farg2;
1013
1014 farg1.ll = arg1;
1015 farg2.ll = arg2;
1016 #if USE_PRECISE_EMULATION
1017 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1018 float64_is_signaling_nan(farg2.d))) {
1019 /* sNaN addition */
1020 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1021 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1022 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
1023 /* Magnitude subtraction of infinities */
1024 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1025 } else {
1026 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1027 }
1028 #else
1029 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1030 #endif
1031 return farg1.ll;
1032 }
1033
1034 /* fsub - fsub. */
1035 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1036 {
1037 CPU_DoubleU farg1, farg2;
1038
1039 farg1.ll = arg1;
1040 farg2.ll = arg2;
1041 #if USE_PRECISE_EMULATION
1042 {
1043 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1044 float64_is_signaling_nan(farg2.d))) {
1045 /* sNaN subtraction */
1046 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1047 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1048 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
1049 /* Magnitude subtraction of infinities */
1050 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1051 } else {
1052 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1053 }
1054 }
1055 #else
1056 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1057 #endif
1058 return farg1.ll;
1059 }
1060
1061 /* fmul - fmul. */
1062 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1063 {
1064 CPU_DoubleU farg1, farg2;
1065
1066 farg1.ll = arg1;
1067 farg2.ll = arg2;
1068 #if USE_PRECISE_EMULATION
1069 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1070 float64_is_signaling_nan(farg2.d))) {
1071 /* sNaN multiplication */
1072 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1073 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1074 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1075 /* Multiplication of zero by infinity */
1076 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1077 } else {
1078 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1079 }
1080 #else
1081 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1082 #endif
1083 return farg1.ll;
1084 }
1085
1086 /* fdiv - fdiv. */
1087 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1088 {
1089 CPU_DoubleU farg1, farg2;
1090
1091 farg1.ll = arg1;
1092 farg2.ll = arg2;
1093 #if USE_PRECISE_EMULATION
1094 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1095 float64_is_signaling_nan(farg2.d))) {
1096 /* sNaN division */
1097 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1098 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
1099 /* Division of infinity by infinity */
1100 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1101 } else if (unlikely(!float64_is_nan(farg1.d) && float64_is_zero(farg2.d))) {
1102 if (float64_is_zero(farg1.d)) {
1103 /* Division of zero by zero */
1104 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1105 } else {
1106 /* Division by zero */
1107 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1108 }
1109 } else {
1110 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1111 }
1112 #else
1113 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1114 #endif
1115 return farg1.ll;
1116 }
1117
1118 /* fabs */
1119 uint64_t helper_fabs (uint64_t arg)
1120 {
1121 CPU_DoubleU farg;
1122
1123 farg.ll = arg;
1124 farg.d = float64_abs(farg.d);
1125 return farg.ll;
1126 }
1127
1128 /* fnabs */
1129 uint64_t helper_fnabs (uint64_t arg)
1130 {
1131 CPU_DoubleU farg;
1132
1133 farg.ll = arg;
1134 farg.d = float64_abs(farg.d);
1135 farg.d = float64_chs(farg.d);
1136 return farg.ll;
1137 }
1138
1139 /* fneg */
1140 uint64_t helper_fneg (uint64_t arg)
1141 {
1142 CPU_DoubleU farg;
1143
1144 farg.ll = arg;
1145 farg.d = float64_chs(farg.d);
1146 return farg.ll;
1147 }
1148
1149 /* fctiw - fctiw. */
1150 uint64_t helper_fctiw (uint64_t arg)
1151 {
1152 CPU_DoubleU farg;
1153 farg.ll = arg;
1154
1155 if (unlikely(float64_is_signaling_nan(farg.d))) {
1156 /* sNaN conversion */
1157 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1158 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1159 /* qNan / infinity conversion */
1160 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1161 } else {
1162 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1163 #if USE_PRECISE_EMULATION
1164 /* XXX: higher bits are not supposed to be significant.
1165 * to make tests easier, return the same as a real PowerPC 750
1166 */
1167 farg.ll |= 0xFFF80000ULL << 32;
1168 #endif
1169 }
1170 return farg.ll;
1171 }
1172
1173 /* fctiwz - fctiwz. */
1174 uint64_t helper_fctiwz (uint64_t arg)
1175 {
1176 CPU_DoubleU farg;
1177 farg.ll = arg;
1178
1179 if (unlikely(float64_is_signaling_nan(farg.d))) {
1180 /* sNaN conversion */
1181 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1182 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1183 /* qNan / infinity conversion */
1184 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1185 } else {
1186 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1187 #if USE_PRECISE_EMULATION
1188 /* XXX: higher bits are not supposed to be significant.
1189 * to make tests easier, return the same as a real PowerPC 750
1190 */
1191 farg.ll |= 0xFFF80000ULL << 32;
1192 #endif
1193 }
1194 return farg.ll;
1195 }
1196
1197 #if defined(TARGET_PPC64)
1198 /* fcfid - fcfid. */
1199 uint64_t helper_fcfid (uint64_t arg)
1200 {
1201 CPU_DoubleU farg;
1202 farg.d = int64_to_float64(arg, &env->fp_status);
1203 return farg.ll;
1204 }
1205
1206 /* fctid - fctid. */
1207 uint64_t helper_fctid (uint64_t arg)
1208 {
1209 CPU_DoubleU farg;
1210 farg.ll = arg;
1211
1212 if (unlikely(float64_is_signaling_nan(farg.d))) {
1213 /* sNaN conversion */
1214 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1215 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1216 /* qNan / infinity conversion */
1217 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1218 } else {
1219 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1220 }
1221 return farg.ll;
1222 }
1223
1224 /* fctidz - fctidz. */
1225 uint64_t helper_fctidz (uint64_t arg)
1226 {
1227 CPU_DoubleU farg;
1228 farg.ll = arg;
1229
1230 if (unlikely(float64_is_signaling_nan(farg.d))) {
1231 /* sNaN conversion */
1232 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1233 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1234 /* qNan / infinity conversion */
1235 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1236 } else {
1237 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1238 }
1239 return farg.ll;
1240 }
1241
1242 #endif
1243
1244 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1245 {
1246 CPU_DoubleU farg;
1247 farg.ll = arg;
1248
1249 if (unlikely(float64_is_signaling_nan(farg.d))) {
1250 /* sNaN round */
1251 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1252 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1253 /* qNan / infinity round */
1254 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1255 } else {
1256 set_float_rounding_mode(rounding_mode, &env->fp_status);
1257 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1258 /* Restore rounding mode from FPSCR */
1259 fpscr_set_rounding_mode();
1260 }
1261 return farg.ll;
1262 }
1263
1264 uint64_t helper_frin (uint64_t arg)
1265 {
1266 return do_fri(arg, float_round_nearest_even);
1267 }
1268
1269 uint64_t helper_friz (uint64_t arg)
1270 {
1271 return do_fri(arg, float_round_to_zero);
1272 }
1273
1274 uint64_t helper_frip (uint64_t arg)
1275 {
1276 return do_fri(arg, float_round_up);
1277 }
1278
1279 uint64_t helper_frim (uint64_t arg)
1280 {
1281 return do_fri(arg, float_round_down);
1282 }
1283
1284 /* fmadd - fmadd. */
1285 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1286 {
1287 CPU_DoubleU farg1, farg2, farg3;
1288
1289 farg1.ll = arg1;
1290 farg2.ll = arg2;
1291 farg3.ll = arg3;
1292 #if USE_PRECISE_EMULATION
1293 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1294 float64_is_signaling_nan(farg2.d) ||
1295 float64_is_signaling_nan(farg3.d))) {
1296 /* sNaN operation */
1297 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1298 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1299 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1300 /* Multiplication of zero by infinity */
1301 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1302 } else {
1303 #ifdef FLOAT128
1304 /* This is the way the PowerPC specification defines it */
1305 float128 ft0_128, ft1_128;
1306
1307 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1308 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1309 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1310 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1311 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1312 /* Magnitude subtraction of infinities */
1313 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1314 } else {
1315 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1316 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1317 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1318 }
1319 #else
1320 /* This is OK on x86 hosts */
1321 farg1.d = (farg1.d * farg2.d) + farg3.d;
1322 #endif
1323 }
1324 #else
1325 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1326 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1327 #endif
1328 return farg1.ll;
1329 }
1330
1331 /* fmsub - fmsub. */
1332 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1333 {
1334 CPU_DoubleU farg1, farg2, farg3;
1335
1336 farg1.ll = arg1;
1337 farg2.ll = arg2;
1338 farg3.ll = arg3;
1339 #if USE_PRECISE_EMULATION
1340 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1341 float64_is_signaling_nan(farg2.d) ||
1342 float64_is_signaling_nan(farg3.d))) {
1343 /* sNaN operation */
1344 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1345 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1346 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1347 /* Multiplication of zero by infinity */
1348 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1349 } else {
1350 #ifdef FLOAT128
1351 /* This is the way the PowerPC specification defines it */
1352 float128 ft0_128, ft1_128;
1353
1354 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1355 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1356 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1357 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1358 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1359 /* Magnitude subtraction of infinities */
1360 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1361 } else {
1362 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1363 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1364 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1365 }
1366 #else
1367 /* This is OK on x86 hosts */
1368 farg1.d = (farg1.d * farg2.d) - farg3.d;
1369 #endif
1370 }
1371 #else
1372 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1373 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1374 #endif
1375 return farg1.ll;
1376 }
1377
1378 /* fnmadd - fnmadd. */
1379 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1380 {
1381 CPU_DoubleU farg1, farg2, farg3;
1382
1383 farg1.ll = arg1;
1384 farg2.ll = arg2;
1385 farg3.ll = arg3;
1386
1387 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1388 float64_is_signaling_nan(farg2.d) ||
1389 float64_is_signaling_nan(farg3.d))) {
1390 /* sNaN operation */
1391 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1392 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1393 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1394 /* Multiplication of zero by infinity */
1395 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1396 } else {
1397 #if USE_PRECISE_EMULATION
1398 #ifdef FLOAT128
1399 /* This is the way the PowerPC specification defines it */
1400 float128 ft0_128, ft1_128;
1401
1402 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1403 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1404 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1405 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1406 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1407 /* Magnitude subtraction of infinities */
1408 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1409 } else {
1410 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1411 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1412 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1413 }
1414 #else
1415 /* This is OK on x86 hosts */
1416 farg1.d = (farg1.d * farg2.d) + farg3.d;
1417 #endif
1418 #else
1419 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1420 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1421 #endif
1422 if (likely(!float64_is_nan(farg1.d)))
1423 farg1.d = float64_chs(farg1.d);
1424 }
1425 return farg1.ll;
1426 }
1427
1428 /* fnmsub - fnmsub. */
1429 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1430 {
1431 CPU_DoubleU farg1, farg2, farg3;
1432
1433 farg1.ll = arg1;
1434 farg2.ll = arg2;
1435 farg3.ll = arg3;
1436
1437 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1438 float64_is_signaling_nan(farg2.d) ||
1439 float64_is_signaling_nan(farg3.d))) {
1440 /* sNaN operation */
1441 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1442 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1443 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1444 /* Multiplication of zero by infinity */
1445 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1446 } else {
1447 #if USE_PRECISE_EMULATION
1448 #ifdef FLOAT128
1449 /* This is the way the PowerPC specification defines it */
1450 float128 ft0_128, ft1_128;
1451
1452 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1453 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1454 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1455 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1456 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1457 /* Magnitude subtraction of infinities */
1458 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1459 } else {
1460 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1461 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1462 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1463 }
1464 #else
1465 /* This is OK on x86 hosts */
1466 farg1.d = (farg1.d * farg2.d) - farg3.d;
1467 #endif
1468 #else
1469 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1470 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1471 #endif
1472 if (likely(!float64_is_nan(farg1.d)))
1473 farg1.d = float64_chs(farg1.d);
1474 }
1475 return farg1.ll;
1476 }
1477
1478 /* frsp - frsp. */
1479 uint64_t helper_frsp (uint64_t arg)
1480 {
1481 CPU_DoubleU farg;
1482 float32 f32;
1483 farg.ll = arg;
1484
1485 #if USE_PRECISE_EMULATION
1486 if (unlikely(float64_is_signaling_nan(farg.d))) {
1487 /* sNaN square root */
1488 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1489 } else {
1490 f32 = float64_to_float32(farg.d, &env->fp_status);
1491 farg.d = float32_to_float64(f32, &env->fp_status);
1492 }
1493 #else
1494 f32 = float64_to_float32(farg.d, &env->fp_status);
1495 farg.d = float32_to_float64(f32, &env->fp_status);
1496 #endif
1497 return farg.ll;
1498 }
1499
1500 /* fsqrt - fsqrt. */
1501 uint64_t helper_fsqrt (uint64_t arg)
1502 {
1503 CPU_DoubleU farg;
1504 farg.ll = arg;
1505
1506 if (unlikely(float64_is_signaling_nan(farg.d))) {
1507 /* sNaN square root */
1508 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1509 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1510 /* Square root of a negative nonzero number */
1511 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1512 } else {
1513 farg.d = float64_sqrt(farg.d, &env->fp_status);
1514 }
1515 return farg.ll;
1516 }
1517
1518 /* fre - fre. */
1519 uint64_t helper_fre (uint64_t arg)
1520 {
1521 CPU_DoubleU fone, farg;
1522 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
1523 farg.ll = arg;
1524
1525 if (unlikely(float64_is_signaling_nan(farg.d))) {
1526 /* sNaN reciprocal */
1527 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1528 } else if (unlikely(float64_is_zero(farg.d))) {
1529 /* Zero reciprocal */
1530 farg.ll = float_zero_divide_excp(fone.d, farg.d);
1531 } else if (likely(isnormal(farg.d))) {
1532 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1533 } else {
1534 if (farg.ll == 0x8000000000000000ULL) {
1535 farg.ll = 0xFFF0000000000000ULL;
1536 } else if (farg.ll == 0x0000000000000000ULL) {
1537 farg.ll = 0x7FF0000000000000ULL;
1538 } else if (float64_is_nan(farg.d)) {
1539 farg.ll = 0x7FF8000000000000ULL;
1540 } else if (float64_is_neg(farg.d)) {
1541 farg.ll = 0x8000000000000000ULL;
1542 } else {
1543 farg.ll = 0x0000000000000000ULL;
1544 }
1545 }
1546 return farg.d;
1547 }
1548
1549 /* fres - fres. */
1550 uint64_t helper_fres (uint64_t arg)
1551 {
1552 CPU_DoubleU fone, farg;
1553 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
1554 farg.ll = arg;
1555
1556 if (unlikely(float64_is_signaling_nan(farg.d))) {
1557 /* sNaN reciprocal */
1558 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1559 } else if (unlikely(float64_is_zero(farg.d))) {
1560 /* Zero reciprocal */
1561 farg.ll = float_zero_divide_excp(fone.d, farg.d);
1562 } else if (likely(isnormal(farg.d))) {
1563 #if USE_PRECISE_EMULATION
1564 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1565 farg.d = float64_to_float32(farg.d, &env->fp_status);
1566 #else
1567 farg.d = float32_div(fone.d, farg.d, &env->fp_status);
1568 #endif
1569 } else {
1570 if (farg.ll == 0x8000000000000000ULL) {
1571 farg.ll = 0xFFF0000000000000ULL;
1572 } else if (farg.ll == 0x0000000000000000ULL) {
1573 farg.ll = 0x7FF0000000000000ULL;
1574 } else if (float64_is_nan(farg.d)) {
1575 farg.ll = 0x7FF8000000000000ULL;
1576 } else if (float64_is_neg(farg.d)) {
1577 farg.ll = 0x8000000000000000ULL;
1578 } else {
1579 farg.ll = 0x0000000000000000ULL;
1580 }
1581 }
1582 return farg.ll;
1583 }
1584
1585 /* frsqrte - frsqrte. */
1586 uint64_t helper_frsqrte (uint64_t arg)
1587 {
1588 CPU_DoubleU fone, farg;
1589 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
1590 farg.ll = arg;
1591
1592 if (unlikely(float64_is_signaling_nan(farg.d))) {
1593 /* sNaN reciprocal square root */
1594 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1595 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1596 /* Reciprocal square root of a negative nonzero number */
1597 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1598 } else if (likely(isnormal(farg.d))) {
1599 farg.d = float64_sqrt(farg.d, &env->fp_status);
1600 farg.d = float32_div(fone.d, farg.d, &env->fp_status);
1601 } else {
1602 if (farg.ll == 0x8000000000000000ULL) {
1603 farg.ll = 0xFFF0000000000000ULL;
1604 } else if (farg.ll == 0x0000000000000000ULL) {
1605 farg.ll = 0x7FF0000000000000ULL;
1606 } else if (float64_is_nan(farg.d)) {
1607 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1608 } else if (float64_is_neg(farg.d)) {
1609 farg.ll = 0x7FF8000000000000ULL;
1610 } else {
1611 farg.ll = 0x0000000000000000ULL;
1612 }
1613 }
1614 return farg.ll;
1615 }
1616
1617 /* fsel - fsel. */
1618 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1619 {
1620 CPU_DoubleU farg1;
1621
1622 farg1.ll = arg1;
1623
1624 if (!float64_is_neg(farg1.d) || float64_is_zero(farg1.d))
1625 return arg2;
1626 else
1627 return arg3;
1628 }
1629
1630 void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1631 {
1632 CPU_DoubleU farg1, farg2;
1633 uint32_t ret = 0;
1634 farg1.ll = arg1;
1635 farg2.ll = arg2;
1636
1637 if (unlikely(float64_is_nan(farg1.d) ||
1638 float64_is_nan(farg2.d))) {
1639 ret = 0x01UL;
1640 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1641 ret = 0x08UL;
1642 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1643 ret = 0x04UL;
1644 } else {
1645 ret = 0x02UL;
1646 }
1647
1648 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1649 env->fpscr |= ret << FPSCR_FPRF;
1650 env->crf[crfD] = ret;
1651 if (unlikely(ret == 0x01UL
1652 && (float64_is_signaling_nan(farg1.d) ||
1653 float64_is_signaling_nan(farg2.d)))) {
1654 /* sNaN comparison */
1655 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1656 }
1657 }
1658
1659 void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1660 {
1661 CPU_DoubleU farg1, farg2;
1662 uint32_t ret = 0;
1663 farg1.ll = arg1;
1664 farg2.ll = arg2;
1665
1666 if (unlikely(float64_is_nan(farg1.d) ||
1667 float64_is_nan(farg2.d))) {
1668 ret = 0x01UL;
1669 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1670 ret = 0x08UL;
1671 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1672 ret = 0x04UL;
1673 } else {
1674 ret = 0x02UL;
1675 }
1676
1677 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1678 env->fpscr |= ret << FPSCR_FPRF;
1679 env->crf[crfD] = ret;
1680 if (unlikely (ret == 0x01UL)) {
1681 if (float64_is_signaling_nan(farg1.d) ||
1682 float64_is_signaling_nan(farg2.d)) {
1683 /* sNaN comparison */
1684 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1685 POWERPC_EXCP_FP_VXVC);
1686 } else {
1687 /* qNaN comparison */
1688 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1689 }
1690 }
1691 }
1692
1693 #if !defined (CONFIG_USER_ONLY)
1694 void helper_store_msr (target_ulong val)
1695 {
1696 val = hreg_store_msr(env, val, 0);
1697 if (val != 0) {
1698 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1699 helper_raise_exception(val);
1700 }
1701 }
1702
1703 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1704 target_ulong msrm, int keep_msrh)
1705 {
1706 #if defined(TARGET_PPC64)
1707 if (msr & (1ULL << MSR_SF)) {
1708 nip = (uint64_t)nip;
1709 msr &= (uint64_t)msrm;
1710 } else {
1711 nip = (uint32_t)nip;
1712 msr = (uint32_t)(msr & msrm);
1713 if (keep_msrh)
1714 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1715 }
1716 #else
1717 nip = (uint32_t)nip;
1718 msr &= (uint32_t)msrm;
1719 #endif
1720 /* XXX: beware: this is false if VLE is supported */
1721 env->nip = nip & ~((target_ulong)0x00000003);
1722 hreg_store_msr(env, msr, 1);
1723 #if defined (DEBUG_OP)
1724 cpu_dump_rfi(env->nip, env->msr);
1725 #endif
1726 /* No need to raise an exception here,
1727 * as rfi is always the last insn of a TB
1728 */
1729 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1730 }
1731
1732 void helper_rfi (void)
1733 {
1734 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1735 ~((target_ulong)0xFFFF0000), 1);
1736 }
1737
1738 #if defined(TARGET_PPC64)
1739 void helper_rfid (void)
1740 {
1741 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1742 ~((target_ulong)0xFFFF0000), 0);
1743 }
1744
1745 void helper_hrfid (void)
1746 {
1747 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1748 ~((target_ulong)0xFFFF0000), 0);
1749 }
1750 #endif
1751 #endif
1752
1753 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1754 {
1755 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1756 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1757 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1758 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1759 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1760 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1761 }
1762 }
1763
1764 #if defined(TARGET_PPC64)
1765 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1766 {
1767 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1768 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1769 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1770 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1771 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1772 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1773 }
1774 #endif
1775
1776 /*****************************************************************************/
1777 /* PowerPC 601 specific instructions (POWER bridge) */
1778
1779 target_ulong helper_clcs (uint32_t arg)
1780 {
1781 switch (arg) {
1782 case 0x0CUL:
1783 /* Instruction cache line size */
1784 return env->icache_line_size;
1785 break;
1786 case 0x0DUL:
1787 /* Data cache line size */
1788 return env->dcache_line_size;
1789 break;
1790 case 0x0EUL:
1791 /* Minimum cache line size */
1792 return (env->icache_line_size < env->dcache_line_size) ?
1793 env->icache_line_size : env->dcache_line_size;
1794 break;
1795 case 0x0FUL:
1796 /* Maximum cache line size */
1797 return (env->icache_line_size > env->dcache_line_size) ?
1798 env->icache_line_size : env->dcache_line_size;
1799 break;
1800 default:
1801 /* Undefined */
1802 return 0;
1803 break;
1804 }
1805 }
1806
1807 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1808 {
1809 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1810
1811 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1812 (int32_t)arg2 == 0) {
1813 env->spr[SPR_MQ] = 0;
1814 return INT32_MIN;
1815 } else {
1816 env->spr[SPR_MQ] = tmp % arg2;
1817 return tmp / (int32_t)arg2;
1818 }
1819 }
1820
1821 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1822 {
1823 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1824
1825 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1826 (int32_t)arg2 == 0) {
1827 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1828 env->spr[SPR_MQ] = 0;
1829 return INT32_MIN;
1830 } else {
1831 env->spr[SPR_MQ] = tmp % arg2;
1832 tmp /= (int32_t)arg2;
1833 if ((int32_t)tmp != tmp) {
1834 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1835 } else {
1836 env->xer &= ~(1 << XER_OV);
1837 }
1838 return tmp;
1839 }
1840 }
1841
1842 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1843 {
1844 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1845 (int32_t)arg2 == 0) {
1846 env->spr[SPR_MQ] = 0;
1847 return INT32_MIN;
1848 } else {
1849 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1850 return (int32_t)arg1 / (int32_t)arg2;
1851 }
1852 }
1853
1854 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1855 {
1856 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1857 (int32_t)arg2 == 0) {
1858 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1859 env->spr[SPR_MQ] = 0;
1860 return INT32_MIN;
1861 } else {
1862 env->xer &= ~(1 << XER_OV);
1863 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1864 return (int32_t)arg1 / (int32_t)arg2;
1865 }
1866 }
1867
1868 #if !defined (CONFIG_USER_ONLY)
1869 target_ulong helper_rac (target_ulong addr)
1870 {
1871 mmu_ctx_t ctx;
1872 int nb_BATs;
1873 target_ulong ret = 0;
1874
1875 /* We don't have to generate many instances of this instruction,
1876 * as rac is supervisor only.
1877 */
1878 /* XXX: FIX THIS: Pretend we have no BAT */
1879 nb_BATs = env->nb_BATs;
1880 env->nb_BATs = 0;
1881 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1882 ret = ctx.raddr;
1883 env->nb_BATs = nb_BATs;
1884 return ret;
1885 }
1886
1887 void helper_rfsvc (void)
1888 {
1889 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1890 }
1891 #endif
1892
1893 /*****************************************************************************/
1894 /* 602 specific instructions */
1895 /* mfrom is the most crazy instruction ever seen, imho ! */
1896 /* Real implementation uses a ROM table. Do the same */
1897 /* Extremly decomposed:
1898 * -arg / 256
1899 * return 256 * log10(10 + 1.0) + 0.5
1900 */
1901 #if !defined (CONFIG_USER_ONLY)
1902 target_ulong helper_602_mfrom (target_ulong arg)
1903 {
1904 if (likely(arg < 602)) {
1905 #include "mfrom_table.c"
1906 return mfrom_ROM_table[arg];
1907 } else {
1908 return 0;
1909 }
1910 }
1911 #endif
1912
1913 /*****************************************************************************/
1914 /* Embedded PowerPC specific helpers */
1915
1916 /* XXX: to be improved to check access rights when in user-mode */
1917 target_ulong helper_load_dcr (target_ulong dcrn)
1918 {
1919 target_ulong val = 0;
1920
1921 if (unlikely(env->dcr_env == NULL)) {
1922 if (loglevel != 0) {
1923 fprintf(logfile, "No DCR environment\n");
1924 }
1925 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1926 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1927 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1928 if (loglevel != 0) {
1929 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1930 }
1931 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1932 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1933 }
1934 return val;
1935 }
1936
1937 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1938 {
1939 if (unlikely(env->dcr_env == NULL)) {
1940 if (loglevel != 0) {
1941 fprintf(logfile, "No DCR environment\n");
1942 }
1943 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1944 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1945 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1946 if (loglevel != 0) {
1947 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1948 }
1949 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1950 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1951 }
1952 }
1953
1954 #if !defined(CONFIG_USER_ONLY)
1955 void helper_40x_rfci (void)
1956 {
1957 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1958 ~((target_ulong)0xFFFF0000), 0);
1959 }
1960
1961 void helper_rfci (void)
1962 {
1963 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1964 ~((target_ulong)0x3FFF0000), 0);
1965 }
1966
1967 void helper_rfdi (void)
1968 {
1969 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1970 ~((target_ulong)0x3FFF0000), 0);
1971 }
1972
1973 void helper_rfmci (void)
1974 {
1975 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1976 ~((target_ulong)0x3FFF0000), 0);
1977 }
1978 #endif
1979
1980 /* 440 specific */
1981 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1982 {
1983 target_ulong mask;
1984 int i;
1985
1986 i = 1;
1987 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1988 if ((high & mask) == 0) {
1989 if (update_Rc) {
1990 env->crf[0] = 0x4;
1991 }
1992 goto done;
1993 }
1994 i++;
1995 }
1996 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1997 if ((low & mask) == 0) {
1998 if (update_Rc) {
1999 env->crf[0] = 0x8;
2000 }
2001 goto done;
2002 }
2003 i++;
2004 }
2005 if (update_Rc) {
2006 env->crf[0] = 0x2;
2007 }
2008 done:
2009 env->xer = (env->xer & ~0x7F) | i;
2010 if (update_Rc) {
2011 env->crf[0] |= xer_so;
2012 }
2013 return i;
2014 }
2015
2016 /*****************************************************************************/
2017 /* SPE extension helpers */
2018 /* Use a table to make this quicker */
2019 static uint8_t hbrev[16] = {
2020 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2021 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2022 };
2023
2024 static always_inline uint8_t byte_reverse (uint8_t val)
2025 {
2026 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2027 }
2028
2029 static always_inline uint32_t word_reverse (uint32_t val)
2030 {
2031 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2032 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2033 }
2034
2035 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2036 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2037 {
2038 uint32_t a, b, d, mask;
2039
2040 mask = UINT32_MAX >> (32 - MASKBITS);
2041 a = arg1 & mask;
2042 b = arg2 & mask;
2043 d = word_reverse(1 + word_reverse(a | ~b));
2044 return (arg1 & ~mask) | (d & b);
2045 }
2046
2047 uint32_t helper_cntlsw32 (uint32_t val)
2048 {
2049 if (val & 0x80000000)
2050 return clz32(~val);
2051 else
2052 return clz32(val);
2053 }
2054
2055 uint32_t helper_cntlzw32 (uint32_t val)
2056 {
2057 return clz32(val);
2058 }
2059
2060 /* Single-precision floating-point conversions */
2061 static always_inline uint32_t efscfsi (uint32_t val)
2062 {
2063 CPU_FloatU u;
2064
2065 u.f = int32_to_float32(val, &env->spe_status);
2066
2067 return u.l;
2068 }
2069
2070 static always_inline uint32_t efscfui (uint32_t val)
2071 {
2072 CPU_FloatU u;
2073
2074 u.f = uint32_to_float32(val, &env->spe_status);
2075
2076 return u.l;
2077 }
2078
2079 static always_inline int32_t efsctsi (uint32_t val)
2080 {
2081 CPU_FloatU u;
2082
2083 u.l = val;
2084 /* NaN are not treated the same way IEEE 754 does */
2085 if (unlikely(float32_is_nan(u.f)))
2086 return 0;
2087
2088 return float32_to_int32(u.f, &env->spe_status);
2089 }
2090
2091 static always_inline uint32_t efsctui (uint32_t val)
2092 {
2093 CPU_FloatU u;
2094
2095 u.l = val;
2096 /* NaN are not treated the same way IEEE 754 does */
2097 if (unlikely(float32_is_nan(u.f)))
2098 return 0;
2099
2100 return float32_to_uint32(u.f, &env->spe_status);
2101 }
2102
2103 static always_inline uint32_t efsctsiz (uint32_t val)
2104 {
2105 CPU_FloatU u;
2106
2107 u.l = val;
2108 /* NaN are not treated the same way IEEE 754 does */
2109 if (unlikely(float32_is_nan(u.f)))
2110 return 0;
2111
2112 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2113 }
2114
2115 static always_inline uint32_t efsctuiz (uint32_t val)
2116 {
2117 CPU_FloatU u;
2118
2119 u.l = val;
2120 /* NaN are not treated the same way IEEE 754 does */
2121 if (unlikely(float32_is_nan(u.f)))
2122 return 0;
2123
2124 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2125 }
2126
2127 static always_inline uint32_t efscfsf (uint32_t val)
2128 {
2129 CPU_FloatU u;
2130 float32 tmp;
2131
2132 u.f = int32_to_float32(val, &env->spe_status);
2133 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2134 u.f = float32_div(u.f, tmp, &env->spe_status);
2135
2136 return u.l;
2137 }
2138
2139 static always_inline uint32_t efscfuf (uint32_t val)
2140 {
2141 CPU_FloatU u;
2142 float32 tmp;
2143
2144 u.f = uint32_to_float32(val, &env->spe_status);
2145 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2146 u.f = float32_div(u.f, tmp, &env->spe_status);
2147
2148 return u.l;
2149 }
2150
2151 static always_inline uint32_t efsctsf (uint32_t val)
2152 {
2153 CPU_FloatU u;
2154 float32 tmp;
2155
2156 u.l = val;
2157 /* NaN are not treated the same way IEEE 754 does */
2158 if (unlikely(float32_is_nan(u.f)))
2159 return 0;
2160 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2161 u.f = float32_mul(u.f, tmp, &env->spe_status);
2162
2163 return float32_to_int32(u.f, &env->spe_status);
2164 }
2165
2166 static always_inline uint32_t efsctuf (uint32_t val)
2167 {
2168 CPU_FloatU u;
2169 float32 tmp;
2170
2171 u.l = val;
2172 /* NaN are not treated the same way IEEE 754 does */
2173 if (unlikely(float32_is_nan(u.f)))
2174 return 0;
2175 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2176 u.f = float32_mul(u.f, tmp, &env->spe_status);
2177
2178 return float32_to_uint32(u.f, &env->spe_status);
2179 }
2180
2181 #define HELPER_SPE_SINGLE_CONV(name) \
2182 uint32_t helper_e##name (uint32_t val) \
2183 { \
2184 return e##name(val); \
2185 }
2186 /* efscfsi */
2187 HELPER_SPE_SINGLE_CONV(fscfsi);
2188 /* efscfui */
2189 HELPER_SPE_SINGLE_CONV(fscfui);
2190 /* efscfuf */
2191 HELPER_SPE_SINGLE_CONV(fscfuf);
2192 /* efscfsf */
2193 HELPER_SPE_SINGLE_CONV(fscfsf);
2194 /* efsctsi */
2195 HELPER_SPE_SINGLE_CONV(fsctsi);
2196 /* efsctui */
2197 HELPER_SPE_SINGLE_CONV(fsctui);
2198 /* efsctsiz */
2199 HELPER_SPE_SINGLE_CONV(fsctsiz);
2200 /* efsctuiz */
2201 HELPER_SPE_SINGLE_CONV(fsctuiz);
2202 /* efsctsf */
2203 HELPER_SPE_SINGLE_CONV(fsctsf);
2204 /* efsctuf */
2205 HELPER_SPE_SINGLE_CONV(fsctuf);
2206
2207 #define HELPER_SPE_VECTOR_CONV(name) \
2208 uint64_t helper_ev##name (uint64_t val) \
2209 { \
2210 return ((uint64_t)e##name(val >> 32) << 32) | \
2211 (uint64_t)e##name(val); \
2212 }
2213 /* evfscfsi */
2214 HELPER_SPE_VECTOR_CONV(fscfsi);
2215 /* evfscfui */
2216 HELPER_SPE_VECTOR_CONV(fscfui);
2217 /* evfscfuf */
2218 HELPER_SPE_VECTOR_CONV(fscfuf);
2219 /* evfscfsf */
2220 HELPER_SPE_VECTOR_CONV(fscfsf);
2221 /* evfsctsi */
2222 HELPER_SPE_VECTOR_CONV(fsctsi);
2223 /* evfsctui */
2224 HELPER_SPE_VECTOR_CONV(fsctui);
2225 /* evfsctsiz */
2226 HELPER_SPE_VECTOR_CONV(fsctsiz);
2227 /* evfsctuiz */
2228 HELPER_SPE_VECTOR_CONV(fsctuiz);
2229 /* evfsctsf */
2230 HELPER_SPE_VECTOR_CONV(fsctsf);
2231 /* evfsctuf */
2232 HELPER_SPE_VECTOR_CONV(fsctuf);
2233
2234 /* Single-precision floating-point arithmetic */
2235 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2236 {
2237 CPU_FloatU u1, u2;
2238 u1.l = op1;
2239 u2.l = op2;
2240 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2241 return u1.l;
2242 }
2243
2244 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2245 {
2246 CPU_FloatU u1, u2;
2247 u1.l = op1;
2248 u2.l = op2;
2249 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2250 return u1.l;
2251 }
2252
2253 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2254 {
2255 CPU_FloatU u1, u2;
2256 u1.l = op1;
2257 u2.l = op2;
2258 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2259 return u1.l;
2260 }
2261
2262 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2263 {
2264 CPU_FloatU u1, u2;
2265 u1.l = op1;
2266 u2.l = op2;
2267 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2268 return u1.l;
2269 }
2270
2271 #define HELPER_SPE_SINGLE_ARITH(name) \
2272 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2273 { \
2274 return e##name(op1, op2); \
2275 }
2276 /* efsadd */
2277 HELPER_SPE_SINGLE_ARITH(fsadd);
2278 /* efssub */
2279 HELPER_SPE_SINGLE_ARITH(fssub);
2280 /* efsmul */
2281 HELPER_SPE_SINGLE_ARITH(fsmul);
2282 /* efsdiv */
2283 HELPER_SPE_SINGLE_ARITH(fsdiv);
2284
2285 #define HELPER_SPE_VECTOR_ARITH(name) \
2286 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2287 { \
2288 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2289 (uint64_t)e##name(op1, op2); \
2290 }
2291 /* evfsadd */
2292 HELPER_SPE_VECTOR_ARITH(fsadd);
2293 /* evfssub */
2294 HELPER_SPE_VECTOR_ARITH(fssub);
2295 /* evfsmul */
2296 HELPER_SPE_VECTOR_ARITH(fsmul);
2297 /* evfsdiv */
2298 HELPER_SPE_VECTOR_ARITH(fsdiv);
2299
2300 /* Single-precision floating-point comparisons */
2301 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2302 {
2303 CPU_FloatU u1, u2;
2304 u1.l = op1;
2305 u2.l = op2;
2306 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2307 }
2308
2309 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2310 {
2311 CPU_FloatU u1, u2;
2312 u1.l = op1;
2313 u2.l = op2;
2314 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2315 }
2316
2317 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2318 {
2319 CPU_FloatU u1, u2;
2320 u1.l = op1;
2321 u2.l = op2;
2322 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2323 }
2324
2325 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2326 {
2327 /* XXX: TODO: test special values (NaN, infinites, ...) */
2328 return efststlt(op1, op2);
2329 }
2330
2331 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2332 {
2333 /* XXX: TODO: test special values (NaN, infinites, ...) */
2334 return efststgt(op1, op2);
2335 }
2336
2337 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2338 {
2339 /* XXX: TODO: test special values (NaN, infinites, ...) */
2340 return efststeq(op1, op2);
2341 }
2342
2343 #define HELPER_SINGLE_SPE_CMP(name) \
2344 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2345 { \
2346 return e##name(op1, op2) << 2; \
2347 }
2348 /* efststlt */
2349 HELPER_SINGLE_SPE_CMP(fststlt);
2350 /* efststgt */
2351 HELPER_SINGLE_SPE_CMP(fststgt);
2352 /* efststeq */
2353 HELPER_SINGLE_SPE_CMP(fststeq);
2354 /* efscmplt */
2355 HELPER_SINGLE_SPE_CMP(fscmplt);
2356 /* efscmpgt */
2357 HELPER_SINGLE_SPE_CMP(fscmpgt);
2358 /* efscmpeq */
2359 HELPER_SINGLE_SPE_CMP(fscmpeq);
2360
2361 static always_inline uint32_t evcmp_merge (int t0, int t1)
2362 {
2363 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2364 }
2365
2366 #define HELPER_VECTOR_SPE_CMP(name) \
2367 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2368 { \
2369 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2370 }
2371 /* evfststlt */
2372 HELPER_VECTOR_SPE_CMP(fststlt);
2373 /* evfststgt */
2374 HELPER_VECTOR_SPE_CMP(fststgt);
2375 /* evfststeq */
2376 HELPER_VECTOR_SPE_CMP(fststeq);
2377 /* evfscmplt */
2378 HELPER_VECTOR_SPE_CMP(fscmplt);
2379 /* evfscmpgt */
2380 HELPER_VECTOR_SPE_CMP(fscmpgt);
2381 /* evfscmpeq */
2382 HELPER_VECTOR_SPE_CMP(fscmpeq);
2383
2384 /* Double-precision floating-point conversion */
2385 uint64_t helper_efdcfsi (uint32_t val)
2386 {
2387 CPU_DoubleU u;
2388
2389 u.d = int32_to_float64(val, &env->spe_status);
2390
2391 return u.ll;
2392 }
2393
2394 uint64_t helper_efdcfsid (uint64_t val)
2395 {
2396 CPU_DoubleU u;
2397
2398 u.d = int64_to_float64(val, &env->spe_status);
2399
2400 return u.ll;
2401 }
2402
2403 uint64_t helper_efdcfui (uint32_t val)
2404 {
2405 CPU_DoubleU u;
2406
2407 u.d = uint32_to_float64(val, &env->spe_status);
2408
2409 return u.ll;
2410 }
2411
2412 uint64_t helper_efdcfuid (uint64_t val)
2413 {
2414 CPU_DoubleU u;
2415
2416 u.d = uint64_to_float64(val, &env->spe_status);
2417
2418 return u.ll;
2419 }
2420
2421 uint32_t helper_efdctsi (uint64_t val)
2422 {
2423 CPU_DoubleU u;
2424
2425 u.ll = val;
2426 /* NaN are not treated the same way IEEE 754 does */
2427 if (unlikely(float64_is_nan(u.d)))
2428 return 0;
2429
2430 return float64_to_int32(u.d, &env->spe_status);
2431 }
2432
2433 uint32_t helper_efdctui (uint64_t val)
2434 {
2435 CPU_DoubleU u;
2436
2437 u.ll = val;
2438 /* NaN are not treated the same way IEEE 754 does */
2439 if (unlikely(float64_is_nan(u.d)))
2440 return 0;
2441
2442 return float64_to_uint32(u.d, &env->spe_status);
2443 }
2444
2445 uint32_t helper_efdctsiz (uint64_t val)
2446 {
2447 CPU_DoubleU u;
2448
2449 u.ll = val;
2450 /* NaN are not treated the same way IEEE 754 does */
2451 if (unlikely(float64_is_nan(u.d)))
2452 return 0;
2453
2454 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2455 }
2456
2457 uint64_t helper_efdctsidz (uint64_t val)
2458 {
2459 CPU_DoubleU u;
2460
2461 u.ll = val;
2462 /* NaN are not treated the same way IEEE 754 does */
2463 if (unlikely(float64_is_nan(u.d)))
2464 return 0;
2465
2466 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2467 }
2468
2469 uint32_t helper_efdctuiz (uint64_t val)
2470 {
2471 CPU_DoubleU u;
2472
2473 u.ll = val;
2474 /* NaN are not treated the same way IEEE 754 does */
2475 if (unlikely(float64_is_nan(u.d)))
2476 return 0;
2477
2478 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2479 }
2480
2481 uint64_t helper_efdctuidz (uint64_t val)
2482 {
2483 CPU_DoubleU u;
2484
2485 u.ll = val;
2486 /* NaN are not treated the same way IEEE 754 does */
2487 if (unlikely(float64_is_nan(u.d)))
2488 return 0;
2489
2490 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2491 }
2492
2493 uint64_t helper_efdcfsf (uint32_t val)
2494 {
2495 CPU_DoubleU u;
2496 float64 tmp;
2497
2498 u.d = int32_to_float64(val, &env->spe_status);
2499 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2500 u.d = float64_div(u.d, tmp, &env->spe_status);
2501
2502 return u.ll;
2503 }
2504
2505 uint64_t helper_efdcfuf (uint32_t val)
2506 {
2507 CPU_DoubleU u;
2508 float64 tmp;
2509
2510 u.d = uint32_to_float64(val, &env->spe_status);
2511 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2512 u.d = float64_div(u.d, tmp, &env->spe_status);
2513
2514 return u.ll;
2515 }
2516
2517 uint32_t helper_efdctsf (uint64_t val)
2518 {
2519 CPU_DoubleU u;
2520 float64 tmp;
2521
2522 u.ll = val;
2523 /* NaN are not treated the same way IEEE 754 does */
2524 if (unlikely(float64_is_nan(u.d)))
2525 return 0;
2526 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2527 u.d = float64_mul(u.d, tmp, &env->spe_status);
2528
2529 return float64_to_int32(u.d, &env->spe_status);
2530 }
2531
2532 uint32_t helper_efdctuf (uint64_t val)
2533 {
2534 CPU_DoubleU u;
2535 float64 tmp;
2536
2537 u.ll = val;
2538 /* NaN are not treated the same way IEEE 754 does */
2539 if (unlikely(float64_is_nan(u.d)))
2540 return 0;
2541 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2542 u.d = float64_mul(u.d, tmp, &env->spe_status);
2543
2544 return float64_to_uint32(u.d, &env->spe_status);
2545 }
2546
2547 uint32_t helper_efscfd (uint64_t val)
2548 {
2549 CPU_DoubleU u1;
2550 CPU_FloatU u2;
2551
2552 u1.ll = val;
2553 u2.f = float64_to_float32(u1.d, &env->spe_status);
2554
2555 return u2.l;
2556 }
2557
2558 uint64_t helper_efdcfs (uint32_t val)
2559 {
2560 CPU_DoubleU u2;
2561 CPU_FloatU u1;
2562
2563 u1.l = val;
2564 u2.d = float32_to_float64(u1.f, &env->spe_status);
2565
2566 return u2.ll;
2567 }
2568
2569 /* Double precision fixed-point arithmetic */
2570 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2571 {
2572 CPU_DoubleU u1, u2;
2573 u1.ll = op1;
2574 u2.ll = op2;
2575 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2576 return u1.ll;
2577 }
2578
2579 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2580 {
2581 CPU_DoubleU u1, u2;
2582 u1.ll = op1;
2583 u2.ll = op2;
2584 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2585 return u1.ll;
2586 }
2587
2588 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2589 {
2590 CPU_DoubleU u1, u2;
2591 u1.ll = op1;
2592 u2.ll = op2;
2593 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2594 return u1.ll;
2595 }
2596
2597 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2598 {
2599 CPU_DoubleU u1, u2;
2600 u1.ll = op1;
2601 u2.ll = op2;
2602 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2603 return u1.ll;
2604 }
2605
2606 /* Double precision floating point helpers */
2607 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2608 {
2609 CPU_DoubleU u1, u2;
2610 u1.ll = op1;
2611 u2.ll = op2;
2612 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2613 }
2614
2615 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2616 {
2617 CPU_DoubleU u1, u2;
2618 u1.ll = op1;
2619 u2.ll = op2;
2620 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2621 }
2622
2623 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2624 {
2625 CPU_DoubleU u1, u2;
2626 u1.ll = op1;
2627 u2.ll = op2;
2628 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2629 }
2630
2631 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2632 {
2633 /* XXX: TODO: test special values (NaN, infinites, ...) */
2634 return helper_efdtstlt(op1, op2);
2635 }
2636
2637 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2638 {
2639 /* XXX: TODO: test special values (NaN, infinites, ...) */
2640 return helper_efdtstgt(op1, op2);
2641 }
2642
2643 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2644 {
2645 /* XXX: TODO: test special values (NaN, infinites, ...) */
2646 return helper_efdtsteq(op1, op2);
2647 }
2648
2649 /*****************************************************************************/
2650 /* Softmmu support */
2651 #if !defined (CONFIG_USER_ONLY)
2652
2653 #define MMUSUFFIX _mmu
2654
2655 #define SHIFT 0
2656 #include "softmmu_template.h"
2657
2658 #define SHIFT 1
2659 #include "softmmu_template.h"
2660
2661 #define SHIFT 2
2662 #include "softmmu_template.h"
2663
2664 #define SHIFT 3
2665 #include "softmmu_template.h"
2666
2667 /* try to fill the TLB and return an exception if error. If retaddr is
2668 NULL, it means that the function was called in C code (i.e. not
2669 from generated code or from helper.c) */
2670 /* XXX: fix it to restore all registers */
2671 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2672 {
2673 TranslationBlock *tb;
2674 CPUState *saved_env;
2675 unsigned long pc;
2676 int ret;
2677
2678 /* XXX: hack to restore env in all cases, even if not called from
2679 generated code */
2680 saved_env = env;
2681 env = cpu_single_env;
2682 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2683 if (unlikely(ret != 0)) {
2684 if (likely(retaddr)) {
2685 /* now we have a real cpu fault */
2686 pc = (unsigned long)retaddr;
2687 tb = tb_find_pc(pc);
2688 if (likely(tb)) {
2689 /* the PC is inside the translated code. It means that we have
2690 a virtual CPU fault */
2691 cpu_restore_state(tb, env, pc, NULL);
2692 }
2693 }
2694 helper_raise_exception_err(env->exception_index, env->error_code);
2695 }
2696 env = saved_env;
2697 }
2698
2699 /* Segment registers load and store */
2700 target_ulong helper_load_sr (target_ulong sr_num)
2701 {
2702 return env->sr[sr_num];
2703 }
2704
2705 void helper_store_sr (target_ulong sr_num, target_ulong val)
2706 {
2707 ppc_store_sr(env, sr_num, val);
2708 }
2709
2710 /* SLB management */
2711 #if defined(TARGET_PPC64)
2712 target_ulong helper_load_slb (target_ulong slb_nr)
2713 {
2714 return ppc_load_slb(env, slb_nr);
2715 }
2716
2717 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2718 {
2719 ppc_store_slb(env, slb_nr, rs);
2720 }
2721
2722 void helper_slbia (void)
2723 {
2724 ppc_slb_invalidate_all(env);
2725 }
2726
2727 void helper_slbie (target_ulong addr)
2728 {
2729 ppc_slb_invalidate_one(env, addr);
2730 }
2731
2732 #endif /* defined(TARGET_PPC64) */
2733
2734 /* TLB management */
2735 void helper_tlbia (void)
2736 {
2737 ppc_tlb_invalidate_all(env);
2738 }
2739
2740 void helper_tlbie (target_ulong addr)
2741 {
2742 ppc_tlb_invalidate_one(env, addr);
2743 }
2744
2745 /* Software driven TLBs management */
2746 /* PowerPC 602/603 software TLB load instructions helpers */
2747 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
2748 {
2749 target_ulong RPN, CMP, EPN;
2750 int way;
2751
2752 RPN = env->spr[SPR_RPA];
2753 if (is_code) {
2754 CMP = env->spr[SPR_ICMP];
2755 EPN = env->spr[SPR_IMISS];
2756 } else {
2757 CMP = env->spr[SPR_DCMP];
2758 EPN = env->spr[SPR_DMISS];
2759 }
2760 way = (env->spr[SPR_SRR1] >> 17) & 1;
2761 #if defined (DEBUG_SOFTWARE_TLB)
2762 if (loglevel != 0) {
2763 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2764 " PTE1 " ADDRX " way %d\n",
2765 __func__, new_EPN, EPN, CMP, RPN, way);
2766 }
2767 #endif
2768 /* Store this TLB */
2769 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2770 way, is_code, CMP, RPN);
2771 }
2772
2773 void helper_6xx_tlbd (target_ulong EPN)
2774 {
2775 do_6xx_tlb(EPN, 0);
2776 }
2777
2778 void helper_6xx_tlbi (target_ulong EPN)
2779 {
2780 do_6xx_tlb(EPN, 1);
2781 }
2782
2783 /* PowerPC 74xx software TLB load instructions helpers */
2784 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
2785 {
2786 target_ulong RPN, CMP, EPN;
2787 int way;
2788
2789 RPN = env->spr[SPR_PTELO];
2790 CMP = env->spr[SPR_PTEHI];
2791 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2792 way = env->spr[SPR_TLBMISS] & 0x3;
2793 #if defined (DEBUG_SOFTWARE_TLB)
2794 if (loglevel != 0) {
2795 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2796 " PTE1 " ADDRX " way %d\n",
2797 __func__, new_EPN, EPN, CMP, RPN, way);
2798 }
2799 #endif
2800 /* Store this TLB */
2801 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2802 way, is_code, CMP, RPN);
2803 }
2804
2805 void helper_74xx_tlbd (target_ulong EPN)
2806 {
2807 do_74xx_tlb(EPN, 0);
2808 }
2809
2810 void helper_74xx_tlbi (target_ulong EPN)
2811 {
2812 do_74xx_tlb(EPN, 1);
2813 }
2814
2815 static always_inline target_ulong booke_tlb_to_page_size (int size)
2816 {
2817 return 1024 << (2 * size);
2818 }
2819
2820 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2821 {
2822 int size;
2823
2824 switch (page_size) {
2825 case 0x00000400UL:
2826 size = 0x0;
2827 break;
2828 case 0x00001000UL:
2829 size = 0x1;
2830 break;
2831 case 0x00004000UL:
2832 size = 0x2;
2833 break;
2834 case 0x00010000UL:
2835 size = 0x3;
2836 break;
2837 case 0x00040000UL:
2838 size = 0x4;
2839 break;
2840 case 0x00100000UL:
2841 size = 0x5;
2842 break;
2843 case 0x00400000UL:
2844 size = 0x6;
2845 break;
2846 case 0x01000000UL:
2847 size = 0x7;
2848 break;
2849 case 0x04000000UL:
2850 size = 0x8;
2851 break;
2852 case 0x10000000UL:
2853 size = 0x9;
2854 break;
2855 case 0x40000000UL:
2856 size = 0xA;
2857 break;
2858 #if defined (TARGET_PPC64)
2859 case 0x000100000000ULL:
2860 size = 0xB;
2861 break;
2862 case 0x000400000000ULL:
2863 size = 0xC;
2864 break;
2865 case 0x001000000000ULL:
2866 size = 0xD;
2867 break;
2868 case 0x004000000000ULL:
2869 size = 0xE;
2870 break;
2871 case 0x010000000000ULL:
2872 size = 0xF;
2873 break;
2874 #endif
2875 default:
2876 size = -1;
2877 break;
2878 }
2879
2880 return size;
2881 }
2882
2883 /* Helpers for 4xx TLB management */
2884 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
2885 {
2886 ppcemb_tlb_t *tlb;
2887 target_ulong ret;
2888 int size;
2889
2890 entry &= 0x3F;
2891 tlb = &env->tlb[entry].tlbe;
2892 ret = tlb->EPN;
2893 if (tlb->prot & PAGE_VALID)
2894 ret |= 0x400;
2895 size = booke_page_size_to_tlb(tlb->size);
2896 if (size < 0 || size > 0x7)
2897 size = 1;
2898 ret |= size << 7;
2899 env->spr[SPR_40x_PID] = tlb->PID;
2900 return ret;
2901 }
2902
2903 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
2904 {
2905 ppcemb_tlb_t *tlb;
2906 target_ulong ret;
2907
2908 entry &= 0x3F;
2909 tlb = &env->tlb[entry].tlbe;
2910 ret = tlb->RPN;
2911 if (tlb->prot & PAGE_EXEC)
2912 ret |= 0x200;
2913 if (tlb->prot & PAGE_WRITE)
2914 ret |= 0x100;
2915 return ret;
2916 }
2917
2918 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
2919 {
2920 ppcemb_tlb_t *tlb;
2921 target_ulong page, end;
2922
2923 #if defined (DEBUG_SOFTWARE_TLB)
2924 if (loglevel != 0) {
2925 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
2926 }
2927 #endif
2928 entry &= 0x3F;
2929 tlb = &env->tlb[entry].tlbe;
2930 /* Invalidate previous TLB (if it's valid) */
2931 if (tlb->prot & PAGE_VALID) {
2932 end = tlb->EPN + tlb->size;
2933 #if defined (DEBUG_SOFTWARE_TLB)
2934 if (loglevel != 0) {
2935 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2936 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2937 }
2938 #endif
2939 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2940 tlb_flush_page(env, page);
2941 }
2942 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
2943 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2944 * If this ever occurs, one should use the ppcemb target instead
2945 * of the ppc or ppc64 one
2946 */
2947 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2948 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2949 "are not supported (%d)\n",
2950 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2951 }
2952 tlb->EPN = val & ~(tlb->size - 1);
2953 if (val & 0x40)
2954 tlb->prot |= PAGE_VALID;
2955 else
2956 tlb->prot &= ~PAGE_VALID;
2957 if (val & 0x20) {
2958 /* XXX: TO BE FIXED */
2959 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2960 }
2961 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2962 tlb->attr = val & 0xFF;
2963 #if defined (DEBUG_SOFTWARE_TLB)
2964 if (loglevel != 0) {
2965 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2966 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2967 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2968 tlb->prot & PAGE_READ ? 'r' : '-',
2969 tlb->prot & PAGE_WRITE ? 'w' : '-',
2970 tlb->prot & PAGE_EXEC ? 'x' : '-',
2971 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2972 }
2973 #endif
2974 /* Invalidate new TLB (if valid) */
2975 if (tlb->prot & PAGE_VALID) {
2976 end = tlb->EPN + tlb->size;
2977 #if defined (DEBUG_SOFTWARE_TLB)
2978 if (loglevel != 0) {
2979 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2980 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2981 }
2982 #endif
2983 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2984 tlb_flush_page(env, page);
2985 }
2986 }
2987
2988 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
2989 {
2990 ppcemb_tlb_t *tlb;
2991
2992 #if defined (DEBUG_SOFTWARE_TLB)
2993 if (loglevel != 0) {
2994 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
2995 }
2996 #endif
2997 entry &= 0x3F;
2998 tlb = &env->tlb[entry].tlbe;
2999 tlb->RPN = val & 0xFFFFFC00;
3000 tlb->prot = PAGE_READ;
3001 if (val & 0x200)
3002 tlb->prot |= PAGE_EXEC;
3003 if (val & 0x100)
3004 tlb->prot |= PAGE_WRITE;
3005 #if defined (DEBUG_SOFTWARE_TLB)
3006 if (loglevel != 0) {
3007 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3008 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3009 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3010 tlb->prot & PAGE_READ ? 'r' : '-',
3011 tlb->prot & PAGE_WRITE ? 'w' : '-',
3012 tlb->prot & PAGE_EXEC ? 'x' : '-',
3013 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3014 }
3015 #endif
3016 }
3017
3018 target_ulong helper_4xx_tlbsx (target_ulong address)
3019 {
3020 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3021 }
3022
3023 /* PowerPC 440 TLB management */
3024 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
3025 {
3026 ppcemb_tlb_t *tlb;
3027 target_ulong EPN, RPN, size;
3028 int do_flush_tlbs;
3029
3030 #if defined (DEBUG_SOFTWARE_TLB)
3031 if (loglevel != 0) {
3032 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3033 __func__, word, (int)entry, value);
3034 }
3035 #endif
3036 do_flush_tlbs = 0;
3037 entry &= 0x3F;
3038 tlb = &env->tlb[entry].tlbe;
3039 switch (word) {
3040 default:
3041 /* Just here to please gcc */
3042 case 0:
3043 EPN = value & 0xFFFFFC00;
3044 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3045 do_flush_tlbs = 1;
3046 tlb->EPN = EPN;
3047 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3048 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3049 do_flush_tlbs = 1;
3050 tlb->size = size;
3051 tlb->attr &= ~0x1;
3052 tlb->attr |= (value >> 8) & 1;
3053 if (value & 0x200) {
3054 tlb->prot |= PAGE_VALID;
3055 } else {
3056 if (tlb->prot & PAGE_VALID) {
3057 tlb->prot &= ~PAGE_VALID;
3058 do_flush_tlbs = 1;
3059 }
3060 }
3061 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3062 if (do_flush_tlbs)
3063 tlb_flush(env, 1);
3064 break;
3065 case 1:
3066 RPN = value & 0xFFFFFC0F;
3067 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3068 tlb_flush(env, 1);
3069 tlb->RPN = RPN;
3070 break;
3071 case 2:
3072 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3073 tlb->prot = tlb->prot & PAGE_VALID;
3074 if (value & 0x1)
3075 tlb->prot |= PAGE_READ << 4;
3076 if (value & 0x2)
3077 tlb->prot |= PAGE_WRITE << 4;
3078 if (value & 0x4)
3079 tlb->prot |= PAGE_EXEC << 4;
3080 if (value & 0x8)
3081 tlb->prot |= PAGE_READ;
3082 if (value & 0x10)
3083 tlb->prot |= PAGE_WRITE;
3084 if (value & 0x20)
3085 tlb->prot |= PAGE_EXEC;
3086 break;
3087 }
3088 }
3089
3090 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3091 {
3092 ppcemb_tlb_t *tlb;
3093 target_ulong ret;
3094 int size;
3095
3096 entry &= 0x3F;
3097 tlb = &env->tlb[entry].tlbe;
3098 switch (word) {
3099 default:
3100 /* Just here to please gcc */
3101 case 0:
3102 ret = tlb->EPN;
3103 size = booke_page_size_to_tlb(tlb->size);
3104 if (size < 0 || size > 0xF)
3105 size = 1;
3106 ret |= size << 4;
3107 if (tlb->attr & 0x1)
3108 ret |= 0x100;
3109 if (tlb->prot & PAGE_VALID)
3110 ret |= 0x200;
3111 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3112 env->spr[SPR_440_MMUCR] |= tlb->PID;
3113 break;
3114 case 1:
3115 ret = tlb->RPN;
3116 break;
3117 case 2:
3118 ret = tlb->attr & ~0x1;
3119 if (tlb->prot & (PAGE_READ << 4))
3120 ret |= 0x1;
3121 if (tlb->prot & (PAGE_WRITE << 4))
3122 ret |= 0x2;
3123 if (tlb->prot & (PAGE_EXEC << 4))
3124 ret |= 0x4;
3125 if (tlb->prot & PAGE_READ)
3126 ret |= 0x8;
3127 if (tlb->prot & PAGE_WRITE)
3128 ret |= 0x10;
3129 if (tlb->prot & PAGE_EXEC)
3130 ret |= 0x20;
3131 break;
3132 }
3133 return ret;
3134 }
3135
3136 target_ulong helper_440_tlbsx (target_ulong address)
3137 {
3138 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3139 }
3140
3141 #endif /* !CONFIG_USER_ONLY */
jz4740 based target emulation