target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25
  26 //#define DEBUG_KVM
  27
  28 #ifdef DEBUG_KVM
  29 #define dprintf(fmt, ...) \
  30     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  31 #else
  32 #define dprintf(fmt, ...) \
  33     do { } while (0)
  34 #endif
  35
  36 int kvm_arch_init_vcpu(CPUState *env)
  37 {
  38     struct {
  39         struct kvm_cpuid cpuid;
  40         struct kvm_cpuid_entry entries[100];
  41     } __attribute__((packed)) cpuid_data;
  42     uint32_t limit, i, cpuid_i;
  43     uint32_t eax, ebx, ecx, edx;
  44
  45     cpuid_i = 0;
  46
  47     cpu_x86_cpuid(env, 0, &eax, &ebx, &ecx, &edx);
  48     limit = eax;
  49
  50     for (i = 0; i <= limit; i++) {
  51         struct kvm_cpuid_entry *c = &cpuid_data.entries[cpuid_i++];
  52
  53         cpu_x86_cpuid(env, i, &eax, &ebx, &ecx, &edx);
  54         c->function = i;
  55         c->eax = eax;
  56         c->ebx = ebx;
  57         c->ecx = ecx;
  58         c->edx = edx;
  59     }
  60
  61     cpu_x86_cpuid(env, 0x80000000, &eax, &ebx, &ecx, &edx);
  62     limit = eax;
  63
  64     for (i = 0x80000000; i <= limit; i++) {
  65         struct kvm_cpuid_entry *c = &cpuid_data.entries[cpuid_i++];
  66
  67         cpu_x86_cpuid(env, i, &eax, &ebx, &ecx, &edx);
  68         c->function = i;
  69         c->eax = eax;
  70         c->ebx = ebx;
  71         c->ecx = ecx;
  72         c->edx = edx;
  73     }
  74
  75     cpuid_data.cpuid.nent = cpuid_i;
  76
  77     return kvm_vcpu_ioctl(env, KVM_SET_CPUID, &cpuid_data);
  78 }
  79
  80 static int kvm_has_msr_star(CPUState *env)
  81 {
  82     static int has_msr_star;
  83     int ret;
  84
  85     /* first time */
  86     if (has_msr_star == 0) {
  87         struct kvm_msr_list msr_list, *kvm_msr_list;
  88
  89         has_msr_star = -1;
  90
  91         /* Obtain MSR list from KVM.  These are the MSRs that we must
  92          * save/restore */
  93         msr_list.nmsrs = 0;
  94         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
  95         if (ret < 0)
  96             return 0;
  97
  98         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
  99                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 100
 101         kvm_msr_list->nmsrs = msr_list.nmsrs;
 102         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 103         if (ret >= 0) {
 104             int i;
 105
 106             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 107                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 108                     has_msr_star = 1;
 109                     break;
 110                 }
 111             }
 112         }
 113
 114         free(kvm_msr_list);
 115     }
 116
 117     if (has_msr_star == 1)
 118         return 1;
 119     return 0;
 120 }
 121
 122 int kvm_arch_init(KVMState *s, int smp_cpus)
 123 {
 124     int ret;
 125
 126     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 127      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 128      * must be part of guest physical memory, we need to allocate it.  Older
 129      * versions of KVM just assumed that it would be at the end of physical
 130      * memory but that doesn't work with more than 4GB of memory.  We simply
 131      * refuse to work with those older versions of KVM. */
 132     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 133     if (ret <= 0) {
 134         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 135         return ret;
 136     }
 137
 138     /* this address is 3 pages before the bios, and the bios should present
 139      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 140      * this?
 141      */
 142     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 143 }
 144
 145 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 146 {
 147     lhs->selector = rhs->selector;
 148     lhs->base = rhs->base;
 149     lhs->limit = rhs->limit;
 150     lhs->type = 3;
 151     lhs->present = 1;
 152     lhs->dpl = 3;
 153     lhs->db = 0;
 154     lhs->s = 1;
 155     lhs->l = 0;
 156     lhs->g = 0;
 157     lhs->avl = 0;
 158     lhs->unusable = 0;
 159 }
 160
 161 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 162 {
 163     unsigned flags = rhs->flags;
 164     lhs->selector = rhs->selector;
 165     lhs->base = rhs->base;
 166     lhs->limit = rhs->limit;
 167     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 168     lhs->present = (flags & DESC_P_MASK) != 0;
 169     lhs->dpl = rhs->selector & 3;
 170     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 171     lhs->s = (flags & DESC_S_MASK) != 0;
 172     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 173     lhs->g = (flags & DESC_G_MASK) != 0;
 174     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 175     lhs->unusable = 0;
 176 }
 177
 178 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 179 {
 180     lhs->selector = rhs->selector;
 181     lhs->base = rhs->base;
 182     lhs->limit = rhs->limit;
 183     lhs->flags =
 184         (rhs->type << DESC_TYPE_SHIFT)
 185         | (rhs->present * DESC_P_MASK)
 186         | (rhs->dpl << DESC_DPL_SHIFT)
 187         | (rhs->db << DESC_B_SHIFT)
 188         | (rhs->s * DESC_S_MASK)
 189         | (rhs->l << DESC_L_SHIFT)
 190         | (rhs->g * DESC_G_MASK)
 191         | (rhs->avl * DESC_AVL_MASK);
 192 }
 193
 194 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 195 {
 196     if (set)
 197         *kvm_reg = *qemu_reg;
 198     else
 199         *qemu_reg = *kvm_reg;
 200 }
 201
 202 static int kvm_getput_regs(CPUState *env, int set)
 203 {
 204     struct kvm_regs regs;
 205     int ret = 0;
 206
 207     if (!set) {
 208         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 209         if (ret < 0)
 210             return ret;
 211     }
 212
 213     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 214     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 215     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 216     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 217     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 218     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 219     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 220     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 221 #ifdef TARGET_X86_64
 222     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 223     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 224     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 225     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 226     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 227     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 228     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 229     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 230 #endif
 231
 232     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 233     kvm_getput_reg(&regs.rip, &env->eip, set);
 234
 235     if (set)
 236         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 237
 238     return ret;
 239 }
 240
 241 static int kvm_put_fpu(CPUState *env)
 242 {
 243     struct kvm_fpu fpu;
 244     int i;
 245
 246     memset(&fpu, 0, sizeof fpu);
 247     fpu.fsw = env->fpus & ~(7 << 11);
 248     fpu.fsw |= (env->fpstt & 7) << 11;
 249     fpu.fcw = env->fpuc;
 250     for (i = 0; i < 8; ++i)
 251         fpu.ftwx |= (!env->fptags[i]) << i;
 252     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 253     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 254     fpu.mxcsr = env->mxcsr;
 255
 256     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 257 }
 258
 259 static int kvm_put_sregs(CPUState *env)
 260 {
 261     struct kvm_sregs sregs;
 262
 263     memcpy(sregs.interrupt_bitmap,
 264            env->interrupt_bitmap,
 265            sizeof(sregs.interrupt_bitmap));
 266
 267     if ((env->eflags & VM_MASK)) {
 268             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 269             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 270             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 271             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 272             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 273             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 274     } else {
 275             set_seg(&sregs.cs, &env->segs[R_CS]);
 276             set_seg(&sregs.ds, &env->segs[R_DS]);
 277             set_seg(&sregs.es, &env->segs[R_ES]);
 278             set_seg(&sregs.fs, &env->segs[R_FS]);
 279             set_seg(&sregs.gs, &env->segs[R_GS]);
 280             set_seg(&sregs.ss, &env->segs[R_SS]);
 281
 282             if (env->cr[0] & CR0_PE_MASK) {
 283                 /* force ss cpl to cs cpl */
 284                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 285                         (sregs.cs.selector & 3);
 286                 sregs.ss.dpl = sregs.ss.selector & 3;
 287             }
 288     }
 289
 290     set_seg(&sregs.tr, &env->tr);
 291     set_seg(&sregs.ldt, &env->ldt);
 292
 293     sregs.idt.limit = env->idt.limit;
 294     sregs.idt.base = env->idt.base;
 295     sregs.gdt.limit = env->gdt.limit;
 296     sregs.gdt.base = env->gdt.base;
 297
 298     sregs.cr0 = env->cr[0];
 299     sregs.cr2 = env->cr[2];
 300     sregs.cr3 = env->cr[3];
 301     sregs.cr4 = env->cr[4];
 302
 303     sregs.cr8 = cpu_get_apic_tpr(env);
 304     sregs.apic_base = cpu_get_apic_base(env);
 305
 306     sregs.efer = env->efer;
 307
 308     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 309 }
 310
 311 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 312                               uint32_t index, uint64_t value)
 313 {
 314     entry->index = index;
 315     entry->data = value;
 316 }
 317
 318 static int kvm_put_msrs(CPUState *env)
 319 {
 320     struct {
 321         struct kvm_msrs info;
 322         struct kvm_msr_entry entries[100];
 323     } msr_data;
 324     struct kvm_msr_entry *msrs = msr_data.entries;
 325     int n = 0;
 326
 327     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 328     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 329     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 330     if (kvm_has_msr_star(env))
 331         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 332     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 333 #ifdef TARGET_X86_64
 334     /* FIXME if lm capable */
 335     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 336     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 337     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 338     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 339 #endif
 340     msr_data.info.nmsrs = n;
 341
 342     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 343
 344 }
 345
 346
 347 static int kvm_get_fpu(CPUState *env)
 348 {
 349     struct kvm_fpu fpu;
 350     int i, ret;
 351
 352     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 353     if (ret < 0)
 354         return ret;
 355
 356     env->fpstt = (fpu.fsw >> 11) & 7;
 357     env->fpus = fpu.fsw;
 358     env->fpuc = fpu.fcw;
 359     for (i = 0; i < 8; ++i)
 360         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 361     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 362     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 363     env->mxcsr = fpu.mxcsr;
 364
 365     return 0;
 366 }
 367
 368 static int kvm_get_sregs(CPUState *env)
 369 {
 370     struct kvm_sregs sregs;
 371     uint32_t hflags;
 372     int ret;
 373
 374     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 375     if (ret < 0)
 376         return ret;
 377
 378     memcpy(env->interrupt_bitmap,
 379            sregs.interrupt_bitmap,
 380            sizeof(sregs.interrupt_bitmap));
 381
 382     get_seg(&env->segs[R_CS], &sregs.cs);
 383     get_seg(&env->segs[R_DS], &sregs.ds);
 384     get_seg(&env->segs[R_ES], &sregs.es);
 385     get_seg(&env->segs[R_FS], &sregs.fs);
 386     get_seg(&env->segs[R_GS], &sregs.gs);
 387     get_seg(&env->segs[R_SS], &sregs.ss);
 388
 389     get_seg(&env->tr, &sregs.tr);
 390     get_seg(&env->ldt, &sregs.ldt);
 391
 392     env->idt.limit = sregs.idt.limit;
 393     env->idt.base = sregs.idt.base;
 394     env->gdt.limit = sregs.gdt.limit;
 395     env->gdt.base = sregs.gdt.base;
 396
 397     env->cr[0] = sregs.cr0;
 398     env->cr[2] = sregs.cr2;
 399     env->cr[3] = sregs.cr3;
 400     env->cr[4] = sregs.cr4;
 401
 402     cpu_set_apic_base(env, sregs.apic_base);
 403
 404     env->efer = sregs.efer;
 405     //cpu_set_apic_tpr(env, sregs.cr8);
 406
 407 #define HFLAG_COPY_MASK ~( \
 408                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 409                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 410                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 411                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 412
 413
 414
 415     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 416     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 417     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 418             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 419     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 420     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 421             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 422
 423     if (env->efer & MSR_EFER_LMA) {
 424         hflags |= HF_LMA_MASK;
 425     }
 426
 427     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 428         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 429     } else {
 430         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 431                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 432         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 433                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 434         if (!(env->cr[0] & CR0_PE_MASK) ||
 435                    (env->eflags & VM_MASK) ||
 436                    !(hflags & HF_CS32_MASK)) {
 437                 hflags |= HF_ADDSEG_MASK;
 438             } else {
 439                 hflags |= ((env->segs[R_DS].base |
 440                                 env->segs[R_ES].base |
 441                                 env->segs[R_SS].base) != 0) <<
 442                     HF_ADDSEG_SHIFT;
 443             }
 444     }
 445     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 446
 447     return 0;
 448 }
 449
 450 static int kvm_get_msrs(CPUState *env)
 451 {
 452     struct {
 453         struct kvm_msrs info;
 454         struct kvm_msr_entry entries[100];
 455     } msr_data;
 456     struct kvm_msr_entry *msrs = msr_data.entries;
 457     int ret, i, n;
 458
 459     n = 0;
 460     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 461     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 462     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 463     if (kvm_has_msr_star(env))
 464         msrs[n++].index = MSR_STAR;
 465     msrs[n++].index = MSR_IA32_TSC;
 466 #ifdef TARGET_X86_64
 467     /* FIXME lm_capable_kernel */
 468     msrs[n++].index = MSR_CSTAR;
 469     msrs[n++].index = MSR_KERNELGSBASE;
 470     msrs[n++].index = MSR_FMASK;
 471     msrs[n++].index = MSR_LSTAR;
 472 #endif
 473     msr_data.info.nmsrs = n;
 474     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 475     if (ret < 0)
 476         return ret;
 477
 478     for (i = 0; i < ret; i++) {
 479         switch (msrs[i].index) {
 480         case MSR_IA32_SYSENTER_CS:
 481             env->sysenter_cs = msrs[i].data;
 482             break;
 483         case MSR_IA32_SYSENTER_ESP:
 484             env->sysenter_esp = msrs[i].data;
 485             break;
 486         case MSR_IA32_SYSENTER_EIP:
 487             env->sysenter_eip = msrs[i].data;
 488             break;
 489         case MSR_STAR:
 490             env->star = msrs[i].data;
 491             break;
 492 #ifdef TARGET_X86_64
 493         case MSR_CSTAR:
 494             env->cstar = msrs[i].data;
 495             break;
 496         case MSR_KERNELGSBASE:
 497             env->kernelgsbase = msrs[i].data;
 498             break;
 499         case MSR_FMASK:
 500             env->fmask = msrs[i].data;
 501             break;
 502         case MSR_LSTAR:
 503             env->lstar = msrs[i].data;
 504             break;
 505 #endif
 506         case MSR_IA32_TSC:
 507             env->tsc = msrs[i].data;
 508             break;
 509         }
 510     }
 511
 512     return 0;
 513 }
 514
 515 int kvm_arch_put_registers(CPUState *env)
 516 {
 517     int ret;
 518
 519     ret = kvm_getput_regs(env, 1);
 520     if (ret < 0)
 521         return ret;
 522
 523     ret = kvm_put_fpu(env);
 524     if (ret < 0)
 525         return ret;
 526
 527     ret = kvm_put_sregs(env);
 528     if (ret < 0)
 529         return ret;
 530
 531     ret = kvm_put_msrs(env);
 532     if (ret < 0)
 533         return ret;
 534
 535     return 0;
 536 }
 537
 538 int kvm_arch_get_registers(CPUState *env)
 539 {
 540     int ret;
 541
 542     ret = kvm_getput_regs(env, 0);
 543     if (ret < 0)
 544         return ret;
 545
 546     ret = kvm_get_fpu(env);
 547     if (ret < 0)
 548         return ret;
 549
 550     ret = kvm_get_sregs(env);
 551     if (ret < 0)
 552         return ret;
 553
 554     ret = kvm_get_msrs(env);
 555     if (ret < 0)
 556         return ret;
 557
 558     return 0;
 559 }
 560
 561 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 562 {
 563     /* Try to inject an interrupt if the guest can accept it */
 564     if (run->ready_for_interrupt_injection &&
 565         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 566         (env->eflags & IF_MASK)) {
 567         int irq;
 568
 569         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 570         irq = cpu_get_pic_interrupt(env);
 571         if (irq >= 0) {
 572             struct kvm_interrupt intr;
 573             intr.irq = irq;
 574             /* FIXME: errors */
 575             dprintf("injected interrupt %d\n", irq);
 576             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 577         }
 578     }
 579
 580     /* If we have an interrupt but the guest is not ready to receive an
 581      * interrupt, request an interrupt window exit.  This will
 582      * cause a return to userspace as soon as the guest is ready to
 583      * receive interrupts. */
 584     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 585         run->request_interrupt_window = 1;
 586     else
 587         run->request_interrupt_window = 0;
 588
 589     dprintf("setting tpr\n");
 590     run->cr8 = cpu_get_apic_tpr(env);
 591
 592     return 0;
 593 }
 594
 595 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 596 {
 597     if (run->if_flag)
 598         env->eflags |= IF_MASK;
 599     else
 600         env->eflags &= ~IF_MASK;
 601
 602     cpu_set_apic_tpr(env, run->cr8);
 603     cpu_set_apic_base(env, run->apic_base);
 604
 605     return 0;
 606 }
 607
 608 static int kvm_handle_halt(CPUState *env)
 609 {
 610     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 611           (env->eflags & IF_MASK)) &&
 612         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 613         env->halted = 1;
 614         env->exception_index = EXCP_HLT;
 615         return 0;
 616     }
 617
 618     return 1;
 619 }
 620
 621 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 622 {
 623     int ret = 0;
 624
 625     switch (run->exit_reason) {
 626     case KVM_EXIT_HLT:
 627         dprintf("handle_hlt\n");
 628         ret = kvm_handle_halt(env);
 629         break;
 630     }
 631
 632     return ret;
 633 }