target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26
  27 //#define DEBUG_KVM
  28
  29 #ifdef DEBUG_KVM
  30 #define dprintf(fmt, ...) \
  31     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  32 #else
  33 #define dprintf(fmt, ...) \
  34     do { } while (0)
  35 #endif
  36
  37 int kvm_arch_init_vcpu(CPUState *env)
  38 {
  39     struct {
  40         struct kvm_cpuid2 cpuid;
  41         struct kvm_cpuid_entry2 entries[100];
  42     } __attribute__((packed)) cpuid_data;
  43     uint32_t limit, i, j, cpuid_i;
  44     uint32_t eax, ebx, ecx, edx;
  45
  46     cpuid_i = 0;
  47
  48     cpu_x86_cpuid(env, 0, 0, &eax, &ebx, &ecx, &edx);
  49     limit = eax;
  50
  51     for (i = 0; i <= limit; i++) {
  52         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
  53
  54         switch (i) {
  55         case 2: {
  56             /* Keep reading function 2 till all the input is received */
  57             int times;
  58
  59             cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
  60             times = eax & 0xff;
  61
  62             c->function = i;
  63             c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
  64             c->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
  65             c->eax = eax;
  66             c->ebx = ebx;
  67             c->ecx = ecx;
  68             c->edx = edx;
  69
  70             for (j = 1; j < times; ++j) {
  71                 cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
  72                 c->function = i;
  73                 c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
  74                 c->eax = eax;
  75                 c->ebx = ebx;
  76                 c->ecx = ecx;
  77                 c->edx = edx;
  78                 c = &cpuid_data.entries[++cpuid_i];
  79             }
  80             break;
  81         }
  82         case 4:
  83         case 0xb:
  84         case 0xd:
  85             for (j = 0; ; j++) {
  86                 cpu_x86_cpuid(env, i, j, &eax, &ebx, &ecx, &edx);
  87                 c->function = i;
  88                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  89                 c->index = j;
  90                 c->eax = eax;
  91                 c->ebx = ebx;
  92                 c->ecx = ecx;
  93                 c->edx = edx;
  94                 c = &cpuid_data.entries[++cpuid_i];
  95
  96                 if (i == 4 && eax == 0)
  97                     break;
  98                 if (i == 0xb && !(ecx & 0xff00))
  99                     break;
 100                 if (i == 0xd && eax == 0)
 101                     break;
 102             }
 103             break;
 104         default:
 105             cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
 106             c->function = i;
 107             c->eax = eax;
 108             c->ebx = ebx;
 109             c->ecx = ecx;
 110             c->edx = edx;
 111             break;
 112         }
 113     }
 114     cpu_x86_cpuid(env, 0x80000000, 0, &eax, &ebx, &ecx, &edx);
 115     limit = eax;
 116
 117     for (i = 0x80000000; i <= limit; i++) {
 118         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 119
 120         cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
 121         c->function = i;
 122         c->eax = eax;
 123         c->ebx = ebx;
 124         c->ecx = ecx;
 125         c->edx = edx;
 126     }
 127
 128     cpuid_data.cpuid.nent = cpuid_i;
 129
 130     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 131 }
 132
 133 static int kvm_has_msr_star(CPUState *env)
 134 {
 135     static int has_msr_star;
 136     int ret;
 137
 138     /* first time */
 139     if (has_msr_star == 0) {
 140         struct kvm_msr_list msr_list, *kvm_msr_list;
 141
 142         has_msr_star = -1;
 143
 144         /* Obtain MSR list from KVM.  These are the MSRs that we must
 145          * save/restore */
 146         msr_list.nmsrs = 0;
 147         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 148         if (ret < 0)
 149             return 0;
 150
 151         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 152                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 153
 154         kvm_msr_list->nmsrs = msr_list.nmsrs;
 155         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 156         if (ret >= 0) {
 157             int i;
 158
 159             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 160                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 161                     has_msr_star = 1;
 162                     break;
 163                 }
 164             }
 165         }
 166
 167         free(kvm_msr_list);
 168     }
 169
 170     if (has_msr_star == 1)
 171         return 1;
 172     return 0;
 173 }
 174
 175 int kvm_arch_init(KVMState *s, int smp_cpus)
 176 {
 177     int ret;
 178
 179     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 180      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 181      * must be part of guest physical memory, we need to allocate it.  Older
 182      * versions of KVM just assumed that it would be at the end of physical
 183      * memory but that doesn't work with more than 4GB of memory.  We simply
 184      * refuse to work with those older versions of KVM. */
 185     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 186     if (ret <= 0) {
 187         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 188         return ret;
 189     }
 190
 191     /* this address is 3 pages before the bios, and the bios should present
 192      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 193      * this?
 194      */
 195     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 196 }
 197
 198 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 199 {
 200     lhs->selector = rhs->selector;
 201     lhs->base = rhs->base;
 202     lhs->limit = rhs->limit;
 203     lhs->type = 3;
 204     lhs->present = 1;
 205     lhs->dpl = 3;
 206     lhs->db = 0;
 207     lhs->s = 1;
 208     lhs->l = 0;
 209     lhs->g = 0;
 210     lhs->avl = 0;
 211     lhs->unusable = 0;
 212 }
 213
 214 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 215 {
 216     unsigned flags = rhs->flags;
 217     lhs->selector = rhs->selector;
 218     lhs->base = rhs->base;
 219     lhs->limit = rhs->limit;
 220     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 221     lhs->present = (flags & DESC_P_MASK) != 0;
 222     lhs->dpl = rhs->selector & 3;
 223     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 224     lhs->s = (flags & DESC_S_MASK) != 0;
 225     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 226     lhs->g = (flags & DESC_G_MASK) != 0;
 227     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 228     lhs->unusable = 0;
 229 }
 230
 231 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 232 {
 233     lhs->selector = rhs->selector;
 234     lhs->base = rhs->base;
 235     lhs->limit = rhs->limit;
 236     lhs->flags =
 237         (rhs->type << DESC_TYPE_SHIFT)
 238         | (rhs->present * DESC_P_MASK)
 239         | (rhs->dpl << DESC_DPL_SHIFT)
 240         | (rhs->db << DESC_B_SHIFT)
 241         | (rhs->s * DESC_S_MASK)
 242         | (rhs->l << DESC_L_SHIFT)
 243         | (rhs->g * DESC_G_MASK)
 244         | (rhs->avl * DESC_AVL_MASK);
 245 }
 246
 247 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 248 {
 249     if (set)
 250         *kvm_reg = *qemu_reg;
 251     else
 252         *qemu_reg = *kvm_reg;
 253 }
 254
 255 static int kvm_getput_regs(CPUState *env, int set)
 256 {
 257     struct kvm_regs regs;
 258     int ret = 0;
 259
 260     if (!set) {
 261         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 262         if (ret < 0)
 263             return ret;
 264     }
 265
 266     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 267     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 268     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 269     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 270     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 271     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 272     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 273     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 274 #ifdef TARGET_X86_64
 275     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 276     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 277     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 278     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 279     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 280     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 281     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 282     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 283 #endif
 284
 285     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 286     kvm_getput_reg(&regs.rip, &env->eip, set);
 287
 288     if (set)
 289         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 290
 291     return ret;
 292 }
 293
 294 static int kvm_put_fpu(CPUState *env)
 295 {
 296     struct kvm_fpu fpu;
 297     int i;
 298
 299     memset(&fpu, 0, sizeof fpu);
 300     fpu.fsw = env->fpus & ~(7 << 11);
 301     fpu.fsw |= (env->fpstt & 7) << 11;
 302     fpu.fcw = env->fpuc;
 303     for (i = 0; i < 8; ++i)
 304         fpu.ftwx |= (!env->fptags[i]) << i;
 305     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 306     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 307     fpu.mxcsr = env->mxcsr;
 308
 309     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 310 }
 311
 312 static int kvm_put_sregs(CPUState *env)
 313 {
 314     struct kvm_sregs sregs;
 315
 316     memcpy(sregs.interrupt_bitmap,
 317            env->interrupt_bitmap,
 318            sizeof(sregs.interrupt_bitmap));
 319
 320     if ((env->eflags & VM_MASK)) {
 321             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 322             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 323             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 324             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 325             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 326             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 327     } else {
 328             set_seg(&sregs.cs, &env->segs[R_CS]);
 329             set_seg(&sregs.ds, &env->segs[R_DS]);
 330             set_seg(&sregs.es, &env->segs[R_ES]);
 331             set_seg(&sregs.fs, &env->segs[R_FS]);
 332             set_seg(&sregs.gs, &env->segs[R_GS]);
 333             set_seg(&sregs.ss, &env->segs[R_SS]);
 334
 335             if (env->cr[0] & CR0_PE_MASK) {
 336                 /* force ss cpl to cs cpl */
 337                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 338                         (sregs.cs.selector & 3);
 339                 sregs.ss.dpl = sregs.ss.selector & 3;
 340             }
 341     }
 342
 343     set_seg(&sregs.tr, &env->tr);
 344     set_seg(&sregs.ldt, &env->ldt);
 345
 346     sregs.idt.limit = env->idt.limit;
 347     sregs.idt.base = env->idt.base;
 348     sregs.gdt.limit = env->gdt.limit;
 349     sregs.gdt.base = env->gdt.base;
 350
 351     sregs.cr0 = env->cr[0];
 352     sregs.cr2 = env->cr[2];
 353     sregs.cr3 = env->cr[3];
 354     sregs.cr4 = env->cr[4];
 355
 356     sregs.cr8 = cpu_get_apic_tpr(env);
 357     sregs.apic_base = cpu_get_apic_base(env);
 358
 359     sregs.efer = env->efer;
 360
 361     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 362 }
 363
 364 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 365                               uint32_t index, uint64_t value)
 366 {
 367     entry->index = index;
 368     entry->data = value;
 369 }
 370
 371 static int kvm_put_msrs(CPUState *env)
 372 {
 373     struct {
 374         struct kvm_msrs info;
 375         struct kvm_msr_entry entries[100];
 376     } msr_data;
 377     struct kvm_msr_entry *msrs = msr_data.entries;
 378     int n = 0;
 379
 380     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 381     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 382     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 383     if (kvm_has_msr_star(env))
 384         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 385     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 386 #ifdef TARGET_X86_64
 387     /* FIXME if lm capable */
 388     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 389     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 390     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 391     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 392 #endif
 393     msr_data.info.nmsrs = n;
 394
 395     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 396
 397 }
 398
 399
 400 static int kvm_get_fpu(CPUState *env)
 401 {
 402     struct kvm_fpu fpu;
 403     int i, ret;
 404
 405     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 406     if (ret < 0)
 407         return ret;
 408
 409     env->fpstt = (fpu.fsw >> 11) & 7;
 410     env->fpus = fpu.fsw;
 411     env->fpuc = fpu.fcw;
 412     for (i = 0; i < 8; ++i)
 413         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 414     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 415     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 416     env->mxcsr = fpu.mxcsr;
 417
 418     return 0;
 419 }
 420
 421 static int kvm_get_sregs(CPUState *env)
 422 {
 423     struct kvm_sregs sregs;
 424     uint32_t hflags;
 425     int ret;
 426
 427     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 428     if (ret < 0)
 429         return ret;
 430
 431     memcpy(env->interrupt_bitmap,
 432            sregs.interrupt_bitmap,
 433            sizeof(sregs.interrupt_bitmap));
 434
 435     get_seg(&env->segs[R_CS], &sregs.cs);
 436     get_seg(&env->segs[R_DS], &sregs.ds);
 437     get_seg(&env->segs[R_ES], &sregs.es);
 438     get_seg(&env->segs[R_FS], &sregs.fs);
 439     get_seg(&env->segs[R_GS], &sregs.gs);
 440     get_seg(&env->segs[R_SS], &sregs.ss);
 441
 442     get_seg(&env->tr, &sregs.tr);
 443     get_seg(&env->ldt, &sregs.ldt);
 444
 445     env->idt.limit = sregs.idt.limit;
 446     env->idt.base = sregs.idt.base;
 447     env->gdt.limit = sregs.gdt.limit;
 448     env->gdt.base = sregs.gdt.base;
 449
 450     env->cr[0] = sregs.cr0;
 451     env->cr[2] = sregs.cr2;
 452     env->cr[3] = sregs.cr3;
 453     env->cr[4] = sregs.cr4;
 454
 455     cpu_set_apic_base(env, sregs.apic_base);
 456
 457     env->efer = sregs.efer;
 458     //cpu_set_apic_tpr(env, sregs.cr8);
 459
 460 #define HFLAG_COPY_MASK ~( \
 461                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 462                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 463                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 464                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 465
 466
 467
 468     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 469     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 470     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 471             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 472     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 473     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 474             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 475
 476     if (env->efer & MSR_EFER_LMA) {
 477         hflags |= HF_LMA_MASK;
 478     }
 479
 480     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 481         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 482     } else {
 483         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 484                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 485         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 486                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 487         if (!(env->cr[0] & CR0_PE_MASK) ||
 488                    (env->eflags & VM_MASK) ||
 489                    !(hflags & HF_CS32_MASK)) {
 490                 hflags |= HF_ADDSEG_MASK;
 491             } else {
 492                 hflags |= ((env->segs[R_DS].base |
 493                                 env->segs[R_ES].base |
 494                                 env->segs[R_SS].base) != 0) <<
 495                     HF_ADDSEG_SHIFT;
 496             }
 497     }
 498     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 499
 500     return 0;
 501 }
 502
 503 static int kvm_get_msrs(CPUState *env)
 504 {
 505     struct {
 506         struct kvm_msrs info;
 507         struct kvm_msr_entry entries[100];
 508     } msr_data;
 509     struct kvm_msr_entry *msrs = msr_data.entries;
 510     int ret, i, n;
 511
 512     n = 0;
 513     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 514     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 515     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 516     if (kvm_has_msr_star(env))
 517         msrs[n++].index = MSR_STAR;
 518     msrs[n++].index = MSR_IA32_TSC;
 519 #ifdef TARGET_X86_64
 520     /* FIXME lm_capable_kernel */
 521     msrs[n++].index = MSR_CSTAR;
 522     msrs[n++].index = MSR_KERNELGSBASE;
 523     msrs[n++].index = MSR_FMASK;
 524     msrs[n++].index = MSR_LSTAR;
 525 #endif
 526     msr_data.info.nmsrs = n;
 527     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 528     if (ret < 0)
 529         return ret;
 530
 531     for (i = 0; i < ret; i++) {
 532         switch (msrs[i].index) {
 533         case MSR_IA32_SYSENTER_CS:
 534             env->sysenter_cs = msrs[i].data;
 535             break;
 536         case MSR_IA32_SYSENTER_ESP:
 537             env->sysenter_esp = msrs[i].data;
 538             break;
 539         case MSR_IA32_SYSENTER_EIP:
 540             env->sysenter_eip = msrs[i].data;
 541             break;
 542         case MSR_STAR:
 543             env->star = msrs[i].data;
 544             break;
 545 #ifdef TARGET_X86_64
 546         case MSR_CSTAR:
 547             env->cstar = msrs[i].data;
 548             break;
 549         case MSR_KERNELGSBASE:
 550             env->kernelgsbase = msrs[i].data;
 551             break;
 552         case MSR_FMASK:
 553             env->fmask = msrs[i].data;
 554             break;
 555         case MSR_LSTAR:
 556             env->lstar = msrs[i].data;
 557             break;
 558 #endif
 559         case MSR_IA32_TSC:
 560             env->tsc = msrs[i].data;
 561             break;
 562         }
 563     }
 564
 565     return 0;
 566 }
 567
 568 int kvm_arch_put_registers(CPUState *env)
 569 {
 570     int ret;
 571
 572     ret = kvm_getput_regs(env, 1);
 573     if (ret < 0)
 574         return ret;
 575
 576     ret = kvm_put_fpu(env);
 577     if (ret < 0)
 578         return ret;
 579
 580     ret = kvm_put_sregs(env);
 581     if (ret < 0)
 582         return ret;
 583
 584     ret = kvm_put_msrs(env);
 585     if (ret < 0)
 586         return ret;
 587
 588     return 0;
 589 }
 590
 591 int kvm_arch_get_registers(CPUState *env)
 592 {
 593     int ret;
 594
 595     ret = kvm_getput_regs(env, 0);
 596     if (ret < 0)
 597         return ret;
 598
 599     ret = kvm_get_fpu(env);
 600     if (ret < 0)
 601         return ret;
 602
 603     ret = kvm_get_sregs(env);
 604     if (ret < 0)
 605         return ret;
 606
 607     ret = kvm_get_msrs(env);
 608     if (ret < 0)
 609         return ret;
 610
 611     return 0;
 612 }
 613
 614 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 615 {
 616     /* Try to inject an interrupt if the guest can accept it */
 617     if (run->ready_for_interrupt_injection &&
 618         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 619         (env->eflags & IF_MASK)) {
 620         int irq;
 621
 622         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 623         irq = cpu_get_pic_interrupt(env);
 624         if (irq >= 0) {
 625             struct kvm_interrupt intr;
 626             intr.irq = irq;
 627             /* FIXME: errors */
 628             dprintf("injected interrupt %d\n", irq);
 629             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 630         }
 631     }
 632
 633     /* If we have an interrupt but the guest is not ready to receive an
 634      * interrupt, request an interrupt window exit.  This will
 635      * cause a return to userspace as soon as the guest is ready to
 636      * receive interrupts. */
 637     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 638         run->request_interrupt_window = 1;
 639     else
 640         run->request_interrupt_window = 0;
 641
 642     dprintf("setting tpr\n");
 643     run->cr8 = cpu_get_apic_tpr(env);
 644
 645     return 0;
 646 }
 647
 648 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 649 {
 650     if (run->if_flag)
 651         env->eflags |= IF_MASK;
 652     else
 653         env->eflags &= ~IF_MASK;
 654
 655     cpu_set_apic_tpr(env, run->cr8);
 656     cpu_set_apic_base(env, run->apic_base);
 657
 658     return 0;
 659 }
 660
 661 static int kvm_handle_halt(CPUState *env)
 662 {
 663     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 664           (env->eflags & IF_MASK)) &&
 665         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 666         env->halted = 1;
 667         env->exception_index = EXCP_HLT;
 668         return 0;
 669     }
 670
 671     return 1;
 672 }
 673
 674 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 675 {
 676     int ret = 0;
 677
 678     switch (run->exit_reason) {
 679     case KVM_EXIT_HLT:
 680         dprintf("handle_hlt\n");
 681         ret = kvm_handle_halt(env);
 682         break;
 683     }
 684
 685     return ret;
 686 }
 687
 688 #ifdef KVM_CAP_SET_GUEST_DEBUG
 689 static int kvm_patch_opcode_byte(CPUState *env, target_ulong addr, uint8_t val)
 690 {
 691     target_phys_addr_t phys_page_addr;
 692     unsigned long pd;
 693     uint8_t *ptr;
 694
 695     phys_page_addr = cpu_get_phys_page_debug(env, addr & TARGET_PAGE_MASK);
 696     if (phys_page_addr == -1)
 697         return -EINVAL;
 698
 699     pd = cpu_get_physical_page_desc(phys_page_addr);
 700     if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
 701         (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM && !(pd & IO_MEM_ROMD))
 702         return -EINVAL;
 703
 704     ptr = phys_ram_base + (pd & TARGET_PAGE_MASK)
 705                         + (addr & ~TARGET_PAGE_MASK);
 706     *ptr = val;
 707     return 0;
 708 }
 709
 710 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 711 {
 712     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 713         kvm_patch_opcode_byte(env, bp->pc, 0xcc))
 714         return -EINVAL;
 715     return 0;
 716 }
 717
 718 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 719 {
 720     uint8_t int3;
 721
 722     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 723         kvm_patch_opcode_byte(env, bp->pc, bp->saved_insn))
 724         return -EINVAL;
 725     return 0;
 726 }
 727
 728 static struct {
 729     target_ulong addr;
 730     int len;
 731     int type;
 732 } hw_breakpoint[4];
 733
 734 static int nb_hw_breakpoint;
 735
 736 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 737 {
 738     int n;
 739
 740     for (n = 0; n < nb_hw_breakpoint; n++)
 741         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 742             (hw_breakpoint[n].len == len || len == -1))
 743             return n;
 744     return -1;
 745 }
 746
 747 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 748                                   target_ulong len, int type)
 749 {
 750     switch (type) {
 751     case GDB_BREAKPOINT_HW:
 752         len = 1;
 753         break;
 754     case GDB_WATCHPOINT_WRITE:
 755     case GDB_WATCHPOINT_ACCESS:
 756         switch (len) {
 757         case 1:
 758             break;
 759         case 2:
 760         case 4:
 761         case 8:
 762             if (addr & (len - 1))
 763                 return -EINVAL;
 764             break;
 765         default:
 766             return -EINVAL;
 767         }
 768         break;
 769     default:
 770         return -ENOSYS;
 771     }
 772
 773     if (nb_hw_breakpoint == 4)
 774         return -ENOBUFS;
 775
 776     if (find_hw_breakpoint(addr, len, type) >= 0)
 777         return -EEXIST;
 778
 779     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 780     hw_breakpoint[nb_hw_breakpoint].len = len;
 781     hw_breakpoint[nb_hw_breakpoint].type = type;
 782     nb_hw_breakpoint++;
 783
 784     return 0;
 785 }
 786
 787 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 788                                   target_ulong len, int type)
 789 {
 790     int n;
 791
 792     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 793     if (n < 0)
 794         return -ENOENT;
 795
 796     nb_hw_breakpoint--;
 797     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 798
 799     return 0;
 800 }
 801
 802 void kvm_arch_remove_all_hw_breakpoints(void)
 803 {
 804     nb_hw_breakpoint = 0;
 805 }
 806
 807 static CPUWatchpoint hw_watchpoint;
 808
 809 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 810 {
 811     int handle = 0;
 812     int n;
 813
 814     if (arch_info->exception == 1) {
 815         if (arch_info->dr6 & (1 << 14)) {
 816             if (cpu_single_env->singlestep_enabled)
 817                 handle = 1;
 818         } else {
 819             for (n = 0; n < 4; n++)
 820                 if (arch_info->dr6 & (1 << n))
 821                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 822                     case 0x0:
 823                         handle = 1;
 824                         break;
 825                     case 0x1:
 826                         handle = 1;
 827                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 828                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 829                         hw_watchpoint.flags = BP_MEM_WRITE;
 830                         break;
 831                     case 0x3:
 832                         handle = 1;
 833                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 834                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 835                         hw_watchpoint.flags = BP_MEM_ACCESS;
 836                         break;
 837                     }
 838         }
 839     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
 840         handle = 1;
 841
 842     if (!handle)
 843         kvm_update_guest_debug(cpu_single_env,
 844                         (arch_info->exception == 1) ?
 845                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 846
 847     return handle;
 848 }
 849
 850 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 851 {
 852     const uint8_t type_code[] = {
 853         [GDB_BREAKPOINT_HW] = 0x0,
 854         [GDB_WATCHPOINT_WRITE] = 0x1,
 855         [GDB_WATCHPOINT_ACCESS] = 0x3
 856     };
 857     const uint8_t len_code[] = {
 858         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 859     };
 860     int n;
 861
 862     if (kvm_sw_breakpoints_active(env))
 863         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 864
 865     if (nb_hw_breakpoint > 0) {
 866         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 867         dbg->arch.debugreg[7] = 0x0600;
 868         for (n = 0; n < nb_hw_breakpoint; n++) {
 869             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 870             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 871                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 872                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 873         }
 874     }
 875 }
 876 #endif /* KVM_CAP_SET_GUEST_DEBUG */