tcg/tcg-op.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "tcg.h"
  25
  26 int gen_new_label(void);
  27
  28 static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
  29 {
  30     *gen_opc_ptr++ = opc;
  31     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  32 }
  33
  34 static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
  35 {
  36     *gen_opc_ptr++ = opc;
  37     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  38 }
  39
  40 static inline void tcg_gen_op1i(int opc, TCGArg arg1)
  41 {
  42     *gen_opc_ptr++ = opc;
  43     *gen_opparam_ptr++ = arg1;
  44 }
  45
  46 static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
  47 {
  48     *gen_opc_ptr++ = opc;
  49     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  50     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
  51 }
  52
  53 static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
  54 {
  55     *gen_opc_ptr++ = opc;
  56     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  57     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
  58 }
  59
  60 static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
  61 {
  62     *gen_opc_ptr++ = opc;
  63     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  64     *gen_opparam_ptr++ = arg2;
  65 }
  66
  67 static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
  68 {
  69     *gen_opc_ptr++ = opc;
  70     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  71     *gen_opparam_ptr++ = arg2;
  72 }
  73
  74 static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
  75 {
  76     *gen_opc_ptr++ = opc;
  77     *gen_opparam_ptr++ = arg1;
  78     *gen_opparam_ptr++ = arg2;
  79 }
  80
  81 static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
  82                                    TCGv_i32 arg3)
  83 {
  84     *gen_opc_ptr++ = opc;
  85     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
  86     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
  87     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
  88 }
  89
  90 static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
  91                                    TCGv_i64 arg3)
  92 {
  93     *gen_opc_ptr++ = opc;
  94     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
  95     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
  96     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
  97 }
  98
  99 static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 100                                     TCGArg arg3)
 101 {
 102     *gen_opc_ptr++ = opc;
 103     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 104     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 105     *gen_opparam_ptr++ = arg3;
 106 }
 107
 108 static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 109                                     TCGArg arg3)
 110 {
 111     *gen_opc_ptr++ = opc;
 112     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 113     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 114     *gen_opparam_ptr++ = arg3;
 115 }
 116
 117 static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
 118                                        TCGArg offset)
 119 {
 120     *gen_opc_ptr++ = opc;
 121     *gen_opparam_ptr++ = GET_TCGV_I32(val);
 122     *gen_opparam_ptr++ = GET_TCGV_PTR(base);
 123     *gen_opparam_ptr++ = offset;
 124 }
 125
 126 static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
 127                                        TCGArg offset)
 128 {
 129     *gen_opc_ptr++ = opc;
 130     *gen_opparam_ptr++ = GET_TCGV_I64(val);
 131     *gen_opparam_ptr++ = GET_TCGV_PTR(base);
 132     *gen_opparam_ptr++ = offset;
 133 }
 134
 135 static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
 136                                                 TCGArg mem_index)
 137 {
 138     *gen_opc_ptr++ = opc;
 139     *gen_opparam_ptr++ = GET_TCGV_I64(val);
 140     *gen_opparam_ptr++ = GET_TCGV_I32(addr);
 141     *gen_opparam_ptr++ = mem_index;
 142 }
 143
 144 static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
 145                                                 TCGArg mem_index)
 146 {
 147     *gen_opc_ptr++ = opc;
 148     *gen_opparam_ptr++ = GET_TCGV_I64(val);
 149     *gen_opparam_ptr++ = GET_TCGV_I64(addr);
 150     *gen_opparam_ptr++ = mem_index;
 151 }
 152
 153 static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 154                                    TCGv_i32 arg3, TCGv_i32 arg4)
 155 {
 156     *gen_opc_ptr++ = opc;
 157     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 158     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 159     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 160     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 161 }
 162
 163 static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 164                                    TCGv_i64 arg3, TCGv_i64 arg4)
 165 {
 166     *gen_opc_ptr++ = opc;
 167     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 168     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 169     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 170     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 171 }
 172
 173 static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 174                                     TCGv_i32 arg3, TCGArg arg4)
 175 {
 176     *gen_opc_ptr++ = opc;
 177     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 178     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 179     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 180     *gen_opparam_ptr++ = arg4;
 181 }
 182
 183 static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 184                                     TCGv_i64 arg3, TCGArg arg4)
 185 {
 186     *gen_opc_ptr++ = opc;
 187     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 188     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 189     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 190     *gen_opparam_ptr++ = arg4;
 191 }
 192
 193 static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 194                                      TCGArg arg3, TCGArg arg4)
 195 {
 196     *gen_opc_ptr++ = opc;
 197     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 198     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 199     *gen_opparam_ptr++ = arg3;
 200     *gen_opparam_ptr++ = arg4;
 201 }
 202
 203 static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 204                                      TCGArg arg3, TCGArg arg4)
 205 {
 206     *gen_opc_ptr++ = opc;
 207     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 208     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 209     *gen_opparam_ptr++ = arg3;
 210     *gen_opparam_ptr++ = arg4;
 211 }
 212
 213 static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 214                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
 215 {
 216     *gen_opc_ptr++ = opc;
 217     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 218     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 219     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 220     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 221     *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
 222 }
 223
 224 static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 225                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
 226 {
 227     *gen_opc_ptr++ = opc;
 228     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 229     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 230     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 231     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 232     *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
 233 }
 234
 235 static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 236                                     TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
 237 {
 238     *gen_opc_ptr++ = opc;
 239     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 240     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 241     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 242     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 243     *gen_opparam_ptr++ = arg5;
 244 }
 245
 246 static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 247                                     TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
 248 {
 249     *gen_opc_ptr++ = opc;
 250     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 251     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 252     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 253     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 254     *gen_opparam_ptr++ = arg5;
 255 }
 256
 257 static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 258                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
 259                                    TCGv_i32 arg6)
 260 {
 261     *gen_opc_ptr++ = opc;
 262     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 263     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 264     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 265     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 266     *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
 267     *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
 268 }
 269
 270 static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 271                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
 272                                    TCGv_i64 arg6)
 273 {
 274     *gen_opc_ptr++ = opc;
 275     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 276     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 277     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 278     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 279     *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
 280     *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
 281 }
 282
 283 static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
 284                                      TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
 285                                      TCGArg arg6)
 286 {
 287     *gen_opc_ptr++ = opc;
 288     *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
 289     *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
 290     *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
 291     *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
 292     *gen_opparam_ptr++ = arg5;
 293     *gen_opparam_ptr++ = arg6;
 294 }
 295
 296 static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
 297                                      TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
 298                                      TCGArg arg6)
 299 {
 300     *gen_opc_ptr++ = opc;
 301     *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
 302     *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
 303     *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
 304     *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
 305     *gen_opparam_ptr++ = arg5;
 306     *gen_opparam_ptr++ = arg6;
 307 }
 308
 309 static inline void gen_set_label(int n)
 310 {
 311     tcg_gen_op1i(INDEX_op_set_label, n);
 312 }
 313
 314 static inline void tcg_gen_br(int label)
 315 {
 316     tcg_gen_op1i(INDEX_op_br, label);
 317 }
 318
 319 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
 320 {
 321     if (!TCGV_EQUAL_I32(ret, arg))
 322         tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
 323 }
 324
 325 static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
 326 {
 327     tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
 328 }
 329
 330 /* helper calls */
 331 static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
 332                                    TCGArg ret, int nargs, TCGArg *args)
 333 {
 334     TCGv_ptr fn;
 335     fn = tcg_const_ptr((tcg_target_long)func);
 336     tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
 337                   nargs, args);
 338     tcg_temp_free_ptr(fn);
 339 }
 340
 341 /* FIXME: Should this be pure?  */
 342 static inline void tcg_gen_helper64(void *func, TCGv_i64 ret,
 343                                     TCGv_i64 a, TCGv_i64 b)
 344 {
 345     TCGv_ptr fn;
 346     TCGArg args[2];
 347     fn = tcg_const_ptr((tcg_target_long)func);
 348     args[0] = GET_TCGV_I64(a);
 349     args[1] = GET_TCGV_I64(b);
 350     tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args);
 351     tcg_temp_free_ptr(fn);
 352 }
 353
 354 /* 32 bit ops */
 355
 356 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 357 {
 358     tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
 359 }
 360
 361 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 362 {
 363     tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
 364 }
 365
 366 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 367 {
 368     tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
 369 }
 370
 371 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 372 {
 373     tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
 374 }
 375
 376 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
 377 {
 378     tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
 379 }
 380
 381 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 382 {
 383     tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
 384 }
 385
 386 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 387 {
 388     tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
 389 }
 390
 391 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
 392 {
 393     tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
 394 }
 395
 396 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 397 {
 398     tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
 399 }
 400
 401 static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 402 {
 403     /* some cases can be optimized here */
 404     if (arg2 == 0) {
 405         tcg_gen_mov_i32(ret, arg1);
 406     } else {
 407         TCGv_i32 t0 = tcg_const_i32(arg2);
 408         tcg_gen_add_i32(ret, arg1, t0);
 409         tcg_temp_free_i32(t0);
 410     }
 411 }
 412
 413 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 414 {
 415     tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
 416 }
 417
 418 static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
 419 {
 420     TCGv_i32 t0 = tcg_const_i32(arg1);
 421     tcg_gen_sub_i32(ret, t0, arg2);
 422     tcg_temp_free_i32(t0);
 423 }
 424
 425 static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 426 {
 427     /* some cases can be optimized here */
 428     if (arg2 == 0) {
 429         tcg_gen_mov_i32(ret, arg1);
 430     } else {
 431         TCGv_i32 t0 = tcg_const_i32(arg2);
 432         tcg_gen_sub_i32(ret, arg1, t0);
 433         tcg_temp_free_i32(t0);
 434     }
 435 }
 436
 437 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 438 {
 439     if (TCGV_EQUAL_I32(arg1, arg2)) {
 440         tcg_gen_mov_i32(ret, arg1);
 441     } else {
 442         tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
 443     }
 444 }
 445
 446 static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 447 {
 448     /* some cases can be optimized here */
 449     if (arg2 == 0) {
 450         tcg_gen_movi_i32(ret, 0);
 451     } else if (arg2 == 0xffffffff) {
 452         tcg_gen_mov_i32(ret, arg1);
 453     } else {
 454         TCGv_i32 t0 = tcg_const_i32(arg2);
 455         tcg_gen_and_i32(ret, arg1, t0);
 456         tcg_temp_free_i32(t0);
 457     }
 458 }
 459
 460 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 461 {
 462     if (TCGV_EQUAL_I32(arg1, arg2)) {
 463         tcg_gen_mov_i32(ret, arg1);
 464     } else {
 465         tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
 466     }
 467 }
 468
 469 static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 470 {
 471     /* some cases can be optimized here */
 472     if (arg2 == 0xffffffff) {
 473         tcg_gen_movi_i32(ret, 0xffffffff);
 474     } else if (arg2 == 0) {
 475         tcg_gen_mov_i32(ret, arg1);
 476     } else {
 477         TCGv_i32 t0 = tcg_const_i32(arg2);
 478         tcg_gen_or_i32(ret, arg1, t0);
 479         tcg_temp_free_i32(t0);
 480     }
 481 }
 482
 483 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 484 {
 485     if (TCGV_EQUAL_I32(arg1, arg2)) {
 486         tcg_gen_movi_i32(ret, 0);
 487     } else {
 488         tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
 489     }
 490 }
 491
 492 static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 493 {
 494     /* some cases can be optimized here */
 495     if (arg2 == 0) {
 496         tcg_gen_mov_i32(ret, arg1);
 497     } else {
 498         TCGv_i32 t0 = tcg_const_i32(arg2);
 499         tcg_gen_xor_i32(ret, arg1, t0);
 500         tcg_temp_free_i32(t0);
 501     }
 502 }
 503
 504 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 505 {
 506     tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
 507 }
 508
 509 static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 510 {
 511     if (arg2 == 0) {
 512         tcg_gen_mov_i32(ret, arg1);
 513     } else {
 514         TCGv_i32 t0 = tcg_const_i32(arg2);
 515         tcg_gen_shl_i32(ret, arg1, t0);
 516         tcg_temp_free_i32(t0);
 517     }
 518 }
 519
 520 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 521 {
 522     tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
 523 }
 524
 525 static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 526 {
 527     if (arg2 == 0) {
 528         tcg_gen_mov_i32(ret, arg1);
 529     } else {
 530         TCGv_i32 t0 = tcg_const_i32(arg2);
 531         tcg_gen_shr_i32(ret, arg1, t0);
 532         tcg_temp_free_i32(t0);
 533     }
 534 }
 535
 536 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 537 {
 538     tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
 539 }
 540
 541 static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 542 {
 543     if (arg2 == 0) {
 544         tcg_gen_mov_i32(ret, arg1);
 545     } else {
 546         TCGv_i32 t0 = tcg_const_i32(arg2);
 547         tcg_gen_sar_i32(ret, arg1, t0);
 548         tcg_temp_free_i32(t0);
 549     }
 550 }
 551
 552 static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
 553                                       int label_index)
 554 {
 555     tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
 556 }
 557
 558 static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
 559                                        int label_index)
 560 {
 561     TCGv_i32 t0 = tcg_const_i32(arg2);
 562     tcg_gen_brcond_i32(cond, arg1, t0, label_index);
 563     tcg_temp_free_i32(t0);
 564 }
 565
 566 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 567 {
 568     tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
 569 }
 570
 571 static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 572 {
 573     TCGv_i32 t0 = tcg_const_i32(arg2);
 574     tcg_gen_mul_i32(ret, arg1, t0);
 575     tcg_temp_free_i32(t0);
 576 }
 577
 578 #ifdef TCG_TARGET_HAS_div_i32
 579 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 580 {
 581     tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
 582 }
 583
 584 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 585 {
 586     tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
 587 }
 588
 589 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 590 {
 591     tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
 592 }
 593
 594 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 595 {
 596     tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
 597 }
 598 #else
 599 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 600 {
 601     TCGv_i32 t0;
 602     t0 = tcg_temp_new_i32();
 603     tcg_gen_sari_i32(t0, arg1, 31);
 604     tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
 605     tcg_temp_free_i32(t0);
 606 }
 607
 608 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 609 {
 610     TCGv_i32 t0;
 611     t0 = tcg_temp_new_i32();
 612     tcg_gen_sari_i32(t0, arg1, 31);
 613     tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
 614     tcg_temp_free_i32(t0);
 615 }
 616
 617 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 618 {
 619     TCGv_i32 t0;
 620     t0 = tcg_temp_new_i32();
 621     tcg_gen_movi_i32(t0, 0);
 622     tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
 623     tcg_temp_free_i32(t0);
 624 }
 625
 626 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 627 {
 628     TCGv_i32 t0;
 629     t0 = tcg_temp_new_i32();
 630     tcg_gen_movi_i32(t0, 0);
 631     tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
 632     tcg_temp_free_i32(t0);
 633 }
 634 #endif
 635
 636 #if TCG_TARGET_REG_BITS == 32
 637
 638 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
 639 {
 640     if (!TCGV_EQUAL_I64(ret, arg)) {
 641         tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
 642         tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
 643     }
 644 }
 645
 646 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
 647 {
 648     tcg_gen_movi_i32(TCGV_LOW(ret), arg);
 649     tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
 650 }
 651
 652 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 653                                     tcg_target_long offset)
 654 {
 655     tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
 656     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 657 }
 658
 659 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 660                                     tcg_target_long offset)
 661 {
 662     tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
 663     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
 664 }
 665
 666 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 667                                      tcg_target_long offset)
 668 {
 669     tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
 670     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 671 }
 672
 673 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 674                                      tcg_target_long offset)
 675 {
 676     tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
 677     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
 678 }
 679
 680 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
 681                                      tcg_target_long offset)
 682 {
 683     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 684     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
 685 }
 686
 687 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
 688                                      tcg_target_long offset)
 689 {
 690     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 691     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
 692 }
 693
 694 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
 695                                   tcg_target_long offset)
 696 {
 697     /* since arg2 and ret have different types, they cannot be the
 698        same temporary */
 699 #ifdef TCG_TARGET_WORDS_BIGENDIAN
 700     tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
 701     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
 702 #else
 703     tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
 704     tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
 705 #endif
 706 }
 707
 708 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 709                                    tcg_target_long offset)
 710 {
 711     tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
 712 }
 713
 714 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 715                                     tcg_target_long offset)
 716 {
 717     tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
 718 }
 719
 720 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 721                                     tcg_target_long offset)
 722 {
 723     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
 724 }
 725
 726 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
 727                                   tcg_target_long offset)
 728 {
 729 #ifdef TCG_TARGET_WORDS_BIGENDIAN
 730     tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
 731     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
 732 #else
 733     tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
 734     tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
 735 #endif
 736 }
 737
 738 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 739 {
 740     tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
 741                     TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 742                     TCGV_HIGH(arg2));
 743 }
 744
 745 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 746 {
 747     tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
 748                     TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 749                     TCGV_HIGH(arg2));
 750 }
 751
 752 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 753 {
 754     tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 755     tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 756 }
 757
 758 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 759 {
 760     tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 761     tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 762 }
 763
 764 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 765 {
 766     tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 767     tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 768 }
 769
 770 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 771 {
 772     tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 773     tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 774 }
 775
 776 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 777 {
 778     tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
 779     tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
 780 }
 781
 782 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 783 {
 784     tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
 785     tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
 786 }
 787
 788 /* XXX: use generic code when basic block handling is OK or CPU
 789    specific code (x86) */
 790 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 791 {
 792     tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2);
 793 }
 794
 795 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 796 {
 797     tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
 798 }
 799
 800 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 801 {
 802     tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2);
 803 }
 804
 805 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 806 {
 807     tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
 808 }
 809
 810 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 811 {
 812     tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2);
 813 }
 814
 815 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 816 {
 817     tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
 818 }
 819
 820 static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
 821                                       int label_index)
 822 {
 823     tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
 824                       TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
 825                       TCGV_HIGH(arg2), cond, label_index);
 826 }
 827
 828 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 829 {
 830     TCGv_i64 t0;
 831     TCGv_i32 t1;
 832
 833     t0 = tcg_temp_new_i64();
 834     t1 = tcg_temp_new_i32();
 835
 836     tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
 837                     TCGV_LOW(arg1), TCGV_LOW(arg2));
 838
 839     tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
 840     tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
 841     tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
 842     tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
 843
 844     tcg_gen_mov_i64(ret, t0);
 845     tcg_temp_free_i64(t0);
 846     tcg_temp_free_i32(t1);
 847 }
 848
 849 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 850 {
 851     tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2);
 852 }
 853
 854 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 855 {
 856     tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2);
 857 }
 858
 859 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 860 {
 861     tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2);
 862 }
 863
 864 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 865 {
 866     tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2);
 867 }
 868
 869 #else
 870
 871 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
 872 {
 873     if (!TCGV_EQUAL_I64(ret, arg))
 874         tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
 875 }
 876
 877 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
 878 {
 879     tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
 880 }
 881
 882 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
 883                                     tcg_target_long offset)
 884 {
 885     tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
 886 }
 887
 888 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
 889                                     tcg_target_long offset)
 890 {
 891     tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
 892 }
 893
 894 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
 895                                      tcg_target_long offset)
 896 {
 897     tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
 898 }
 899
 900 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
 901                                      tcg_target_long offset)
 902 {
 903     tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
 904 }
 905
 906 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
 907                                      tcg_target_long offset)
 908 {
 909     tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
 910 }
 911
 912 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
 913                                      tcg_target_long offset)
 914 {
 915     tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
 916 }
 917
 918 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
 919 {
 920     tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
 921 }
 922
 923 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
 924                                    tcg_target_long offset)
 925 {
 926     tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
 927 }
 928
 929 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
 930                                     tcg_target_long offset)
 931 {
 932     tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
 933 }
 934
 935 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
 936                                     tcg_target_long offset)
 937 {
 938     tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
 939 }
 940
 941 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
 942 {
 943     tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
 944 }
 945
 946 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 947 {
 948     tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
 949 }
 950
 951 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 952 {
 953     tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
 954 }
 955
 956 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 957 {
 958     if (TCGV_EQUAL_I64(arg1, arg2)) {
 959         tcg_gen_mov_i64(ret, arg1);
 960     } else {
 961         tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
 962     }
 963 }
 964
 965 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 966 {
 967     TCGv_i64 t0 = tcg_const_i64(arg2);
 968     tcg_gen_and_i64(ret, arg1, t0);
 969     tcg_temp_free_i64(t0);
 970 }
 971
 972 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 973 {
 974     if (TCGV_EQUAL_I64(arg1, arg2)) {
 975         tcg_gen_mov_i64(ret, arg1);
 976     } else {
 977         tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
 978     }
 979 }
 980
 981 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 982 {
 983     TCGv_i64 t0 = tcg_const_i64(arg2);
 984     tcg_gen_or_i64(ret, arg1, t0);
 985     tcg_temp_free_i64(t0);
 986 }
 987
 988 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 989 {
 990     if (TCGV_EQUAL_I64(arg1, arg2)) {
 991         tcg_gen_movi_i64(ret, 0);
 992     } else {
 993         tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
 994     }
 995 }
 996
 997 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 998 {
 999     TCGv_i64 t0 = tcg_const_i64(arg2);
1000     tcg_gen_xor_i64(ret, arg1, t0);
1001     tcg_temp_free_i64(t0);
1002 }
1003
1004 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1005 {
1006     tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1007 }
1008
1009 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1010 {
1011     if (arg2 == 0) {
1012         tcg_gen_mov_i64(ret, arg1);
1013     } else {
1014         TCGv_i64 t0 = tcg_const_i64(arg2);
1015         tcg_gen_shl_i64(ret, arg1, t0);
1016         tcg_temp_free_i64(t0);
1017     }
1018 }
1019
1020 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1021 {
1022     tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1023 }
1024
1025 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1026 {
1027     if (arg2 == 0) {
1028         tcg_gen_mov_i64(ret, arg1);
1029     } else {
1030         TCGv_i64 t0 = tcg_const_i64(arg2);
1031         tcg_gen_shr_i64(ret, arg1, t0);
1032         tcg_temp_free_i64(t0);
1033     }
1034 }
1035
1036 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1037 {
1038     tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1039 }
1040
1041 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1042 {
1043     if (arg2 == 0) {
1044         tcg_gen_mov_i64(ret, arg1);
1045     } else {
1046         TCGv_i64 t0 = tcg_const_i64(arg2);
1047         tcg_gen_sar_i64(ret, arg1, t0);
1048         tcg_temp_free_i64(t0);
1049     }
1050 }
1051
1052 static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
1053                                       int label_index)
1054 {
1055     tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1056 }
1057
1058 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1059 {
1060     tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1061 }
1062
1063 #ifdef TCG_TARGET_HAS_div_i64
1064 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1065 {
1066     tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1067 }
1068
1069 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1070 {
1071     tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1072 }
1073
1074 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1075 {
1076     tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1077 }
1078
1079 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1080 {
1081     tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1082 }
1083 #else
1084 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1085 {
1086     TCGv_i64 t0;
1087     t0 = tcg_temp_new_i64();
1088     tcg_gen_sari_i64(t0, arg1, 63);
1089     tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1090     tcg_temp_free_i64(t0);
1091 }
1092
1093 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1094 {
1095     TCGv_i64 t0;
1096     t0 = tcg_temp_new_i64();
1097     tcg_gen_sari_i64(t0, arg1, 63);
1098     tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1099     tcg_temp_free_i64(t0);
1100 }
1101
1102 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1103 {
1104     TCGv_i64 t0;
1105     t0 = tcg_temp_new_i64();
1106     tcg_gen_movi_i64(t0, 0);
1107     tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1108     tcg_temp_free_i64(t0);
1109 }
1110
1111 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1112 {
1113     TCGv_i64 t0;
1114     t0 = tcg_temp_new_i64();
1115     tcg_gen_movi_i64(t0, 0);
1116     tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1117     tcg_temp_free_i64(t0);
1118 }
1119 #endif
1120
1121 #endif
1122
1123 static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1124 {
1125     /* some cases can be optimized here */
1126     if (arg2 == 0) {
1127         tcg_gen_mov_i64(ret, arg1);
1128     } else {
1129         TCGv_i64 t0 = tcg_const_i64(arg2);
1130         tcg_gen_add_i64(ret, arg1, t0);
1131         tcg_temp_free_i64(t0);
1132     }
1133 }
1134
1135 static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1136 {
1137     TCGv_i64 t0 = tcg_const_i64(arg1);
1138     tcg_gen_sub_i64(ret, t0, arg2);
1139     tcg_temp_free_i64(t0);
1140 }
1141
1142 static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1143 {
1144     /* some cases can be optimized here */
1145     if (arg2 == 0) {
1146         tcg_gen_mov_i64(ret, arg1);
1147     } else {
1148         TCGv_i64 t0 = tcg_const_i64(arg2);
1149         tcg_gen_sub_i64(ret, arg1, t0);
1150         tcg_temp_free_i64(t0);
1151     }
1152 }
1153 static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
1154                                        int label_index)
1155 {
1156     TCGv_i64 t0 = tcg_const_i64(arg2);
1157     tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1158     tcg_temp_free_i64(t0);
1159 }
1160
1161 static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1162 {
1163     TCGv_i64 t0 = tcg_const_i64(arg2);
1164     tcg_gen_mul_i64(ret, arg1, t0);
1165     tcg_temp_free_i64(t0);
1166 }
1167
1168
1169 /***************************************/
1170 /* optional operations */
1171
1172 static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1173 {
1174 #ifdef TCG_TARGET_HAS_ext8s_i32
1175     tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1176 #else
1177     tcg_gen_shli_i32(ret, arg, 24);
1178     tcg_gen_sari_i32(ret, ret, 24);
1179 #endif
1180 }
1181
1182 static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1183 {
1184 #ifdef TCG_TARGET_HAS_ext16s_i32
1185     tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1186 #else
1187     tcg_gen_shli_i32(ret, arg, 16);
1188     tcg_gen_sari_i32(ret, ret, 16);
1189 #endif
1190 }
1191
1192 /* These are currently just for convenience.
1193    We assume a target will recognise these automatically .  */
1194 static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1195 {
1196     tcg_gen_andi_i32(ret, arg, 0xffu);
1197 }
1198
1199 static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1200 {
1201     tcg_gen_andi_i32(ret, arg, 0xffffu);
1202 }
1203
1204 /* Note: we assume the two high bytes are set to zero */
1205 static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1206 {
1207 #ifdef TCG_TARGET_HAS_bswap16_i32
1208     tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1209 #else
1210     TCGv_i32 t0 = tcg_temp_new_i32();
1211
1212     tcg_gen_ext8u_i32(t0, arg);
1213     tcg_gen_shli_i32(t0, t0, 8);
1214     tcg_gen_shri_i32(ret, arg, 8);
1215     tcg_gen_or_i32(ret, ret, t0);
1216     tcg_temp_free_i32(t0);
1217 #endif
1218 }
1219
1220 static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1221 {
1222 #ifdef TCG_TARGET_HAS_bswap32_i32
1223     tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1224 #else
1225     TCGv_i32 t0, t1;
1226     t0 = tcg_temp_new_i32();
1227     t1 = tcg_temp_new_i32();
1228
1229     tcg_gen_shli_i32(t0, arg, 24);
1230
1231     tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1232     tcg_gen_shli_i32(t1, t1, 8);
1233     tcg_gen_or_i32(t0, t0, t1);
1234
1235     tcg_gen_shri_i32(t1, arg, 8);
1236     tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1237     tcg_gen_or_i32(t0, t0, t1);
1238
1239     tcg_gen_shri_i32(t1, arg, 24);
1240     tcg_gen_or_i32(ret, t0, t1);
1241     tcg_temp_free_i32(t0);
1242     tcg_temp_free_i32(t1);
1243 #endif
1244 }
1245
1246 #if TCG_TARGET_REG_BITS == 32
1247 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1248 {
1249     tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1250     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1251 }
1252
1253 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1254 {
1255     tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1256     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1257 }
1258
1259 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1260 {
1261     tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1262     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1263 }
1264
1265 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1266 {
1267     tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1268     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1269 }
1270
1271 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1272 {
1273     tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1274     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1275 }
1276
1277 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1278 {
1279     tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1280     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1281 }
1282
1283 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1284 {
1285     tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1286 }
1287
1288 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1289 {
1290     tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1291     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1292 }
1293
1294 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1295 {
1296     tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1297     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1298 }
1299
1300 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1301 {
1302     TCGv_i32 t0, t1;
1303     t0 = tcg_temp_new_i32();
1304     t1 = tcg_temp_new_i32();
1305
1306     tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1307     tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1308     tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1309     tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1310     tcg_temp_free_i32(t0);
1311     tcg_temp_free_i32(t1);
1312 }
1313 #else
1314
1315 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1316 {
1317 #ifdef TCG_TARGET_HAS_ext8s_i64
1318     tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1319 #else
1320     tcg_gen_shli_i64(ret, arg, 56);
1321     tcg_gen_sari_i64(ret, ret, 56);
1322 #endif
1323 }
1324
1325 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1326 {
1327 #ifdef TCG_TARGET_HAS_ext16s_i64
1328     tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1329 #else
1330     tcg_gen_shli_i64(ret, arg, 48);
1331     tcg_gen_sari_i64(ret, ret, 48);
1332 #endif
1333 }
1334
1335 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1336 {
1337 #ifdef TCG_TARGET_HAS_ext32s_i64
1338     tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1339 #else
1340     tcg_gen_shli_i64(ret, arg, 32);
1341     tcg_gen_sari_i64(ret, ret, 32);
1342 #endif
1343 }
1344
1345 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1346 {
1347     tcg_gen_andi_i64(ret, arg, 0xffu);
1348 }
1349
1350 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1351 {
1352     tcg_gen_andi_i64(ret, arg, 0xffffu);
1353 }
1354
1355 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1356 {
1357     tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1358 }
1359
1360 /* Note: we assume the target supports move between 32 and 64 bit
1361    registers.  This will probably break MIPS64 targets.  */
1362 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1363 {
1364     tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1365 }
1366
1367 /* Note: we assume the target supports move between 32 and 64 bit
1368    registers */
1369 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1370 {
1371     tcg_gen_andi_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)), 0xffffffffu);
1372 }
1373
1374 /* Note: we assume the target supports move between 32 and 64 bit
1375    registers */
1376 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1377 {
1378     tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1379 }
1380
1381 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1382 {
1383 #ifdef TCG_TARGET_HAS_bswap64_i64
1384     tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1385 #else
1386     TCGv_i32 t0, t1;
1387     t0 = tcg_temp_new_i32();
1388     t1 = tcg_temp_new_i32();
1389
1390     tcg_gen_shli_i64(t0, arg, 56);
1391
1392     tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1393     tcg_gen_shli_i64(t1, t1, 40);
1394     tcg_gen_or_i64(t0, t0, t1);
1395
1396     tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1397     tcg_gen_shli_i64(t1, t1, 24);
1398     tcg_gen_or_i64(t0, t0, t1);
1399
1400     tcg_gen_andi_i64(t1, arg, 0xff000000);
1401     tcg_gen_shli_i64(t1, t1, 8);
1402     tcg_gen_or_i64(t0, t0, t1);
1403
1404     tcg_gen_shri_i64(t1, arg, 8);
1405     tcg_gen_andi_i64(t1, t1, 0xff000000);
1406     tcg_gen_or_i64(t0, t0, t1);
1407
1408     tcg_gen_shri_i64(t1, arg, 24);
1409     tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1410     tcg_gen_or_i64(t0, t0, t1);
1411
1412     tcg_gen_shri_i64(t1, arg, 40);
1413     tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1414     tcg_gen_or_i64(t0, t0, t1);
1415
1416     tcg_gen_shri_i64(t1, arg, 56);
1417     tcg_gen_or_i64(ret, t0, t1);
1418     tcg_temp_free_i32(t0);
1419     tcg_temp_free_i32(t1);
1420 #endif
1421 }
1422
1423 #endif
1424
1425 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1426 {
1427 #ifdef TCG_TARGET_HAS_neg_i32
1428     tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1429 #else
1430     TCGv_i32 t0 = tcg_const_i32(0);
1431     tcg_gen_sub_i32(ret, t0, arg);
1432     tcg_temp_free_i32(t0);
1433 #endif
1434 }
1435
1436 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1437 {
1438 #ifdef TCG_TARGET_HAS_neg_i64
1439     tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1440 #else
1441     TCGv_i64 t0 = tcg_const_i64(0);
1442     tcg_gen_sub_i64(ret, t0, arg);
1443     tcg_temp_free_i64(t0);
1444 #endif
1445 }
1446
1447 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1448 {
1449 #ifdef TCG_TARGET_HAS_not_i32
1450     tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1451 #else
1452     tcg_gen_xori_i32(ret, arg, -1);
1453 #endif
1454 }
1455
1456 static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1457 {
1458 #ifdef TCG_TARGET_HAS_not_i64
1459     tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1460 #else
1461     tcg_gen_xori_i64(ret, arg, -1);
1462 #endif
1463 }
1464
1465 static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1466 {
1467     tcg_gen_op1_i32(INDEX_op_discard, arg);
1468 }
1469
1470 #if TCG_TARGET_REG_BITS == 32
1471 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1472 {
1473     tcg_gen_discard_i32(TCGV_LOW(arg));
1474     tcg_gen_discard_i32(TCGV_HIGH(arg));
1475 }
1476 #else
1477 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1478 {
1479     tcg_gen_op1_i64(INDEX_op_discard, arg);
1480 }
1481 #endif
1482
1483 static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1484 {
1485 #if TCG_TARGET_REG_BITS == 32
1486     tcg_gen_mov_i32(TCGV_LOW(dest), low);
1487     tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1488 #else
1489     TCGv_i64 tmp = tcg_temp_new_i64();
1490     /* This extension is only needed for type correctness.
1491        We may be able to do better given target specific information.  */
1492     tcg_gen_extu_i32_i64(tmp, high);
1493     tcg_gen_shli_i64(tmp, tmp, 32);
1494     tcg_gen_extu_i32_i64(dest, low);
1495     tcg_gen_or_i64(dest, dest, tmp);
1496     tcg_temp_free_i64(tmp);
1497 #endif
1498 }
1499
1500 static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1501 {
1502 #if TCG_TARGET_REG_BITS == 32
1503     tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1504 #else
1505     TCGv_i64 tmp = tcg_temp_new_i64();
1506     tcg_gen_ext32u_i64(dest, low);
1507     tcg_gen_shli_i64(tmp, high, 32);
1508     tcg_gen_or_i64(dest, dest, tmp);
1509     tcg_temp_free_i64(tmp);
1510 #endif
1511 }
1512
1513 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1514 {
1515     TCGv_i32 t0;
1516     t0 = tcg_temp_new_i32();
1517     tcg_gen_not_i32(t0, arg2);
1518     tcg_gen_and_i32(ret, arg1, t0);
1519     tcg_temp_free_i32(t0);
1520 }
1521
1522 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1523 {
1524     TCGv_i64 t0;
1525     t0 = tcg_temp_new_i64();
1526     tcg_gen_not_i64(t0, arg2);
1527     tcg_gen_and_i64(ret, arg1, t0);
1528     tcg_temp_free_i64(t0);
1529 }
1530
1531 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1532 {
1533     tcg_gen_xor_i32(ret, arg1, arg2);
1534     tcg_gen_not_i32(ret, ret);
1535 }
1536
1537 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1538 {
1539     tcg_gen_xor_i64(ret, arg1, arg2);
1540     tcg_gen_not_i64(ret, ret);
1541 }
1542
1543 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1544 {
1545     tcg_gen_and_i32(ret, arg1, arg2);
1546     tcg_gen_not_i32(ret, ret);
1547 }
1548
1549 static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1550 {
1551     tcg_gen_and_i64(ret, arg1, arg2);
1552     tcg_gen_not_i64(ret, ret);
1553 }
1554
1555 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1556 {
1557     tcg_gen_or_i32(ret, arg1, arg2);
1558     tcg_gen_not_i32(ret, ret);
1559 }
1560
1561 static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1562 {
1563     tcg_gen_or_i64(ret, arg1, arg2);
1564     tcg_gen_not_i64(ret, ret);
1565 }
1566
1567 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1568 {
1569     TCGv_i32 t0;
1570     t0 = tcg_temp_new_i32();
1571     tcg_gen_not_i32(t0, arg2);
1572     tcg_gen_or_i32(ret, arg1, t0);
1573     tcg_temp_free_i32(t0);
1574 }
1575
1576 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1577 {
1578     TCGv_i64 t0;
1579     t0 = tcg_temp_new_i64();
1580     tcg_gen_not_i64(t0, arg2);
1581     tcg_gen_or_i64(ret, arg1, t0);
1582     tcg_temp_free_i64(t0);
1583 }
1584
1585 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1586 {
1587 #ifdef TCG_TARGET_HAS_rot_i32
1588     tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1589 #else
1590     TCGv_i32 t0, t1;
1591
1592     t0 = tcg_temp_new_i32();
1593     t1 = tcg_temp_new_i32();
1594     tcg_gen_shl_i32(t0, arg1, arg2);
1595     tcg_gen_subfi_i32(t1, 32, arg2);
1596     tcg_gen_shr_i32(t1, arg1, t1);
1597     tcg_gen_or_i32(ret, t0, t1);
1598     tcg_temp_free_i32(t0);
1599     tcg_temp_free_i32(t1);
1600 #endif
1601 }
1602
1603 static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1604 {
1605 #ifdef TCG_TARGET_HAS_rot_i64
1606     tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1607 #else
1608     TCGv_i64 t0, t1;
1609
1610     t0 = tcg_temp_new_i64();
1611     t1 = tcg_temp_new_i64();
1612     tcg_gen_shl_i64(t0, arg1, arg2);
1613     tcg_gen_subfi_i64(t1, 64, arg2);
1614     tcg_gen_shr_i64(t1, arg1, t1);
1615     tcg_gen_or_i64(ret, t0, t1);
1616     tcg_temp_free_i64(t0);
1617     tcg_temp_free_i64(t1);
1618 #endif
1619 }
1620
1621 static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1622 {
1623     /* some cases can be optimized here */
1624     if (arg2 == 0) {
1625         tcg_gen_mov_i32(ret, arg1);
1626     } else {
1627 #ifdef TCG_TARGET_HAS_rot_i32
1628         TCGv_i32 t0 = tcg_const_i32(arg2);
1629         tcg_gen_rotl_i32(ret, arg1, t0);
1630         tcg_temp_free_i32(t0);
1631 #else
1632         TCGv_i32 t0, t1;
1633         t0 = tcg_temp_new_i32();
1634         t1 = tcg_temp_new_i32();
1635         tcg_gen_shli_i32(t0, arg1, arg2);
1636         tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1637         tcg_gen_or_i32(ret, t0, t1);
1638         tcg_temp_free_i32(t0);
1639         tcg_temp_free_i32(t1);
1640 #endif
1641     }
1642 }
1643
1644 static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1645 {
1646     /* some cases can be optimized here */
1647     if (arg2 == 0) {
1648         tcg_gen_mov_i64(ret, arg1);
1649     } else {
1650 #ifdef TCG_TARGET_HAS_rot_i64
1651         TCGv_i64 t0 = tcg_const_i64(arg2);
1652         tcg_gen_rotl_i64(ret, arg1, t0);
1653         tcg_temp_free_i64(t0);
1654 #else
1655         TCGv_i64 t0, t1;
1656         t0 = tcg_temp_new_i64();
1657         t1 = tcg_temp_new_i64();
1658         tcg_gen_shli_i64(t0, arg1, arg2);
1659         tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1660         tcg_gen_or_i64(ret, t0, t1);
1661         tcg_temp_free_i64(t0);
1662         tcg_temp_free_i64(t1);
1663 #endif
1664     }
1665 }
1666
1667 static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1668 {
1669 #ifdef TCG_TARGET_HAS_rot_i32
1670     tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
1671 #else
1672     TCGv_i32 t0, t1;
1673
1674     t0 = tcg_temp_new_i32();
1675     t1 = tcg_temp_new_i32();
1676     tcg_gen_shr_i32(t0, arg1, arg2);
1677     tcg_gen_subfi_i32(t1, 32, arg2);
1678     tcg_gen_shl_i32(t1, arg1, t1);
1679     tcg_gen_or_i32(ret, t0, t1);
1680     tcg_temp_free_i32(t0);
1681     tcg_temp_free_i32(t1);
1682 #endif
1683 }
1684
1685 static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1686 {
1687 #ifdef TCG_TARGET_HAS_rot_i64
1688     tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
1689 #else
1690     TCGv_i64 t0, t1;
1691
1692     t0 = tcg_temp_new_i64();
1693     t1 = tcg_temp_new_i64();
1694     tcg_gen_shl_i64(t0, arg1, arg2);
1695     tcg_gen_subfi_i64(t1, 64, arg2);
1696     tcg_gen_shl_i64(t1, arg1, t1);
1697     tcg_gen_or_i64(ret, t0, t1);
1698     tcg_temp_free_i64(t0);
1699     tcg_temp_free_i64(t1);
1700 #endif
1701 }
1702
1703 static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1704 {
1705     /* some cases can be optimized here */
1706     if (arg2 == 0) {
1707         tcg_gen_mov_i32(ret, arg1);
1708     } else {
1709         tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
1710     }
1711 }
1712
1713 static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1714 {
1715     /* some cases can be optimized here */
1716     if (arg2 == 0) {
1717         tcg_gen_mov_i64(ret, arg1);
1718     } else {
1719         tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
1720     }
1721 }
1722
1723 /***************************************/
1724 /* QEMU specific operations. Their type depend on the QEMU CPU
1725    type. */
1726 #ifndef TARGET_LONG_BITS
1727 #error must include QEMU headers
1728 #endif
1729
1730 #if TARGET_LONG_BITS == 32
1731 #define TCGv TCGv_i32
1732 #define tcg_temp_new() tcg_temp_new_i32()
1733 #define tcg_global_reg_new tcg_global_reg_new_i32
1734 #define tcg_global_mem_new tcg_global_mem_new_i32
1735 #define tcg_temp_local_new() tcg_temp_local_new_i32()
1736 #define tcg_temp_free tcg_temp_free_i32
1737 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
1738 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
1739 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1740 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
1741 #else
1742 #define TCGv TCGv_i64
1743 #define tcg_temp_new() tcg_temp_new_i64()
1744 #define tcg_global_reg_new tcg_global_reg_new_i64
1745 #define tcg_global_mem_new tcg_global_mem_new_i64
1746 #define tcg_temp_local_new() tcg_temp_local_new_i64()
1747 #define tcg_temp_free tcg_temp_free_i64
1748 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
1749 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
1750 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1751 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
1752 #endif
1753
1754 /* debug info: write the PC of the corresponding QEMU CPU instruction */
1755 static inline void tcg_gen_debug_insn_start(uint64_t pc)
1756 {
1757     /* XXX: must really use a 32 bit size for TCGArg in all cases */
1758 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1759     tcg_gen_op2ii(INDEX_op_debug_insn_start,
1760                   (uint32_t)(pc), (uint32_t)(pc >> 32));
1761 #else
1762     tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1763 #endif
1764 }
1765
1766 static inline void tcg_gen_exit_tb(tcg_target_long val)
1767 {
1768     tcg_gen_op1i(INDEX_op_exit_tb, val);
1769 }
1770
1771 static inline void tcg_gen_goto_tb(int idx)
1772 {
1773     tcg_gen_op1i(INDEX_op_goto_tb, idx);
1774 }
1775
1776 #if TCG_TARGET_REG_BITS == 32
1777 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1778 {
1779 #if TARGET_LONG_BITS == 32
1780     tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1781 #else
1782     tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
1783                      TCGV_HIGH(addr), mem_index);
1784     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1785 #endif
1786 }
1787
1788 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1789 {
1790 #if TARGET_LONG_BITS == 32
1791     tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1792 #else
1793     tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
1794                      TCGV_HIGH(addr), mem_index);
1795     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1796 #endif
1797 }
1798
1799 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1800 {
1801 #if TARGET_LONG_BITS == 32
1802     tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1803 #else
1804     tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
1805                      TCGV_HIGH(addr), mem_index);
1806     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1807 #endif
1808 }
1809
1810 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1811 {
1812 #if TARGET_LONG_BITS == 32
1813     tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1814 #else
1815     tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
1816                      TCGV_HIGH(addr), mem_index);
1817     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1818 #endif
1819 }
1820
1821 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1822 {
1823 #if TARGET_LONG_BITS == 32
1824     tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1825 #else
1826     tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1827                      TCGV_HIGH(addr), mem_index);
1828     tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1829 #endif
1830 }
1831
1832 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1833 {
1834 #if TARGET_LONG_BITS == 32
1835     tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1836 #else
1837     tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1838                      TCGV_HIGH(addr), mem_index);
1839     tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1840 #endif
1841 }
1842
1843 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1844 {
1845 #if TARGET_LONG_BITS == 32
1846     tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
1847 #else
1848     tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
1849                      TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1850 #endif
1851 }
1852
1853 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1854 {
1855 #if TARGET_LONG_BITS == 32
1856     tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
1857 #else
1858     tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
1859                      TCGV_HIGH(addr), mem_index);
1860 #endif
1861 }
1862
1863 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1864 {
1865 #if TARGET_LONG_BITS == 32
1866     tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
1867 #else
1868     tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
1869                      TCGV_HIGH(addr), mem_index);
1870 #endif
1871 }
1872
1873 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1874 {
1875 #if TARGET_LONG_BITS == 32
1876     tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
1877 #else
1878     tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
1879                      TCGV_HIGH(addr), mem_index);
1880 #endif
1881 }
1882
1883 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1884 {
1885 #if TARGET_LONG_BITS == 32
1886     tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
1887                      mem_index);
1888 #else
1889     tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
1890                      TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1891 #endif
1892 }
1893
1894 #define tcg_gen_ld_ptr tcg_gen_ld_i32
1895 #define tcg_gen_discard_ptr tcg_gen_discard_i32
1896
1897 #else /* TCG_TARGET_REG_BITS == 32 */
1898
1899 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1900 {
1901     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1902 }
1903
1904 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1905 {
1906     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1907 }
1908
1909 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1910 {
1911     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1912 }
1913
1914 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1915 {
1916     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1917 }
1918
1919 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1920 {
1921     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1922 }
1923
1924 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1925 {
1926     tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1927 }
1928
1929 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1930 {
1931     tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
1932 }
1933
1934 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1935 {
1936     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
1937 }
1938
1939 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1940 {
1941     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
1942 }
1943
1944 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1945 {
1946     tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
1947 }
1948
1949 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1950 {
1951     tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
1952 }
1953
1954 #define tcg_gen_ld_ptr tcg_gen_ld_i64
1955 #define tcg_gen_discard_ptr tcg_gen_discard_i64
1956
1957 #endif /* TCG_TARGET_REG_BITS != 32 */
1958
1959 #if TARGET_LONG_BITS == 64
1960 #define TCG_TYPE_TL TCG_TYPE_I64
1961 #define tcg_gen_movi_tl tcg_gen_movi_i64
1962 #define tcg_gen_mov_tl tcg_gen_mov_i64
1963 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1964 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1965 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1966 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1967 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1968 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1969 #define tcg_gen_ld_tl tcg_gen_ld_i64
1970 #define tcg_gen_st8_tl tcg_gen_st8_i64
1971 #define tcg_gen_st16_tl tcg_gen_st16_i64
1972 #define tcg_gen_st32_tl tcg_gen_st32_i64
1973 #define tcg_gen_st_tl tcg_gen_st_i64
1974 #define tcg_gen_add_tl tcg_gen_add_i64
1975 #define tcg_gen_addi_tl tcg_gen_addi_i64
1976 #define tcg_gen_sub_tl tcg_gen_sub_i64
1977 #define tcg_gen_neg_tl tcg_gen_neg_i64
1978 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
1979 #define tcg_gen_subi_tl tcg_gen_subi_i64
1980 #define tcg_gen_and_tl tcg_gen_and_i64
1981 #define tcg_gen_andi_tl tcg_gen_andi_i64
1982 #define tcg_gen_or_tl tcg_gen_or_i64
1983 #define tcg_gen_ori_tl tcg_gen_ori_i64
1984 #define tcg_gen_xor_tl tcg_gen_xor_i64
1985 #define tcg_gen_xori_tl tcg_gen_xori_i64
1986 #define tcg_gen_not_tl tcg_gen_not_i64
1987 #define tcg_gen_shl_tl tcg_gen_shl_i64
1988 #define tcg_gen_shli_tl tcg_gen_shli_i64
1989 #define tcg_gen_shr_tl tcg_gen_shr_i64
1990 #define tcg_gen_shri_tl tcg_gen_shri_i64
1991 #define tcg_gen_sar_tl tcg_gen_sar_i64
1992 #define tcg_gen_sari_tl tcg_gen_sari_i64
1993 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
1994 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
1995 #define tcg_gen_mul_tl tcg_gen_mul_i64
1996 #define tcg_gen_muli_tl tcg_gen_muli_i64
1997 #define tcg_gen_discard_tl tcg_gen_discard_i64
1998 #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
1999 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2000 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2001 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2002 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2003 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2004 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2005 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2006 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2007 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2008 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2009 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2010 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2011 #define tcg_gen_andc_tl tcg_gen_andc_i64
2012 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
2013 #define tcg_gen_nand_tl tcg_gen_nand_i64
2014 #define tcg_gen_nor_tl tcg_gen_nor_i64
2015 #define tcg_gen_orc_tl tcg_gen_orc_i64
2016 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
2017 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
2018 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
2019 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
2020 #define tcg_const_tl tcg_const_i64
2021 #define tcg_const_local_tl tcg_const_local_i64
2022 #else
2023 #define TCG_TYPE_TL TCG_TYPE_I32
2024 #define tcg_gen_movi_tl tcg_gen_movi_i32
2025 #define tcg_gen_mov_tl tcg_gen_mov_i32
2026 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2027 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2028 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2029 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2030 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
2031 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
2032 #define tcg_gen_ld_tl tcg_gen_ld_i32
2033 #define tcg_gen_st8_tl tcg_gen_st8_i32
2034 #define tcg_gen_st16_tl tcg_gen_st16_i32
2035 #define tcg_gen_st32_tl tcg_gen_st_i32
2036 #define tcg_gen_st_tl tcg_gen_st_i32
2037 #define tcg_gen_add_tl tcg_gen_add_i32
2038 #define tcg_gen_addi_tl tcg_gen_addi_i32
2039 #define tcg_gen_sub_tl tcg_gen_sub_i32
2040 #define tcg_gen_neg_tl tcg_gen_neg_i32
2041 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2042 #define tcg_gen_subi_tl tcg_gen_subi_i32
2043 #define tcg_gen_and_tl tcg_gen_and_i32
2044 #define tcg_gen_andi_tl tcg_gen_andi_i32
2045 #define tcg_gen_or_tl tcg_gen_or_i32
2046 #define tcg_gen_ori_tl tcg_gen_ori_i32
2047 #define tcg_gen_xor_tl tcg_gen_xor_i32
2048 #define tcg_gen_xori_tl tcg_gen_xori_i32
2049 #define tcg_gen_not_tl tcg_gen_not_i32
2050 #define tcg_gen_shl_tl tcg_gen_shl_i32
2051 #define tcg_gen_shli_tl tcg_gen_shli_i32
2052 #define tcg_gen_shr_tl tcg_gen_shr_i32
2053 #define tcg_gen_shri_tl tcg_gen_shri_i32
2054 #define tcg_gen_sar_tl tcg_gen_sar_i32
2055 #define tcg_gen_sari_tl tcg_gen_sari_i32
2056 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2057 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2058 #define tcg_gen_mul_tl tcg_gen_mul_i32
2059 #define tcg_gen_muli_tl tcg_gen_muli_i32
2060 #define tcg_gen_discard_tl tcg_gen_discard_i32
2061 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2062 #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2063 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2064 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2065 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2066 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2067 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2068 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2069 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2070 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2071 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2072 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
2073 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2074 #define tcg_gen_andc_tl tcg_gen_andc_i32
2075 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2076 #define tcg_gen_nand_tl tcg_gen_nand_i32
2077 #define tcg_gen_nor_tl tcg_gen_nor_i32
2078 #define tcg_gen_orc_tl tcg_gen_orc_i32
2079 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2080 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2081 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2082 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
2083 #define tcg_const_tl tcg_const_i32
2084 #define tcg_const_local_tl tcg_const_local_i32
2085 #endif
2086
2087 #if TCG_TARGET_REG_BITS == 32
2088 #define tcg_gen_add_ptr tcg_gen_add_i32
2089 #define tcg_gen_addi_ptr tcg_gen_addi_i32
2090 #define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2091 #else /* TCG_TARGET_REG_BITS == 32 */
2092 #define tcg_gen_add_ptr tcg_gen_add_i64
2093 #define tcg_gen_addi_ptr tcg_gen_addi_i64
2094 #define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2095 #endif /* TCG_TARGET_REG_BITS != 32 */