tcg/tcg-opc.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #ifndef DEF2
  25 #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0)
  26 #endif
  27
  28 /* predefined ops */
  29 DEF2(end, 0, 0, 0, 0) /* must be kept first */
  30 DEF2(nop, 0, 0, 0, 0)
  31 DEF2(nop1, 0, 0, 1, 0)
  32 DEF2(nop2, 0, 0, 2, 0)
  33 DEF2(nop3, 0, 0, 3, 0)
  34 DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */
  35
  36 DEF2(discard, 1, 0, 0, 0)
  37
  38 DEF2(set_label, 0, 0, 1, 0)
  39 DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
  40 DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
  41 DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
  42
  43 DEF2(mov_i32, 1, 1, 0, 0)
  44 DEF2(movi_i32, 1, 0, 1, 0)
  45 /* load/store */
  46 DEF2(ld8u_i32, 1, 1, 1, 0)
  47 DEF2(ld8s_i32, 1, 1, 1, 0)
  48 DEF2(ld16u_i32, 1, 1, 1, 0)
  49 DEF2(ld16s_i32, 1, 1, 1, 0)
  50 DEF2(ld_i32, 1, 1, 1, 0)
  51 DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
  52 DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
  53 DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
  54 /* arith */
  55 DEF2(add_i32, 1, 2, 0, 0)
  56 DEF2(sub_i32, 1, 2, 0, 0)
  57 DEF2(mul_i32, 1, 2, 0, 0)
  58 #ifdef TCG_TARGET_HAS_div_i32
  59 DEF2(div_i32, 1, 2, 0, 0)
  60 DEF2(divu_i32, 1, 2, 0, 0)
  61 DEF2(rem_i32, 1, 2, 0, 0)
  62 DEF2(remu_i32, 1, 2, 0, 0)
  63 #else
  64 DEF2(div2_i32, 2, 3, 0, 0)
  65 DEF2(divu2_i32, 2, 3, 0, 0)
  66 #endif
  67 DEF2(and_i32, 1, 2, 0, 0)
  68 DEF2(or_i32, 1, 2, 0, 0)
  69 DEF2(xor_i32, 1, 2, 0, 0)
  70 /* shifts/rotates */
  71 DEF2(shl_i32, 1, 2, 0, 0)
  72 DEF2(shr_i32, 1, 2, 0, 0)
  73 DEF2(sar_i32, 1, 2, 0, 0)
  74 DEF2(rotl_i32, 1, 2, 0, 0)
  75 DEF2(rotr_i32, 1, 2, 0, 0)
  76
  77 DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
  78 #if TCG_TARGET_REG_BITS == 32
  79 DEF2(add2_i32, 2, 4, 0, 0)
  80 DEF2(sub2_i32, 2, 4, 0, 0)
  81 DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
  82 DEF2(mulu2_i32, 2, 2, 0, 0)
  83 #endif
  84 #ifdef TCG_TARGET_HAS_ext8s_i32
  85 DEF2(ext8s_i32, 1, 1, 0, 0)
  86 #endif
  87 #ifdef TCG_TARGET_HAS_ext16s_i32
  88 DEF2(ext16s_i32, 1, 1, 0, 0)
  89 #endif
  90 #ifdef TCG_TARGET_HAS_bswap_i32
  91 DEF2(bswap_i32, 1, 1, 0, 0)
  92 #endif
  93
  94 #if TCG_TARGET_REG_BITS == 64
  95 DEF2(mov_i64, 1, 1, 0, 0)
  96 DEF2(movi_i64, 1, 0, 1, 0)
  97 /* load/store */
  98 DEF2(ld8u_i64, 1, 1, 1, 0)
  99 DEF2(ld8s_i64, 1, 1, 1, 0)
 100 DEF2(ld16u_i64, 1, 1, 1, 0)
 101 DEF2(ld16s_i64, 1, 1, 1, 0)
 102 DEF2(ld32u_i64, 1, 1, 1, 0)
 103 DEF2(ld32s_i64, 1, 1, 1, 0)
 104 DEF2(ld_i64, 1, 1, 1, 0)
 105 DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
 106 DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
 107 DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
 108 DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
 109 /* arith */
 110 DEF2(add_i64, 1, 2, 0, 0)
 111 DEF2(sub_i64, 1, 2, 0, 0)
 112 DEF2(mul_i64, 1, 2, 0, 0)
 113 #ifdef TCG_TARGET_HAS_div_i64
 114 DEF2(div_i64, 1, 2, 0, 0)
 115 DEF2(divu_i64, 1, 2, 0, 0)
 116 DEF2(rem_i64, 1, 2, 0, 0)
 117 DEF2(remu_i64, 1, 2, 0, 0)
 118 #else
 119 DEF2(div2_i64, 2, 3, 0, 0)
 120 DEF2(divu2_i64, 2, 3, 0, 0)
 121 #endif
 122 DEF2(and_i64, 1, 2, 0, 0)
 123 DEF2(or_i64, 1, 2, 0, 0)
 124 DEF2(xor_i64, 1, 2, 0, 0)
 125 /* shifts/rotates */
 126 DEF2(shl_i64, 1, 2, 0, 0)
 127 DEF2(shr_i64, 1, 2, 0, 0)
 128 DEF2(sar_i64, 1, 2, 0, 0)
 129 DEF2(rotl_i64, 1, 2, 0, 0)
 130 DEF2(rotr_i64, 1, 2, 0, 0)
 131
 132 DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
 133 #ifdef TCG_TARGET_HAS_ext8s_i64
 134 DEF2(ext8s_i64, 1, 1, 0, 0)
 135 #endif
 136 #ifdef TCG_TARGET_HAS_ext16s_i64
 137 DEF2(ext16s_i64, 1, 1, 0, 0)
 138 #endif
 139 #ifdef TCG_TARGET_HAS_ext32s_i64
 140 DEF2(ext32s_i64, 1, 1, 0, 0)
 141 #endif
 142 #ifdef TCG_TARGET_HAS_bswap_i64
 143 DEF2(bswap_i64, 1, 1, 0, 0)
 144 #endif
 145 #endif
 146 #ifdef TCG_TARGET_HAS_neg_i32
 147 DEF2(neg_i32, 1, 1, 0, 0)
 148 #endif
 149 #ifdef TCG_TARGET_HAS_neg_i64
 150 DEF2(neg_i64, 1, 1, 0, 0)
 151 #endif
 152
 153 /* QEMU specific */
 154 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
 155 DEF2(debug_insn_start, 0, 0, 2, 0)
 156 #else
 157 DEF2(debug_insn_start, 0, 0, 1, 0)
 158 #endif
 159 DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
 160 DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
 161 /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
 162    constants must be defined */
 163 #if TCG_TARGET_REG_BITS == 32
 164 #if TARGET_LONG_BITS == 32
 165 DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 166 #else
 167 DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 168 #endif
 169 #if TARGET_LONG_BITS == 32
 170 DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 171 #else
 172 DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 173 #endif
 174 #if TARGET_LONG_BITS == 32
 175 DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 176 #else
 177 DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 178 #endif
 179 #if TARGET_LONG_BITS == 32
 180 DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 181 #else
 182 DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 183 #endif
 184 #if TARGET_LONG_BITS == 32
 185 DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 186 #else
 187 DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 188 #endif
 189 #if TARGET_LONG_BITS == 32
 190 DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 191 #else
 192 DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 193 #endif
 194 #if TARGET_LONG_BITS == 32
 195 DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 196 #else
 197 DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 198 #endif
 199
 200 #if TARGET_LONG_BITS == 32
 201 DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 202 #else
 203 DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 204 #endif
 205 #if TARGET_LONG_BITS == 32
 206 DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 207 #else
 208 DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 209 #endif
 210 #if TARGET_LONG_BITS == 32
 211 DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 212 #else
 213 DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 214 #endif
 215 #if TARGET_LONG_BITS == 32
 216 DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 217 #else
 218 DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 219 #endif
 220
 221 #else /* TCG_TARGET_REG_BITS == 32 */
 222
 223 DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 224 DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 225 DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 226 DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 227 DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 228 DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 229 DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 230
 231 DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 232 DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 233 DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 234 DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 235
 236 #endif /* TCG_TARGET_REG_BITS != 32 */
 237
 238 #undef DEF2