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tcg: optimize nor(X, Y, Y), used on PPC for not(X, Y)
[qemu/mini2440/sniper_sniper_test.git] / target-ppc / translate.c
blob0368c374309a79246dfd95e47c5c8dbc071106e5
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31 #include "host-utils.h"
32
33 #include "helper.h"
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 #define CPU_SINGLE_STEP 0x1
38 #define CPU_BRANCH_STEP 0x2
39 #define GDBSTUB_SINGLE_STEP 0x4
40
41 /* Include definitions for instructions classes and implementations flags */
42 //#define DO_SINGLE_STEP
43 //#define PPC_DEBUG_DISAS
44 //#define DO_PPC_STATISTICS
45
46 #ifdef PPC_DEBUG_DISAS
47 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 #else
49 # define LOG_DISAS(...) do { } while (0)
50 #endif
51 /*****************************************************************************/
52 /* Code translation helpers */
53
54 /* global register indexes */
55 static TCGv_ptr cpu_env;
56 static char cpu_reg_names[10*3 + 22*4 /* GPR */
57 #if !defined(TARGET_PPC64)
58 + 10*4 + 22*5 /* SPE GPRh */
59 #endif
60 + 10*4 + 22*5 /* FPR */
61 + 2*(10*6 + 22*7) /* AVRh, AVRl */
62 + 8*5 /* CRF */];
63 static TCGv cpu_gpr[32];
64 #if !defined(TARGET_PPC64)
65 static TCGv cpu_gprh[32];
66 #endif
67 static TCGv_i64 cpu_fpr[32];
68 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
69 static TCGv_i32 cpu_crf[8];
70 static TCGv cpu_nip;
71 static TCGv cpu_msr;
72 static TCGv cpu_ctr;
73 static TCGv cpu_lr;
74 static TCGv cpu_xer;
75 static TCGv cpu_reserve;
76 static TCGv_i32 cpu_fpscr;
77 static TCGv_i32 cpu_access_type;
78
79 #include "gen-icount.h"
80
81 void ppc_translate_init(void)
82 {
83 int i;
84 char* p;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91
92 p = cpu_reg_names;
93
94 for (i = 0; i < 8; i++) {
95 sprintf(p, "crf%d", i);
96 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97 offsetof(CPUState, crf[i]), p);
98 p += 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 sprintf(p, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 #if !defined(TARGET_PPC64)
107 sprintf(p, "r%dH", i);
108 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
109 offsetof(CPUState, gprh[i]), p);
110 p += (i < 10) ? 4 : 5;
111 #endif
112
113 sprintf(p, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117
118 sprintf(p, "avr%dH", i);
119 #ifdef WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127
128 sprintf(p, "avr%dL", i);
129 #ifdef WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr[i].u64[1]), p);
132 #else
133 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
134 offsetof(CPUState, avr[i].u64[0]), p);
135 #endif
136 p += (i < 10) ? 6 : 7;
137 }
138
139 cpu_nip = tcg_global_mem_new(TCG_AREG0,
140 offsetof(CPUState, nip), "nip");
141
142 cpu_msr = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUState, msr), "msr");
144
145 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUState, ctr), "ctr");
147
148 cpu_lr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUState, lr), "lr");
150
151 cpu_xer = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUState, xer), "xer");
153
154 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, reserve), "reserve");
156
157 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
158 offsetof(CPUState, fpscr), "fpscr");
159
160 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
161 offsetof(CPUState, access_type), "access_type");
162
163 /* register helpers */
164 #define GEN_HELPER 2
165 #include "helper.h"
166
167 done_init = 1;
168 }
169
170 /* internal defines */
171 typedef struct DisasContext {
172 struct TranslationBlock *tb;
173 target_ulong nip;
174 uint32_t opcode;
175 uint32_t exception;
176 /* Routine used to access memory */
177 int mem_idx;
178 int access_type;
179 /* Translation flags */
180 int le_mode;
181 #if defined(TARGET_PPC64)
182 int sf_mode;
183 #endif
184 int fpu_enabled;
185 int altivec_enabled;
186 int spe_enabled;
187 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
188 int singlestep_enabled;
189 } DisasContext;
190
191 struct opc_handler_t {
192 /* invalid bits */
193 uint32_t inval;
194 /* instruction type */
195 uint64_t type;
196 /* handler */
197 void (*handler)(DisasContext *ctx);
198 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
199 const char *oname;
200 #endif
201 #if defined(DO_PPC_STATISTICS)
202 uint64_t count;
203 #endif
204 };
205
206 static always_inline void gen_reset_fpstatus (void)
207 {
208 #ifdef CONFIG_SOFTFLOAT
209 gen_helper_reset_fpstatus();
210 #endif
211 }
212
213 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
214 {
215 TCGv_i32 t0 = tcg_temp_new_i32();
216
217 if (set_fprf != 0) {
218 /* This case might be optimized later */
219 tcg_gen_movi_i32(t0, 1);
220 gen_helper_compute_fprf(t0, arg, t0);
221 if (unlikely(set_rc)) {
222 tcg_gen_mov_i32(cpu_crf[1], t0);
223 }
224 gen_helper_float_check_status();
225 } else if (unlikely(set_rc)) {
226 /* We always need to compute fpcc */
227 tcg_gen_movi_i32(t0, 0);
228 gen_helper_compute_fprf(t0, arg, t0);
229 tcg_gen_mov_i32(cpu_crf[1], t0);
230 }
231
232 tcg_temp_free_i32(t0);
233 }
234
235 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
236 {
237 if (ctx->access_type != access_type) {
238 tcg_gen_movi_i32(cpu_access_type, access_type);
239 ctx->access_type = access_type;
240 }
241 }
242
243 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
244 {
245 #if defined(TARGET_PPC64)
246 if (ctx->sf_mode)
247 tcg_gen_movi_tl(cpu_nip, nip);
248 else
249 #endif
250 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
251 }
252
253 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
254 {
255 TCGv_i32 t0, t1;
256 if (ctx->exception == POWERPC_EXCP_NONE) {
257 gen_update_nip(ctx, ctx->nip);
258 }
259 t0 = tcg_const_i32(excp);
260 t1 = tcg_const_i32(error);
261 gen_helper_raise_exception_err(t0, t1);
262 tcg_temp_free_i32(t0);
263 tcg_temp_free_i32(t1);
264 ctx->exception = (excp);
265 }
266
267 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
268 {
269 TCGv_i32 t0;
270 if (ctx->exception == POWERPC_EXCP_NONE) {
271 gen_update_nip(ctx, ctx->nip);
272 }
273 t0 = tcg_const_i32(excp);
274 gen_helper_raise_exception(t0);
275 tcg_temp_free_i32(t0);
276 ctx->exception = (excp);
277 }
278
279 static always_inline void gen_debug_exception (DisasContext *ctx)
280 {
281 TCGv_i32 t0;
282
283 if (ctx->exception != POWERPC_EXCP_BRANCH)
284 gen_update_nip(ctx, ctx->nip);
285 t0 = tcg_const_i32(EXCP_DEBUG);
286 gen_helper_raise_exception(t0);
287 tcg_temp_free_i32(t0);
288 }
289
290 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
291 {
292 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
293 }
294
295 /* Stop translation */
296 static always_inline void gen_stop_exception (DisasContext *ctx)
297 {
298 gen_update_nip(ctx, ctx->nip);
299 ctx->exception = POWERPC_EXCP_STOP;
300 }
301
302 /* No need to update nip here, as execution flow will change */
303 static always_inline void gen_sync_exception (DisasContext *ctx)
304 {
305 ctx->exception = POWERPC_EXCP_SYNC;
306 }
307
308 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
309 static void gen_##name (DisasContext *ctx); \
310 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
311 static void gen_##name (DisasContext *ctx)
312
313 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
314 static void gen_##name (DisasContext *ctx); \
315 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
316 static void gen_##name (DisasContext *ctx)
317
318 typedef struct opcode_t {
319 unsigned char opc1, opc2, opc3;
320 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
321 unsigned char pad[5];
322 #else
323 unsigned char pad[1];
324 #endif
325 opc_handler_t handler;
326 const char *oname;
327 } opcode_t;
328
329 /*****************************************************************************/
330 /*** Instruction decoding ***/
331 #define EXTRACT_HELPER(name, shift, nb) \
332 static always_inline uint32_t name (uint32_t opcode) \
333 { \
334 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
335 }
336
337 #define EXTRACT_SHELPER(name, shift, nb) \
338 static always_inline int32_t name (uint32_t opcode) \
339 { \
340 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
341 }
342
343 /* Opcode part 1 */
344 EXTRACT_HELPER(opc1, 26, 6);
345 /* Opcode part 2 */
346 EXTRACT_HELPER(opc2, 1, 5);
347 /* Opcode part 3 */
348 EXTRACT_HELPER(opc3, 6, 5);
349 /* Update Cr0 flags */
350 EXTRACT_HELPER(Rc, 0, 1);
351 /* Destination */
352 EXTRACT_HELPER(rD, 21, 5);
353 /* Source */
354 EXTRACT_HELPER(rS, 21, 5);
355 /* First operand */
356 EXTRACT_HELPER(rA, 16, 5);
357 /* Second operand */
358 EXTRACT_HELPER(rB, 11, 5);
359 /* Third operand */
360 EXTRACT_HELPER(rC, 6, 5);
361 /*** Get CRn ***/
362 EXTRACT_HELPER(crfD, 23, 3);
363 EXTRACT_HELPER(crfS, 18, 3);
364 EXTRACT_HELPER(crbD, 21, 5);
365 EXTRACT_HELPER(crbA, 16, 5);
366 EXTRACT_HELPER(crbB, 11, 5);
367 /* SPR / TBL */
368 EXTRACT_HELPER(_SPR, 11, 10);
369 static always_inline uint32_t SPR (uint32_t opcode)
370 {
371 uint32_t sprn = _SPR(opcode);
372
373 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
374 }
375 /*** Get constants ***/
376 EXTRACT_HELPER(IMM, 12, 8);
377 /* 16 bits signed immediate value */
378 EXTRACT_SHELPER(SIMM, 0, 16);
379 /* 16 bits unsigned immediate value */
380 EXTRACT_HELPER(UIMM, 0, 16);
381 /* 5 bits signed immediate value */
382 EXTRACT_HELPER(SIMM5, 16, 5);
383 /* 5 bits signed immediate value */
384 EXTRACT_HELPER(UIMM5, 16, 5);
385 /* Bit count */
386 EXTRACT_HELPER(NB, 11, 5);
387 /* Shift count */
388 EXTRACT_HELPER(SH, 11, 5);
389 /* Vector shift count */
390 EXTRACT_HELPER(VSH, 6, 4);
391 /* Mask start */
392 EXTRACT_HELPER(MB, 6, 5);
393 /* Mask end */
394 EXTRACT_HELPER(ME, 1, 5);
395 /* Trap operand */
396 EXTRACT_HELPER(TO, 21, 5);
397
398 EXTRACT_HELPER(CRM, 12, 8);
399 EXTRACT_HELPER(FM, 17, 8);
400 EXTRACT_HELPER(SR, 16, 4);
401 EXTRACT_HELPER(FPIMM, 12, 4);
402
403 /*** Jump target decoding ***/
404 /* Displacement */
405 EXTRACT_SHELPER(d, 0, 16);
406 /* Immediate address */
407 static always_inline target_ulong LI (uint32_t opcode)
408 {
409 return (opcode >> 0) & 0x03FFFFFC;
410 }
411
412 static always_inline uint32_t BD (uint32_t opcode)
413 {
414 return (opcode >> 0) & 0xFFFC;
415 }
416
417 EXTRACT_HELPER(BO, 21, 5);
418 EXTRACT_HELPER(BI, 16, 5);
419 /* Absolute/relative address */
420 EXTRACT_HELPER(AA, 1, 1);
421 /* Link */
422 EXTRACT_HELPER(LK, 0, 1);
423
424 /* Create a mask between <start> and <end> bits */
425 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
426 {
427 target_ulong ret;
428
429 #if defined(TARGET_PPC64)
430 if (likely(start == 0)) {
431 ret = UINT64_MAX << (63 - end);
432 } else if (likely(end == 63)) {
433 ret = UINT64_MAX >> start;
434 }
435 #else
436 if (likely(start == 0)) {
437 ret = UINT32_MAX << (31 - end);
438 } else if (likely(end == 31)) {
439 ret = UINT32_MAX >> start;
440 }
441 #endif
442 else {
443 ret = (((target_ulong)(-1ULL)) >> (start)) ^
444 (((target_ulong)(-1ULL) >> (end)) >> 1);
445 if (unlikely(start > end))
446 return ~ret;
447 }
448
449 return ret;
450 }
451
452 /*****************************************************************************/
453 /* PowerPC Instructions types definitions */
454 enum {
455 PPC_NONE = 0x0000000000000000ULL,
456 /* PowerPC base instructions set */
457 PPC_INSNS_BASE = 0x0000000000000001ULL,
458 /* integer operations instructions */
459 #define PPC_INTEGER PPC_INSNS_BASE
460 /* flow control instructions */
461 #define PPC_FLOW PPC_INSNS_BASE
462 /* virtual memory instructions */
463 #define PPC_MEM PPC_INSNS_BASE
464 /* ld/st with reservation instructions */
465 #define PPC_RES PPC_INSNS_BASE
466 /* spr/msr access instructions */
467 #define PPC_MISC PPC_INSNS_BASE
468 /* Deprecated instruction sets */
469 /* Original POWER instruction set */
470 PPC_POWER = 0x0000000000000002ULL,
471 /* POWER2 instruction set extension */
472 PPC_POWER2 = 0x0000000000000004ULL,
473 /* Power RTC support */
474 PPC_POWER_RTC = 0x0000000000000008ULL,
475 /* Power-to-PowerPC bridge (601) */
476 PPC_POWER_BR = 0x0000000000000010ULL,
477 /* 64 bits PowerPC instruction set */
478 PPC_64B = 0x0000000000000020ULL,
479 /* New 64 bits extensions (PowerPC 2.0x) */
480 PPC_64BX = 0x0000000000000040ULL,
481 /* 64 bits hypervisor extensions */
482 PPC_64H = 0x0000000000000080ULL,
483 /* New wait instruction (PowerPC 2.0x) */
484 PPC_WAIT = 0x0000000000000100ULL,
485 /* Time base mftb instruction */
486 PPC_MFTB = 0x0000000000000200ULL,
487
488 /* Fixed-point unit extensions */
489 /* PowerPC 602 specific */
490 PPC_602_SPEC = 0x0000000000000400ULL,
491 /* isel instruction */
492 PPC_ISEL = 0x0000000000000800ULL,
493 /* popcntb instruction */
494 PPC_POPCNTB = 0x0000000000001000ULL,
495 /* string load / store */
496 PPC_STRING = 0x0000000000002000ULL,
497
498 /* Floating-point unit extensions */
499 /* Optional floating point instructions */
500 PPC_FLOAT = 0x0000000000010000ULL,
501 /* New floating-point extensions (PowerPC 2.0x) */
502 PPC_FLOAT_EXT = 0x0000000000020000ULL,
503 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
504 PPC_FLOAT_FRES = 0x0000000000080000ULL,
505 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
506 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
507 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
508 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
509
510 /* Vector/SIMD extensions */
511 /* Altivec support */
512 PPC_ALTIVEC = 0x0000000001000000ULL,
513 /* PowerPC 2.03 SPE extension */
514 PPC_SPE = 0x0000000002000000ULL,
515 /* PowerPC 2.03 SPE single-precision floating-point extension */
516 PPC_SPE_SINGLE = 0x0000000004000000ULL,
517 /* PowerPC 2.03 SPE double-precision floating-point extension */
518 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
519
520 /* Optional memory control instructions */
521 PPC_MEM_TLBIA = 0x0000000010000000ULL,
522 PPC_MEM_TLBIE = 0x0000000020000000ULL,
523 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
524 /* sync instruction */
525 PPC_MEM_SYNC = 0x0000000080000000ULL,
526 /* eieio instruction */
527 PPC_MEM_EIEIO = 0x0000000100000000ULL,
528
529 /* Cache control instructions */
530 PPC_CACHE = 0x0000000200000000ULL,
531 /* icbi instruction */
532 PPC_CACHE_ICBI = 0x0000000400000000ULL,
533 /* dcbz instruction with fixed cache line size */
534 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
535 /* dcbz instruction with tunable cache line size */
536 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
537 /* dcba instruction */
538 PPC_CACHE_DCBA = 0x0000002000000000ULL,
539 /* Freescale cache locking instructions */
540 PPC_CACHE_LOCK = 0x0000004000000000ULL,
541
542 /* MMU related extensions */
543 /* external control instructions */
544 PPC_EXTERN = 0x0000010000000000ULL,
545 /* segment register access instructions */
546 PPC_SEGMENT = 0x0000020000000000ULL,
547 /* PowerPC 6xx TLB management instructions */
548 PPC_6xx_TLB = 0x0000040000000000ULL,
549 /* PowerPC 74xx TLB management instructions */
550 PPC_74xx_TLB = 0x0000080000000000ULL,
551 /* PowerPC 40x TLB management instructions */
552 PPC_40x_TLB = 0x0000100000000000ULL,
553 /* segment register access instructions for PowerPC 64 "bridge" */
554 PPC_SEGMENT_64B = 0x0000200000000000ULL,
555 /* SLB management */
556 PPC_SLBI = 0x0000400000000000ULL,
557
558 /* Embedded PowerPC dedicated instructions */
559 PPC_WRTEE = 0x0001000000000000ULL,
560 /* PowerPC 40x exception model */
561 PPC_40x_EXCP = 0x0002000000000000ULL,
562 /* PowerPC 405 Mac instructions */
563 PPC_405_MAC = 0x0004000000000000ULL,
564 /* PowerPC 440 specific instructions */
565 PPC_440_SPEC = 0x0008000000000000ULL,
566 /* BookE (embedded) PowerPC specification */
567 PPC_BOOKE = 0x0010000000000000ULL,
568 /* mfapidi instruction */
569 PPC_MFAPIDI = 0x0020000000000000ULL,
570 /* tlbiva instruction */
571 PPC_TLBIVA = 0x0040000000000000ULL,
572 /* tlbivax instruction */
573 PPC_TLBIVAX = 0x0080000000000000ULL,
574 /* PowerPC 4xx dedicated instructions */
575 PPC_4xx_COMMON = 0x0100000000000000ULL,
576 /* PowerPC 40x ibct instructions */
577 PPC_40x_ICBT = 0x0200000000000000ULL,
578 /* rfmci is not implemented in all BookE PowerPC */
579 PPC_RFMCI = 0x0400000000000000ULL,
580 /* rfdi instruction */
581 PPC_RFDI = 0x0800000000000000ULL,
582 /* DCR accesses */
583 PPC_DCR = 0x1000000000000000ULL,
584 /* DCR extended accesse */
585 PPC_DCRX = 0x2000000000000000ULL,
586 /* user-mode DCR access, implemented in PowerPC 460 */
587 PPC_DCRUX = 0x4000000000000000ULL,
588 };
589
590 /*****************************************************************************/
591 /* PowerPC instructions table */
592 #if HOST_LONG_BITS == 64
593 #define OPC_ALIGN 8
594 #else
595 #define OPC_ALIGN 4
596 #endif
597 #if defined(__APPLE__)
598 #define OPCODES_SECTION \
599 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
600 #else
601 #define OPCODES_SECTION \
602 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
603 #endif
604
605 #if defined(DO_PPC_STATISTICS)
606 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
607 extern opcode_t opc_##name; \
608 OPCODES_SECTION opcode_t opc_##name = { \
609 .opc1 = op1, \
610 .opc2 = op2, \
611 .opc3 = op3, \
612 .pad = { 0, }, \
613 .handler = { \
614 .inval = invl, \
615 .type = _typ, \
616 .handler = &gen_##name, \
617 .oname = stringify(name), \
618 }, \
619 .oname = stringify(name), \
620 }
621 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
622 OPCODES_SECTION opcode_t opc_##name = { \
623 .opc1 = op1, \
624 .opc2 = op2, \
625 .opc3 = op3, \
626 .pad = { 0, }, \
627 .handler = { \
628 .inval = invl, \
629 .type = _typ, \
630 .handler = &gen_##name, \
631 .oname = onam, \
632 }, \
633 .oname = onam, \
634 }
635 #else
636 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
637 extern opcode_t opc_##name; \
638 OPCODES_SECTION opcode_t opc_##name = { \
639 .opc1 = op1, \
640 .opc2 = op2, \
641 .opc3 = op3, \
642 .pad = { 0, }, \
643 .handler = { \
644 .inval = invl, \
645 .type = _typ, \
646 .handler = &gen_##name, \
647 }, \
648 .oname = stringify(name), \
649 }
650 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
651 extern opcode_t opc_##name; \
652 OPCODES_SECTION opcode_t opc_##name = { \
653 .opc1 = op1, \
654 .opc2 = op2, \
655 .opc3 = op3, \
656 .pad = { 0, }, \
657 .handler = { \
658 .inval = invl, \
659 .type = _typ, \
660 .handler = &gen_##name, \
661 }, \
662 .oname = onam, \
663 }
664 #endif
665
666 #define GEN_OPCODE_MARK(name) \
667 extern opcode_t opc_##name; \
668 OPCODES_SECTION opcode_t opc_##name = { \
669 .opc1 = 0xFF, \
670 .opc2 = 0xFF, \
671 .opc3 = 0xFF, \
672 .pad = { 0, }, \
673 .handler = { \
674 .inval = 0x00000000, \
675 .type = 0x00, \
676 .handler = NULL, \
677 }, \
678 .oname = stringify(name), \
679 }
680
681 /* SPR load/store helpers */
682 static always_inline void gen_load_spr(TCGv t, int reg)
683 {
684 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
685 }
686
687 static always_inline void gen_store_spr(int reg, TCGv t)
688 {
689 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
690 }
691
692 /* Start opcode list */
693 GEN_OPCODE_MARK(start);
694
695 /* Invalid instruction */
696 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
697 {
698 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
699 }
700
701 static opc_handler_t invalid_handler = {
702 .inval = 0xFFFFFFFF,
703 .type = PPC_NONE,
704 .handler = gen_invalid,
705 };
706
707 /*** Integer comparison ***/
708
709 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
710 {
711 int l1, l2, l3;
712
713 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
714 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
715 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
716
717 l1 = gen_new_label();
718 l2 = gen_new_label();
719 l3 = gen_new_label();
720 if (s) {
721 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
723 } else {
724 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
725 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
726 }
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
728 tcg_gen_br(l3);
729 gen_set_label(l1);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
731 tcg_gen_br(l3);
732 gen_set_label(l2);
733 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
734 gen_set_label(l3);
735 }
736
737 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
738 {
739 TCGv t0 = tcg_const_local_tl(arg1);
740 gen_op_cmp(arg0, t0, s, crf);
741 tcg_temp_free(t0);
742 }
743
744 #if defined(TARGET_PPC64)
745 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
746 {
747 TCGv t0, t1;
748 t0 = tcg_temp_local_new();
749 t1 = tcg_temp_local_new();
750 if (s) {
751 tcg_gen_ext32s_tl(t0, arg0);
752 tcg_gen_ext32s_tl(t1, arg1);
753 } else {
754 tcg_gen_ext32u_tl(t0, arg0);
755 tcg_gen_ext32u_tl(t1, arg1);
756 }
757 gen_op_cmp(t0, t1, s, crf);
758 tcg_temp_free(t1);
759 tcg_temp_free(t0);
760 }
761
762 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
763 {
764 TCGv t0 = tcg_const_local_tl(arg1);
765 gen_op_cmp32(arg0, t0, s, crf);
766 tcg_temp_free(t0);
767 }
768 #endif
769
770 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
771 {
772 #if defined(TARGET_PPC64)
773 if (!(ctx->sf_mode))
774 gen_op_cmpi32(reg, 0, 1, 0);
775 else
776 #endif
777 gen_op_cmpi(reg, 0, 1, 0);
778 }
779
780 /* cmp */
781 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
782 {
783 #if defined(TARGET_PPC64)
784 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
785 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787 else
788 #endif
789 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
790 1, crfD(ctx->opcode));
791 }
792
793 /* cmpi */
794 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
795 {
796 #if defined(TARGET_PPC64)
797 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
798 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800 else
801 #endif
802 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
803 1, crfD(ctx->opcode));
804 }
805
806 /* cmpl */
807 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
808 {
809 #if defined(TARGET_PPC64)
810 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
811 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813 else
814 #endif
815 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
816 0, crfD(ctx->opcode));
817 }
818
819 /* cmpli */
820 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
821 {
822 #if defined(TARGET_PPC64)
823 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
824 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826 else
827 #endif
828 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
829 0, crfD(ctx->opcode));
830 }
831
832 /* isel (PowerPC 2.03 specification) */
833 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
834 {
835 int l1, l2;
836 uint32_t bi = rC(ctx->opcode);
837 uint32_t mask;
838 TCGv_i32 t0;
839
840 l1 = gen_new_label();
841 l2 = gen_new_label();
842
843 mask = 1 << (3 - (bi & 0x03));
844 t0 = tcg_temp_new_i32();
845 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
846 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
847 if (rA(ctx->opcode) == 0)
848 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
849 else
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
851 tcg_gen_br(l2);
852 gen_set_label(l1);
853 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
854 gen_set_label(l2);
855 tcg_temp_free_i32(t0);
856 }
857
858 /*** Integer arithmetic ***/
859
860 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
861 {
862 int l1;
863 TCGv t0;
864
865 l1 = gen_new_label();
866 /* Start with XER OV disabled, the most likely case */
867 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
868 t0 = tcg_temp_local_new();
869 tcg_gen_xor_tl(t0, arg0, arg1);
870 #if defined(TARGET_PPC64)
871 if (!ctx->sf_mode)
872 tcg_gen_ext32s_tl(t0, t0);
873 #endif
874 if (sub)
875 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
876 else
877 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
878 tcg_gen_xor_tl(t0, arg1, arg2);
879 #if defined(TARGET_PPC64)
880 if (!ctx->sf_mode)
881 tcg_gen_ext32s_tl(t0, t0);
882 #endif
883 if (sub)
884 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
885 else
886 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
887 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
888 gen_set_label(l1);
889 tcg_temp_free(t0);
890 }
891
892 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
893 {
894 int l1 = gen_new_label();
895
896 #if defined(TARGET_PPC64)
897 if (!(ctx->sf_mode)) {
898 TCGv t0, t1;
899 t0 = tcg_temp_new();
900 t1 = tcg_temp_new();
901
902 tcg_gen_ext32u_tl(t0, arg1);
903 tcg_gen_ext32u_tl(t1, arg2);
904 if (sub) {
905 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
906 } else {
907 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
908 }
909 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
910 gen_set_label(l1);
911 tcg_temp_free(t0);
912 tcg_temp_free(t1);
913 } else
914 #endif
915 {
916 if (sub) {
917 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
918 } else {
919 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
920 }
921 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
922 gen_set_label(l1);
923 }
924 }
925
926 /* Common add function */
927 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
928 int add_ca, int compute_ca, int compute_ov)
929 {
930 TCGv t0, t1;
931
932 if ((!compute_ca && !compute_ov) ||
933 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
934 t0 = ret;
935 } else {
936 t0 = tcg_temp_local_new();
937 }
938
939 if (add_ca) {
940 t1 = tcg_temp_local_new();
941 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
942 tcg_gen_shri_tl(t1, t1, XER_CA);
943 }
944
945 if (compute_ca && compute_ov) {
946 /* Start with XER CA and OV disabled, the most likely case */
947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
948 } else if (compute_ca) {
949 /* Start with XER CA disabled, the most likely case */
950 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
951 } else if (compute_ov) {
952 /* Start with XER OV disabled, the most likely case */
953 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
954 }
955
956 tcg_gen_add_tl(t0, arg1, arg2);
957
958 if (compute_ca) {
959 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
960 }
961 if (add_ca) {
962 tcg_gen_add_tl(t0, t0, t1);
963 gen_op_arith_compute_ca(ctx, t0, t1, 0);
964 tcg_temp_free(t1);
965 }
966 if (compute_ov) {
967 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
968 }
969
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, t0);
972
973 if (!TCGV_EQUAL(t0, ret)) {
974 tcg_gen_mov_tl(ret, t0);
975 tcg_temp_free(t0);
976 }
977 }
978 /* Add functions with two operands */
979 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
980 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
981 { \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 add_ca, compute_ca, compute_ov); \
985 }
986 /* Add functions with one operand and one immediate */
987 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
988 add_ca, compute_ca, compute_ov) \
989 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
990 { \
991 TCGv t0 = tcg_const_local_tl(const_val); \
992 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], t0, \
994 add_ca, compute_ca, compute_ov); \
995 tcg_temp_free(t0); \
996 }
997
998 /* add add. addo addo. */
999 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1000 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1001 /* addc addc. addco addco. */
1002 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1003 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1004 /* adde adde. addeo addeo. */
1005 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1006 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1007 /* addme addme. addmeo addmeo. */
1008 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1009 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1010 /* addze addze. addzeo addzeo.*/
1011 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1012 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1013 /* addi */
1014 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1015 {
1016 target_long simm = SIMM(ctx->opcode);
1017
1018 if (rA(ctx->opcode) == 0) {
1019 /* li case */
1020 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1021 } else {
1022 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1023 }
1024 }
1025 /* addic addic.*/
1026 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1027 int compute_Rc0)
1028 {
1029 target_long simm = SIMM(ctx->opcode);
1030
1031 /* Start with XER CA and OV disabled, the most likely case */
1032 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1033
1034 if (likely(simm != 0)) {
1035 TCGv t0 = tcg_temp_local_new();
1036 tcg_gen_addi_tl(t0, arg1, simm);
1037 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1038 tcg_gen_mov_tl(ret, t0);
1039 tcg_temp_free(t0);
1040 } else {
1041 tcg_gen_mov_tl(ret, arg1);
1042 }
1043 if (compute_Rc0) {
1044 gen_set_Rc0(ctx, ret);
1045 }
1046 }
1047 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1048 {
1049 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1050 }
1051 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1052 {
1053 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1054 }
1055 /* addis */
1056 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1057 {
1058 target_long simm = SIMM(ctx->opcode);
1059
1060 if (rA(ctx->opcode) == 0) {
1061 /* lis case */
1062 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1063 } else {
1064 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1065 }
1066 }
1067
1068 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1069 int sign, int compute_ov)
1070 {
1071 int l1 = gen_new_label();
1072 int l2 = gen_new_label();
1073 TCGv_i32 t0 = tcg_temp_local_new_i32();
1074 TCGv_i32 t1 = tcg_temp_local_new_i32();
1075
1076 tcg_gen_trunc_tl_i32(t0, arg1);
1077 tcg_gen_trunc_tl_i32(t1, arg2);
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1079 if (sign) {
1080 int l3 = gen_new_label();
1081 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1082 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1083 gen_set_label(l3);
1084 tcg_gen_div_i32(t0, t0, t1);
1085 } else {
1086 tcg_gen_divu_i32(t0, t0, t1);
1087 }
1088 if (compute_ov) {
1089 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1090 }
1091 tcg_gen_br(l2);
1092 gen_set_label(l1);
1093 if (sign) {
1094 tcg_gen_sari_i32(t0, t0, 31);
1095 } else {
1096 tcg_gen_movi_i32(t0, 0);
1097 }
1098 if (compute_ov) {
1099 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1100 }
1101 gen_set_label(l2);
1102 tcg_gen_extu_i32_tl(ret, t0);
1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, ret);
1107 }
1108 /* Div functions */
1109 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1110 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1111 { \
1112 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1114 sign, compute_ov); \
1115 }
1116 /* divwu divwu. divwuo divwuo. */
1117 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1118 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1119 /* divw divw. divwo divwo. */
1120 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1121 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1122 #if defined(TARGET_PPC64)
1123 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1124 int sign, int compute_ov)
1125 {
1126 int l1 = gen_new_label();
1127 int l2 = gen_new_label();
1128
1129 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1130 if (sign) {
1131 int l3 = gen_new_label();
1132 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1134 gen_set_label(l3);
1135 tcg_gen_div_i64(ret, arg1, arg2);
1136 } else {
1137 tcg_gen_divu_i64(ret, arg1, arg2);
1138 }
1139 if (compute_ov) {
1140 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1141 }
1142 tcg_gen_br(l2);
1143 gen_set_label(l1);
1144 if (sign) {
1145 tcg_gen_sari_i64(ret, arg1, 63);
1146 } else {
1147 tcg_gen_movi_i64(ret, 0);
1148 }
1149 if (compute_ov) {
1150 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1151 }
1152 gen_set_label(l2);
1153 if (unlikely(Rc(ctx->opcode) != 0))
1154 gen_set_Rc0(ctx, ret);
1155 }
1156 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1157 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1158 { \
1159 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign, compute_ov); \
1162 }
1163 /* divwu divwu. divwuo divwuo. */
1164 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1165 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1166 /* divw divw. divwo divwo. */
1167 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1168 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1169 #endif
1170
1171 /* mulhw mulhw. */
1172 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1173 {
1174 TCGv_i64 t0, t1;
1175
1176 t0 = tcg_temp_new_i64();
1177 t1 = tcg_temp_new_i64();
1178 #if defined(TARGET_PPC64)
1179 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1183 #else
1184 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1185 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1186 tcg_gen_mul_i64(t0, t0, t1);
1187 tcg_gen_shri_i64(t0, t0, 32);
1188 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1189 #endif
1190 tcg_temp_free_i64(t0);
1191 tcg_temp_free_i64(t1);
1192 if (unlikely(Rc(ctx->opcode) != 0))
1193 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1194 }
1195 /* mulhwu mulhwu. */
1196 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1197 {
1198 TCGv_i64 t0, t1;
1199
1200 t0 = tcg_temp_new_i64();
1201 t1 = tcg_temp_new_i64();
1202 #if defined(TARGET_PPC64)
1203 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1207 #else
1208 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1209 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1210 tcg_gen_mul_i64(t0, t0, t1);
1211 tcg_gen_shri_i64(t0, t0, 32);
1212 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1213 #endif
1214 tcg_temp_free_i64(t0);
1215 tcg_temp_free_i64(t1);
1216 if (unlikely(Rc(ctx->opcode) != 0))
1217 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1218 }
1219 /* mullw mullw. */
1220 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1221 {
1222 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1223 cpu_gpr[rB(ctx->opcode)]);
1224 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1227 }
1228 /* mullwo mullwo. */
1229 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1230 {
1231 int l1;
1232 TCGv_i64 t0, t1;
1233
1234 t0 = tcg_temp_new_i64();
1235 t1 = tcg_temp_new_i64();
1236 l1 = gen_new_label();
1237 /* Start with XER OV disabled, the most likely case */
1238 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1239 #if defined(TARGET_PPC64)
1240 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1241 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1242 #else
1243 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1244 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1245 #endif
1246 tcg_gen_mul_i64(t0, t0, t1);
1247 #if defined(TARGET_PPC64)
1248 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1249 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1250 #else
1251 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1252 tcg_gen_ext32s_i64(t1, t0);
1253 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1254 #endif
1255 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1256 gen_set_label(l1);
1257 tcg_temp_free_i64(t0);
1258 tcg_temp_free_i64(t1);
1259 if (unlikely(Rc(ctx->opcode) != 0))
1260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1261 }
1262 /* mulli */
1263 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1264 {
1265 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1266 SIMM(ctx->opcode));
1267 }
1268 #if defined(TARGET_PPC64)
1269 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1270 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1271 { \
1272 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1274 if (unlikely(Rc(ctx->opcode) != 0)) \
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1276 }
1277 /* mulhd mulhd. */
1278 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1279 /* mulhdu mulhdu. */
1280 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1281 /* mulld mulld. */
1282 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1283 {
1284 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1285 cpu_gpr[rB(ctx->opcode)]);
1286 if (unlikely(Rc(ctx->opcode) != 0))
1287 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1288 }
1289 /* mulldo mulldo. */
1290 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1291 #endif
1292
1293 /* neg neg. nego nego. */
1294 static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1295 {
1296 int l1 = gen_new_label();
1297 int l2 = gen_new_label();
1298 TCGv t0 = tcg_temp_local_new();
1299 #if defined(TARGET_PPC64)
1300 if (ctx->sf_mode) {
1301 tcg_gen_mov_tl(t0, arg1);
1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1303 } else
1304 #endif
1305 {
1306 tcg_gen_ext32s_tl(t0, arg1);
1307 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1308 }
1309 tcg_gen_neg_tl(ret, arg1);
1310 if (ov_check) {
1311 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1312 }
1313 tcg_gen_br(l2);
1314 gen_set_label(l1);
1315 tcg_gen_mov_tl(ret, t0);
1316 if (ov_check) {
1317 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1318 }
1319 gen_set_label(l2);
1320 tcg_temp_free(t0);
1321 if (unlikely(Rc(ctx->opcode) != 0))
1322 gen_set_Rc0(ctx, ret);
1323 }
1324 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1325 {
1326 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1327 }
1328 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1329 {
1330 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1331 }
1332
1333 /* Common subf function */
1334 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1335 int add_ca, int compute_ca, int compute_ov)
1336 {
1337 TCGv t0, t1;
1338
1339 if ((!compute_ca && !compute_ov) ||
1340 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1341 t0 = ret;
1342 } else {
1343 t0 = tcg_temp_local_new();
1344 }
1345
1346 if (add_ca) {
1347 t1 = tcg_temp_local_new();
1348 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1349 tcg_gen_shri_tl(t1, t1, XER_CA);
1350 }
1351
1352 if (compute_ca && compute_ov) {
1353 /* Start with XER CA and OV disabled, the most likely case */
1354 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1355 } else if (compute_ca) {
1356 /* Start with XER CA disabled, the most likely case */
1357 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1358 } else if (compute_ov) {
1359 /* Start with XER OV disabled, the most likely case */
1360 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1361 }
1362
1363 if (add_ca) {
1364 tcg_gen_not_tl(t0, arg1);
1365 tcg_gen_add_tl(t0, t0, arg2);
1366 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1367 tcg_gen_add_tl(t0, t0, t1);
1368 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1369 tcg_temp_free(t1);
1370 } else {
1371 tcg_gen_sub_tl(t0, arg2, arg1);
1372 if (compute_ca) {
1373 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1374 }
1375 }
1376 if (compute_ov) {
1377 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1378 }
1379
1380 if (unlikely(Rc(ctx->opcode) != 0))
1381 gen_set_Rc0(ctx, t0);
1382
1383 if (!TCGV_EQUAL(t0, ret)) {
1384 tcg_gen_mov_tl(ret, t0);
1385 tcg_temp_free(t0);
1386 }
1387 }
1388 /* Sub functions with Two operands functions */
1389 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1390 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1391 { \
1392 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1393 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1394 add_ca, compute_ca, compute_ov); \
1395 }
1396 /* Sub functions with one operand and one immediate */
1397 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1398 add_ca, compute_ca, compute_ov) \
1399 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1400 { \
1401 TCGv t0 = tcg_const_local_tl(const_val); \
1402 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1403 cpu_gpr[rA(ctx->opcode)], t0, \
1404 add_ca, compute_ca, compute_ov); \
1405 tcg_temp_free(t0); \
1406 }
1407 /* subf subf. subfo subfo. */
1408 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1409 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1410 /* subfc subfc. subfco subfco. */
1411 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1412 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1413 /* subfe subfe. subfeo subfo. */
1414 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1415 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1416 /* subfme subfme. subfmeo subfmeo. */
1417 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1418 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1419 /* subfze subfze. subfzeo subfzeo.*/
1420 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1421 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1422 /* subfic */
1423 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1424 {
1425 /* Start with XER CA and OV disabled, the most likely case */
1426 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1427 TCGv t0 = tcg_temp_local_new();
1428 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1429 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1430 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1431 tcg_temp_free(t1);
1432 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1433 tcg_temp_free(t0);
1434 }
1435
1436 /*** Integer logical ***/
1437 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1438 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1439 { \
1440 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1441 cpu_gpr[rB(ctx->opcode)]); \
1442 if (unlikely(Rc(ctx->opcode) != 0)) \
1443 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1444 }
1445
1446 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1447 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1448 { \
1449 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1450 if (unlikely(Rc(ctx->opcode) != 0)) \
1451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1452 }
1453
1454 /* and & and. */
1455 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1456 /* andc & andc. */
1457 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1458 /* andi. */
1459 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1460 {
1461 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1463 }
1464 /* andis. */
1465 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1466 {
1467 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1469 }
1470 /* cntlzw */
1471 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1472 {
1473 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1474 if (unlikely(Rc(ctx->opcode) != 0))
1475 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1476 }
1477 /* eqv & eqv. */
1478 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1479 /* extsb & extsb. */
1480 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1481 /* extsh & extsh. */
1482 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1483 /* nand & nand. */
1484 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1485 /* nor & nor. */
1486 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1487 /* or & or. */
1488 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1489 {
1490 int rs, ra, rb;
1491
1492 rs = rS(ctx->opcode);
1493 ra = rA(ctx->opcode);
1494 rb = rB(ctx->opcode);
1495 /* Optimisation for mr. ri case */
1496 if (rs != ra || rs != rb) {
1497 if (rs != rb)
1498 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1499 else
1500 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1501 if (unlikely(Rc(ctx->opcode) != 0))
1502 gen_set_Rc0(ctx, cpu_gpr[ra]);
1503 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1504 gen_set_Rc0(ctx, cpu_gpr[rs]);
1505 #if defined(TARGET_PPC64)
1506 } else {
1507 int prio = 0;
1508
1509 switch (rs) {
1510 case 1:
1511 /* Set process priority to low */
1512 prio = 2;
1513 break;
1514 case 6:
1515 /* Set process priority to medium-low */
1516 prio = 3;
1517 break;
1518 case 2:
1519 /* Set process priority to normal */
1520 prio = 4;
1521 break;
1522 #if !defined(CONFIG_USER_ONLY)
1523 case 31:
1524 if (ctx->mem_idx > 0) {
1525 /* Set process priority to very low */
1526 prio = 1;
1527 }
1528 break;
1529 case 5:
1530 if (ctx->mem_idx > 0) {
1531 /* Set process priority to medium-hight */
1532 prio = 5;
1533 }
1534 break;
1535 case 3:
1536 if (ctx->mem_idx > 0) {
1537 /* Set process priority to high */
1538 prio = 6;
1539 }
1540 break;
1541 case 7:
1542 if (ctx->mem_idx > 1) {
1543 /* Set process priority to very high */
1544 prio = 7;
1545 }
1546 break;
1547 #endif
1548 default:
1549 /* nop */
1550 break;
1551 }
1552 if (prio) {
1553 TCGv t0 = tcg_temp_new();
1554 gen_load_spr(t0, SPR_PPR);
1555 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1556 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1557 gen_store_spr(SPR_PPR, t0);
1558 tcg_temp_free(t0);
1559 }
1560 #endif
1561 }
1562 }
1563 /* orc & orc. */
1564 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1565 /* xor & xor. */
1566 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1567 {
1568 /* Optimisation for "set to zero" case */
1569 if (rS(ctx->opcode) != rB(ctx->opcode))
1570 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1571 else
1572 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1573 if (unlikely(Rc(ctx->opcode) != 0))
1574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1575 }
1576 /* ori */
1577 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1578 {
1579 target_ulong uimm = UIMM(ctx->opcode);
1580
1581 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1582 /* NOP */
1583 /* XXX: should handle special NOPs for POWER series */
1584 return;
1585 }
1586 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1587 }
1588 /* oris */
1589 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1590 {
1591 target_ulong uimm = UIMM(ctx->opcode);
1592
1593 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1594 /* NOP */
1595 return;
1596 }
1597 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1598 }
1599 /* xori */
1600 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1601 {
1602 target_ulong uimm = UIMM(ctx->opcode);
1603
1604 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1605 /* NOP */
1606 return;
1607 }
1608 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1609 }
1610 /* xoris */
1611 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1612 {
1613 target_ulong uimm = UIMM(ctx->opcode);
1614
1615 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1616 /* NOP */
1617 return;
1618 }
1619 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1620 }
1621 /* popcntb : PowerPC 2.03 specification */
1622 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1623 {
1624 #if defined(TARGET_PPC64)
1625 if (ctx->sf_mode)
1626 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1627 else
1628 #endif
1629 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1630 }
1631
1632 #if defined(TARGET_PPC64)
1633 /* extsw & extsw. */
1634 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1635 /* cntlzd */
1636 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1637 {
1638 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1639 if (unlikely(Rc(ctx->opcode) != 0))
1640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1641 }
1642 #endif
1643
1644 /*** Integer rotate ***/
1645 /* rlwimi & rlwimi. */
1646 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1647 {
1648 uint32_t mb, me, sh;
1649
1650 mb = MB(ctx->opcode);
1651 me = ME(ctx->opcode);
1652 sh = SH(ctx->opcode);
1653 if (likely(sh == 0 && mb == 0 && me == 31)) {
1654 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 } else {
1656 target_ulong mask;
1657 TCGv t1;
1658 TCGv t0 = tcg_temp_new();
1659 #if defined(TARGET_PPC64)
1660 TCGv_i32 t2 = tcg_temp_new_i32();
1661 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_rotli_i32(t2, t2, sh);
1663 tcg_gen_extu_i32_i64(t0, t2);
1664 tcg_temp_free_i32(t2);
1665 #else
1666 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1667 #endif
1668 #if defined(TARGET_PPC64)
1669 mb += 32;
1670 me += 32;
1671 #endif
1672 mask = MASK(mb, me);
1673 t1 = tcg_temp_new();
1674 tcg_gen_andi_tl(t0, t0, mask);
1675 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1676 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1677 tcg_temp_free(t0);
1678 tcg_temp_free(t1);
1679 }
1680 if (unlikely(Rc(ctx->opcode) != 0))
1681 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1682 }
1683 /* rlwinm & rlwinm. */
1684 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1685 {
1686 uint32_t mb, me, sh;
1687
1688 sh = SH(ctx->opcode);
1689 mb = MB(ctx->opcode);
1690 me = ME(ctx->opcode);
1691
1692 if (likely(mb == 0 && me == (31 - sh))) {
1693 if (likely(sh == 0)) {
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1695 } else {
1696 TCGv t0 = tcg_temp_new();
1697 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1698 tcg_gen_shli_tl(t0, t0, sh);
1699 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1700 tcg_temp_free(t0);
1701 }
1702 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1703 TCGv t0 = tcg_temp_new();
1704 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1705 tcg_gen_shri_tl(t0, t0, mb);
1706 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1707 tcg_temp_free(t0);
1708 } else {
1709 TCGv t0 = tcg_temp_new();
1710 #if defined(TARGET_PPC64)
1711 TCGv_i32 t1 = tcg_temp_new_i32();
1712 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1713 tcg_gen_rotli_i32(t1, t1, sh);
1714 tcg_gen_extu_i32_i64(t0, t1);
1715 tcg_temp_free_i32(t1);
1716 #else
1717 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1718 #endif
1719 #if defined(TARGET_PPC64)
1720 mb += 32;
1721 me += 32;
1722 #endif
1723 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1724 tcg_temp_free(t0);
1725 }
1726 if (unlikely(Rc(ctx->opcode) != 0))
1727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1728 }
1729 /* rlwnm & rlwnm. */
1730 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1731 {
1732 uint32_t mb, me;
1733 TCGv t0;
1734 #if defined(TARGET_PPC64)
1735 TCGv_i32 t1, t2;
1736 #endif
1737
1738 mb = MB(ctx->opcode);
1739 me = ME(ctx->opcode);
1740 t0 = tcg_temp_new();
1741 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1742 #if defined(TARGET_PPC64)
1743 t1 = tcg_temp_new_i32();
1744 t2 = tcg_temp_new_i32();
1745 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1746 tcg_gen_trunc_i64_i32(t2, t0);
1747 tcg_gen_rotl_i32(t1, t1, t2);
1748 tcg_gen_extu_i32_i64(t0, t1);
1749 tcg_temp_free_i32(t1);
1750 tcg_temp_free_i32(t2);
1751 #else
1752 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1753 #endif
1754 if (unlikely(mb != 0 || me != 31)) {
1755 #if defined(TARGET_PPC64)
1756 mb += 32;
1757 me += 32;
1758 #endif
1759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1760 } else {
1761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1762 }
1763 tcg_temp_free(t0);
1764 if (unlikely(Rc(ctx->opcode) != 0))
1765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1766 }
1767
1768 #if defined(TARGET_PPC64)
1769 #define GEN_PPC64_R2(name, opc1, opc2) \
1770 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1771 { \
1772 gen_##name(ctx, 0); \
1773 } \
1774 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1775 PPC_64B) \
1776 { \
1777 gen_##name(ctx, 1); \
1778 }
1779 #define GEN_PPC64_R4(name, opc1, opc2) \
1780 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1781 { \
1782 gen_##name(ctx, 0, 0); \
1783 } \
1784 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1785 PPC_64B) \
1786 { \
1787 gen_##name(ctx, 0, 1); \
1788 } \
1789 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1790 PPC_64B) \
1791 { \
1792 gen_##name(ctx, 1, 0); \
1793 } \
1794 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1795 PPC_64B) \
1796 { \
1797 gen_##name(ctx, 1, 1); \
1798 }
1799
1800 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1801 uint32_t me, uint32_t sh)
1802 {
1803 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1804 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1805 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1806 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1807 } else {
1808 TCGv t0 = tcg_temp_new();
1809 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1810 if (likely(mb == 0 && me == 63)) {
1811 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1812 } else {
1813 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1814 }
1815 tcg_temp_free(t0);
1816 }
1817 if (unlikely(Rc(ctx->opcode) != 0))
1818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1819 }
1820 /* rldicl - rldicl. */
1821 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1822 {
1823 uint32_t sh, mb;
1824
1825 sh = SH(ctx->opcode) | (shn << 5);
1826 mb = MB(ctx->opcode) | (mbn << 5);
1827 gen_rldinm(ctx, mb, 63, sh);
1828 }
1829 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1830 /* rldicr - rldicr. */
1831 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1832 {
1833 uint32_t sh, me;
1834
1835 sh = SH(ctx->opcode) | (shn << 5);
1836 me = MB(ctx->opcode) | (men << 5);
1837 gen_rldinm(ctx, 0, me, sh);
1838 }
1839 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1840 /* rldic - rldic. */
1841 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1842 {
1843 uint32_t sh, mb;
1844
1845 sh = SH(ctx->opcode) | (shn << 5);
1846 mb = MB(ctx->opcode) | (mbn << 5);
1847 gen_rldinm(ctx, mb, 63 - sh, sh);
1848 }
1849 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1850
1851 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1852 uint32_t me)
1853 {
1854 TCGv t0;
1855
1856 mb = MB(ctx->opcode);
1857 me = ME(ctx->opcode);
1858 t0 = tcg_temp_new();
1859 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1860 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1861 if (unlikely(mb != 0 || me != 63)) {
1862 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1863 } else {
1864 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1865 }
1866 tcg_temp_free(t0);
1867 if (unlikely(Rc(ctx->opcode) != 0))
1868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1869 }
1870
1871 /* rldcl - rldcl. */
1872 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1873 {
1874 uint32_t mb;
1875
1876 mb = MB(ctx->opcode) | (mbn << 5);
1877 gen_rldnm(ctx, mb, 63);
1878 }
1879 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1880 /* rldcr - rldcr. */
1881 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1882 {
1883 uint32_t me;
1884
1885 me = MB(ctx->opcode) | (men << 5);
1886 gen_rldnm(ctx, 0, me);
1887 }
1888 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1889 /* rldimi - rldimi. */
1890 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1891 {
1892 uint32_t sh, mb, me;
1893
1894 sh = SH(ctx->opcode) | (shn << 5);
1895 mb = MB(ctx->opcode) | (mbn << 5);
1896 me = 63 - sh;
1897 if (unlikely(sh == 0 && mb == 0)) {
1898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1899 } else {
1900 TCGv t0, t1;
1901 target_ulong mask;
1902
1903 t0 = tcg_temp_new();
1904 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1905 t1 = tcg_temp_new();
1906 mask = MASK(mb, me);
1907 tcg_gen_andi_tl(t0, t0, mask);
1908 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1909 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1910 tcg_temp_free(t0);
1911 tcg_temp_free(t1);
1912 }
1913 if (unlikely(Rc(ctx->opcode) != 0))
1914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1915 }
1916 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1917 #endif
1918
1919 /*** Integer shift ***/
1920 /* slw & slw. */
1921 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1922 {
1923 TCGv t0;
1924 int l1, l2;
1925 l1 = gen_new_label();
1926 l2 = gen_new_label();
1927
1928 t0 = tcg_temp_local_new();
1929 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1930 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1931 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1932 tcg_gen_br(l2);
1933 gen_set_label(l1);
1934 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1935 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1936 gen_set_label(l2);
1937 tcg_temp_free(t0);
1938 if (unlikely(Rc(ctx->opcode) != 0))
1939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1940 }
1941 /* sraw & sraw. */
1942 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1943 {
1944 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1945 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948 }
1949 /* srawi & srawi. */
1950 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1951 {
1952 int sh = SH(ctx->opcode);
1953 if (sh != 0) {
1954 int l1, l2;
1955 TCGv t0;
1956 l1 = gen_new_label();
1957 l2 = gen_new_label();
1958 t0 = tcg_temp_local_new();
1959 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1960 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1961 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1962 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1963 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1964 tcg_gen_br(l2);
1965 gen_set_label(l1);
1966 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1967 gen_set_label(l2);
1968 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1969 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1970 tcg_temp_free(t0);
1971 } else {
1972 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1973 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1974 }
1975 if (unlikely(Rc(ctx->opcode) != 0))
1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1977 }
1978 /* srw & srw. */
1979 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1980 {
1981 TCGv t0, t1;
1982 int l1, l2;
1983 l1 = gen_new_label();
1984 l2 = gen_new_label();
1985
1986 t0 = tcg_temp_local_new();
1987 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1988 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1989 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1990 tcg_gen_br(l2);
1991 gen_set_label(l1);
1992 t1 = tcg_temp_new();
1993 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1994 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1995 tcg_temp_free(t1);
1996 gen_set_label(l2);
1997 tcg_temp_free(t0);
1998 if (unlikely(Rc(ctx->opcode) != 0))
1999 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2000 }
2001 #if defined(TARGET_PPC64)
2002 /* sld & sld. */
2003 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2004 {
2005 TCGv t0;
2006 int l1, l2;
2007 l1 = gen_new_label();
2008 l2 = gen_new_label();
2009
2010 t0 = tcg_temp_local_new();
2011 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2012 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2013 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2014 tcg_gen_br(l2);
2015 gen_set_label(l1);
2016 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2017 gen_set_label(l2);
2018 tcg_temp_free(t0);
2019 if (unlikely(Rc(ctx->opcode) != 0))
2020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2021 }
2022 /* srad & srad. */
2023 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2024 {
2025 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2026 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029 }
2030 /* sradi & sradi. */
2031 static always_inline void gen_sradi (DisasContext *ctx, int n)
2032 {
2033 int sh = SH(ctx->opcode) + (n << 5);
2034 if (sh != 0) {
2035 int l1, l2;
2036 TCGv t0;
2037 l1 = gen_new_label();
2038 l2 = gen_new_label();
2039 t0 = tcg_temp_local_new();
2040 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2041 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2042 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2043 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2044 tcg_gen_br(l2);
2045 gen_set_label(l1);
2046 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2047 gen_set_label(l2);
2048 tcg_temp_free(t0);
2049 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2050 } else {
2051 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2052 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2053 }
2054 if (unlikely(Rc(ctx->opcode) != 0))
2055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2056 }
2057 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2058 {
2059 gen_sradi(ctx, 0);
2060 }
2061 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2062 {
2063 gen_sradi(ctx, 1);
2064 }
2065 /* srd & srd. */
2066 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2067 {
2068 TCGv t0;
2069 int l1, l2;
2070 l1 = gen_new_label();
2071 l2 = gen_new_label();
2072
2073 t0 = tcg_temp_local_new();
2074 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2075 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2076 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2077 tcg_gen_br(l2);
2078 gen_set_label(l1);
2079 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2080 gen_set_label(l2);
2081 tcg_temp_free(t0);
2082 if (unlikely(Rc(ctx->opcode) != 0))
2083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2084 }
2085 #endif
2086
2087 /*** Floating-Point arithmetic ***/
2088 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2089 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2090 { \
2091 if (unlikely(!ctx->fpu_enabled)) { \
2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
2093 return; \
2094 } \
2095 /* NIP cannot be restored if the memory exception comes from an helper */ \
2096 gen_update_nip(ctx, ctx->nip - 4); \
2097 gen_reset_fpstatus(); \
2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2100 if (isfloat) { \
2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2102 } \
2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2104 Rc(ctx->opcode) != 0); \
2105 }
2106
2107 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2108 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2109 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2110
2111 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2112 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2113 { \
2114 if (unlikely(!ctx->fpu_enabled)) { \
2115 gen_exception(ctx, POWERPC_EXCP_FPU); \
2116 return; \
2117 } \
2118 /* NIP cannot be restored if the memory exception comes from an helper */ \
2119 gen_update_nip(ctx, ctx->nip - 4); \
2120 gen_reset_fpstatus(); \
2121 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2122 cpu_fpr[rB(ctx->opcode)]); \
2123 if (isfloat) { \
2124 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2125 } \
2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2127 set_fprf, Rc(ctx->opcode) != 0); \
2128 }
2129 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2130 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2131 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2132
2133 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2134 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2135 { \
2136 if (unlikely(!ctx->fpu_enabled)) { \
2137 gen_exception(ctx, POWERPC_EXCP_FPU); \
2138 return; \
2139 } \
2140 /* NIP cannot be restored if the memory exception comes from an helper */ \
2141 gen_update_nip(ctx, ctx->nip - 4); \
2142 gen_reset_fpstatus(); \
2143 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2144 cpu_fpr[rC(ctx->opcode)]); \
2145 if (isfloat) { \
2146 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
2147 } \
2148 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2149 set_fprf, Rc(ctx->opcode) != 0); \
2150 }
2151 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2152 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2153 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2154
2155 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2156 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2157 { \
2158 if (unlikely(!ctx->fpu_enabled)) { \
2159 gen_exception(ctx, POWERPC_EXCP_FPU); \
2160 return; \
2161 } \
2162 /* NIP cannot be restored if the memory exception comes from an helper */ \
2163 gen_update_nip(ctx, ctx->nip - 4); \
2164 gen_reset_fpstatus(); \
2165 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2167 set_fprf, Rc(ctx->opcode) != 0); \
2168 }
2169
2170 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2171 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2172 { \
2173 if (unlikely(!ctx->fpu_enabled)) { \
2174 gen_exception(ctx, POWERPC_EXCP_FPU); \
2175 return; \
2176 } \
2177 /* NIP cannot be restored if the memory exception comes from an helper */ \
2178 gen_update_nip(ctx, ctx->nip - 4); \
2179 gen_reset_fpstatus(); \
2180 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2181 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2182 set_fprf, Rc(ctx->opcode) != 0); \
2183 }
2184
2185 /* fadd - fadds */
2186 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2187 /* fdiv - fdivs */
2188 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2189 /* fmul - fmuls */
2190 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2191
2192 /* fre */
2193 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2194
2195 /* fres */
2196 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2197
2198 /* frsqrte */
2199 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2200
2201 /* frsqrtes */
2202 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
2203 {
2204 if (unlikely(!ctx->fpu_enabled)) {
2205 gen_exception(ctx, POWERPC_EXCP_FPU);
2206 return;
2207 }
2208 /* NIP cannot be restored if the memory exception comes from an helper */
2209 gen_update_nip(ctx, ctx->nip - 4);
2210 gen_reset_fpstatus();
2211 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2212 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2214 }
2215
2216 /* fsel */
2217 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2218 /* fsub - fsubs */
2219 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2220 /* Optional: */
2221 /* fsqrt */
2222 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2223 {
2224 if (unlikely(!ctx->fpu_enabled)) {
2225 gen_exception(ctx, POWERPC_EXCP_FPU);
2226 return;
2227 }
2228 /* NIP cannot be restored if the memory exception comes from an helper */
2229 gen_update_nip(ctx, ctx->nip - 4);
2230 gen_reset_fpstatus();
2231 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2233 }
2234
2235 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2236 {
2237 if (unlikely(!ctx->fpu_enabled)) {
2238 gen_exception(ctx, POWERPC_EXCP_FPU);
2239 return;
2240 }
2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
2243 gen_reset_fpstatus();
2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2245 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2247 }
2248
2249 /*** Floating-Point multiply-and-add ***/
2250 /* fmadd - fmadds */
2251 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2252 /* fmsub - fmsubs */
2253 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2254 /* fnmadd - fnmadds */
2255 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2256 /* fnmsub - fnmsubs */
2257 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2258
2259 /*** Floating-Point round & convert ***/
2260 /* fctiw */
2261 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2262 /* fctiwz */
2263 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2264 /* frsp */
2265 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2266 #if defined(TARGET_PPC64)
2267 /* fcfid */
2268 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2269 /* fctid */
2270 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2271 /* fctidz */
2272 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2273 #endif
2274
2275 /* frin */
2276 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2277 /* friz */
2278 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2279 /* frip */
2280 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2281 /* frim */
2282 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2283
2284 /*** Floating-Point compare ***/
2285 /* fcmpo */
2286 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2287 {
2288 TCGv_i32 crf;
2289 if (unlikely(!ctx->fpu_enabled)) {
2290 gen_exception(ctx, POWERPC_EXCP_FPU);
2291 return;
2292 }
2293 /* NIP cannot be restored if the memory exception comes from an helper */
2294 gen_update_nip(ctx, ctx->nip - 4);
2295 gen_reset_fpstatus();
2296 crf = tcg_const_i32(crfD(ctx->opcode));
2297 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2298 tcg_temp_free_i32(crf);
2299 gen_helper_float_check_status();
2300 }
2301
2302 /* fcmpu */
2303 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2304 {
2305 TCGv_i32 crf;
2306 if (unlikely(!ctx->fpu_enabled)) {
2307 gen_exception(ctx, POWERPC_EXCP_FPU);
2308 return;
2309 }
2310 /* NIP cannot be restored if the memory exception comes from an helper */
2311 gen_update_nip(ctx, ctx->nip - 4);
2312 gen_reset_fpstatus();
2313 crf = tcg_const_i32(crfD(ctx->opcode));
2314 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
2315 tcg_temp_free_i32(crf);
2316 gen_helper_float_check_status();
2317 }
2318
2319 /*** Floating-point move ***/
2320 /* fabs */
2321 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2322 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2323
2324 /* fmr - fmr. */
2325 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2326 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2327 {
2328 if (unlikely(!ctx->fpu_enabled)) {
2329 gen_exception(ctx, POWERPC_EXCP_FPU);
2330 return;
2331 }
2332 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2333 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2334 }
2335
2336 /* fnabs */
2337 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2338 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2339 /* fneg */
2340 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2341 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2342
2343 /*** Floating-Point status & ctrl register ***/
2344 /* mcrfs */
2345 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2346 {
2347 int bfa;
2348
2349 if (unlikely(!ctx->fpu_enabled)) {
2350 gen_exception(ctx, POWERPC_EXCP_FPU);
2351 return;
2352 }
2353 bfa = 4 * (7 - crfS(ctx->opcode));
2354 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2355 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2356 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2357 }
2358
2359 /* mffs */
2360 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2361 {
2362 if (unlikely(!ctx->fpu_enabled)) {
2363 gen_exception(ctx, POWERPC_EXCP_FPU);
2364 return;
2365 }
2366 gen_reset_fpstatus();
2367 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2368 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2369 }
2370
2371 /* mtfsb0 */
2372 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2373 {
2374 uint8_t crb;
2375
2376 if (unlikely(!ctx->fpu_enabled)) {
2377 gen_exception(ctx, POWERPC_EXCP_FPU);
2378 return;
2379 }
2380 crb = 31 - crbD(ctx->opcode);
2381 gen_reset_fpstatus();
2382 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2383 TCGv_i32 t0;
2384 /* NIP cannot be restored if the memory exception comes from an helper */
2385 gen_update_nip(ctx, ctx->nip - 4);
2386 t0 = tcg_const_i32(crb);
2387 gen_helper_fpscr_clrbit(t0);
2388 tcg_temp_free_i32(t0);
2389 }
2390 if (unlikely(Rc(ctx->opcode) != 0)) {
2391 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2392 }
2393 }
2394
2395 /* mtfsb1 */
2396 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2397 {
2398 uint8_t crb;
2399
2400 if (unlikely(!ctx->fpu_enabled)) {
2401 gen_exception(ctx, POWERPC_EXCP_FPU);
2402 return;
2403 }
2404 crb = 31 - crbD(ctx->opcode);
2405 gen_reset_fpstatus();
2406 /* XXX: we pretend we can only do IEEE floating-point computations */
2407 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2408 TCGv_i32 t0;
2409 /* NIP cannot be restored if the memory exception comes from an helper */
2410 gen_update_nip(ctx, ctx->nip - 4);
2411 t0 = tcg_const_i32(crb);
2412 gen_helper_fpscr_setbit(t0);
2413 tcg_temp_free_i32(t0);
2414 }
2415 if (unlikely(Rc(ctx->opcode) != 0)) {
2416 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2417 }
2418 /* We can raise a differed exception */
2419 gen_helper_float_check_status();
2420 }
2421
2422 /* mtfsf */
2423 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT)
2424 {
2425 TCGv_i32 t0;
2426 int L = ctx->opcode & 0x02000000;
2427
2428 if (unlikely(!ctx->fpu_enabled)) {
2429 gen_exception(ctx, POWERPC_EXCP_FPU);
2430 return;
2431 }
2432 /* NIP cannot be restored if the memory exception comes from an helper */
2433 gen_update_nip(ctx, ctx->nip - 4);
2434 gen_reset_fpstatus();
2435 if (L)
2436 t0 = tcg_const_i32(0xff);
2437 else
2438 t0 = tcg_const_i32(FM(ctx->opcode));
2439 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
2440 tcg_temp_free_i32(t0);
2441 if (unlikely(Rc(ctx->opcode) != 0)) {
2442 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2443 }
2444 /* We can raise a differed exception */
2445 gen_helper_float_check_status();
2446 }
2447
2448 /* mtfsfi */
2449 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2450 {
2451 int bf, sh;
2452 TCGv_i64 t0;
2453 TCGv_i32 t1;
2454
2455 if (unlikely(!ctx->fpu_enabled)) {
2456 gen_exception(ctx, POWERPC_EXCP_FPU);
2457 return;
2458 }
2459 bf = crbD(ctx->opcode) >> 2;
2460 sh = 7 - bf;
2461 /* NIP cannot be restored if the memory exception comes from an helper */
2462 gen_update_nip(ctx, ctx->nip - 4);
2463 gen_reset_fpstatus();
2464 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2465 t1 = tcg_const_i32(1 << sh);
2466 gen_helper_store_fpscr(t0, t1);
2467 tcg_temp_free_i64(t0);
2468 tcg_temp_free_i32(t1);
2469 if (unlikely(Rc(ctx->opcode) != 0)) {
2470 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2471 }
2472 /* We can raise a differed exception */
2473 gen_helper_float_check_status();
2474 }
2475
2476 /*** Addressing modes ***/
2477 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2478 static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
2479 {
2480 target_long simm = SIMM(ctx->opcode);
2481
2482 simm &= ~maskl;
2483 if (rA(ctx->opcode) == 0) {
2484 #if defined(TARGET_PPC64)
2485 if (!ctx->sf_mode) {
2486 tcg_gen_movi_tl(EA, (uint32_t)simm);
2487 } else
2488 #endif
2489 tcg_gen_movi_tl(EA, simm);
2490 } else if (likely(simm != 0)) {
2491 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2492 #if defined(TARGET_PPC64)
2493 if (!ctx->sf_mode) {
2494 tcg_gen_ext32u_tl(EA, EA);
2495 }
2496 #endif
2497 } else {
2498 #if defined(TARGET_PPC64)
2499 if (!ctx->sf_mode) {
2500 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2501 } else
2502 #endif
2503 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2504 }
2505 }
2506
2507 static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
2508 {
2509 if (rA(ctx->opcode) == 0) {
2510 #if defined(TARGET_PPC64)
2511 if (!ctx->sf_mode) {
2512 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2513 } else
2514 #endif
2515 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2516 } else {
2517 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2518 #if defined(TARGET_PPC64)
2519 if (!ctx->sf_mode) {
2520 tcg_gen_ext32u_tl(EA, EA);
2521 }
2522 #endif
2523 }
2524 }
2525
2526 static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
2527 {
2528 if (rA(ctx->opcode) == 0) {
2529 tcg_gen_movi_tl(EA, 0);
2530 } else {
2531 #if defined(TARGET_PPC64)
2532 if (!ctx->sf_mode) {
2533 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2534 } else
2535 #endif
2536 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2537 }
2538 }
2539
2540 static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2541 {
2542 tcg_gen_addi_tl(ret, arg1, val);
2543 #if defined(TARGET_PPC64)
2544 if (!ctx->sf_mode) {
2545 tcg_gen_ext32u_tl(ret, ret);
2546 }
2547 #endif
2548 }
2549
2550 static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2551 {
2552 int l1 = gen_new_label();
2553 TCGv t0 = tcg_temp_new();
2554 TCGv_i32 t1, t2;
2555 /* NIP cannot be restored if the memory exception comes from an helper */
2556 gen_update_nip(ctx, ctx->nip - 4);
2557 tcg_gen_andi_tl(t0, EA, mask);
2558 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2559 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2560 t2 = tcg_const_i32(0);
2561 gen_helper_raise_exception_err(t1, t2);
2562 tcg_temp_free_i32(t1);
2563 tcg_temp_free_i32(t2);
2564 gen_set_label(l1);
2565 tcg_temp_free(t0);
2566 }
2567
2568 /*** Integer load ***/
2569 static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2570 {
2571 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2572 }
2573
2574 static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2575 {
2576 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2577 }
2578
2579 static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2580 {
2581 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2582 if (unlikely(ctx->le_mode)) {
2583 #if defined(TARGET_PPC64)
2584 TCGv_i32 t0 = tcg_temp_new_i32();
2585 tcg_gen_trunc_tl_i32(t0, arg1);
2586 tcg_gen_bswap16_i32(t0, t0);
2587 tcg_gen_extu_i32_tl(arg1, t0);
2588 tcg_temp_free_i32(t0);
2589 #else
2590 tcg_gen_bswap16_i32(arg1, arg1);
2591 #endif
2592 }
2593 }
2594
2595 static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2596 {
2597 if (unlikely(ctx->le_mode)) {
2598 #if defined(TARGET_PPC64)
2599 TCGv_i32 t0;
2600 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2601 t0 = tcg_temp_new_i32();
2602 tcg_gen_trunc_tl_i32(t0, arg1);
2603 tcg_gen_bswap16_i32(t0, t0);
2604 tcg_gen_extu_i32_tl(arg1, t0);
2605 tcg_gen_ext16s_tl(arg1, arg1);
2606 tcg_temp_free_i32(t0);
2607 #else
2608 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2609 tcg_gen_bswap16_i32(arg1, arg1);
2610 tcg_gen_ext16s_i32(arg1, arg1);
2611 #endif
2612 } else {
2613 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2614 }
2615 }
2616
2617 static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2618 {
2619 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2620 if (unlikely(ctx->le_mode)) {
2621 #if defined(TARGET_PPC64)
2622 TCGv_i32 t0 = tcg_temp_new_i32();
2623 tcg_gen_trunc_tl_i32(t0, arg1);
2624 tcg_gen_bswap_i32(t0, t0);
2625 tcg_gen_extu_i32_tl(arg1, t0);
2626 tcg_temp_free_i32(t0);
2627 #else
2628 tcg_gen_bswap_i32(arg1, arg1);
2629 #endif
2630 }
2631 }
2632
2633 #if defined(TARGET_PPC64)
2634 static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2635 {
2636 if (unlikely(ctx->le_mode)) {
2637 TCGv_i32 t0;
2638 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2639 t0 = tcg_temp_new_i32();
2640 tcg_gen_trunc_tl_i32(t0, arg1);
2641 tcg_gen_bswap_i32(t0, t0);
2642 tcg_gen_ext_i32_tl(arg1, t0);
2643 tcg_temp_free_i32(t0);
2644 } else
2645 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2646 }
2647 #endif
2648
2649 static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2650 {
2651 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2652 if (unlikely(ctx->le_mode)) {
2653 tcg_gen_bswap_i64(arg1, arg1);
2654 }
2655 }
2656
2657 static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2658 {
2659 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2660 }
2661
2662 static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2663 {
2664 if (unlikely(ctx->le_mode)) {
2665 #if defined(TARGET_PPC64)
2666 TCGv_i32 t0;
2667 TCGv t1;
2668 t0 = tcg_temp_new_i32();
2669 tcg_gen_trunc_tl_i32(t0, arg1);
2670 tcg_gen_ext16u_i32(t0, t0);
2671 tcg_gen_bswap16_i32(t0, t0);
2672 t1 = tcg_temp_new();
2673 tcg_gen_extu_i32_tl(t1, t0);
2674 tcg_temp_free_i32(t0);
2675 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2676 tcg_temp_free(t1);
2677 #else
2678 TCGv t0 = tcg_temp_new();
2679 tcg_gen_ext16u_tl(t0, arg1);
2680 tcg_gen_bswap16_i32(t0, t0);
2681 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2682 tcg_temp_free(t0);
2683 #endif
2684 } else {
2685 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2686 }
2687 }
2688
2689 static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2690 {
2691 if (unlikely(ctx->le_mode)) {
2692 #if defined(TARGET_PPC64)
2693 TCGv_i32 t0;
2694 TCGv t1;
2695 t0 = tcg_temp_new_i32();
2696 tcg_gen_trunc_tl_i32(t0, arg1);
2697 tcg_gen_bswap_i32(t0, t0);
2698 t1 = tcg_temp_new();
2699 tcg_gen_extu_i32_tl(t1, t0);
2700 tcg_temp_free_i32(t0);
2701 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2702 tcg_temp_free(t1);
2703 #else
2704 TCGv t0 = tcg_temp_new_i32();
2705 tcg_gen_bswap_i32(t0, arg1);
2706 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2707 tcg_temp_free(t0);
2708 #endif
2709 } else {
2710 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2711 }
2712 }
2713
2714 static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2715 {
2716 if (unlikely(ctx->le_mode)) {
2717 TCGv_i64 t0 = tcg_temp_new_i64();
2718 tcg_gen_bswap_i64(t0, arg1);
2719 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2720 tcg_temp_free_i64(t0);
2721 } else
2722 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2723 }
2724
2725 #define GEN_LD(name, ldop, opc, type) \
2726 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2727 { \
2728 TCGv EA; \
2729 gen_set_access_type(ctx, ACCESS_INT); \
2730 EA = tcg_temp_new(); \
2731 gen_addr_imm_index(ctx, EA, 0); \
2732 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2733 tcg_temp_free(EA); \
2734 }
2735
2736 #define GEN_LDU(name, ldop, opc, type) \
2737 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2738 { \
2739 TCGv EA; \
2740 if (unlikely(rA(ctx->opcode) == 0 || \
2741 rA(ctx->opcode) == rD(ctx->opcode))) { \
2742 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2743 return; \
2744 } \
2745 gen_set_access_type(ctx, ACCESS_INT); \
2746 EA = tcg_temp_new(); \
2747 if (type == PPC_64B) \
2748 gen_addr_imm_index(ctx, EA, 0x03); \
2749 else \
2750 gen_addr_imm_index(ctx, EA, 0); \
2751 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2752 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2753 tcg_temp_free(EA); \
2754 }
2755
2756 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2757 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2758 { \
2759 TCGv EA; \
2760 if (unlikely(rA(ctx->opcode) == 0 || \
2761 rA(ctx->opcode) == rD(ctx->opcode))) { \
2762 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2763 return; \
2764 } \
2765 gen_set_access_type(ctx, ACCESS_INT); \
2766 EA = tcg_temp_new(); \
2767 gen_addr_reg_index(ctx, EA); \
2768 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2771 }
2772
2773 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2774 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2775 { \
2776 TCGv EA; \
2777 gen_set_access_type(ctx, ACCESS_INT); \
2778 EA = tcg_temp_new(); \
2779 gen_addr_reg_index(ctx, EA); \
2780 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2781 tcg_temp_free(EA); \
2782 }
2783
2784 #define GEN_LDS(name, ldop, op, type) \
2785 GEN_LD(name, ldop, op | 0x20, type); \
2786 GEN_LDU(name, ldop, op | 0x21, type); \
2787 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2788 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2789
2790 /* lbz lbzu lbzux lbzx */
2791 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2792 /* lha lhau lhaux lhax */
2793 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2794 /* lhz lhzu lhzux lhzx */
2795 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2796 /* lwz lwzu lwzux lwzx */
2797 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2798 #if defined(TARGET_PPC64)
2799 /* lwaux */
2800 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2801 /* lwax */
2802 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2803 /* ldux */
2804 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2805 /* ldx */
2806 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2807 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2808 {
2809 TCGv EA;
2810 if (Rc(ctx->opcode)) {
2811 if (unlikely(rA(ctx->opcode) == 0 ||
2812 rA(ctx->opcode) == rD(ctx->opcode))) {
2813 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2814 return;
2815 }
2816 }
2817 gen_set_access_type(ctx, ACCESS_INT);
2818 EA = tcg_temp_new();
2819 gen_addr_imm_index(ctx, EA, 0x03);
2820 if (ctx->opcode & 0x02) {
2821 /* lwa (lwau is undefined) */
2822 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2823 } else {
2824 /* ld - ldu */
2825 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2826 }
2827 if (Rc(ctx->opcode))
2828 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2829 tcg_temp_free(EA);
2830 }
2831 /* lq */
2832 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2833 {
2834 #if defined(CONFIG_USER_ONLY)
2835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2836 #else
2837 int ra, rd;
2838 TCGv EA;
2839
2840 /* Restore CPU state */
2841 if (unlikely(ctx->mem_idx == 0)) {
2842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2843 return;
2844 }
2845 ra = rA(ctx->opcode);
2846 rd = rD(ctx->opcode);
2847 if (unlikely((rd & 1) || rd == ra)) {
2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2849 return;
2850 }
2851 if (unlikely(ctx->le_mode)) {
2852 /* Little-endian mode is not handled */
2853 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2854 return;
2855 }
2856 gen_set_access_type(ctx, ACCESS_INT);
2857 EA = tcg_temp_new();
2858 gen_addr_imm_index(ctx, EA, 0x0F);
2859 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2860 gen_addr_add(ctx, EA, EA, 8);
2861 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2862 tcg_temp_free(EA);
2863 #endif
2864 }
2865 #endif
2866
2867 /*** Integer store ***/
2868 #define GEN_ST(name, stop, opc, type) \
2869 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
2870 { \
2871 TCGv EA; \
2872 gen_set_access_type(ctx, ACCESS_INT); \
2873 EA = tcg_temp_new(); \
2874 gen_addr_imm_index(ctx, EA, 0); \
2875 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2876 tcg_temp_free(EA); \
2877 }
2878
2879 #define GEN_STU(name, stop, opc, type) \
2880 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2881 { \
2882 TCGv EA; \
2883 if (unlikely(rA(ctx->opcode) == 0)) { \
2884 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2885 return; \
2886 } \
2887 gen_set_access_type(ctx, ACCESS_INT); \
2888 EA = tcg_temp_new(); \
2889 if (type == PPC_64B) \
2890 gen_addr_imm_index(ctx, EA, 0x03); \
2891 else \
2892 gen_addr_imm_index(ctx, EA, 0); \
2893 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2894 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2895 tcg_temp_free(EA); \
2896 }
2897
2898 #define GEN_STUX(name, stop, opc2, opc3, type) \
2899 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2900 { \
2901 TCGv EA; \
2902 if (unlikely(rA(ctx->opcode) == 0)) { \
2903 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2904 return; \
2905 } \
2906 gen_set_access_type(ctx, ACCESS_INT); \
2907 EA = tcg_temp_new(); \
2908 gen_addr_reg_index(ctx, EA); \
2909 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2910 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2911 tcg_temp_free(EA); \
2912 }
2913
2914 #define GEN_STX(name, stop, opc2, opc3, type) \
2915 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
2916 { \
2917 TCGv EA; \
2918 gen_set_access_type(ctx, ACCESS_INT); \
2919 EA = tcg_temp_new(); \
2920 gen_addr_reg_index(ctx, EA); \
2921 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2922 tcg_temp_free(EA); \
2923 }
2924
2925 #define GEN_STS(name, stop, op, type) \
2926 GEN_ST(name, stop, op | 0x20, type); \
2927 GEN_STU(name, stop, op | 0x21, type); \
2928 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2929 GEN_STX(name, stop, 0x17, op | 0x00, type)
2930
2931 /* stb stbu stbux stbx */
2932 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2933 /* sth sthu sthux sthx */
2934 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2935 /* stw stwu stwux stwx */
2936 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2937 #if defined(TARGET_PPC64)
2938 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2939 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2940 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2941 {
2942 int rs;
2943 TCGv EA;
2944
2945 rs = rS(ctx->opcode);
2946 if ((ctx->opcode & 0x3) == 0x2) {
2947 #if defined(CONFIG_USER_ONLY)
2948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2949 #else
2950 /* stq */
2951 if (unlikely(ctx->mem_idx == 0)) {
2952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2953 return;
2954 }
2955 if (unlikely(rs & 1)) {
2956 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2957 return;
2958 }
2959 if (unlikely(ctx->le_mode)) {
2960 /* Little-endian mode is not handled */
2961 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2962 return;
2963 }
2964 gen_set_access_type(ctx, ACCESS_INT);
2965 EA = tcg_temp_new();
2966 gen_addr_imm_index(ctx, EA, 0x03);
2967 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2968 gen_addr_add(ctx, EA, EA, 8);
2969 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2970 tcg_temp_free(EA);
2971 #endif
2972 } else {
2973 /* std / stdu */
2974 if (Rc(ctx->opcode)) {
2975 if (unlikely(rA(ctx->opcode) == 0)) {
2976 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2977 return;
2978 }
2979 }
2980 gen_set_access_type(ctx, ACCESS_INT);
2981 EA = tcg_temp_new();
2982 gen_addr_imm_index(ctx, EA, 0x03);
2983 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2984 if (Rc(ctx->opcode))
2985 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2986 tcg_temp_free(EA);
2987 }
2988 }
2989 #endif
2990 /*** Integer load and store with byte reverse ***/
2991 /* lhbrx */
2992 static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2993 {
2994 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2995 if (likely(!ctx->le_mode)) {
2996 #if defined(TARGET_PPC64)
2997 TCGv_i32 t0 = tcg_temp_new_i32();
2998 tcg_gen_trunc_tl_i32(t0, arg1);
2999 tcg_gen_bswap16_i32(t0, t0);
3000 tcg_gen_extu_i32_tl(arg1, t0);
3001 tcg_temp_free_i32(t0);
3002 #else
3003 tcg_gen_bswap16_i32(arg1, arg1);
3004 #endif
3005 }
3006 }
3007 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3008
3009 /* lwbrx */
3010 static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3011 {
3012 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3013 if (likely(!ctx->le_mode)) {
3014 #if defined(TARGET_PPC64)
3015 TCGv_i32 t0 = tcg_temp_new_i32();
3016 tcg_gen_trunc_tl_i32(t0, arg1);
3017 tcg_gen_bswap_i32(t0, t0);
3018 tcg_gen_extu_i32_tl(arg1, t0);
3019 tcg_temp_free_i32(t0);
3020 #else
3021 tcg_gen_bswap_i32(arg1, arg1);
3022 #endif
3023 }
3024 }
3025 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3026
3027 /* sthbrx */
3028 static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3029 {
3030 if (likely(!ctx->le_mode)) {
3031 #if defined(TARGET_PPC64)
3032 TCGv_i32 t0;
3033 TCGv t1;
3034 t0 = tcg_temp_new_i32();
3035 tcg_gen_trunc_tl_i32(t0, arg1);
3036 tcg_gen_ext16u_i32(t0, t0);
3037 tcg_gen_bswap16_i32(t0, t0);
3038 t1 = tcg_temp_new();
3039 tcg_gen_extu_i32_tl(t1, t0);
3040 tcg_temp_free_i32(t0);
3041 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3042 tcg_temp_free(t1);
3043 #else
3044 TCGv t0 = tcg_temp_new();
3045 tcg_gen_ext16u_tl(t0, arg1);
3046 tcg_gen_bswap16_i32(t0, t0);
3047 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3048 tcg_temp_free(t0);
3049 #endif
3050 } else {
3051 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3052 }
3053 }
3054 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3055
3056 /* stwbrx */
3057 static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3058 {
3059 if (likely(!ctx->le_mode)) {
3060 #if defined(TARGET_PPC64)
3061 TCGv_i32 t0;
3062 TCGv t1;
3063 t0 = tcg_temp_new_i32();
3064 tcg_gen_trunc_tl_i32(t0, arg1);
3065 tcg_gen_bswap_i32(t0, t0);
3066 t1 = tcg_temp_new();
3067 tcg_gen_extu_i32_tl(t1, t0);
3068 tcg_temp_free_i32(t0);
3069 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3070 tcg_temp_free(t1);
3071 #else
3072 TCGv t0 = tcg_temp_new_i32();
3073 tcg_gen_bswap_i32(t0, arg1);
3074 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3075 tcg_temp_free(t0);
3076 #endif
3077 } else {
3078 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3079 }
3080 }
3081 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3082
3083 /*** Integer load and store multiple ***/
3084 /* lmw */
3085 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3086 {
3087 TCGv t0;
3088 TCGv_i32 t1;
3089 gen_set_access_type(ctx, ACCESS_INT);
3090 /* NIP cannot be restored if the memory exception comes from an helper */
3091 gen_update_nip(ctx, ctx->nip - 4);
3092 t0 = tcg_temp_new();
3093 t1 = tcg_const_i32(rD(ctx->opcode));
3094 gen_addr_imm_index(ctx, t0, 0);
3095 gen_helper_lmw(t0, t1);
3096 tcg_temp_free(t0);
3097 tcg_temp_free_i32(t1);
3098 }
3099
3100 /* stmw */
3101 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3102 {
3103 TCGv t0;
3104 TCGv_i32 t1;
3105 gen_set_access_type(ctx, ACCESS_INT);
3106 /* NIP cannot be restored if the memory exception comes from an helper */
3107 gen_update_nip(ctx, ctx->nip - 4);
3108 t0 = tcg_temp_new();
3109 t1 = tcg_const_i32(rS(ctx->opcode));
3110 gen_addr_imm_index(ctx, t0, 0);
3111 gen_helper_stmw(t0, t1);
3112 tcg_temp_free(t0);
3113 tcg_temp_free_i32(t1);
3114 }
3115
3116 /*** Integer load and store strings ***/
3117 /* lswi */
3118 /* PowerPC32 specification says we must generate an exception if
3119 * rA is in the range of registers to be loaded.
3120 * In an other hand, IBM says this is valid, but rA won't be loaded.
3121 * For now, I'll follow the spec...
3122 */
3123 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3124 {
3125 TCGv t0;
3126 TCGv_i32 t1, t2;
3127 int nb = NB(ctx->opcode);
3128 int start = rD(ctx->opcode);
3129 int ra = rA(ctx->opcode);
3130 int nr;
3131
3132 if (nb == 0)
3133 nb = 32;
3134 nr = nb / 4;
3135 if (unlikely(((start + nr) > 32 &&
3136 start <= ra && (start + nr - 32) > ra) ||
3137 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3138 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3139 return;
3140 }
3141 gen_set_access_type(ctx, ACCESS_INT);
3142 /* NIP cannot be restored if the memory exception comes from an helper */
3143 gen_update_nip(ctx, ctx->nip - 4);
3144 t0 = tcg_temp_new();
3145 gen_addr_register(ctx, t0);
3146 t1 = tcg_const_i32(nb);
3147 t2 = tcg_const_i32(start);
3148 gen_helper_lsw(t0, t1, t2);
3149 tcg_temp_free(t0);
3150 tcg_temp_free_i32(t1);
3151 tcg_temp_free_i32(t2);
3152 }
3153
3154 /* lswx */
3155 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3156 {
3157 TCGv t0;
3158 TCGv_i32 t1, t2, t3;
3159 gen_set_access_type(ctx, ACCESS_INT);
3160 /* NIP cannot be restored if the memory exception comes from an helper */
3161 gen_update_nip(ctx, ctx->nip - 4);
3162 t0 = tcg_temp_new();
3163 gen_addr_reg_index(ctx, t0);
3164 t1 = tcg_const_i32(rD(ctx->opcode));
3165 t2 = tcg_const_i32(rA(ctx->opcode));
3166 t3 = tcg_const_i32(rB(ctx->opcode));
3167 gen_helper_lswx(t0, t1, t2, t3);
3168 tcg_temp_free(t0);
3169 tcg_temp_free_i32(t1);
3170 tcg_temp_free_i32(t2);
3171 tcg_temp_free_i32(t3);
3172 }
3173
3174 /* stswi */
3175 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3176 {
3177 TCGv t0;
3178 TCGv_i32 t1, t2;
3179 int nb = NB(ctx->opcode);
3180 gen_set_access_type(ctx, ACCESS_INT);
3181 /* NIP cannot be restored if the memory exception comes from an helper */
3182 gen_update_nip(ctx, ctx->nip - 4);
3183 t0 = tcg_temp_new();
3184 gen_addr_register(ctx, t0);
3185 if (nb == 0)
3186 nb = 32;
3187 t1 = tcg_const_i32(nb);
3188 t2 = tcg_const_i32(rS(ctx->opcode));
3189 gen_helper_stsw(t0, t1, t2);
3190 tcg_temp_free(t0);
3191 tcg_temp_free_i32(t1);
3192 tcg_temp_free_i32(t2);
3193 }
3194
3195 /* stswx */
3196 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3197 {
3198 TCGv t0;
3199 TCGv_i32 t1, t2;
3200 gen_set_access_type(ctx, ACCESS_INT);
3201 /* NIP cannot be restored if the memory exception comes from an helper */
3202 gen_update_nip(ctx, ctx->nip - 4);
3203 t0 = tcg_temp_new();
3204 gen_addr_reg_index(ctx, t0);
3205 t1 = tcg_temp_new_i32();
3206 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3207 tcg_gen_andi_i32(t1, t1, 0x7F);
3208 t2 = tcg_const_i32(rS(ctx->opcode));
3209 gen_helper_stsw(t0, t1, t2);
3210 tcg_temp_free(t0);
3211 tcg_temp_free_i32(t1);
3212 tcg_temp_free_i32(t2);
3213 }
3214
3215 /*** Memory synchronisation ***/
3216 /* eieio */
3217 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3218 {
3219 }
3220
3221 /* isync */
3222 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3223 {
3224 gen_stop_exception(ctx);
3225 }
3226
3227 /* lwarx */
3228 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3229 {
3230 TCGv t0;
3231 gen_set_access_type(ctx, ACCESS_RES);
3232 t0 = tcg_temp_local_new();
3233 gen_addr_reg_index(ctx, t0);
3234 gen_check_align(ctx, t0, 0x03);
3235 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3236 tcg_gen_mov_tl(cpu_reserve, t0);
3237 tcg_temp_free(t0);
3238 }
3239
3240 /* stwcx. */
3241 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3242 {
3243 int l1;
3244 TCGv t0;
3245 gen_set_access_type(ctx, ACCESS_RES);
3246 t0 = tcg_temp_local_new();
3247 gen_addr_reg_index(ctx, t0);
3248 gen_check_align(ctx, t0, 0x03);
3249 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3250 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3251 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3252 l1 = gen_new_label();
3253 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3254 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3255 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3256 gen_set_label(l1);
3257 tcg_gen_movi_tl(cpu_reserve, -1);
3258 tcg_temp_free(t0);
3259 }
3260
3261 #if defined(TARGET_PPC64)
3262 /* ldarx */
3263 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3264 {
3265 TCGv t0;
3266 gen_set_access_type(ctx, ACCESS_RES);
3267 t0 = tcg_temp_local_new();
3268 gen_addr_reg_index(ctx, t0);
3269 gen_check_align(ctx, t0, 0x07);
3270 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
3271 tcg_gen_mov_tl(cpu_reserve, t0);
3272 tcg_temp_free(t0);
3273 }
3274
3275 /* stdcx. */
3276 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3277 {
3278 int l1;
3279 TCGv t0;
3280 gen_set_access_type(ctx, ACCESS_RES);
3281 t0 = tcg_temp_local_new();
3282 gen_addr_reg_index(ctx, t0);
3283 gen_check_align(ctx, t0, 0x07);
3284 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3285 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3286 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3287 l1 = gen_new_label();
3288 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3289 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3290 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3291 gen_set_label(l1);
3292 tcg_gen_movi_tl(cpu_reserve, -1);
3293 tcg_temp_free(t0);
3294 }
3295 #endif /* defined(TARGET_PPC64) */
3296
3297 /* sync */
3298 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3299 {
3300 }
3301
3302 /* wait */
3303 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3304 {
3305 TCGv_i32 t0 = tcg_temp_new_i32();
3306 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3307 tcg_temp_free_i32(t0);
3308 /* Stop translation, as the CPU is supposed to sleep from now */
3309 gen_exception_err(ctx, EXCP_HLT, 1);
3310 }
3311
3312 /*** Floating-point load ***/
3313 #define GEN_LDF(name, ldop, opc, type) \
3314 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3315 { \
3316 TCGv EA; \
3317 if (unlikely(!ctx->fpu_enabled)) { \
3318 gen_exception(ctx, POWERPC_EXCP_FPU); \
3319 return; \
3320 } \
3321 gen_set_access_type(ctx, ACCESS_FLOAT); \
3322 EA = tcg_temp_new(); \
3323 gen_addr_imm_index(ctx, EA, 0); \
3324 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3325 tcg_temp_free(EA); \
3326 }
3327
3328 #define GEN_LDUF(name, ldop, opc, type) \
3329 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3330 { \
3331 TCGv EA; \
3332 if (unlikely(!ctx->fpu_enabled)) { \
3333 gen_exception(ctx, POWERPC_EXCP_FPU); \
3334 return; \
3335 } \
3336 if (unlikely(rA(ctx->opcode) == 0)) { \
3337 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3338 return; \
3339 } \
3340 gen_set_access_type(ctx, ACCESS_FLOAT); \
3341 EA = tcg_temp_new(); \
3342 gen_addr_imm_index(ctx, EA, 0); \
3343 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3344 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3345 tcg_temp_free(EA); \
3346 }
3347
3348 #define GEN_LDUXF(name, ldop, opc, type) \
3349 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3350 { \
3351 TCGv EA; \
3352 if (unlikely(!ctx->fpu_enabled)) { \
3353 gen_exception(ctx, POWERPC_EXCP_FPU); \
3354 return; \
3355 } \
3356 if (unlikely(rA(ctx->opcode) == 0)) { \
3357 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3358 return; \
3359 } \
3360 gen_set_access_type(ctx, ACCESS_FLOAT); \
3361 EA = tcg_temp_new(); \
3362 gen_addr_reg_index(ctx, EA); \
3363 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3364 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3365 tcg_temp_free(EA); \
3366 }
3367
3368 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3369 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3370 { \
3371 TCGv EA; \
3372 if (unlikely(!ctx->fpu_enabled)) { \
3373 gen_exception(ctx, POWERPC_EXCP_FPU); \
3374 return; \
3375 } \
3376 gen_set_access_type(ctx, ACCESS_FLOAT); \
3377 EA = tcg_temp_new(); \
3378 gen_addr_reg_index(ctx, EA); \
3379 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3380 tcg_temp_free(EA); \
3381 }
3382
3383 #define GEN_LDFS(name, ldop, op, type) \
3384 GEN_LDF(name, ldop, op | 0x20, type); \
3385 GEN_LDUF(name, ldop, op | 0x21, type); \
3386 GEN_LDUXF(name, ldop, op | 0x01, type); \
3387 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3388
3389 static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3390 {
3391 TCGv t0 = tcg_temp_new();
3392 TCGv_i32 t1 = tcg_temp_new_i32();
3393 gen_qemu_ld32u(ctx, t0, arg2);
3394 tcg_gen_trunc_tl_i32(t1, t0);
3395 tcg_temp_free(t0);
3396 gen_helper_float32_to_float64(arg1, t1);
3397 tcg_temp_free_i32(t1);
3398 }
3399
3400 /* lfd lfdu lfdux lfdx */
3401 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3402 /* lfs lfsu lfsux lfsx */
3403 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3404
3405 /*** Floating-point store ***/
3406 #define GEN_STF(name, stop, opc, type) \
3407 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
3408 { \
3409 TCGv EA; \
3410 if (unlikely(!ctx->fpu_enabled)) { \
3411 gen_exception(ctx, POWERPC_EXCP_FPU); \
3412 return; \
3413 } \
3414 gen_set_access_type(ctx, ACCESS_FLOAT); \
3415 EA = tcg_temp_new(); \
3416 gen_addr_imm_index(ctx, EA, 0); \
3417 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3418 tcg_temp_free(EA); \
3419 }
3420
3421 #define GEN_STUF(name, stop, opc, type) \
3422 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3423 { \
3424 TCGv EA; \
3425 if (unlikely(!ctx->fpu_enabled)) { \
3426 gen_exception(ctx, POWERPC_EXCP_FPU); \
3427 return; \
3428 } \
3429 if (unlikely(rA(ctx->opcode) == 0)) { \
3430 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3431 return; \
3432 } \
3433 gen_set_access_type(ctx, ACCESS_FLOAT); \
3434 EA = tcg_temp_new(); \
3435 gen_addr_imm_index(ctx, EA, 0); \
3436 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3437 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3438 tcg_temp_free(EA); \
3439 }
3440
3441 #define GEN_STUXF(name, stop, opc, type) \
3442 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3443 { \
3444 TCGv EA; \
3445 if (unlikely(!ctx->fpu_enabled)) { \
3446 gen_exception(ctx, POWERPC_EXCP_FPU); \
3447 return; \
3448 } \
3449 if (unlikely(rA(ctx->opcode) == 0)) { \
3450 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3451 return; \
3452 } \
3453 gen_set_access_type(ctx, ACCESS_FLOAT); \
3454 EA = tcg_temp_new(); \
3455 gen_addr_reg_index(ctx, EA); \
3456 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3457 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3458 tcg_temp_free(EA); \
3459 }
3460
3461 #define GEN_STXF(name, stop, opc2, opc3, type) \
3462 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
3463 { \
3464 TCGv EA; \
3465 if (unlikely(!ctx->fpu_enabled)) { \
3466 gen_exception(ctx, POWERPC_EXCP_FPU); \
3467 return; \
3468 } \
3469 gen_set_access_type(ctx, ACCESS_FLOAT); \
3470 EA = tcg_temp_new(); \
3471 gen_addr_reg_index(ctx, EA); \
3472 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3473 tcg_temp_free(EA); \
3474 }
3475
3476 #define GEN_STFS(name, stop, op, type) \
3477 GEN_STF(name, stop, op | 0x20, type); \
3478 GEN_STUF(name, stop, op | 0x21, type); \
3479 GEN_STUXF(name, stop, op | 0x01, type); \
3480 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3481
3482 static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3483 {
3484 TCGv_i32 t0 = tcg_temp_new_i32();
3485 TCGv t1 = tcg_temp_new();
3486 gen_helper_float64_to_float32(t0, arg1);
3487 tcg_gen_extu_i32_tl(t1, t0);
3488 tcg_temp_free_i32(t0);
3489 gen_qemu_st32(ctx, t1, arg2);
3490 tcg_temp_free(t1);
3491 }
3492
3493 /* stfd stfdu stfdux stfdx */
3494 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3495 /* stfs stfsu stfsux stfsx */
3496 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3497
3498 /* Optional: */
3499 static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3500 {
3501 TCGv t0 = tcg_temp_new();
3502 tcg_gen_trunc_i64_tl(t0, arg1),
3503 gen_qemu_st32(ctx, t0, arg2);
3504 tcg_temp_free(t0);
3505 }
3506 /* stfiwx */
3507 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3508
3509 /*** Branch ***/
3510 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3511 target_ulong dest)
3512 {
3513 TranslationBlock *tb;
3514 tb = ctx->tb;
3515 #if defined(TARGET_PPC64)
3516 if (!ctx->sf_mode)
3517 dest = (uint32_t) dest;
3518 #endif
3519 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3520 likely(!ctx->singlestep_enabled)) {
3521 tcg_gen_goto_tb(n);
3522 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3523 tcg_gen_exit_tb((long)tb + n);
3524 } else {
3525 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3526 if (unlikely(ctx->singlestep_enabled)) {
3527 if ((ctx->singlestep_enabled &
3528 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3529 ctx->exception == POWERPC_EXCP_BRANCH) {
3530 target_ulong tmp = ctx->nip;
3531 ctx->nip = dest;
3532 gen_exception(ctx, POWERPC_EXCP_TRACE);
3533 ctx->nip = tmp;
3534 }
3535 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3536 gen_debug_exception(ctx);
3537 }
3538 }
3539 tcg_gen_exit_tb(0);
3540 }
3541 }
3542
3543 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3544 {
3545 #if defined(TARGET_PPC64)
3546 if (ctx->sf_mode == 0)
3547 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3548 else
3549 #endif
3550 tcg_gen_movi_tl(cpu_lr, nip);
3551 }
3552
3553 /* b ba bl bla */
3554 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3555 {
3556 target_ulong li, target;
3557
3558 ctx->exception = POWERPC_EXCP_BRANCH;
3559 /* sign extend LI */
3560 #if defined(TARGET_PPC64)
3561 if (ctx->sf_mode)
3562 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3563 else
3564 #endif
3565 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3566 if (likely(AA(ctx->opcode) == 0))
3567 target = ctx->nip + li - 4;
3568 else
3569 target = li;
3570 if (LK(ctx->opcode))
3571 gen_setlr(ctx, ctx->nip);
3572 gen_goto_tb(ctx, 0, target);
3573 }
3574
3575 #define BCOND_IM 0
3576 #define BCOND_LR 1
3577 #define BCOND_CTR 2
3578
3579 static always_inline void gen_bcond (DisasContext *ctx, int type)
3580 {
3581 uint32_t bo = BO(ctx->opcode);
3582 int l1 = gen_new_label();
3583 TCGv target;
3584
3585 ctx->exception = POWERPC_EXCP_BRANCH;
3586 if (type == BCOND_LR || type == BCOND_CTR) {
3587 target = tcg_temp_local_new();
3588 if (type == BCOND_CTR)
3589 tcg_gen_mov_tl(target, cpu_ctr);
3590 else
3591 tcg_gen_mov_tl(target, cpu_lr);
3592 }
3593 if (LK(ctx->opcode))
3594 gen_setlr(ctx, ctx->nip);
3595 l1 = gen_new_label();
3596 if ((bo & 0x4) == 0) {
3597 /* Decrement and test CTR */
3598 TCGv temp = tcg_temp_new();
3599 if (unlikely(type == BCOND_CTR)) {
3600 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3601 return;
3602 }
3603 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3604 #if defined(TARGET_PPC64)
3605 if (!ctx->sf_mode)
3606 tcg_gen_ext32u_tl(temp, cpu_ctr);
3607 else
3608 #endif
3609 tcg_gen_mov_tl(temp, cpu_ctr);
3610 if (bo & 0x2) {
3611 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3612 } else {
3613 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3614 }
3615 tcg_temp_free(temp);
3616 }
3617 if ((bo & 0x10) == 0) {
3618 /* Test CR */
3619 uint32_t bi = BI(ctx->opcode);
3620 uint32_t mask = 1 << (3 - (bi & 0x03));
3621 TCGv_i32 temp = tcg_temp_new_i32();
3622
3623 if (bo & 0x8) {
3624 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3625 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3626 } else {
3627 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3628 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3629 }
3630 tcg_temp_free_i32(temp);
3631 }
3632 if (type == BCOND_IM) {
3633 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3634 if (likely(AA(ctx->opcode) == 0)) {
3635 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3636 } else {
3637 gen_goto_tb(ctx, 0, li);
3638 }
3639 gen_set_label(l1);
3640 gen_goto_tb(ctx, 1, ctx->nip);
3641 } else {
3642 #if defined(TARGET_PPC64)
3643 if (!(ctx->sf_mode))
3644 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3645 else
3646 #endif
3647 tcg_gen_andi_tl(cpu_nip, target, ~3);
3648 tcg_gen_exit_tb(0);
3649 gen_set_label(l1);
3650 #if defined(TARGET_PPC64)
3651 if (!(ctx->sf_mode))
3652 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3653 else
3654 #endif
3655 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3656 tcg_gen_exit_tb(0);
3657 }
3658 }
3659
3660 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3661 {
3662 gen_bcond(ctx, BCOND_IM);
3663 }
3664
3665 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3666 {
3667 gen_bcond(ctx, BCOND_CTR);
3668 }
3669
3670 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3671 {
3672 gen_bcond(ctx, BCOND_LR);
3673 }
3674
3675 /*** Condition register logical ***/
3676 #define GEN_CRLOGIC(name, tcg_op, opc) \
3677 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3678 { \
3679 uint8_t bitmask; \
3680 int sh; \
3681 TCGv_i32 t0, t1; \
3682 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3683 t0 = tcg_temp_new_i32(); \
3684 if (sh > 0) \
3685 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3686 else if (sh < 0) \
3687 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3688 else \
3689 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3690 t1 = tcg_temp_new_i32(); \
3691 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3692 if (sh > 0) \
3693 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3694 else if (sh < 0) \
3695 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3696 else \
3697 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3698 tcg_op(t0, t0, t1); \
3699 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3700 tcg_gen_andi_i32(t0, t0, bitmask); \
3701 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3702 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3703 tcg_temp_free_i32(t0); \
3704 tcg_temp_free_i32(t1); \
3705 }
3706
3707 /* crand */
3708 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3709 /* crandc */
3710 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3711 /* creqv */
3712 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3713 /* crnand */
3714 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3715 /* crnor */
3716 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3717 /* cror */
3718 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3719 /* crorc */
3720 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3721 /* crxor */
3722 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3723 /* mcrf */
3724 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3725 {
3726 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3727 }
3728
3729 /*** System linkage ***/
3730 /* rfi (mem_idx only) */
3731 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3732 {
3733 #if defined(CONFIG_USER_ONLY)
3734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3735 #else
3736 /* Restore CPU state */
3737 if (unlikely(!ctx->mem_idx)) {
3738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3739 return;
3740 }
3741 gen_helper_rfi();
3742 gen_sync_exception(ctx);
3743 #endif
3744 }
3745
3746 #if defined(TARGET_PPC64)
3747 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3748 {
3749 #if defined(CONFIG_USER_ONLY)
3750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3751 #else
3752 /* Restore CPU state */
3753 if (unlikely(!ctx->mem_idx)) {
3754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3755 return;
3756 }
3757 gen_helper_rfid();
3758 gen_sync_exception(ctx);
3759 #endif
3760 }
3761
3762 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3763 {
3764 #if defined(CONFIG_USER_ONLY)
3765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3766 #else
3767 /* Restore CPU state */
3768 if (unlikely(ctx->mem_idx <= 1)) {
3769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3770 return;
3771 }
3772 gen_helper_hrfid();
3773 gen_sync_exception(ctx);
3774 #endif
3775 }
3776 #endif
3777
3778 /* sc */
3779 #if defined(CONFIG_USER_ONLY)
3780 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3781 #else
3782 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3783 #endif
3784 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3785 {
3786 uint32_t lev;
3787
3788 lev = (ctx->opcode >> 5) & 0x7F;
3789 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3790 }
3791
3792 /*** Trap ***/
3793 /* tw */
3794 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3795 {
3796 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3797 /* Update the nip since this might generate a trap exception */
3798 gen_update_nip(ctx, ctx->nip);
3799 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3800 tcg_temp_free_i32(t0);
3801 }
3802
3803 /* twi */
3804 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3805 {
3806 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3807 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3808 /* Update the nip since this might generate a trap exception */
3809 gen_update_nip(ctx, ctx->nip);
3810 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3811 tcg_temp_free(t0);
3812 tcg_temp_free_i32(t1);
3813 }
3814
3815 #if defined(TARGET_PPC64)
3816 /* td */
3817 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3818 {
3819 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3820 /* Update the nip since this might generate a trap exception */
3821 gen_update_nip(ctx, ctx->nip);
3822 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3823 tcg_temp_free_i32(t0);
3824 }
3825
3826 /* tdi */
3827 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3828 {
3829 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3830 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3831 /* Update the nip since this might generate a trap exception */
3832 gen_update_nip(ctx, ctx->nip);
3833 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3834 tcg_temp_free(t0);
3835 tcg_temp_free_i32(t1);
3836 }
3837 #endif
3838
3839 /*** Processor control ***/
3840 /* mcrxr */
3841 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3842 {
3843 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3844 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3845 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3846 }
3847
3848 /* mfcr mfocrf */
3849 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3850 {
3851 uint32_t crm, crn;
3852
3853 if (likely(ctx->opcode & 0x00100000)) {
3854 crm = CRM(ctx->opcode);
3855 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3856 crn = ctz32 (crm);
3857 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3858 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3859 cpu_gpr[rD(ctx->opcode)], crn * 4);
3860 }
3861 } else {
3862 TCGv_i32 t0 = tcg_temp_new_i32();
3863 tcg_gen_mov_i32(t0, cpu_crf[0]);
3864 tcg_gen_shli_i32(t0, t0, 4);
3865 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3866 tcg_gen_shli_i32(t0, t0, 4);
3867 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3868 tcg_gen_shli_i32(t0, t0, 4);
3869 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3870 tcg_gen_shli_i32(t0, t0, 4);
3871 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3872 tcg_gen_shli_i32(t0, t0, 4);
3873 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3874 tcg_gen_shli_i32(t0, t0, 4);
3875 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3876 tcg_gen_shli_i32(t0, t0, 4);
3877 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3878 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3879 tcg_temp_free_i32(t0);
3880 }
3881 }
3882
3883 /* mfmsr */
3884 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3885 {
3886 #if defined(CONFIG_USER_ONLY)
3887 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3888 #else
3889 if (unlikely(!ctx->mem_idx)) {
3890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3891 return;
3892 }
3893 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3894 #endif
3895 }
3896
3897 #if 1
3898 #define SPR_NOACCESS ((void *)(-1UL))
3899 #else
3900 static void spr_noaccess (void *opaque, int sprn)
3901 {
3902 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3903 printf("ERROR: try to access SPR %d !\n", sprn);
3904 }
3905 #define SPR_NOACCESS (&spr_noaccess)
3906 #endif
3907
3908 /* mfspr */
3909 static always_inline void gen_op_mfspr (DisasContext *ctx)
3910 {
3911 void (*read_cb)(void *opaque, int gprn, int sprn);
3912 uint32_t sprn = SPR(ctx->opcode);
3913
3914 #if !defined(CONFIG_USER_ONLY)
3915 if (ctx->mem_idx == 2)
3916 read_cb = ctx->spr_cb[sprn].hea_read;
3917 else if (ctx->mem_idx)
3918 read_cb = ctx->spr_cb[sprn].oea_read;
3919 else
3920 #endif
3921 read_cb = ctx->spr_cb[sprn].uea_read;
3922 if (likely(read_cb != NULL)) {
3923 if (likely(read_cb != SPR_NOACCESS)) {
3924 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3925 } else {
3926 /* Privilege exception */
3927 /* This is a hack to avoid warnings when running Linux:
3928 * this OS breaks the PowerPC virtualisation model,
3929 * allowing userland application to read the PVR
3930 */
3931 if (sprn != SPR_PVR) {
3932 qemu_log("Trying to read privileged spr %d %03x at "
3933 ADDRX "\n", sprn, sprn, ctx->nip);
3934 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3935 sprn, sprn, ctx->nip);
3936 }
3937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3938 }
3939 } else {
3940 /* Not defined */
3941 qemu_log("Trying to read invalid spr %d %03x at "
3942 ADDRX "\n", sprn, sprn, ctx->nip);
3943 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3944 sprn, sprn, ctx->nip);
3945 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3946 }
3947 }
3948
3949 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3950 {
3951 gen_op_mfspr(ctx);
3952 }
3953
3954 /* mftb */
3955 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3956 {
3957 gen_op_mfspr(ctx);
3958 }
3959
3960 /* mtcrf mtocrf*/
3961 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3962 {
3963 uint32_t crm, crn;
3964
3965 crm = CRM(ctx->opcode);
3966 if (likely((ctx->opcode & 0x00100000))) {
3967 if (crm && ((crm & (crm - 1)) == 0)) {
3968 TCGv_i32 temp = tcg_temp_new_i32();
3969 crn = ctz32 (crm);
3970 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3971 tcg_gen_shri_i32(temp, temp, crn * 4);
3972 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3973 tcg_temp_free_i32(temp);
3974 }
3975 } else {
3976 TCGv_i32 temp = tcg_temp_new_i32();
3977 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3978 for (crn = 0 ; crn < 8 ; crn++) {
3979 if (crm & (1 << crn)) {
3980 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3981 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3982 }
3983 }
3984 tcg_temp_free_i32(temp);
3985 }
3986 }
3987
3988 /* mtmsr */
3989 #if defined(TARGET_PPC64)
3990 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3991 {
3992 #if defined(CONFIG_USER_ONLY)
3993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3994 #else
3995 if (unlikely(!ctx->mem_idx)) {
3996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3997 return;
3998 }
3999 if (ctx->opcode & 0x00010000) {
4000 /* Special form that does not need any synchronisation */
4001 TCGv t0 = tcg_temp_new();
4002 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4003 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4004 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4005 tcg_temp_free(t0);
4006 } else {
4007 /* XXX: we need to update nip before the store
4008 * if we enter power saving mode, we will exit the loop
4009 * directly from ppc_store_msr
4010 */
4011 gen_update_nip(ctx, ctx->nip);
4012 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4013 /* Must stop the translation as machine state (may have) changed */
4014 /* Note that mtmsr is not always defined as context-synchronizing */
4015 gen_stop_exception(ctx);
4016 }
4017 #endif
4018 }
4019 #endif
4020
4021 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
4022 {
4023 #if defined(CONFIG_USER_ONLY)
4024 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4025 #else
4026 if (unlikely(!ctx->mem_idx)) {
4027 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4028 return;
4029 }
4030 if (ctx->opcode & 0x00010000) {
4031 /* Special form that does not need any synchronisation */
4032 TCGv t0 = tcg_temp_new();
4033 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4034 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4035 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4036 tcg_temp_free(t0);
4037 } else {
4038 /* XXX: we need to update nip before the store
4039 * if we enter power saving mode, we will exit the loop
4040 * directly from ppc_store_msr
4041 */
4042 gen_update_nip(ctx, ctx->nip);
4043 #if defined(TARGET_PPC64)
4044 if (!ctx->sf_mode) {
4045 TCGv t0 = tcg_temp_new();
4046 TCGv t1 = tcg_temp_new();
4047 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4048 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4049 tcg_gen_or_tl(t0, t0, t1);
4050 tcg_temp_free(t1);
4051 gen_helper_store_msr(t0);
4052 tcg_temp_free(t0);
4053 } else
4054 #endif
4055 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
4056 /* Must stop the translation as machine state (may have) changed */
4057 /* Note that mtmsr is not always defined as context-synchronizing */
4058 gen_stop_exception(ctx);
4059 }
4060 #endif
4061 }
4062
4063 /* mtspr */
4064 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4065 {
4066 void (*write_cb)(void *opaque, int sprn, int gprn);
4067 uint32_t sprn = SPR(ctx->opcode);
4068
4069 #if !defined(CONFIG_USER_ONLY)
4070 if (ctx->mem_idx == 2)
4071 write_cb = ctx->spr_cb[sprn].hea_write;
4072 else if (ctx->mem_idx)
4073 write_cb = ctx->spr_cb[sprn].oea_write;
4074 else
4075 #endif
4076 write_cb = ctx->spr_cb[sprn].uea_write;
4077 if (likely(write_cb != NULL)) {
4078 if (likely(write_cb != SPR_NOACCESS)) {
4079 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4080 } else {
4081 /* Privilege exception */
4082 qemu_log("Trying to write privileged spr %d %03x at "
4083 ADDRX "\n", sprn, sprn, ctx->nip);
4084 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4085 sprn, sprn, ctx->nip);
4086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4087 }
4088 } else {
4089 /* Not defined */
4090 qemu_log("Trying to write invalid spr %d %03x at "
4091 ADDRX "\n", sprn, sprn, ctx->nip);
4092 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4093 sprn, sprn, ctx->nip);
4094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4095 }
4096 }
4097
4098 /*** Cache management ***/
4099 /* dcbf */
4100 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4101 {
4102 /* XXX: specification says this is treated as a load by the MMU */
4103 TCGv t0;
4104 gen_set_access_type(ctx, ACCESS_CACHE);
4105 t0 = tcg_temp_new();
4106 gen_addr_reg_index(ctx, t0);
4107 gen_qemu_ld8u(ctx, t0, t0);
4108 tcg_temp_free(t0);
4109 }
4110
4111 /* dcbi (Supervisor only) */
4112 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4113 {
4114 #if defined(CONFIG_USER_ONLY)
4115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4116 #else
4117 TCGv EA, val;
4118 if (unlikely(!ctx->mem_idx)) {
4119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4120 return;
4121 }
4122 EA = tcg_temp_new();
4123 gen_set_access_type(ctx, ACCESS_CACHE);
4124 gen_addr_reg_index(ctx, EA);
4125 val = tcg_temp_new();
4126 /* XXX: specification says this should be treated as a store by the MMU */
4127 gen_qemu_ld8u(ctx, val, EA);
4128 gen_qemu_st8(ctx, val, EA);
4129 tcg_temp_free(val);
4130 tcg_temp_free(EA);
4131 #endif
4132 }
4133
4134 /* dcdst */
4135 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4136 {
4137 /* XXX: specification say this is treated as a load by the MMU */
4138 TCGv t0;
4139 gen_set_access_type(ctx, ACCESS_CACHE);
4140 t0 = tcg_temp_new();
4141 gen_addr_reg_index(ctx, t0);
4142 gen_qemu_ld8u(ctx, t0, t0);
4143 tcg_temp_free(t0);
4144 }
4145
4146 /* dcbt */
4147 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4148 {
4149 /* interpreted as no-op */
4150 /* XXX: specification say this is treated as a load by the MMU
4151 * but does not generate any exception
4152 */
4153 }
4154
4155 /* dcbtst */
4156 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4157 {
4158 /* interpreted as no-op */
4159 /* XXX: specification say this is treated as a load by the MMU
4160 * but does not generate any exception
4161 */
4162 }
4163
4164 /* dcbz */
4165 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4166 {
4167 TCGv t0;
4168 gen_set_access_type(ctx, ACCESS_CACHE);
4169 /* NIP cannot be restored if the memory exception comes from an helper */
4170 gen_update_nip(ctx, ctx->nip - 4);
4171 t0 = tcg_temp_new();
4172 gen_addr_reg_index(ctx, t0);
4173 gen_helper_dcbz(t0);
4174 tcg_temp_free(t0);
4175 }
4176
4177 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4178 {
4179 TCGv t0;
4180 gen_set_access_type(ctx, ACCESS_CACHE);
4181 /* NIP cannot be restored if the memory exception comes from an helper */
4182 gen_update_nip(ctx, ctx->nip - 4);
4183 t0 = tcg_temp_new();
4184 gen_addr_reg_index(ctx, t0);
4185 if (ctx->opcode & 0x00200000)
4186 gen_helper_dcbz(t0);
4187 else
4188 gen_helper_dcbz_970(t0);
4189 tcg_temp_free(t0);
4190 }
4191
4192 /* dst / dstt */
4193 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4194 {
4195 if (rA(ctx->opcode) == 0) {
4196 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4197 } else {
4198 /* interpreted as no-op */
4199 }
4200 }
4201
4202 /* dstst /dststt */
4203 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4204 {
4205 if (rA(ctx->opcode) == 0) {
4206 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4207 } else {
4208 /* interpreted as no-op */
4209 }
4210
4211 }
4212
4213 /* dss / dssall */
4214 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4215 {
4216 /* interpreted as no-op */
4217 }
4218
4219 /* icbi */
4220 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4221 {
4222 TCGv t0;
4223 gen_set_access_type(ctx, ACCESS_CACHE);
4224 /* NIP cannot be restored if the memory exception comes from an helper */
4225 gen_update_nip(ctx, ctx->nip - 4);
4226 t0 = tcg_temp_new();
4227 gen_addr_reg_index(ctx, t0);
4228 gen_helper_icbi(t0);
4229 tcg_temp_free(t0);
4230 }
4231
4232 /* Optional: */
4233 /* dcba */
4234 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4235 {
4236 /* interpreted as no-op */
4237 /* XXX: specification say this is treated as a store by the MMU
4238 * but does not generate any exception
4239 */
4240 }
4241
4242 /*** Segment register manipulation ***/
4243 /* Supervisor only: */
4244 /* mfsr */
4245 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4246 {
4247 #if defined(CONFIG_USER_ONLY)
4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4249 #else
4250 TCGv t0;
4251 if (unlikely(!ctx->mem_idx)) {
4252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4253 return;
4254 }
4255 t0 = tcg_const_tl(SR(ctx->opcode));
4256 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4257 tcg_temp_free(t0);
4258 #endif
4259 }
4260
4261 /* mfsrin */
4262 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4263 {
4264 #if defined(CONFIG_USER_ONLY)
4265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4266 #else
4267 TCGv t0;
4268 if (unlikely(!ctx->mem_idx)) {
4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4270 return;
4271 }
4272 t0 = tcg_temp_new();
4273 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4274 tcg_gen_andi_tl(t0, t0, 0xF);
4275 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4276 tcg_temp_free(t0);
4277 #endif
4278 }
4279
4280 /* mtsr */
4281 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4282 {
4283 #if defined(CONFIG_USER_ONLY)
4284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4285 #else
4286 TCGv t0;
4287 if (unlikely(!ctx->mem_idx)) {
4288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4289 return;
4290 }
4291 t0 = tcg_const_tl(SR(ctx->opcode));
4292 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4293 tcg_temp_free(t0);
4294 #endif
4295 }
4296
4297 /* mtsrin */
4298 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4299 {
4300 #if defined(CONFIG_USER_ONLY)
4301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4302 #else
4303 TCGv t0;
4304 if (unlikely(!ctx->mem_idx)) {
4305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4306 return;
4307 }
4308 t0 = tcg_temp_new();
4309 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4310 tcg_gen_andi_tl(t0, t0, 0xF);
4311 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4312 tcg_temp_free(t0);
4313 #endif
4314 }
4315
4316 #if defined(TARGET_PPC64)
4317 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4318 /* mfsr */
4319 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4320 {
4321 #if defined(CONFIG_USER_ONLY)
4322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4323 #else
4324 TCGv t0;
4325 if (unlikely(!ctx->mem_idx)) {
4326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4327 return;
4328 }
4329 t0 = tcg_const_tl(SR(ctx->opcode));
4330 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4331 tcg_temp_free(t0);
4332 #endif
4333 }
4334
4335 /* mfsrin */
4336 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4337 PPC_SEGMENT_64B)
4338 {
4339 #if defined(CONFIG_USER_ONLY)
4340 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4341 #else
4342 TCGv t0;
4343 if (unlikely(!ctx->mem_idx)) {
4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4345 return;
4346 }
4347 t0 = tcg_temp_new();
4348 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4349 tcg_gen_andi_tl(t0, t0, 0xF);
4350 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4351 tcg_temp_free(t0);
4352 #endif
4353 }
4354
4355 /* mtsr */
4356 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4357 {
4358 #if defined(CONFIG_USER_ONLY)
4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4360 #else
4361 TCGv t0;
4362 if (unlikely(!ctx->mem_idx)) {
4363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4364 return;
4365 }
4366 t0 = tcg_const_tl(SR(ctx->opcode));
4367 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4368 tcg_temp_free(t0);
4369 #endif
4370 }
4371
4372 /* mtsrin */
4373 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4374 PPC_SEGMENT_64B)
4375 {
4376 #if defined(CONFIG_USER_ONLY)
4377 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4378 #else
4379 TCGv t0;
4380 if (unlikely(!ctx->mem_idx)) {
4381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4382 return;
4383 }
4384 t0 = tcg_temp_new();
4385 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4386 tcg_gen_andi_tl(t0, t0, 0xF);
4387 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4388 tcg_temp_free(t0);
4389 #endif
4390 }
4391
4392 /* slbmte */
4393 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B)
4394 {
4395 #if defined(CONFIG_USER_ONLY)
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4397 #else
4398 if (unlikely(!ctx->mem_idx)) {
4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4400 return;
4401 }
4402 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4403 #endif
4404 }
4405
4406 #endif /* defined(TARGET_PPC64) */
4407
4408 /*** Lookaside buffer management ***/
4409 /* Optional & mem_idx only: */
4410 /* tlbia */
4411 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4412 {
4413 #if defined(CONFIG_USER_ONLY)
4414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4415 #else
4416 if (unlikely(!ctx->mem_idx)) {
4417 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4418 return;
4419 }
4420 gen_helper_tlbia();
4421 #endif
4422 }
4423
4424 /* tlbiel */
4425 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE)
4426 {
4427 #if defined(CONFIG_USER_ONLY)
4428 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4429 #else
4430 if (unlikely(!ctx->mem_idx)) {
4431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4432 return;
4433 }
4434 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4435 #endif
4436 }
4437
4438 /* tlbie */
4439 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4440 {
4441 #if defined(CONFIG_USER_ONLY)
4442 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4443 #else
4444 if (unlikely(!ctx->mem_idx)) {
4445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4446 return;
4447 }
4448 #if defined(TARGET_PPC64)
4449 if (!ctx->sf_mode) {
4450 TCGv t0 = tcg_temp_new();
4451 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4452 gen_helper_tlbie(t0);
4453 tcg_temp_free(t0);
4454 } else
4455 #endif
4456 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4457 #endif
4458 }
4459
4460 /* tlbsync */
4461 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4462 {
4463 #if defined(CONFIG_USER_ONLY)
4464 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4465 #else
4466 if (unlikely(!ctx->mem_idx)) {
4467 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4468 return;
4469 }
4470 /* This has no effect: it should ensure that all previous
4471 * tlbie have completed
4472 */
4473 gen_stop_exception(ctx);
4474 #endif
4475 }
4476
4477 #if defined(TARGET_PPC64)
4478 /* slbia */
4479 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4480 {
4481 #if defined(CONFIG_USER_ONLY)
4482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4483 #else
4484 if (unlikely(!ctx->mem_idx)) {
4485 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4486 return;
4487 }
4488 gen_helper_slbia();
4489 #endif
4490 }
4491
4492 /* slbie */
4493 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4494 {
4495 #if defined(CONFIG_USER_ONLY)
4496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4497 #else
4498 if (unlikely(!ctx->mem_idx)) {
4499 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4500 return;
4501 }
4502 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
4503 #endif
4504 }
4505 #endif
4506
4507 /*** External control ***/
4508 /* Optional: */
4509 /* eciwx */
4510 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4511 {
4512 TCGv t0;
4513 /* Should check EAR[E] ! */
4514 gen_set_access_type(ctx, ACCESS_EXT);
4515 t0 = tcg_temp_new();
4516 gen_addr_reg_index(ctx, t0);
4517 gen_check_align(ctx, t0, 0x03);
4518 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4519 tcg_temp_free(t0);
4520 }
4521
4522 /* ecowx */
4523 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4524 {
4525 TCGv t0;
4526 /* Should check EAR[E] ! */
4527 gen_set_access_type(ctx, ACCESS_EXT);
4528 t0 = tcg_temp_new();
4529 gen_addr_reg_index(ctx, t0);
4530 gen_check_align(ctx, t0, 0x03);
4531 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4532 tcg_temp_free(t0);
4533 }
4534
4535 /* PowerPC 601 specific instructions */
4536 /* abs - abs. */
4537 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4538 {
4539 int l1 = gen_new_label();
4540 int l2 = gen_new_label();
4541 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4542 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4543 tcg_gen_br(l2);
4544 gen_set_label(l1);
4545 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4546 gen_set_label(l2);
4547 if (unlikely(Rc(ctx->opcode) != 0))
4548 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4549 }
4550
4551 /* abso - abso. */
4552 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4553 {
4554 int l1 = gen_new_label();
4555 int l2 = gen_new_label();
4556 int l3 = gen_new_label();
4557 /* Start with XER OV disabled, the most likely case */
4558 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4559 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4560 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4561 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4562 tcg_gen_br(l2);
4563 gen_set_label(l1);
4564 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4565 tcg_gen_br(l3);
4566 gen_set_label(l2);
4567 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4568 gen_set_label(l3);
4569 if (unlikely(Rc(ctx->opcode) != 0))
4570 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4571 }
4572
4573 /* clcs */
4574 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4575 {
4576 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4577 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4578 tcg_temp_free_i32(t0);
4579 /* Rc=1 sets CR0 to an undefined state */
4580 }
4581
4582 /* div - div. */
4583 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4584 {
4585 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4586 if (unlikely(Rc(ctx->opcode) != 0))
4587 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4588 }
4589
4590 /* divo - divo. */
4591 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4592 {
4593 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4594 if (unlikely(Rc(ctx->opcode) != 0))
4595 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4596 }
4597
4598 /* divs - divs. */
4599 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4600 {
4601 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4602 if (unlikely(Rc(ctx->opcode) != 0))
4603 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4604 }
4605
4606 /* divso - divso. */
4607 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4608 {
4609 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4610 if (unlikely(Rc(ctx->opcode) != 0))
4611 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4612 }
4613
4614 /* doz - doz. */
4615 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4616 {
4617 int l1 = gen_new_label();
4618 int l2 = gen_new_label();
4619 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4620 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4621 tcg_gen_br(l2);
4622 gen_set_label(l1);
4623 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4624 gen_set_label(l2);
4625 if (unlikely(Rc(ctx->opcode) != 0))
4626 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4627 }
4628
4629 /* dozo - dozo. */
4630 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4631 {
4632 int l1 = gen_new_label();
4633 int l2 = gen_new_label();
4634 TCGv t0 = tcg_temp_new();
4635 TCGv t1 = tcg_temp_new();
4636 TCGv t2 = tcg_temp_new();
4637 /* Start with XER OV disabled, the most likely case */
4638 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4639 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4640 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4641 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4642 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4643 tcg_gen_andc_tl(t1, t1, t2);
4644 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4645 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4646 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4647 tcg_gen_br(l2);
4648 gen_set_label(l1);
4649 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4650 gen_set_label(l2);
4651 tcg_temp_free(t0);
4652 tcg_temp_free(t1);
4653 tcg_temp_free(t2);
4654 if (unlikely(Rc(ctx->opcode) != 0))
4655 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4656 }
4657
4658 /* dozi */
4659 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4660 {
4661 target_long simm = SIMM(ctx->opcode);
4662 int l1 = gen_new_label();
4663 int l2 = gen_new_label();
4664 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4665 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4666 tcg_gen_br(l2);
4667 gen_set_label(l1);
4668 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4669 gen_set_label(l2);
4670 if (unlikely(Rc(ctx->opcode) != 0))
4671 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4672 }
4673
4674 /* lscbx - lscbx. */
4675 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4676 {
4677 TCGv t0 = tcg_temp_new();
4678 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4679 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4680 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4681
4682 gen_addr_reg_index(ctx, t0);
4683 /* NIP cannot be restored if the memory exception comes from an helper */
4684 gen_update_nip(ctx, ctx->nip - 4);
4685 gen_helper_lscbx(t0, t0, t1, t2, t3);
4686 tcg_temp_free_i32(t1);
4687 tcg_temp_free_i32(t2);
4688 tcg_temp_free_i32(t3);
4689 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4690 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4691 if (unlikely(Rc(ctx->opcode) != 0))
4692 gen_set_Rc0(ctx, t0);
4693 tcg_temp_free(t0);
4694 }
4695
4696 /* maskg - maskg. */
4697 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4698 {
4699 int l1 = gen_new_label();
4700 TCGv t0 = tcg_temp_new();
4701 TCGv t1 = tcg_temp_new();
4702 TCGv t2 = tcg_temp_new();
4703 TCGv t3 = tcg_temp_new();
4704 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4705 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4706 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4707 tcg_gen_addi_tl(t2, t0, 1);
4708 tcg_gen_shr_tl(t2, t3, t2);
4709 tcg_gen_shr_tl(t3, t3, t1);
4710 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4711 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4712 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4713 gen_set_label(l1);
4714 tcg_temp_free(t0);
4715 tcg_temp_free(t1);
4716 tcg_temp_free(t2);
4717 tcg_temp_free(t3);
4718 if (unlikely(Rc(ctx->opcode) != 0))
4719 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4720 }
4721
4722 /* maskir - maskir. */
4723 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4724 {
4725 TCGv t0 = tcg_temp_new();
4726 TCGv t1 = tcg_temp_new();
4727 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4728 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4729 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4730 tcg_temp_free(t0);
4731 tcg_temp_free(t1);
4732 if (unlikely(Rc(ctx->opcode) != 0))
4733 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4734 }
4735
4736 /* mul - mul. */
4737 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4738 {
4739 TCGv_i64 t0 = tcg_temp_new_i64();
4740 TCGv_i64 t1 = tcg_temp_new_i64();
4741 TCGv t2 = tcg_temp_new();
4742 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4743 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4744 tcg_gen_mul_i64(t0, t0, t1);
4745 tcg_gen_trunc_i64_tl(t2, t0);
4746 gen_store_spr(SPR_MQ, t2);
4747 tcg_gen_shri_i64(t1, t0, 32);
4748 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4749 tcg_temp_free_i64(t0);
4750 tcg_temp_free_i64(t1);
4751 tcg_temp_free(t2);
4752 if (unlikely(Rc(ctx->opcode) != 0))
4753 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4754 }
4755
4756 /* mulo - mulo. */
4757 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4758 {
4759 int l1 = gen_new_label();
4760 TCGv_i64 t0 = tcg_temp_new_i64();
4761 TCGv_i64 t1 = tcg_temp_new_i64();
4762 TCGv t2 = tcg_temp_new();
4763 /* Start with XER OV disabled, the most likely case */
4764 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4765 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4766 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4767 tcg_gen_mul_i64(t0, t0, t1);
4768 tcg_gen_trunc_i64_tl(t2, t0);
4769 gen_store_spr(SPR_MQ, t2);
4770 tcg_gen_shri_i64(t1, t0, 32);
4771 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4772 tcg_gen_ext32s_i64(t1, t0);
4773 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4774 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4775 gen_set_label(l1);
4776 tcg_temp_free_i64(t0);
4777 tcg_temp_free_i64(t1);
4778 tcg_temp_free(t2);
4779 if (unlikely(Rc(ctx->opcode) != 0))
4780 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4781 }
4782
4783 /* nabs - nabs. */
4784 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4785 {
4786 int l1 = gen_new_label();
4787 int l2 = gen_new_label();
4788 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4789 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4790 tcg_gen_br(l2);
4791 gen_set_label(l1);
4792 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4793 gen_set_label(l2);
4794 if (unlikely(Rc(ctx->opcode) != 0))
4795 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4796 }
4797
4798 /* nabso - nabso. */
4799 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4800 {
4801 int l1 = gen_new_label();
4802 int l2 = gen_new_label();
4803 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4804 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4805 tcg_gen_br(l2);
4806 gen_set_label(l1);
4807 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4808 gen_set_label(l2);
4809 /* nabs never overflows */
4810 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4811 if (unlikely(Rc(ctx->opcode) != 0))
4812 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4813 }
4814
4815 /* rlmi - rlmi. */
4816 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4817 {
4818 uint32_t mb = MB(ctx->opcode);
4819 uint32_t me = ME(ctx->opcode);
4820 TCGv t0 = tcg_temp_new();
4821 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4822 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4823 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4824 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4825 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4826 tcg_temp_free(t0);
4827 if (unlikely(Rc(ctx->opcode) != 0))
4828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4829 }
4830
4831 /* rrib - rrib. */
4832 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4833 {
4834 TCGv t0 = tcg_temp_new();
4835 TCGv t1 = tcg_temp_new();
4836 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4837 tcg_gen_movi_tl(t1, 0x80000000);
4838 tcg_gen_shr_tl(t1, t1, t0);
4839 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4840 tcg_gen_and_tl(t0, t0, t1);
4841 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4842 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
4845 if (unlikely(Rc(ctx->opcode) != 0))
4846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4847 }
4848
4849 /* sle - sle. */
4850 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4851 {
4852 TCGv t0 = tcg_temp_new();
4853 TCGv t1 = tcg_temp_new();
4854 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4855 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4856 tcg_gen_subfi_tl(t1, 32, t1);
4857 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4858 tcg_gen_or_tl(t1, t0, t1);
4859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4860 gen_store_spr(SPR_MQ, t1);
4861 tcg_temp_free(t0);
4862 tcg_temp_free(t1);
4863 if (unlikely(Rc(ctx->opcode) != 0))
4864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4865 }
4866
4867 /* sleq - sleq. */
4868 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4869 {
4870 TCGv t0 = tcg_temp_new();
4871 TCGv t1 = tcg_temp_new();
4872 TCGv t2 = tcg_temp_new();
4873 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4874 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4875 tcg_gen_shl_tl(t2, t2, t0);
4876 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4877 gen_load_spr(t1, SPR_MQ);
4878 gen_store_spr(SPR_MQ, t0);
4879 tcg_gen_and_tl(t0, t0, t2);
4880 tcg_gen_andc_tl(t1, t1, t2);
4881 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4882 tcg_temp_free(t0);
4883 tcg_temp_free(t1);
4884 tcg_temp_free(t2);
4885 if (unlikely(Rc(ctx->opcode) != 0))
4886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4887 }
4888
4889 /* sliq - sliq. */
4890 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4891 {
4892 int sh = SH(ctx->opcode);
4893 TCGv t0 = tcg_temp_new();
4894 TCGv t1 = tcg_temp_new();
4895 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4896 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4897 tcg_gen_or_tl(t1, t0, t1);
4898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4899 gen_store_spr(SPR_MQ, t1);
4900 tcg_temp_free(t0);
4901 tcg_temp_free(t1);
4902 if (unlikely(Rc(ctx->opcode) != 0))
4903 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4904 }
4905
4906 /* slliq - slliq. */
4907 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4908 {
4909 int sh = SH(ctx->opcode);
4910 TCGv t0 = tcg_temp_new();
4911 TCGv t1 = tcg_temp_new();
4912 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4913 gen_load_spr(t1, SPR_MQ);
4914 gen_store_spr(SPR_MQ, t0);
4915 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4916 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4917 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
4920 if (unlikely(Rc(ctx->opcode) != 0))
4921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4922 }
4923
4924 /* sllq - sllq. */
4925 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4926 {
4927 int l1 = gen_new_label();
4928 int l2 = gen_new_label();
4929 TCGv t0 = tcg_temp_local_new();
4930 TCGv t1 = tcg_temp_local_new();
4931 TCGv t2 = tcg_temp_local_new();
4932 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4933 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4934 tcg_gen_shl_tl(t1, t1, t2);
4935 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4936 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4937 gen_load_spr(t0, SPR_MQ);
4938 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4939 tcg_gen_br(l2);
4940 gen_set_label(l1);
4941 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4942 gen_load_spr(t2, SPR_MQ);
4943 tcg_gen_andc_tl(t1, t2, t1);
4944 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4945 gen_set_label(l2);
4946 tcg_temp_free(t0);
4947 tcg_temp_free(t1);
4948 tcg_temp_free(t2);
4949 if (unlikely(Rc(ctx->opcode) != 0))
4950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4951 }
4952
4953 /* slq - slq. */
4954 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4955 {
4956 int l1 = gen_new_label();
4957 TCGv t0 = tcg_temp_new();
4958 TCGv t1 = tcg_temp_new();
4959 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4960 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4961 tcg_gen_subfi_tl(t1, 32, t1);
4962 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4963 tcg_gen_or_tl(t1, t0, t1);
4964 gen_store_spr(SPR_MQ, t1);
4965 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4966 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4967 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4968 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4969 gen_set_label(l1);
4970 tcg_temp_free(t0);
4971 tcg_temp_free(t1);
4972 if (unlikely(Rc(ctx->opcode) != 0))
4973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4974 }
4975
4976 /* sraiq - sraiq. */
4977 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4978 {
4979 int sh = SH(ctx->opcode);
4980 int l1 = gen_new_label();
4981 TCGv t0 = tcg_temp_new();
4982 TCGv t1 = tcg_temp_new();
4983 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4984 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4985 tcg_gen_or_tl(t0, t0, t1);
4986 gen_store_spr(SPR_MQ, t0);
4987 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4988 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4989 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4990 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4991 gen_set_label(l1);
4992 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4993 tcg_temp_free(t0);
4994 tcg_temp_free(t1);
4995 if (unlikely(Rc(ctx->opcode) != 0))
4996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4997 }
4998
4999 /* sraq - sraq. */
5000 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
5001 {
5002 int l1 = gen_new_label();
5003 int l2 = gen_new_label();
5004 TCGv t0 = tcg_temp_new();
5005 TCGv t1 = tcg_temp_local_new();
5006 TCGv t2 = tcg_temp_local_new();
5007 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5008 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5009 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5010 tcg_gen_subfi_tl(t2, 32, t2);
5011 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5012 tcg_gen_or_tl(t0, t0, t2);
5013 gen_store_spr(SPR_MQ, t0);
5014 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5015 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5016 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5017 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5018 gen_set_label(l1);
5019 tcg_temp_free(t0);
5020 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5021 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
5022 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5023 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5024 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
5025 gen_set_label(l2);
5026 tcg_temp_free(t1);
5027 tcg_temp_free(t2);
5028 if (unlikely(Rc(ctx->opcode) != 0))
5029 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5030 }
5031
5032 /* sre - sre. */
5033 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
5034 {
5035 TCGv t0 = tcg_temp_new();
5036 TCGv t1 = tcg_temp_new();
5037 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5038 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5039 tcg_gen_subfi_tl(t1, 32, t1);
5040 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5041 tcg_gen_or_tl(t1, t0, t1);
5042 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5043 gen_store_spr(SPR_MQ, t1);
5044 tcg_temp_free(t0);
5045 tcg_temp_free(t1);
5046 if (unlikely(Rc(ctx->opcode) != 0))
5047 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5048 }
5049
5050 /* srea - srea. */
5051 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
5052 {
5053 TCGv t0 = tcg_temp_new();
5054 TCGv t1 = tcg_temp_new();
5055 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5056 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5057 gen_store_spr(SPR_MQ, t0);
5058 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5059 tcg_temp_free(t0);
5060 tcg_temp_free(t1);
5061 if (unlikely(Rc(ctx->opcode) != 0))
5062 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5063 }
5064
5065 /* sreq */
5066 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
5067 {
5068 TCGv t0 = tcg_temp_new();
5069 TCGv t1 = tcg_temp_new();
5070 TCGv t2 = tcg_temp_new();
5071 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5072 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5073 tcg_gen_shr_tl(t1, t1, t0);
5074 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5075 gen_load_spr(t2, SPR_MQ);
5076 gen_store_spr(SPR_MQ, t0);
5077 tcg_gen_and_tl(t0, t0, t1);
5078 tcg_gen_andc_tl(t2, t2, t1);
5079 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5085 }
5086
5087 /* sriq */
5088 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5089 {
5090 int sh = SH(ctx->opcode);
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5094 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5095 tcg_gen_or_tl(t1, t0, t1);
5096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5097 gen_store_spr(SPR_MQ, t1);
5098 tcg_temp_free(t0);
5099 tcg_temp_free(t1);
5100 if (unlikely(Rc(ctx->opcode) != 0))
5101 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5102 }
5103
5104 /* srliq */
5105 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5106 {
5107 int sh = SH(ctx->opcode);
5108 TCGv t0 = tcg_temp_new();
5109 TCGv t1 = tcg_temp_new();
5110 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5111 gen_load_spr(t1, SPR_MQ);
5112 gen_store_spr(SPR_MQ, t0);
5113 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5114 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5116 tcg_temp_free(t0);
5117 tcg_temp_free(t1);
5118 if (unlikely(Rc(ctx->opcode) != 0))
5119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5120 }
5121
5122 /* srlq */
5123 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5124 {
5125 int l1 = gen_new_label();
5126 int l2 = gen_new_label();
5127 TCGv t0 = tcg_temp_local_new();
5128 TCGv t1 = tcg_temp_local_new();
5129 TCGv t2 = tcg_temp_local_new();
5130 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5131 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5132 tcg_gen_shr_tl(t2, t1, t2);
5133 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5134 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5135 gen_load_spr(t0, SPR_MQ);
5136 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5137 tcg_gen_br(l2);
5138 gen_set_label(l1);
5139 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5140 tcg_gen_and_tl(t0, t0, t2);
5141 gen_load_spr(t1, SPR_MQ);
5142 tcg_gen_andc_tl(t1, t1, t2);
5143 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5144 gen_set_label(l2);
5145 tcg_temp_free(t0);
5146 tcg_temp_free(t1);
5147 tcg_temp_free(t2);
5148 if (unlikely(Rc(ctx->opcode) != 0))
5149 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5150 }
5151
5152 /* srq */
5153 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5154 {
5155 int l1 = gen_new_label();
5156 TCGv t0 = tcg_temp_new();
5157 TCGv t1 = tcg_temp_new();
5158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5159 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5160 tcg_gen_subfi_tl(t1, 32, t1);
5161 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5162 tcg_gen_or_tl(t1, t0, t1);
5163 gen_store_spr(SPR_MQ, t1);
5164 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5165 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5166 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5167 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5168 gen_set_label(l1);
5169 tcg_temp_free(t0);
5170 tcg_temp_free(t1);
5171 if (unlikely(Rc(ctx->opcode) != 0))
5172 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5173 }
5174
5175 /* PowerPC 602 specific instructions */
5176 /* dsa */
5177 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5178 {
5179 /* XXX: TODO */
5180 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5181 }
5182
5183 /* esa */
5184 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5185 {
5186 /* XXX: TODO */
5187 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5188 }
5189
5190 /* mfrom */
5191 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5192 {
5193 #if defined(CONFIG_USER_ONLY)
5194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5195 #else
5196 if (unlikely(!ctx->mem_idx)) {
5197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5198 return;
5199 }
5200 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5201 #endif
5202 }
5203
5204 /* 602 - 603 - G2 TLB management */
5205 /* tlbld */
5206 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
5207 {
5208 #if defined(CONFIG_USER_ONLY)
5209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5210 #else
5211 if (unlikely(!ctx->mem_idx)) {
5212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5213 return;
5214 }
5215 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5216 #endif
5217 }
5218
5219 /* tlbli */
5220 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
5221 {
5222 #if defined(CONFIG_USER_ONLY)
5223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5224 #else
5225 if (unlikely(!ctx->mem_idx)) {
5226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5227 return;
5228 }
5229 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5230 #endif
5231 }
5232
5233 /* 74xx TLB management */
5234 /* tlbld */
5235 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
5236 {
5237 #if defined(CONFIG_USER_ONLY)
5238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5239 #else
5240 if (unlikely(!ctx->mem_idx)) {
5241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5242 return;
5243 }
5244 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
5245 #endif
5246 }
5247
5248 /* tlbli */
5249 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
5250 {
5251 #if defined(CONFIG_USER_ONLY)
5252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5253 #else
5254 if (unlikely(!ctx->mem_idx)) {
5255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5256 return;
5257 }
5258 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
5259 #endif
5260 }
5261
5262 /* POWER instructions not in PowerPC 601 */
5263 /* clf */
5264 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5265 {
5266 /* Cache line flush: implemented as no-op */
5267 }
5268
5269 /* cli */
5270 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5271 {
5272 /* Cache line invalidate: privileged and treated as no-op */
5273 #if defined(CONFIG_USER_ONLY)
5274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5275 #else
5276 if (unlikely(!ctx->mem_idx)) {
5277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5278 return;
5279 }
5280 #endif
5281 }
5282
5283 /* dclst */
5284 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5285 {
5286 /* Data cache line store: treated as no-op */
5287 }
5288
5289 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5290 {
5291 #if defined(CONFIG_USER_ONLY)
5292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5293 #else
5294 int ra = rA(ctx->opcode);
5295 int rd = rD(ctx->opcode);
5296 TCGv t0;
5297 if (unlikely(!ctx->mem_idx)) {
5298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5299 return;
5300 }
5301 t0 = tcg_temp_new();
5302 gen_addr_reg_index(ctx, t0);
5303 tcg_gen_shri_tl(t0, t0, 28);
5304 tcg_gen_andi_tl(t0, t0, 0xF);
5305 gen_helper_load_sr(cpu_gpr[rd], t0);
5306 tcg_temp_free(t0);
5307 if (ra != 0 && ra != rd)
5308 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5309 #endif
5310 }
5311
5312 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5313 {
5314 #if defined(CONFIG_USER_ONLY)
5315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5316 #else
5317 TCGv t0;
5318 if (unlikely(!ctx->mem_idx)) {
5319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5320 return;
5321 }
5322 t0 = tcg_temp_new();
5323 gen_addr_reg_index(ctx, t0);
5324 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5325 tcg_temp_free(t0);
5326 #endif
5327 }
5328
5329 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5330 {
5331 #if defined(CONFIG_USER_ONLY)
5332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5333 #else
5334 if (unlikely(!ctx->mem_idx)) {
5335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5336 return;
5337 }
5338 gen_helper_rfsvc();
5339 gen_sync_exception(ctx);
5340 #endif
5341 }
5342
5343 /* svc is not implemented for now */
5344
5345 /* POWER2 specific instructions */
5346 /* Quad manipulation (load/store two floats at a time) */
5347
5348 /* lfq */
5349 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5350 {
5351 int rd = rD(ctx->opcode);
5352 TCGv t0;
5353 gen_set_access_type(ctx, ACCESS_FLOAT);
5354 t0 = tcg_temp_new();
5355 gen_addr_imm_index(ctx, t0, 0);
5356 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5357 gen_addr_add(ctx, t0, t0, 8);
5358 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5359 tcg_temp_free(t0);
5360 }
5361
5362 /* lfqu */
5363 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5364 {
5365 int ra = rA(ctx->opcode);
5366 int rd = rD(ctx->opcode);
5367 TCGv t0, t1;
5368 gen_set_access_type(ctx, ACCESS_FLOAT);
5369 t0 = tcg_temp_new();
5370 t1 = tcg_temp_new();
5371 gen_addr_imm_index(ctx, t0, 0);
5372 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5373 gen_addr_add(ctx, t1, t0, 8);
5374 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5375 if (ra != 0)
5376 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5377 tcg_temp_free(t0);
5378 tcg_temp_free(t1);
5379 }
5380
5381 /* lfqux */
5382 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5383 {
5384 int ra = rA(ctx->opcode);
5385 int rd = rD(ctx->opcode);
5386 gen_set_access_type(ctx, ACCESS_FLOAT);
5387 TCGv t0, t1;
5388 t0 = tcg_temp_new();
5389 gen_addr_reg_index(ctx, t0);
5390 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5391 t1 = tcg_temp_new();
5392 gen_addr_add(ctx, t1, t0, 8);
5393 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5394 tcg_temp_free(t1);
5395 if (ra != 0)
5396 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5397 tcg_temp_free(t0);
5398 }
5399
5400 /* lfqx */
5401 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5402 {
5403 int rd = rD(ctx->opcode);
5404 TCGv t0;
5405 gen_set_access_type(ctx, ACCESS_FLOAT);
5406 t0 = tcg_temp_new();
5407 gen_addr_reg_index(ctx, t0);
5408 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5409 gen_addr_add(ctx, t0, t0, 8);
5410 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5411 tcg_temp_free(t0);
5412 }
5413
5414 /* stfq */
5415 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5416 {
5417 int rd = rD(ctx->opcode);
5418 TCGv t0;
5419 gen_set_access_type(ctx, ACCESS_FLOAT);
5420 t0 = tcg_temp_new();
5421 gen_addr_imm_index(ctx, t0, 0);
5422 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5423 gen_addr_add(ctx, t0, t0, 8);
5424 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5425 tcg_temp_free(t0);
5426 }
5427
5428 /* stfqu */
5429 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5430 {
5431 int ra = rA(ctx->opcode);
5432 int rd = rD(ctx->opcode);
5433 TCGv t0, t1;
5434 gen_set_access_type(ctx, ACCESS_FLOAT);
5435 t0 = tcg_temp_new();
5436 gen_addr_imm_index(ctx, t0, 0);
5437 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5438 t1 = tcg_temp_new();
5439 gen_addr_add(ctx, t1, t0, 8);
5440 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5441 tcg_temp_free(t1);
5442 if (ra != 0)
5443 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5444 tcg_temp_free(t0);
5445 }
5446
5447 /* stfqux */
5448 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5449 {
5450 int ra = rA(ctx->opcode);
5451 int rd = rD(ctx->opcode);
5452 TCGv t0, t1;
5453 gen_set_access_type(ctx, ACCESS_FLOAT);
5454 t0 = tcg_temp_new();
5455 gen_addr_reg_index(ctx, t0);
5456 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5457 t1 = tcg_temp_new();
5458 gen_addr_add(ctx, t1, t0, 8);
5459 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5460 tcg_temp_free(t1);
5461 if (ra != 0)
5462 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5463 tcg_temp_free(t0);
5464 }
5465
5466 /* stfqx */
5467 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5468 {
5469 int rd = rD(ctx->opcode);
5470 TCGv t0;
5471 gen_set_access_type(ctx, ACCESS_FLOAT);
5472 t0 = tcg_temp_new();
5473 gen_addr_reg_index(ctx, t0);
5474 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5475 gen_addr_add(ctx, t0, t0, 8);
5476 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5477 tcg_temp_free(t0);
5478 }
5479
5480 /* BookE specific instructions */
5481 /* XXX: not implemented on 440 ? */
5482 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5483 {
5484 /* XXX: TODO */
5485 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5486 }
5487
5488 /* XXX: not implemented on 440 ? */
5489 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5490 {
5491 #if defined(CONFIG_USER_ONLY)
5492 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5493 #else
5494 TCGv t0;
5495 if (unlikely(!ctx->mem_idx)) {
5496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5497 return;
5498 }
5499 t0 = tcg_temp_new();
5500 gen_addr_reg_index(ctx, t0);
5501 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5502 tcg_temp_free(t0);
5503 #endif
5504 }
5505
5506 /* All 405 MAC instructions are translated here */
5507 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5508 int opc2, int opc3,
5509 int ra, int rb, int rt, int Rc)
5510 {
5511 TCGv t0, t1;
5512
5513 t0 = tcg_temp_local_new();
5514 t1 = tcg_temp_local_new();
5515
5516 switch (opc3 & 0x0D) {
5517 case 0x05:
5518 /* macchw - macchw. - macchwo - macchwo. */
5519 /* macchws - macchws. - macchwso - macchwso. */
5520 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5521 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5522 /* mulchw - mulchw. */
5523 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5524 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5525 tcg_gen_ext16s_tl(t1, t1);
5526 break;
5527 case 0x04:
5528 /* macchwu - macchwu. - macchwuo - macchwuo. */
5529 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5530 /* mulchwu - mulchwu. */
5531 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5532 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5533 tcg_gen_ext16u_tl(t1, t1);
5534 break;
5535 case 0x01:
5536 /* machhw - machhw. - machhwo - machhwo. */
5537 /* machhws - machhws. - machhwso - machhwso. */
5538 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5539 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5540 /* mulhhw - mulhhw. */
5541 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5542 tcg_gen_ext16s_tl(t0, t0);
5543 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5544 tcg_gen_ext16s_tl(t1, t1);
5545 break;
5546 case 0x00:
5547 /* machhwu - machhwu. - machhwuo - machhwuo. */
5548 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5549 /* mulhhwu - mulhhwu. */
5550 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5551 tcg_gen_ext16u_tl(t0, t0);
5552 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5553 tcg_gen_ext16u_tl(t1, t1);
5554 break;
5555 case 0x0D:
5556 /* maclhw - maclhw. - maclhwo - maclhwo. */
5557 /* maclhws - maclhws. - maclhwso - maclhwso. */
5558 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5559 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5560 /* mullhw - mullhw. */
5561 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5562 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5563 break;
5564 case 0x0C:
5565 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5566 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5567 /* mullhwu - mullhwu. */
5568 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5569 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5570 break;
5571 }
5572 if (opc2 & 0x04) {
5573 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5574 tcg_gen_mul_tl(t1, t0, t1);
5575 if (opc2 & 0x02) {
5576 /* nmultiply-and-accumulate (0x0E) */
5577 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5578 } else {
5579 /* multiply-and-accumulate (0x0C) */
5580 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5581 }
5582
5583 if (opc3 & 0x12) {
5584 /* Check overflow and/or saturate */
5585 int l1 = gen_new_label();
5586
5587 if (opc3 & 0x10) {
5588 /* Start with XER OV disabled, the most likely case */
5589 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5590 }
5591 if (opc3 & 0x01) {
5592 /* Signed */
5593 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5594 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5595 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5596 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5597 if (opc3 & 0x02) {
5598 /* Saturate */
5599 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5600 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5601 }
5602 } else {
5603 /* Unsigned */
5604 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5605 if (opc3 & 0x02) {
5606 /* Saturate */
5607 tcg_gen_movi_tl(t0, UINT32_MAX);
5608 }
5609 }
5610 if (opc3 & 0x10) {
5611 /* Check overflow */
5612 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5613 }
5614 gen_set_label(l1);
5615 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5616 }
5617 } else {
5618 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5619 }
5620 tcg_temp_free(t0);
5621 tcg_temp_free(t1);
5622 if (unlikely(Rc) != 0) {
5623 /* Update Rc0 */
5624 gen_set_Rc0(ctx, cpu_gpr[rt]);
5625 }
5626 }
5627
5628 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5629 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5630 { \
5631 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5632 rD(ctx->opcode), Rc(ctx->opcode)); \
5633 }
5634
5635 /* macchw - macchw. */
5636 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5637 /* macchwo - macchwo. */
5638 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5639 /* macchws - macchws. */
5640 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5641 /* macchwso - macchwso. */
5642 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5643 /* macchwsu - macchwsu. */
5644 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5645 /* macchwsuo - macchwsuo. */
5646 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5647 /* macchwu - macchwu. */
5648 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5649 /* macchwuo - macchwuo. */
5650 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5651 /* machhw - machhw. */
5652 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5653 /* machhwo - machhwo. */
5654 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5655 /* machhws - machhws. */
5656 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5657 /* machhwso - machhwso. */
5658 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5659 /* machhwsu - machhwsu. */
5660 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5661 /* machhwsuo - machhwsuo. */
5662 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5663 /* machhwu - machhwu. */
5664 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5665 /* machhwuo - machhwuo. */
5666 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5667 /* maclhw - maclhw. */
5668 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5669 /* maclhwo - maclhwo. */
5670 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5671 /* maclhws - maclhws. */
5672 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5673 /* maclhwso - maclhwso. */
5674 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5675 /* maclhwu - maclhwu. */
5676 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5677 /* maclhwuo - maclhwuo. */
5678 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5679 /* maclhwsu - maclhwsu. */
5680 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5681 /* maclhwsuo - maclhwsuo. */
5682 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5683 /* nmacchw - nmacchw. */
5684 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5685 /* nmacchwo - nmacchwo. */
5686 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5687 /* nmacchws - nmacchws. */
5688 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5689 /* nmacchwso - nmacchwso. */
5690 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5691 /* nmachhw - nmachhw. */
5692 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5693 /* nmachhwo - nmachhwo. */
5694 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5695 /* nmachhws - nmachhws. */
5696 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5697 /* nmachhwso - nmachhwso. */
5698 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5699 /* nmaclhw - nmaclhw. */
5700 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5701 /* nmaclhwo - nmaclhwo. */
5702 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5703 /* nmaclhws - nmaclhws. */
5704 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5705 /* nmaclhwso - nmaclhwso. */
5706 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5707
5708 /* mulchw - mulchw. */
5709 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5710 /* mulchwu - mulchwu. */
5711 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5712 /* mulhhw - mulhhw. */
5713 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5714 /* mulhhwu - mulhhwu. */
5715 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5716 /* mullhw - mullhw. */
5717 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5718 /* mullhwu - mullhwu. */
5719 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5720
5721 /* mfdcr */
5722 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5723 {
5724 #if defined(CONFIG_USER_ONLY)
5725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5726 #else
5727 TCGv dcrn;
5728 if (unlikely(!ctx->mem_idx)) {
5729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5730 return;
5731 }
5732 /* NIP cannot be restored if the memory exception comes from an helper */
5733 gen_update_nip(ctx, ctx->nip - 4);
5734 dcrn = tcg_const_tl(SPR(ctx->opcode));
5735 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5736 tcg_temp_free(dcrn);
5737 #endif
5738 }
5739
5740 /* mtdcr */
5741 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5742 {
5743 #if defined(CONFIG_USER_ONLY)
5744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5745 #else
5746 TCGv dcrn;
5747 if (unlikely(!ctx->mem_idx)) {
5748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5749 return;
5750 }
5751 /* NIP cannot be restored if the memory exception comes from an helper */
5752 gen_update_nip(ctx, ctx->nip - 4);
5753 dcrn = tcg_const_tl(SPR(ctx->opcode));
5754 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5755 tcg_temp_free(dcrn);
5756 #endif
5757 }
5758
5759 /* mfdcrx */
5760 /* XXX: not implemented on 440 ? */
5761 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5762 {
5763 #if defined(CONFIG_USER_ONLY)
5764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5765 #else
5766 if (unlikely(!ctx->mem_idx)) {
5767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5768 return;
5769 }
5770 /* NIP cannot be restored if the memory exception comes from an helper */
5771 gen_update_nip(ctx, ctx->nip - 4);
5772 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5773 /* Note: Rc update flag set leads to undefined state of Rc0 */
5774 #endif
5775 }
5776
5777 /* mtdcrx */
5778 /* XXX: not implemented on 440 ? */
5779 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5780 {
5781 #if defined(CONFIG_USER_ONLY)
5782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5783 #else
5784 if (unlikely(!ctx->mem_idx)) {
5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5786 return;
5787 }
5788 /* NIP cannot be restored if the memory exception comes from an helper */
5789 gen_update_nip(ctx, ctx->nip - 4);
5790 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5791 /* Note: Rc update flag set leads to undefined state of Rc0 */
5792 #endif
5793 }
5794
5795 /* mfdcrux (PPC 460) : user-mode access to DCR */
5796 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5797 {
5798 /* NIP cannot be restored if the memory exception comes from an helper */
5799 gen_update_nip(ctx, ctx->nip - 4);
5800 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5801 /* Note: Rc update flag set leads to undefined state of Rc0 */
5802 }
5803
5804 /* mtdcrux (PPC 460) : user-mode access to DCR */
5805 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5806 {
5807 /* NIP cannot be restored if the memory exception comes from an helper */
5808 gen_update_nip(ctx, ctx->nip - 4);
5809 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
5810 /* Note: Rc update flag set leads to undefined state of Rc0 */
5811 }
5812
5813 /* dccci */
5814 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5815 {
5816 #if defined(CONFIG_USER_ONLY)
5817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5818 #else
5819 if (unlikely(!ctx->mem_idx)) {
5820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5821 return;
5822 }
5823 /* interpreted as no-op */
5824 #endif
5825 }
5826
5827 /* dcread */
5828 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5829 {
5830 #if defined(CONFIG_USER_ONLY)
5831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5832 #else
5833 TCGv EA, val;
5834 if (unlikely(!ctx->mem_idx)) {
5835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5836 return;
5837 }
5838 gen_set_access_type(ctx, ACCESS_CACHE);
5839 EA = tcg_temp_new();
5840 gen_addr_reg_index(ctx, EA);
5841 val = tcg_temp_new();
5842 gen_qemu_ld32u(ctx, val, EA);
5843 tcg_temp_free(val);
5844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5845 tcg_temp_free(EA);
5846 #endif
5847 }
5848
5849 /* icbt */
5850 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5851 {
5852 /* interpreted as no-op */
5853 /* XXX: specification say this is treated as a load by the MMU
5854 * but does not generate any exception
5855 */
5856 }
5857
5858 /* iccci */
5859 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5860 {
5861 #if defined(CONFIG_USER_ONLY)
5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5863 #else
5864 if (unlikely(!ctx->mem_idx)) {
5865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5866 return;
5867 }
5868 /* interpreted as no-op */
5869 #endif
5870 }
5871
5872 /* icread */
5873 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5874 {
5875 #if defined(CONFIG_USER_ONLY)
5876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5877 #else
5878 if (unlikely(!ctx->mem_idx)) {
5879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5880 return;
5881 }
5882 /* interpreted as no-op */
5883 #endif
5884 }
5885
5886 /* rfci (mem_idx only) */
5887 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5888 {
5889 #if defined(CONFIG_USER_ONLY)
5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5891 #else
5892 if (unlikely(!ctx->mem_idx)) {
5893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5894 return;
5895 }
5896 /* Restore CPU state */
5897 gen_helper_40x_rfci();
5898 gen_sync_exception(ctx);
5899 #endif
5900 }
5901
5902 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5903 {
5904 #if defined(CONFIG_USER_ONLY)
5905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5906 #else
5907 if (unlikely(!ctx->mem_idx)) {
5908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5909 return;
5910 }
5911 /* Restore CPU state */
5912 gen_helper_rfci();
5913 gen_sync_exception(ctx);
5914 #endif
5915 }
5916
5917 /* BookE specific */
5918 /* XXX: not implemented on 440 ? */
5919 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5920 {
5921 #if defined(CONFIG_USER_ONLY)
5922 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5923 #else
5924 if (unlikely(!ctx->mem_idx)) {
5925 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5926 return;
5927 }
5928 /* Restore CPU state */
5929 gen_helper_rfdi();
5930 gen_sync_exception(ctx);
5931 #endif
5932 }
5933
5934 /* XXX: not implemented on 440 ? */
5935 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5936 {
5937 #if defined(CONFIG_USER_ONLY)
5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5939 #else
5940 if (unlikely(!ctx->mem_idx)) {
5941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5942 return;
5943 }
5944 /* Restore CPU state */
5945 gen_helper_rfmci();
5946 gen_sync_exception(ctx);
5947 #endif
5948 }
5949
5950 /* TLB management - PowerPC 405 implementation */
5951 /* tlbre */
5952 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5953 {
5954 #if defined(CONFIG_USER_ONLY)
5955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5956 #else
5957 if (unlikely(!ctx->mem_idx)) {
5958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5959 return;
5960 }
5961 switch (rB(ctx->opcode)) {
5962 case 0:
5963 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5964 break;
5965 case 1:
5966 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5967 break;
5968 default:
5969 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5970 break;
5971 }
5972 #endif
5973 }
5974
5975 /* tlbsx - tlbsx. */
5976 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5977 {
5978 #if defined(CONFIG_USER_ONLY)
5979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5980 #else
5981 TCGv t0;
5982 if (unlikely(!ctx->mem_idx)) {
5983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5984 return;
5985 }
5986 t0 = tcg_temp_new();
5987 gen_addr_reg_index(ctx, t0);
5988 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5989 tcg_temp_free(t0);
5990 if (Rc(ctx->opcode)) {
5991 int l1 = gen_new_label();
5992 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5993 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5994 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5995 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5996 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5997 gen_set_label(l1);
5998 }
5999 #endif
6000 }
6001
6002 /* tlbwe */
6003 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
6004 {
6005 #if defined(CONFIG_USER_ONLY)
6006 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6007 #else
6008 if (unlikely(!ctx->mem_idx)) {
6009 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6010 return;
6011 }
6012 switch (rB(ctx->opcode)) {
6013 case 0:
6014 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6015 break;
6016 case 1:
6017 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6018 break;
6019 default:
6020 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6021 break;
6022 }
6023 #endif
6024 }
6025
6026 /* TLB management - PowerPC 440 implementation */
6027 /* tlbre */
6028 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
6029 {
6030 #if defined(CONFIG_USER_ONLY)
6031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6032 #else
6033 if (unlikely(!ctx->mem_idx)) {
6034 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6035 return;
6036 }
6037 switch (rB(ctx->opcode)) {
6038 case 0:
6039 case 1:
6040 case 2:
6041 {
6042 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6043 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6044 tcg_temp_free_i32(t0);
6045 }
6046 break;
6047 default:
6048 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6049 break;
6050 }
6051 #endif
6052 }
6053
6054 /* tlbsx - tlbsx. */
6055 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
6056 {
6057 #if defined(CONFIG_USER_ONLY)
6058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6059 #else
6060 TCGv t0;
6061 if (unlikely(!ctx->mem_idx)) {
6062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6063 return;
6064 }
6065 t0 = tcg_temp_new();
6066 gen_addr_reg_index(ctx, t0);
6067 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6068 tcg_temp_free(t0);
6069 if (Rc(ctx->opcode)) {
6070 int l1 = gen_new_label();
6071 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6072 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6073 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6074 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6075 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6076 gen_set_label(l1);
6077 }
6078 #endif
6079 }
6080
6081 /* tlbwe */
6082 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
6083 {
6084 #if defined(CONFIG_USER_ONLY)
6085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6086 #else
6087 if (unlikely(!ctx->mem_idx)) {
6088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6089 return;
6090 }
6091 switch (rB(ctx->opcode)) {
6092 case 0:
6093 case 1:
6094 case 2:
6095 {
6096 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6097 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6098 tcg_temp_free_i32(t0);
6099 }
6100 break;
6101 default:
6102 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6103 break;
6104 }
6105 #endif
6106 }
6107
6108 /* wrtee */
6109 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
6110 {
6111 #if defined(CONFIG_USER_ONLY)
6112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6113 #else
6114 TCGv t0;
6115 if (unlikely(!ctx->mem_idx)) {
6116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6117 return;
6118 }
6119 t0 = tcg_temp_new();
6120 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6121 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6122 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6123 tcg_temp_free(t0);
6124 /* Stop translation to have a chance to raise an exception
6125 * if we just set msr_ee to 1
6126 */
6127 gen_stop_exception(ctx);
6128 #endif
6129 }
6130
6131 /* wrteei */
6132 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
6133 {
6134 #if defined(CONFIG_USER_ONLY)
6135 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6136 #else
6137 if (unlikely(!ctx->mem_idx)) {
6138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6139 return;
6140 }
6141 if (ctx->opcode & 0x00010000) {
6142 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6143 /* Stop translation to have a chance to raise an exception */
6144 gen_stop_exception(ctx);
6145 } else {
6146 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6147 }
6148 #endif
6149 }
6150
6151 /* PowerPC 440 specific instructions */
6152 /* dlmzb */
6153 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6154 {
6155 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6156 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6157 cpu_gpr[rB(ctx->opcode)], t0);
6158 tcg_temp_free_i32(t0);
6159 }
6160
6161 /* mbar replaces eieio on 440 */
6162 GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
6163 {
6164 /* interpreted as no-op */
6165 }
6166
6167 /* msync replaces sync on 440 */
6168 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
6169 {
6170 /* interpreted as no-op */
6171 }
6172
6173 /* icbt */
6174 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
6175 {
6176 /* interpreted as no-op */
6177 /* XXX: specification say this is treated as a load by the MMU
6178 * but does not generate any exception
6179 */
6180 }
6181
6182 /*** Altivec vector extension ***/
6183 /* Altivec registers moves */
6184
6185 static always_inline TCGv_ptr gen_avr_ptr(int reg)
6186 {
6187 TCGv_ptr r = tcg_temp_new_ptr();
6188 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6189 return r;
6190 }
6191
6192 #define GEN_VR_LDX(name, opc2, opc3) \
6193 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6194 { \
6195 TCGv EA; \
6196 if (unlikely(!ctx->altivec_enabled)) { \
6197 gen_exception(ctx, POWERPC_EXCP_VPU); \
6198 return; \
6199 } \
6200 gen_set_access_type(ctx, ACCESS_INT); \
6201 EA = tcg_temp_new(); \
6202 gen_addr_reg_index(ctx, EA); \
6203 tcg_gen_andi_tl(EA, EA, ~0xf); \
6204 if (ctx->le_mode) { \
6205 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6206 tcg_gen_addi_tl(EA, EA, 8); \
6207 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6208 } else { \
6209 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6210 tcg_gen_addi_tl(EA, EA, 8); \
6211 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6212 } \
6213 tcg_temp_free(EA); \
6214 }
6215
6216 #define GEN_VR_STX(name, opc2, opc3) \
6217 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6218 { \
6219 TCGv EA; \
6220 if (unlikely(!ctx->altivec_enabled)) { \
6221 gen_exception(ctx, POWERPC_EXCP_VPU); \
6222 return; \
6223 } \
6224 gen_set_access_type(ctx, ACCESS_INT); \
6225 EA = tcg_temp_new(); \
6226 gen_addr_reg_index(ctx, EA); \
6227 tcg_gen_andi_tl(EA, EA, ~0xf); \
6228 if (ctx->le_mode) { \
6229 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6230 tcg_gen_addi_tl(EA, EA, 8); \
6231 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6232 } else { \
6233 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6234 tcg_gen_addi_tl(EA, EA, 8); \
6235 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6236 } \
6237 tcg_temp_free(EA); \
6238 }
6239
6240 #define GEN_VR_LVE(name, opc2, opc3) \
6241 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6242 { \
6243 TCGv EA; \
6244 TCGv_ptr rs; \
6245 if (unlikely(!ctx->altivec_enabled)) { \
6246 gen_exception(ctx, POWERPC_EXCP_VPU); \
6247 return; \
6248 } \
6249 gen_set_access_type(ctx, ACCESS_INT); \
6250 EA = tcg_temp_new(); \
6251 gen_addr_reg_index(ctx, EA); \
6252 rs = gen_avr_ptr(rS(ctx->opcode)); \
6253 gen_helper_lve##name (rs, EA); \
6254 tcg_temp_free(EA); \
6255 tcg_temp_free_ptr(rs); \
6256 }
6257
6258 #define GEN_VR_STVE(name, opc2, opc3) \
6259 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6260 { \
6261 TCGv EA; \
6262 TCGv_ptr rs; \
6263 if (unlikely(!ctx->altivec_enabled)) { \
6264 gen_exception(ctx, POWERPC_EXCP_VPU); \
6265 return; \
6266 } \
6267 gen_set_access_type(ctx, ACCESS_INT); \
6268 EA = tcg_temp_new(); \
6269 gen_addr_reg_index(ctx, EA); \
6270 rs = gen_avr_ptr(rS(ctx->opcode)); \
6271 gen_helper_stve##name (rs, EA); \
6272 tcg_temp_free(EA); \
6273 tcg_temp_free_ptr(rs); \
6274 }
6275
6276 GEN_VR_LDX(lvx, 0x07, 0x03);
6277 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6278 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6279
6280 GEN_VR_LVE(bx, 0x07, 0x00);
6281 GEN_VR_LVE(hx, 0x07, 0x01);
6282 GEN_VR_LVE(wx, 0x07, 0x02);
6283
6284 GEN_VR_STX(svx, 0x07, 0x07);
6285 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6286 GEN_VR_STX(svxl, 0x07, 0x0F);
6287
6288 GEN_VR_STVE(bx, 0x07, 0x04);
6289 GEN_VR_STVE(hx, 0x07, 0x05);
6290 GEN_VR_STVE(wx, 0x07, 0x06);
6291
6292 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6293 {
6294 TCGv_ptr rd;
6295 TCGv EA;
6296 if (unlikely(!ctx->altivec_enabled)) {
6297 gen_exception(ctx, POWERPC_EXCP_VPU);
6298 return;
6299 }
6300 EA = tcg_temp_new();
6301 gen_addr_reg_index(ctx, EA);
6302 rd = gen_avr_ptr(rD(ctx->opcode));
6303 gen_helper_lvsl(rd, EA);
6304 tcg_temp_free(EA);
6305 tcg_temp_free_ptr(rd);
6306 }
6307
6308 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6309 {
6310 TCGv_ptr rd;
6311 TCGv EA;
6312 if (unlikely(!ctx->altivec_enabled)) {
6313 gen_exception(ctx, POWERPC_EXCP_VPU);
6314 return;
6315 }
6316 EA = tcg_temp_new();
6317 gen_addr_reg_index(ctx, EA);
6318 rd = gen_avr_ptr(rD(ctx->opcode));
6319 gen_helper_lvsr(rd, EA);
6320 tcg_temp_free(EA);
6321 tcg_temp_free_ptr(rd);
6322 }
6323
6324 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6325 {
6326 TCGv_i32 t;
6327 if (unlikely(!ctx->altivec_enabled)) {
6328 gen_exception(ctx, POWERPC_EXCP_VPU);
6329 return;
6330 }
6331 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6332 t = tcg_temp_new_i32();
6333 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6334 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6335 tcg_temp_free_i32(t);
6336 }
6337
6338 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6339 {
6340 TCGv_ptr p;
6341 if (unlikely(!ctx->altivec_enabled)) {
6342 gen_exception(ctx, POWERPC_EXCP_VPU);
6343 return;
6344 }
6345 p = gen_avr_ptr(rD(ctx->opcode));
6346 gen_helper_mtvscr(p);
6347 tcg_temp_free_ptr(p);
6348 }
6349
6350 /* Logical operations */
6351 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6352 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6353 { \
6354 if (unlikely(!ctx->altivec_enabled)) { \
6355 gen_exception(ctx, POWERPC_EXCP_VPU); \
6356 return; \
6357 } \
6358 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6359 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6360 }
6361
6362 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6363 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6364 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6365 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6366 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6367
6368 #define GEN_VXFORM(name, opc2, opc3) \
6369 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6370 { \
6371 TCGv_ptr ra, rb, rd; \
6372 if (unlikely(!ctx->altivec_enabled)) { \
6373 gen_exception(ctx, POWERPC_EXCP_VPU); \
6374 return; \
6375 } \
6376 ra = gen_avr_ptr(rA(ctx->opcode)); \
6377 rb = gen_avr_ptr(rB(ctx->opcode)); \
6378 rd = gen_avr_ptr(rD(ctx->opcode)); \
6379 gen_helper_##name (rd, ra, rb); \
6380 tcg_temp_free_ptr(ra); \
6381 tcg_temp_free_ptr(rb); \
6382 tcg_temp_free_ptr(rd); \
6383 }
6384
6385 GEN_VXFORM(vaddubm, 0, 0);
6386 GEN_VXFORM(vadduhm, 0, 1);
6387 GEN_VXFORM(vadduwm, 0, 2);
6388 GEN_VXFORM(vsububm, 0, 16);
6389 GEN_VXFORM(vsubuhm, 0, 17);
6390 GEN_VXFORM(vsubuwm, 0, 18);
6391 GEN_VXFORM(vmaxub, 1, 0);
6392 GEN_VXFORM(vmaxuh, 1, 1);
6393 GEN_VXFORM(vmaxuw, 1, 2);
6394 GEN_VXFORM(vmaxsb, 1, 4);
6395 GEN_VXFORM(vmaxsh, 1, 5);
6396 GEN_VXFORM(vmaxsw, 1, 6);
6397 GEN_VXFORM(vminub, 1, 8);
6398 GEN_VXFORM(vminuh, 1, 9);
6399 GEN_VXFORM(vminuw, 1, 10);
6400 GEN_VXFORM(vminsb, 1, 12);
6401 GEN_VXFORM(vminsh, 1, 13);
6402 GEN_VXFORM(vminsw, 1, 14);
6403 GEN_VXFORM(vavgub, 1, 16);
6404 GEN_VXFORM(vavguh, 1, 17);
6405 GEN_VXFORM(vavguw, 1, 18);
6406 GEN_VXFORM(vavgsb, 1, 20);
6407 GEN_VXFORM(vavgsh, 1, 21);
6408 GEN_VXFORM(vavgsw, 1, 22);
6409 GEN_VXFORM(vmrghb, 6, 0);
6410 GEN_VXFORM(vmrghh, 6, 1);
6411 GEN_VXFORM(vmrghw, 6, 2);
6412 GEN_VXFORM(vmrglb, 6, 4);
6413 GEN_VXFORM(vmrglh, 6, 5);
6414 GEN_VXFORM(vmrglw, 6, 6);
6415 GEN_VXFORM(vmuloub, 4, 0);
6416 GEN_VXFORM(vmulouh, 4, 1);
6417 GEN_VXFORM(vmulosb, 4, 4);
6418 GEN_VXFORM(vmulosh, 4, 5);
6419 GEN_VXFORM(vmuleub, 4, 8);
6420 GEN_VXFORM(vmuleuh, 4, 9);
6421 GEN_VXFORM(vmulesb, 4, 12);
6422 GEN_VXFORM(vmulesh, 4, 13);
6423 GEN_VXFORM(vslb, 2, 4);
6424 GEN_VXFORM(vslh, 2, 5);
6425 GEN_VXFORM(vslw, 2, 6);
6426 GEN_VXFORM(vsrb, 2, 8);
6427 GEN_VXFORM(vsrh, 2, 9);
6428 GEN_VXFORM(vsrw, 2, 10);
6429 GEN_VXFORM(vsrab, 2, 12);
6430 GEN_VXFORM(vsrah, 2, 13);
6431 GEN_VXFORM(vsraw, 2, 14);
6432 GEN_VXFORM(vslo, 6, 16);
6433 GEN_VXFORM(vsro, 6, 17);
6434 GEN_VXFORM(vaddcuw, 0, 6);
6435 GEN_VXFORM(vsubcuw, 0, 22);
6436 GEN_VXFORM(vaddubs, 0, 8);
6437 GEN_VXFORM(vadduhs, 0, 9);
6438 GEN_VXFORM(vadduws, 0, 10);
6439 GEN_VXFORM(vaddsbs, 0, 12);
6440 GEN_VXFORM(vaddshs, 0, 13);
6441 GEN_VXFORM(vaddsws, 0, 14);
6442 GEN_VXFORM(vsububs, 0, 24);
6443 GEN_VXFORM(vsubuhs, 0, 25);
6444 GEN_VXFORM(vsubuws, 0, 26);
6445 GEN_VXFORM(vsubsbs, 0, 28);
6446 GEN_VXFORM(vsubshs, 0, 29);
6447 GEN_VXFORM(vsubsws, 0, 30);
6448 GEN_VXFORM(vrlb, 2, 0);
6449 GEN_VXFORM(vrlh, 2, 1);
6450 GEN_VXFORM(vrlw, 2, 2);
6451 GEN_VXFORM(vsl, 2, 7);
6452 GEN_VXFORM(vsr, 2, 11);
6453 GEN_VXFORM(vpkuhum, 7, 0);
6454 GEN_VXFORM(vpkuwum, 7, 1);
6455 GEN_VXFORM(vpkuhus, 7, 2);
6456 GEN_VXFORM(vpkuwus, 7, 3);
6457 GEN_VXFORM(vpkshus, 7, 4);
6458 GEN_VXFORM(vpkswus, 7, 5);
6459 GEN_VXFORM(vpkshss, 7, 6);
6460 GEN_VXFORM(vpkswss, 7, 7);
6461 GEN_VXFORM(vpkpx, 7, 12);
6462 GEN_VXFORM(vsum4ubs, 4, 24);
6463 GEN_VXFORM(vsum4sbs, 4, 28);
6464 GEN_VXFORM(vsum4shs, 4, 25);
6465 GEN_VXFORM(vsum2sws, 4, 26);
6466 GEN_VXFORM(vsumsws, 4, 30);
6467 GEN_VXFORM(vaddfp, 5, 0);
6468 GEN_VXFORM(vsubfp, 5, 1);
6469 GEN_VXFORM(vmaxfp, 5, 16);
6470 GEN_VXFORM(vminfp, 5, 17);
6471
6472 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6473 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6474 { \
6475 TCGv_ptr ra, rb, rd; \
6476 if (unlikely(!ctx->altivec_enabled)) { \
6477 gen_exception(ctx, POWERPC_EXCP_VPU); \
6478 return; \
6479 } \
6480 ra = gen_avr_ptr(rA(ctx->opcode)); \
6481 rb = gen_avr_ptr(rB(ctx->opcode)); \
6482 rd = gen_avr_ptr(rD(ctx->opcode)); \
6483 gen_helper_##opname (rd, ra, rb); \
6484 tcg_temp_free_ptr(ra); \
6485 tcg_temp_free_ptr(rb); \
6486 tcg_temp_free_ptr(rd); \
6487 }
6488
6489 #define GEN_VXRFORM(name, opc2, opc3) \
6490 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6491 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6492
6493 GEN_VXRFORM(vcmpequb, 3, 0)
6494 GEN_VXRFORM(vcmpequh, 3, 1)
6495 GEN_VXRFORM(vcmpequw, 3, 2)
6496 GEN_VXRFORM(vcmpgtsb, 3, 12)
6497 GEN_VXRFORM(vcmpgtsh, 3, 13)
6498 GEN_VXRFORM(vcmpgtsw, 3, 14)
6499 GEN_VXRFORM(vcmpgtub, 3, 8)
6500 GEN_VXRFORM(vcmpgtuh, 3, 9)
6501 GEN_VXRFORM(vcmpgtuw, 3, 10)
6502 GEN_VXRFORM(vcmpeqfp, 3, 3)
6503 GEN_VXRFORM(vcmpgefp, 3, 7)
6504 GEN_VXRFORM(vcmpgtfp, 3, 11)
6505 GEN_VXRFORM(vcmpbfp, 3, 15)
6506
6507 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6508 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6509 { \
6510 TCGv_ptr rd; \
6511 TCGv_i32 simm; \
6512 if (unlikely(!ctx->altivec_enabled)) { \
6513 gen_exception(ctx, POWERPC_EXCP_VPU); \
6514 return; \
6515 } \
6516 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6517 rd = gen_avr_ptr(rD(ctx->opcode)); \
6518 gen_helper_##name (rd, simm); \
6519 tcg_temp_free_i32(simm); \
6520 tcg_temp_free_ptr(rd); \
6521 }
6522
6523 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6524 GEN_VXFORM_SIMM(vspltish, 6, 13);
6525 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6526
6527 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6528 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6529 { \
6530 TCGv_ptr rb, rd; \
6531 if (unlikely(!ctx->altivec_enabled)) { \
6532 gen_exception(ctx, POWERPC_EXCP_VPU); \
6533 return; \
6534 } \
6535 rb = gen_avr_ptr(rB(ctx->opcode)); \
6536 rd = gen_avr_ptr(rD(ctx->opcode)); \
6537 gen_helper_##name (rd, rb); \
6538 tcg_temp_free_ptr(rb); \
6539 tcg_temp_free_ptr(rd); \
6540 }
6541
6542 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6543 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6544 GEN_VXFORM_NOA(vupklsb, 7, 10);
6545 GEN_VXFORM_NOA(vupklsh, 7, 11);
6546 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6547 GEN_VXFORM_NOA(vupklpx, 7, 15);
6548 GEN_VXFORM_NOA(vrefp, 5, 4);
6549 GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
6550 GEN_VXFORM_NOA(vlogefp, 5, 7);
6551 GEN_VXFORM_NOA(vrfim, 5, 8);
6552 GEN_VXFORM_NOA(vrfin, 5, 9);
6553 GEN_VXFORM_NOA(vrfip, 5, 10);
6554 GEN_VXFORM_NOA(vrfiz, 5, 11);
6555
6556 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6557 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6558 { \
6559 TCGv_ptr rd; \
6560 TCGv_i32 simm; \
6561 if (unlikely(!ctx->altivec_enabled)) { \
6562 gen_exception(ctx, POWERPC_EXCP_VPU); \
6563 return; \
6564 } \
6565 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6566 rd = gen_avr_ptr(rD(ctx->opcode)); \
6567 gen_helper_##name (rd, simm); \
6568 tcg_temp_free_i32(simm); \
6569 tcg_temp_free_ptr(rd); \
6570 }
6571
6572 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6573 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6574 { \
6575 TCGv_ptr rb, rd; \
6576 TCGv_i32 uimm; \
6577 if (unlikely(!ctx->altivec_enabled)) { \
6578 gen_exception(ctx, POWERPC_EXCP_VPU); \
6579 return; \
6580 } \
6581 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6582 rb = gen_avr_ptr(rB(ctx->opcode)); \
6583 rd = gen_avr_ptr(rD(ctx->opcode)); \
6584 gen_helper_##name (rd, rb, uimm); \
6585 tcg_temp_free_i32(uimm); \
6586 tcg_temp_free_ptr(rb); \
6587 tcg_temp_free_ptr(rd); \
6588 }
6589
6590 GEN_VXFORM_UIMM(vspltb, 6, 8);
6591 GEN_VXFORM_UIMM(vsplth, 6, 9);
6592 GEN_VXFORM_UIMM(vspltw, 6, 10);
6593 GEN_VXFORM_UIMM(vcfux, 5, 12);
6594 GEN_VXFORM_UIMM(vcfsx, 5, 13);
6595 GEN_VXFORM_UIMM(vctuxs, 5, 14);
6596 GEN_VXFORM_UIMM(vctsxs, 5, 15);
6597
6598 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6599 {
6600 TCGv_ptr ra, rb, rd;
6601 TCGv_i32 sh;
6602 if (unlikely(!ctx->altivec_enabled)) {
6603 gen_exception(ctx, POWERPC_EXCP_VPU);
6604 return;
6605 }
6606 ra = gen_avr_ptr(rA(ctx->opcode));
6607 rb = gen_avr_ptr(rB(ctx->opcode));
6608 rd = gen_avr_ptr(rD(ctx->opcode));
6609 sh = tcg_const_i32(VSH(ctx->opcode));
6610 gen_helper_vsldoi (rd, ra, rb, sh);
6611 tcg_temp_free_ptr(ra);
6612 tcg_temp_free_ptr(rb);
6613 tcg_temp_free_ptr(rd);
6614 tcg_temp_free_i32(sh);
6615 }
6616
6617 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6618 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6619 { \
6620 TCGv_ptr ra, rb, rc, rd; \
6621 if (unlikely(!ctx->altivec_enabled)) { \
6622 gen_exception(ctx, POWERPC_EXCP_VPU); \
6623 return; \
6624 } \
6625 ra = gen_avr_ptr(rA(ctx->opcode)); \
6626 rb = gen_avr_ptr(rB(ctx->opcode)); \
6627 rc = gen_avr_ptr(rC(ctx->opcode)); \
6628 rd = gen_avr_ptr(rD(ctx->opcode)); \
6629 if (Rc(ctx->opcode)) { \
6630 gen_helper_##name1 (rd, ra, rb, rc); \
6631 } else { \
6632 gen_helper_##name0 (rd, ra, rb, rc); \
6633 } \
6634 tcg_temp_free_ptr(ra); \
6635 tcg_temp_free_ptr(rb); \
6636 tcg_temp_free_ptr(rc); \
6637 tcg_temp_free_ptr(rd); \
6638 }
6639
6640 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6641
6642 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6643 {
6644 TCGv_ptr ra, rb, rc, rd;
6645 if (unlikely(!ctx->altivec_enabled)) {
6646 gen_exception(ctx, POWERPC_EXCP_VPU);
6647 return;
6648 }
6649 ra = gen_avr_ptr(rA(ctx->opcode));
6650 rb = gen_avr_ptr(rB(ctx->opcode));
6651 rc = gen_avr_ptr(rC(ctx->opcode));
6652 rd = gen_avr_ptr(rD(ctx->opcode));
6653 gen_helper_vmladduhm(rd, ra, rb, rc);
6654 tcg_temp_free_ptr(ra);
6655 tcg_temp_free_ptr(rb);
6656 tcg_temp_free_ptr(rc);
6657 tcg_temp_free_ptr(rd);
6658 }
6659
6660 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6661 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6662 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6663 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6664 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6665
6666 /*** SPE extension ***/
6667 /* Register moves */
6668
6669 static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
6670 #if defined(TARGET_PPC64)
6671 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6672 #else
6673 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6674 #endif
6675 }
6676
6677 static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
6678 #if defined(TARGET_PPC64)
6679 tcg_gen_mov_i64(cpu_gpr[reg], t);
6680 #else
6681 TCGv_i64 tmp = tcg_temp_new_i64();
6682 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6683 tcg_gen_shri_i64(tmp, t, 32);
6684 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6685 tcg_temp_free_i64(tmp);
6686 #endif
6687 }
6688
6689 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6690 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6691 { \
6692 if (Rc(ctx->opcode)) \
6693 gen_##name1(ctx); \
6694 else \
6695 gen_##name0(ctx); \
6696 }
6697
6698 /* Handler for undefined SPE opcodes */
6699 static always_inline void gen_speundef (DisasContext *ctx)
6700 {
6701 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6702 }
6703
6704 /* SPE logic */
6705 #if defined(TARGET_PPC64)
6706 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6707 static always_inline void gen_##name (DisasContext *ctx) \
6708 { \
6709 if (unlikely(!ctx->spe_enabled)) { \
6710 gen_exception(ctx, POWERPC_EXCP_APU); \
6711 return; \
6712 } \
6713 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6714 cpu_gpr[rB(ctx->opcode)]); \
6715 }
6716 #else
6717 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6718 static always_inline void gen_##name (DisasContext *ctx) \
6719 { \
6720 if (unlikely(!ctx->spe_enabled)) { \
6721 gen_exception(ctx, POWERPC_EXCP_APU); \
6722 return; \
6723 } \
6724 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6725 cpu_gpr[rB(ctx->opcode)]); \
6726 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6727 cpu_gprh[rB(ctx->opcode)]); \
6728 }
6729 #endif
6730
6731 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6732 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6733 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6734 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6735 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6736 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6737 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6738 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6739
6740 /* SPE logic immediate */
6741 #if defined(TARGET_PPC64)
6742 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6743 static always_inline void gen_##name (DisasContext *ctx) \
6744 { \
6745 if (unlikely(!ctx->spe_enabled)) { \
6746 gen_exception(ctx, POWERPC_EXCP_APU); \
6747 return; \
6748 } \
6749 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6750 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6751 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6752 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6753 tcg_opi(t0, t0, rB(ctx->opcode)); \
6754 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6755 tcg_gen_trunc_i64_i32(t1, t2); \
6756 tcg_temp_free_i64(t2); \
6757 tcg_opi(t1, t1, rB(ctx->opcode)); \
6758 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6759 tcg_temp_free_i32(t0); \
6760 tcg_temp_free_i32(t1); \
6761 }
6762 #else
6763 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6764 static always_inline void gen_##name (DisasContext *ctx) \
6765 { \
6766 if (unlikely(!ctx->spe_enabled)) { \
6767 gen_exception(ctx, POWERPC_EXCP_APU); \
6768 return; \
6769 } \
6770 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6771 rB(ctx->opcode)); \
6772 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6773 rB(ctx->opcode)); \
6774 }
6775 #endif
6776 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6777 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6778 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6779 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6780
6781 /* SPE arithmetic */
6782 #if defined(TARGET_PPC64)
6783 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6784 static always_inline void gen_##name (DisasContext *ctx) \
6785 { \
6786 if (unlikely(!ctx->spe_enabled)) { \
6787 gen_exception(ctx, POWERPC_EXCP_APU); \
6788 return; \
6789 } \
6790 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6791 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6792 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6793 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6794 tcg_op(t0, t0); \
6795 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6796 tcg_gen_trunc_i64_i32(t1, t2); \
6797 tcg_temp_free_i64(t2); \
6798 tcg_op(t1, t1); \
6799 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6800 tcg_temp_free_i32(t0); \
6801 tcg_temp_free_i32(t1); \
6802 }
6803 #else
6804 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6805 static always_inline void gen_##name (DisasContext *ctx) \
6806 { \
6807 if (unlikely(!ctx->spe_enabled)) { \
6808 gen_exception(ctx, POWERPC_EXCP_APU); \
6809 return; \
6810 } \
6811 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6812 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6813 }
6814 #endif
6815
6816 static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
6817 {
6818 int l1 = gen_new_label();
6819 int l2 = gen_new_label();
6820
6821 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6822 tcg_gen_neg_i32(ret, arg1);
6823 tcg_gen_br(l2);
6824 gen_set_label(l1);
6825 tcg_gen_mov_i32(ret, arg1);
6826 gen_set_label(l2);
6827 }
6828 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6829 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6830 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6831 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6832 static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
6833 {
6834 tcg_gen_addi_i32(ret, arg1, 0x8000);
6835 tcg_gen_ext16u_i32(ret, ret);
6836 }
6837 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6838 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6839 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6840
6841 #if defined(TARGET_PPC64)
6842 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6843 static always_inline void gen_##name (DisasContext *ctx) \
6844 { \
6845 if (unlikely(!ctx->spe_enabled)) { \
6846 gen_exception(ctx, POWERPC_EXCP_APU); \
6847 return; \
6848 } \
6849 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6850 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6851 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6852 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6853 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6854 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6855 tcg_op(t0, t0, t2); \
6856 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6857 tcg_gen_trunc_i64_i32(t1, t3); \
6858 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6859 tcg_gen_trunc_i64_i32(t2, t3); \
6860 tcg_temp_free_i64(t3); \
6861 tcg_op(t1, t1, t2); \
6862 tcg_temp_free_i32(t2); \
6863 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6864 tcg_temp_free_i32(t0); \
6865 tcg_temp_free_i32(t1); \
6866 }
6867 #else
6868 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6869 static always_inline void gen_##name (DisasContext *ctx) \
6870 { \
6871 if (unlikely(!ctx->spe_enabled)) { \
6872 gen_exception(ctx, POWERPC_EXCP_APU); \
6873 return; \
6874 } \
6875 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6876 cpu_gpr[rB(ctx->opcode)]); \
6877 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6878 cpu_gprh[rB(ctx->opcode)]); \
6879 }
6880 #endif
6881
6882 static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6883 {
6884 TCGv_i32 t0;
6885 int l1, l2;
6886
6887 l1 = gen_new_label();
6888 l2 = gen_new_label();
6889 t0 = tcg_temp_local_new_i32();
6890 /* No error here: 6 bits are used */
6891 tcg_gen_andi_i32(t0, arg2, 0x3F);
6892 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6893 tcg_gen_shr_i32(ret, arg1, t0);
6894 tcg_gen_br(l2);
6895 gen_set_label(l1);
6896 tcg_gen_movi_i32(ret, 0);
6897 tcg_gen_br(l2);
6898 tcg_temp_free_i32(t0);
6899 }
6900 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6901 static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6902 {
6903 TCGv_i32 t0;
6904 int l1, l2;
6905
6906 l1 = gen_new_label();
6907 l2 = gen_new_label();
6908 t0 = tcg_temp_local_new_i32();
6909 /* No error here: 6 bits are used */
6910 tcg_gen_andi_i32(t0, arg2, 0x3F);
6911 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6912 tcg_gen_sar_i32(ret, arg1, t0);
6913 tcg_gen_br(l2);
6914 gen_set_label(l1);
6915 tcg_gen_movi_i32(ret, 0);
6916 tcg_gen_br(l2);
6917 tcg_temp_free_i32(t0);
6918 }
6919 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6920 static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6921 {
6922 TCGv_i32 t0;
6923 int l1, l2;
6924
6925 l1 = gen_new_label();
6926 l2 = gen_new_label();
6927 t0 = tcg_temp_local_new_i32();
6928 /* No error here: 6 bits are used */
6929 tcg_gen_andi_i32(t0, arg2, 0x3F);
6930 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6931 tcg_gen_shl_i32(ret, arg1, t0);
6932 tcg_gen_br(l2);
6933 gen_set_label(l1);
6934 tcg_gen_movi_i32(ret, 0);
6935 tcg_gen_br(l2);
6936 tcg_temp_free_i32(t0);
6937 }
6938 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6939 static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6940 {
6941 TCGv_i32 t0 = tcg_temp_new_i32();
6942 tcg_gen_andi_i32(t0, arg2, 0x1F);
6943 tcg_gen_rotl_i32(ret, arg1, t0);
6944 tcg_temp_free_i32(t0);
6945 }
6946 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6947 static always_inline void gen_evmergehi (DisasContext *ctx)
6948 {
6949 if (unlikely(!ctx->spe_enabled)) {
6950 gen_exception(ctx, POWERPC_EXCP_APU);
6951 return;
6952 }
6953 #if defined(TARGET_PPC64)
6954 TCGv t0 = tcg_temp_new();
6955 TCGv t1 = tcg_temp_new();
6956 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6957 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6958 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6959 tcg_temp_free(t0);
6960 tcg_temp_free(t1);
6961 #else
6962 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6963 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6964 #endif
6965 }
6966 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6967 static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
6968 {
6969 tcg_gen_sub_i32(ret, arg2, arg1);
6970 }
6971 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6972
6973 /* SPE arithmetic immediate */
6974 #if defined(TARGET_PPC64)
6975 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6976 static always_inline void gen_##name (DisasContext *ctx) \
6977 { \
6978 if (unlikely(!ctx->spe_enabled)) { \
6979 gen_exception(ctx, POWERPC_EXCP_APU); \
6980 return; \
6981 } \
6982 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6983 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6984 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6985 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6986 tcg_op(t0, t0, rA(ctx->opcode)); \
6987 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6988 tcg_gen_trunc_i64_i32(t1, t2); \
6989 tcg_temp_free_i64(t2); \
6990 tcg_op(t1, t1, rA(ctx->opcode)); \
6991 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6992 tcg_temp_free_i32(t0); \
6993 tcg_temp_free_i32(t1); \
6994 }
6995 #else
6996 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6997 static always_inline void gen_##name (DisasContext *ctx) \
6998 { \
6999 if (unlikely(!ctx->spe_enabled)) { \
7000 gen_exception(ctx, POWERPC_EXCP_APU); \
7001 return; \
7002 } \
7003 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7004 rA(ctx->opcode)); \
7005 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7006 rA(ctx->opcode)); \
7007 }
7008 #endif
7009 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7010 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7011
7012 /* SPE comparison */
7013 #if defined(TARGET_PPC64)
7014 #define GEN_SPEOP_COMP(name, tcg_cond) \
7015 static always_inline void gen_##name (DisasContext *ctx) \
7016 { \
7017 if (unlikely(!ctx->spe_enabled)) { \
7018 gen_exception(ctx, POWERPC_EXCP_APU); \
7019 return; \
7020 } \
7021 int l1 = gen_new_label(); \
7022 int l2 = gen_new_label(); \
7023 int l3 = gen_new_label(); \
7024 int l4 = gen_new_label(); \
7025 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7026 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7027 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7028 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7029 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7030 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7031 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7032 tcg_gen_br(l2); \
7033 gen_set_label(l1); \
7034 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7035 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7036 gen_set_label(l2); \
7037 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7038 tcg_gen_trunc_i64_i32(t0, t2); \
7039 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7040 tcg_gen_trunc_i64_i32(t1, t2); \
7041 tcg_temp_free_i64(t2); \
7042 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7043 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7044 ~(CRF_CH | CRF_CH_AND_CL)); \
7045 tcg_gen_br(l4); \
7046 gen_set_label(l3); \
7047 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7048 CRF_CH | CRF_CH_OR_CL); \
7049 gen_set_label(l4); \
7050 tcg_temp_free_i32(t0); \
7051 tcg_temp_free_i32(t1); \
7052 }
7053 #else
7054 #define GEN_SPEOP_COMP(name, tcg_cond) \
7055 static always_inline void gen_##name (DisasContext *ctx) \
7056 { \
7057 if (unlikely(!ctx->spe_enabled)) { \
7058 gen_exception(ctx, POWERPC_EXCP_APU); \
7059 return; \
7060 } \
7061 int l1 = gen_new_label(); \
7062 int l2 = gen_new_label(); \
7063 int l3 = gen_new_label(); \
7064 int l4 = gen_new_label(); \
7065 \
7066 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7067 cpu_gpr[rB(ctx->opcode)], l1); \
7068 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7069 tcg_gen_br(l2); \
7070 gen_set_label(l1); \
7071 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7072 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7073 gen_set_label(l2); \
7074 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7075 cpu_gprh[rB(ctx->opcode)], l3); \
7076 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7077 ~(CRF_CH | CRF_CH_AND_CL)); \
7078 tcg_gen_br(l4); \
7079 gen_set_label(l3); \
7080 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7081 CRF_CH | CRF_CH_OR_CL); \
7082 gen_set_label(l4); \
7083 }
7084 #endif
7085 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7086 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7087 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7088 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7089 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7090
7091 /* SPE misc */
7092 static always_inline void gen_brinc (DisasContext *ctx)
7093 {
7094 /* Note: brinc is usable even if SPE is disabled */
7095 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7096 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7097 }
7098 static always_inline void gen_evmergelo (DisasContext *ctx)
7099 {
7100 if (unlikely(!ctx->spe_enabled)) {
7101 gen_exception(ctx, POWERPC_EXCP_APU);
7102 return;
7103 }
7104 #if defined(TARGET_PPC64)
7105 TCGv t0 = tcg_temp_new();
7106 TCGv t1 = tcg_temp_new();
7107 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7108 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7109 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7110 tcg_temp_free(t0);
7111 tcg_temp_free(t1);
7112 #else
7113 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7114 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7115 #endif
7116 }
7117 static always_inline void gen_evmergehilo (DisasContext *ctx)
7118 {
7119 if (unlikely(!ctx->spe_enabled)) {
7120 gen_exception(ctx, POWERPC_EXCP_APU);
7121 return;
7122 }
7123 #if defined(TARGET_PPC64)
7124 TCGv t0 = tcg_temp_new();
7125 TCGv t1 = tcg_temp_new();
7126 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7127 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7128 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7129 tcg_temp_free(t0);
7130 tcg_temp_free(t1);
7131 #else
7132 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7133 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7134 #endif
7135 }
7136 static always_inline void gen_evmergelohi (DisasContext *ctx)
7137 {
7138 if (unlikely(!ctx->spe_enabled)) {
7139 gen_exception(ctx, POWERPC_EXCP_APU);
7140 return;
7141 }
7142 #if defined(TARGET_PPC64)
7143 TCGv t0 = tcg_temp_new();
7144 TCGv t1 = tcg_temp_new();
7145 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7146 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7147 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7148 tcg_temp_free(t0);
7149 tcg_temp_free(t1);
7150 #else
7151 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7152 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7153 #endif
7154 }
7155 static always_inline void gen_evsplati (DisasContext *ctx)
7156 {
7157 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
7158
7159 #if defined(TARGET_PPC64)
7160 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7161 #else
7162 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7163 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7164 #endif
7165 }
7166 static always_inline void gen_evsplatfi (DisasContext *ctx)
7167 {
7168 uint64_t imm = rA(ctx->opcode) << 11;
7169
7170 #if defined(TARGET_PPC64)
7171 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7172 #else
7173 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7174 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7175 #endif
7176 }
7177
7178 static always_inline void gen_evsel (DisasContext *ctx)
7179 {
7180 int l1 = gen_new_label();
7181 int l2 = gen_new_label();
7182 int l3 = gen_new_label();
7183 int l4 = gen_new_label();
7184 TCGv_i32 t0 = tcg_temp_local_new_i32();
7185 #if defined(TARGET_PPC64)
7186 TCGv t1 = tcg_temp_local_new();
7187 TCGv t2 = tcg_temp_local_new();
7188 #endif
7189 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7190 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7191 #if defined(TARGET_PPC64)
7192 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7193 #else
7194 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7195 #endif
7196 tcg_gen_br(l2);
7197 gen_set_label(l1);
7198 #if defined(TARGET_PPC64)
7199 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7200 #else
7201 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7202 #endif
7203 gen_set_label(l2);
7204 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7205 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7206 #if defined(TARGET_PPC64)
7207 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7208 #else
7209 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7210 #endif
7211 tcg_gen_br(l4);
7212 gen_set_label(l3);
7213 #if defined(TARGET_PPC64)
7214 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7215 #else
7216 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7217 #endif
7218 gen_set_label(l4);
7219 tcg_temp_free_i32(t0);
7220 #if defined(TARGET_PPC64)
7221 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7222 tcg_temp_free(t1);
7223 tcg_temp_free(t2);
7224 #endif
7225 }
7226 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7227 {
7228 gen_evsel(ctx);
7229 }
7230 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7231 {
7232 gen_evsel(ctx);
7233 }
7234 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7235 {
7236 gen_evsel(ctx);
7237 }
7238 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7239 {
7240 gen_evsel(ctx);
7241 }
7242
7243 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7244 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7245 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7246 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7247 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7248 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7249 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7250 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7251 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7252 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7253 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7254 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7255 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7256 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7257 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7258 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7259 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7260 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7261 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7262 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7263 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7264 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7265 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7266 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7267 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7268
7269 /* SPE load and stores */
7270 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
7271 {
7272 target_ulong uimm = rB(ctx->opcode);
7273
7274 if (rA(ctx->opcode) == 0) {
7275 tcg_gen_movi_tl(EA, uimm << sh);
7276 } else {
7277 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7278 #if defined(TARGET_PPC64)
7279 if (!ctx->sf_mode) {
7280 tcg_gen_ext32u_tl(EA, EA);
7281 }
7282 #endif
7283 }
7284 }
7285
7286 static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7287 {
7288 #if defined(TARGET_PPC64)
7289 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7290 #else
7291 TCGv_i64 t0 = tcg_temp_new_i64();
7292 gen_qemu_ld64(ctx, t0, addr);
7293 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7294 tcg_gen_shri_i64(t0, t0, 32);
7295 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7296 tcg_temp_free_i64(t0);
7297 #endif
7298 }
7299
7300 static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7301 {
7302 #if defined(TARGET_PPC64)
7303 TCGv t0 = tcg_temp_new();
7304 gen_qemu_ld32u(ctx, t0, addr);
7305 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7306 gen_addr_add(ctx, addr, addr, 4);
7307 gen_qemu_ld32u(ctx, t0, addr);
7308 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7309 tcg_temp_free(t0);
7310 #else
7311 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7312 gen_addr_add(ctx, addr, addr, 4);
7313 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7314 #endif
7315 }
7316
7317 static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7318 {
7319 TCGv t0 = tcg_temp_new();
7320 #if defined(TARGET_PPC64)
7321 gen_qemu_ld16u(ctx, t0, addr);
7322 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7323 gen_addr_add(ctx, addr, addr, 2);
7324 gen_qemu_ld16u(ctx, t0, addr);
7325 tcg_gen_shli_tl(t0, t0, 32);
7326 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7327 gen_addr_add(ctx, addr, addr, 2);
7328 gen_qemu_ld16u(ctx, t0, addr);
7329 tcg_gen_shli_tl(t0, t0, 16);
7330 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7331 gen_addr_add(ctx, addr, addr, 2);
7332 gen_qemu_ld16u(ctx, t0, addr);
7333 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7334 #else
7335 gen_qemu_ld16u(ctx, t0, addr);
7336 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7337 gen_addr_add(ctx, addr, addr, 2);
7338 gen_qemu_ld16u(ctx, t0, addr);
7339 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7340 gen_addr_add(ctx, addr, addr, 2);
7341 gen_qemu_ld16u(ctx, t0, addr);
7342 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7343 gen_addr_add(ctx, addr, addr, 2);
7344 gen_qemu_ld16u(ctx, t0, addr);
7345 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7346 #endif
7347 tcg_temp_free(t0);
7348 }
7349
7350 static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7351 {
7352 TCGv t0 = tcg_temp_new();
7353 gen_qemu_ld16u(ctx, t0, addr);
7354 #if defined(TARGET_PPC64)
7355 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7356 tcg_gen_shli_tl(t0, t0, 16);
7357 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7358 #else
7359 tcg_gen_shli_tl(t0, t0, 16);
7360 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7361 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7362 #endif
7363 tcg_temp_free(t0);
7364 }
7365
7366 static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7367 {
7368 TCGv t0 = tcg_temp_new();
7369 gen_qemu_ld16u(ctx, t0, addr);
7370 #if defined(TARGET_PPC64)
7371 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7372 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7373 #else
7374 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7375 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7376 #endif
7377 tcg_temp_free(t0);
7378 }
7379
7380 static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7381 {
7382 TCGv t0 = tcg_temp_new();
7383 gen_qemu_ld16s(ctx, t0, addr);
7384 #if defined(TARGET_PPC64)
7385 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7386 tcg_gen_ext32u_tl(t0, t0);
7387 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7388 #else
7389 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7390 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7391 #endif
7392 tcg_temp_free(t0);
7393 }
7394
7395 static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7396 {
7397 TCGv t0 = tcg_temp_new();
7398 #if defined(TARGET_PPC64)
7399 gen_qemu_ld16u(ctx, t0, addr);
7400 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7401 gen_addr_add(ctx, addr, addr, 2);
7402 gen_qemu_ld16u(ctx, t0, addr);
7403 tcg_gen_shli_tl(t0, t0, 16);
7404 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7405 #else
7406 gen_qemu_ld16u(ctx, t0, addr);
7407 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7408 gen_addr_add(ctx, addr, addr, 2);
7409 gen_qemu_ld16u(ctx, t0, addr);
7410 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7411 #endif
7412 tcg_temp_free(t0);
7413 }
7414
7415 static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7416 {
7417 #if defined(TARGET_PPC64)
7418 TCGv t0 = tcg_temp_new();
7419 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7420 gen_addr_add(ctx, addr, addr, 2);
7421 gen_qemu_ld16u(ctx, t0, addr);
7422 tcg_gen_shli_tl(t0, t0, 32);
7423 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7424 tcg_temp_free(t0);
7425 #else
7426 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7427 gen_addr_add(ctx, addr, addr, 2);
7428 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7429 #endif
7430 }
7431
7432 static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7433 {
7434 #if defined(TARGET_PPC64)
7435 TCGv t0 = tcg_temp_new();
7436 gen_qemu_ld16s(ctx, t0, addr);
7437 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7438 gen_addr_add(ctx, addr, addr, 2);
7439 gen_qemu_ld16s(ctx, t0, addr);
7440 tcg_gen_shli_tl(t0, t0, 32);
7441 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7442 tcg_temp_free(t0);
7443 #else
7444 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7445 gen_addr_add(ctx, addr, addr, 2);
7446 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7447 #endif
7448 }
7449
7450 static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7451 {
7452 TCGv t0 = tcg_temp_new();
7453 gen_qemu_ld32u(ctx, t0, addr);
7454 #if defined(TARGET_PPC64)
7455 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7456 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7457 #else
7458 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7459 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7460 #endif
7461 tcg_temp_free(t0);
7462 }
7463
7464 static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7465 {
7466 TCGv t0 = tcg_temp_new();
7467 #if defined(TARGET_PPC64)
7468 gen_qemu_ld16u(ctx, t0, addr);
7469 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7470 tcg_gen_shli_tl(t0, t0, 32);
7471 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7472 gen_addr_add(ctx, addr, addr, 2);
7473 gen_qemu_ld16u(ctx, t0, addr);
7474 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7475 tcg_gen_shli_tl(t0, t0, 16);
7476 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7477 #else
7478 gen_qemu_ld16u(ctx, t0, addr);
7479 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7480 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7481 gen_addr_add(ctx, addr, addr, 2);
7482 gen_qemu_ld16u(ctx, t0, addr);
7483 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7484 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7485 #endif
7486 tcg_temp_free(t0);
7487 }
7488
7489 static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7490 {
7491 #if defined(TARGET_PPC64)
7492 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7493 #else
7494 TCGv_i64 t0 = tcg_temp_new_i64();
7495 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7496 gen_qemu_st64(ctx, t0, addr);
7497 tcg_temp_free_i64(t0);
7498 #endif
7499 }
7500
7501 static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7502 {
7503 #if defined(TARGET_PPC64)
7504 TCGv t0 = tcg_temp_new();
7505 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7506 gen_qemu_st32(ctx, t0, addr);
7507 tcg_temp_free(t0);
7508 #else
7509 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7510 #endif
7511 gen_addr_add(ctx, addr, addr, 4);
7512 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7513 }
7514
7515 static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7516 {
7517 TCGv t0 = tcg_temp_new();
7518 #if defined(TARGET_PPC64)
7519 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7520 #else
7521 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7522 #endif
7523 gen_qemu_st16(ctx, t0, addr);
7524 gen_addr_add(ctx, addr, addr, 2);
7525 #if defined(TARGET_PPC64)
7526 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7527 gen_qemu_st16(ctx, t0, addr);
7528 #else
7529 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7530 #endif
7531 gen_addr_add(ctx, addr, addr, 2);
7532 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7533 gen_qemu_st16(ctx, t0, addr);
7534 tcg_temp_free(t0);
7535 gen_addr_add(ctx, addr, addr, 2);
7536 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7537 }
7538
7539 static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7540 {
7541 TCGv t0 = tcg_temp_new();
7542 #if defined(TARGET_PPC64)
7543 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7544 #else
7545 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7546 #endif
7547 gen_qemu_st16(ctx, t0, addr);
7548 gen_addr_add(ctx, addr, addr, 2);
7549 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7550 gen_qemu_st16(ctx, t0, addr);
7551 tcg_temp_free(t0);
7552 }
7553
7554 static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7555 {
7556 #if defined(TARGET_PPC64)
7557 TCGv t0 = tcg_temp_new();
7558 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7559 gen_qemu_st16(ctx, t0, addr);
7560 tcg_temp_free(t0);
7561 #else
7562 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7563 #endif
7564 gen_addr_add(ctx, addr, addr, 2);
7565 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7566 }
7567
7568 static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7569 {
7570 #if defined(TARGET_PPC64)
7571 TCGv t0 = tcg_temp_new();
7572 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7573 gen_qemu_st32(ctx, t0, addr);
7574 tcg_temp_free(t0);
7575 #else
7576 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7577 #endif
7578 }
7579
7580 static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7581 {
7582 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7583 }
7584
7585 #define GEN_SPEOP_LDST(name, opc2, sh) \
7586 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
7587 { \
7588 TCGv t0; \
7589 if (unlikely(!ctx->spe_enabled)) { \
7590 gen_exception(ctx, POWERPC_EXCP_APU); \
7591 return; \
7592 } \
7593 gen_set_access_type(ctx, ACCESS_INT); \
7594 t0 = tcg_temp_new(); \
7595 if (Rc(ctx->opcode)) { \
7596 gen_addr_spe_imm_index(ctx, t0, sh); \
7597 } else { \
7598 gen_addr_reg_index(ctx, t0); \
7599 } \
7600 gen_op_##name(ctx, t0); \
7601 tcg_temp_free(t0); \
7602 }
7603
7604 GEN_SPEOP_LDST(evldd, 0x00, 3);
7605 GEN_SPEOP_LDST(evldw, 0x01, 3);
7606 GEN_SPEOP_LDST(evldh, 0x02, 3);
7607 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7608 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7609 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7610 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7611 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7612 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7613 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7614 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7615
7616 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7617 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7618 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7619 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7620 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7621 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7622 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7623
7624 /* Multiply and add - TODO */
7625 #if 0
7626 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7627 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7628 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7629 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7630 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7631 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7632 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7633 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7634 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7635 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7636 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7637 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7638
7639 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7640 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7641 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7642 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7643 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7644 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7645 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7646 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7647 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7648 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7649 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7650 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7651 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7652 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7653
7654 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7655 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7656 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7657 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7658 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7659 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7660
7661 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7662 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7663 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7664 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7665 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7666 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7667 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7668 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7669 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7670 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7671 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7672 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7673
7674 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7675 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7676 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7677 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7678 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7679
7680 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7681 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7682 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7683 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7684 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7685 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7686 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7687 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7688 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7689 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7690 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7691 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7692
7693 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7694 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7695 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7696 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7697 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7698 #endif
7699
7700 /*** SPE floating-point extension ***/
7701 #if defined(TARGET_PPC64)
7702 #define GEN_SPEFPUOP_CONV_32_32(name) \
7703 static always_inline void gen_##name (DisasContext *ctx) \
7704 { \
7705 TCGv_i32 t0; \
7706 TCGv t1; \
7707 t0 = tcg_temp_new_i32(); \
7708 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7709 gen_helper_##name(t0, t0); \
7710 t1 = tcg_temp_new(); \
7711 tcg_gen_extu_i32_tl(t1, t0); \
7712 tcg_temp_free_i32(t0); \
7713 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7714 0xFFFFFFFF00000000ULL); \
7715 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7716 tcg_temp_free(t1); \
7717 }
7718 #define GEN_SPEFPUOP_CONV_32_64(name) \
7719 static always_inline void gen_##name (DisasContext *ctx) \
7720 { \
7721 TCGv_i32 t0; \
7722 TCGv t1; \
7723 t0 = tcg_temp_new_i32(); \
7724 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7725 t1 = tcg_temp_new(); \
7726 tcg_gen_extu_i32_tl(t1, t0); \
7727 tcg_temp_free_i32(t0); \
7728 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7729 0xFFFFFFFF00000000ULL); \
7730 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7731 tcg_temp_free(t1); \
7732 }
7733 #define GEN_SPEFPUOP_CONV_64_32(name) \
7734 static always_inline void gen_##name (DisasContext *ctx) \
7735 { \
7736 TCGv_i32 t0 = tcg_temp_new_i32(); \
7737 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7738 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7739 tcg_temp_free_i32(t0); \
7740 }
7741 #define GEN_SPEFPUOP_CONV_64_64(name) \
7742 static always_inline void gen_##name (DisasContext *ctx) \
7743 { \
7744 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7745 }
7746 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7747 static always_inline void gen_##name (DisasContext *ctx) \
7748 { \
7749 TCGv_i32 t0, t1; \
7750 TCGv_i64 t2; \
7751 if (unlikely(!ctx->spe_enabled)) { \
7752 gen_exception(ctx, POWERPC_EXCP_APU); \
7753 return; \
7754 } \
7755 t0 = tcg_temp_new_i32(); \
7756 t1 = tcg_temp_new_i32(); \
7757 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7758 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7759 gen_helper_##name(t0, t0, t1); \
7760 tcg_temp_free_i32(t1); \
7761 t2 = tcg_temp_new(); \
7762 tcg_gen_extu_i32_tl(t2, t0); \
7763 tcg_temp_free_i32(t0); \
7764 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7765 0xFFFFFFFF00000000ULL); \
7766 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7767 tcg_temp_free(t2); \
7768 }
7769 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7770 static always_inline void gen_##name (DisasContext *ctx) \
7771 { \
7772 if (unlikely(!ctx->spe_enabled)) { \
7773 gen_exception(ctx, POWERPC_EXCP_APU); \
7774 return; \
7775 } \
7776 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7777 cpu_gpr[rB(ctx->opcode)]); \
7778 }
7779 #define GEN_SPEFPUOP_COMP_32(name) \
7780 static always_inline void gen_##name (DisasContext *ctx) \
7781 { \
7782 TCGv_i32 t0, t1; \
7783 if (unlikely(!ctx->spe_enabled)) { \
7784 gen_exception(ctx, POWERPC_EXCP_APU); \
7785 return; \
7786 } \
7787 t0 = tcg_temp_new_i32(); \
7788 t1 = tcg_temp_new_i32(); \
7789 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7790 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7791 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7792 tcg_temp_free_i32(t0); \
7793 tcg_temp_free_i32(t1); \
7794 }
7795 #define GEN_SPEFPUOP_COMP_64(name) \
7796 static always_inline void gen_##name (DisasContext *ctx) \
7797 { \
7798 if (unlikely(!ctx->spe_enabled)) { \
7799 gen_exception(ctx, POWERPC_EXCP_APU); \
7800 return; \
7801 } \
7802 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7803 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7804 }
7805 #else
7806 #define GEN_SPEFPUOP_CONV_32_32(name) \
7807 static always_inline void gen_##name (DisasContext *ctx) \
7808 { \
7809 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7810 }
7811 #define GEN_SPEFPUOP_CONV_32_64(name) \
7812 static always_inline void gen_##name (DisasContext *ctx) \
7813 { \
7814 TCGv_i64 t0 = tcg_temp_new_i64(); \
7815 gen_load_gpr64(t0, rB(ctx->opcode)); \
7816 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7817 tcg_temp_free_i64(t0); \
7818 }
7819 #define GEN_SPEFPUOP_CONV_64_32(name) \
7820 static always_inline void gen_##name (DisasContext *ctx) \
7821 { \
7822 TCGv_i64 t0 = tcg_temp_new_i64(); \
7823 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7824 gen_store_gpr64(rD(ctx->opcode), t0); \
7825 tcg_temp_free_i64(t0); \
7826 }
7827 #define GEN_SPEFPUOP_CONV_64_64(name) \
7828 static always_inline void gen_##name (DisasContext *ctx) \
7829 { \
7830 TCGv_i64 t0 = tcg_temp_new_i64(); \
7831 gen_load_gpr64(t0, rB(ctx->opcode)); \
7832 gen_helper_##name(t0, t0); \
7833 gen_store_gpr64(rD(ctx->opcode), t0); \
7834 tcg_temp_free_i64(t0); \
7835 }
7836 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
7837 static always_inline void gen_##name (DisasContext *ctx) \
7838 { \
7839 if (unlikely(!ctx->spe_enabled)) { \
7840 gen_exception(ctx, POWERPC_EXCP_APU); \
7841 return; \
7842 } \
7843 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7844 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7845 }
7846 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
7847 static always_inline void gen_##name (DisasContext *ctx) \
7848 { \
7849 TCGv_i64 t0, t1; \
7850 if (unlikely(!ctx->spe_enabled)) { \
7851 gen_exception(ctx, POWERPC_EXCP_APU); \
7852 return; \
7853 } \
7854 t0 = tcg_temp_new_i64(); \
7855 t1 = tcg_temp_new_i64(); \
7856 gen_load_gpr64(t0, rA(ctx->opcode)); \
7857 gen_load_gpr64(t1, rB(ctx->opcode)); \
7858 gen_helper_##name(t0, t0, t1); \
7859 gen_store_gpr64(rD(ctx->opcode), t0); \
7860 tcg_temp_free_i64(t0); \
7861 tcg_temp_free_i64(t1); \
7862 }
7863 #define GEN_SPEFPUOP_COMP_32(name) \
7864 static always_inline void gen_##name (DisasContext *ctx) \
7865 { \
7866 if (unlikely(!ctx->spe_enabled)) { \
7867 gen_exception(ctx, POWERPC_EXCP_APU); \
7868 return; \
7869 } \
7870 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7871 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7872 }
7873 #define GEN_SPEFPUOP_COMP_64(name) \
7874 static always_inline void gen_##name (DisasContext *ctx) \
7875 { \
7876 TCGv_i64 t0, t1; \
7877 if (unlikely(!ctx->spe_enabled)) { \
7878 gen_exception(ctx, POWERPC_EXCP_APU); \
7879 return; \
7880 } \
7881 t0 = tcg_temp_new_i64(); \
7882 t1 = tcg_temp_new_i64(); \
7883 gen_load_gpr64(t0, rA(ctx->opcode)); \
7884 gen_load_gpr64(t1, rB(ctx->opcode)); \
7885 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7886 tcg_temp_free_i64(t0); \
7887 tcg_temp_free_i64(t1); \
7888 }
7889 #endif
7890
7891 /* Single precision floating-point vectors operations */
7892 /* Arithmetic */
7893 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7894 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7895 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7896 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7897 static always_inline void gen_evfsabs (DisasContext *ctx)
7898 {
7899 if (unlikely(!ctx->spe_enabled)) {
7900 gen_exception(ctx, POWERPC_EXCP_APU);
7901 return;
7902 }
7903 #if defined(TARGET_PPC64)
7904 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7905 #else
7906 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7907 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7908 #endif
7909 }
7910 static always_inline void gen_evfsnabs (DisasContext *ctx)
7911 {
7912 if (unlikely(!ctx->spe_enabled)) {
7913 gen_exception(ctx, POWERPC_EXCP_APU);
7914 return;
7915 }
7916 #if defined(TARGET_PPC64)
7917 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7918 #else
7919 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7920 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7921 #endif
7922 }
7923 static always_inline void gen_evfsneg (DisasContext *ctx)
7924 {
7925 if (unlikely(!ctx->spe_enabled)) {
7926 gen_exception(ctx, POWERPC_EXCP_APU);
7927 return;
7928 }
7929 #if defined(TARGET_PPC64)
7930 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7931 #else
7932 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7933 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7934 #endif
7935 }
7936
7937 /* Conversion */
7938 GEN_SPEFPUOP_CONV_64_64(evfscfui);
7939 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7940 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7941 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7942 GEN_SPEFPUOP_CONV_64_64(evfsctui);
7943 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7944 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7945 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7946 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7947 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7948
7949 /* Comparison */
7950 GEN_SPEFPUOP_COMP_64(evfscmpgt);
7951 GEN_SPEFPUOP_COMP_64(evfscmplt);
7952 GEN_SPEFPUOP_COMP_64(evfscmpeq);
7953 GEN_SPEFPUOP_COMP_64(evfststgt);
7954 GEN_SPEFPUOP_COMP_64(evfststlt);
7955 GEN_SPEFPUOP_COMP_64(evfststeq);
7956
7957 /* Opcodes definitions */
7958 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7959 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7960 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7961 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7962 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7963 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7964 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7965 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7966 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7967 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7968 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7969 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7970 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7971 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7972
7973 /* Single precision floating-point operations */
7974 /* Arithmetic */
7975 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7976 GEN_SPEFPUOP_ARITH2_32_32(efssub);
7977 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7978 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7979 static always_inline void gen_efsabs (DisasContext *ctx)
7980 {
7981 if (unlikely(!ctx->spe_enabled)) {
7982 gen_exception(ctx, POWERPC_EXCP_APU);
7983 return;
7984 }
7985 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7986 }
7987 static always_inline void gen_efsnabs (DisasContext *ctx)
7988 {
7989 if (unlikely(!ctx->spe_enabled)) {
7990 gen_exception(ctx, POWERPC_EXCP_APU);
7991 return;
7992 }
7993 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7994 }
7995 static always_inline void gen_efsneg (DisasContext *ctx)
7996 {
7997 if (unlikely(!ctx->spe_enabled)) {
7998 gen_exception(ctx, POWERPC_EXCP_APU);
7999 return;
8000 }
8001 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8002 }
8003
8004 /* Conversion */
8005 GEN_SPEFPUOP_CONV_32_32(efscfui);
8006 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8007 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8008 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8009 GEN_SPEFPUOP_CONV_32_32(efsctui);
8010 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8011 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8012 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8013 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8014 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8015 GEN_SPEFPUOP_CONV_32_64(efscfd);
8016
8017 /* Comparison */
8018 GEN_SPEFPUOP_COMP_32(efscmpgt);
8019 GEN_SPEFPUOP_COMP_32(efscmplt);
8020 GEN_SPEFPUOP_COMP_32(efscmpeq);
8021 GEN_SPEFPUOP_COMP_32(efststgt);
8022 GEN_SPEFPUOP_COMP_32(efststlt);
8023 GEN_SPEFPUOP_COMP_32(efststeq);
8024
8025 /* Opcodes definitions */
8026 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8027 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8028 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8029 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8030 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8031 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8032 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8033 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8034 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8035 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8036 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8037 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8038 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8039 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8040
8041 /* Double precision floating-point operations */
8042 /* Arithmetic */
8043 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8044 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8045 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8046 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8047 static always_inline void gen_efdabs (DisasContext *ctx)
8048 {
8049 if (unlikely(!ctx->spe_enabled)) {
8050 gen_exception(ctx, POWERPC_EXCP_APU);
8051 return;
8052 }
8053 #if defined(TARGET_PPC64)
8054 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8055 #else
8056 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8057 #endif
8058 }
8059 static always_inline void gen_efdnabs (DisasContext *ctx)
8060 {
8061 if (unlikely(!ctx->spe_enabled)) {
8062 gen_exception(ctx, POWERPC_EXCP_APU);
8063 return;
8064 }
8065 #if defined(TARGET_PPC64)
8066 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8067 #else
8068 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8069 #endif
8070 }
8071 static always_inline void gen_efdneg (DisasContext *ctx)
8072 {
8073 if (unlikely(!ctx->spe_enabled)) {
8074 gen_exception(ctx, POWERPC_EXCP_APU);
8075 return;
8076 }
8077 #if defined(TARGET_PPC64)
8078 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8079 #else
8080 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8081 #endif
8082 }
8083
8084 /* Conversion */
8085 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8086 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8087 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8088 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8089 GEN_SPEFPUOP_CONV_32_64(efdctui);
8090 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8091 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8092 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8093 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8094 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8095 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8096 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8097 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8098 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8099 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8100
8101 /* Comparison */
8102 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8103 GEN_SPEFPUOP_COMP_64(efdcmplt);
8104 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8105 GEN_SPEFPUOP_COMP_64(efdtstgt);
8106 GEN_SPEFPUOP_COMP_64(efdtstlt);
8107 GEN_SPEFPUOP_COMP_64(efdtsteq);
8108
8109 /* Opcodes definitions */
8110 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8111 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8112 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8113 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8114 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8115 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8116 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8117 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8118 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8119 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8120 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8121 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8122 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8123 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8124 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8125 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8126
8127 /* End opcode list */
8128 GEN_OPCODE_MARK(end);
8129
8130 #include "translate_init.c"
8131 #include "helper_regs.h"
8132
8133 /*****************************************************************************/
8134 /* Misc PowerPC helpers */
8135 void cpu_dump_state (CPUState *env, FILE *f,
8136 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8137 int flags)
8138 {
8139 #define RGPL 4
8140 #define RFPL 4
8141
8142 int i;
8143
8144 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
8145 env->nip, env->lr, env->ctr, env->xer);
8146 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8147 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
8148 #if !defined(NO_TIMER_DUMP)
8149 cpu_fprintf(f, "TB %08x %08x "
8150 #if !defined(CONFIG_USER_ONLY)
8151 "DECR %08x"
8152 #endif
8153 "\n",
8154 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8155 #if !defined(CONFIG_USER_ONLY)
8156 , cpu_ppc_load_decr(env)
8157 #endif
8158 );
8159 #endif
8160 for (i = 0; i < 32; i++) {
8161 if ((i & (RGPL - 1)) == 0)
8162 cpu_fprintf(f, "GPR%02d", i);
8163 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
8164 if ((i & (RGPL - 1)) == (RGPL - 1))
8165 cpu_fprintf(f, "\n");
8166 }
8167 cpu_fprintf(f, "CR ");
8168 for (i = 0; i < 8; i++)
8169 cpu_fprintf(f, "%01x", env->crf[i]);
8170 cpu_fprintf(f, " [");
8171 for (i = 0; i < 8; i++) {
8172 char a = '-';
8173 if (env->crf[i] & 0x08)
8174 a = 'L';
8175 else if (env->crf[i] & 0x04)
8176 a = 'G';
8177 else if (env->crf[i] & 0x02)
8178 a = 'E';
8179 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8180 }
8181 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
8182 for (i = 0; i < 32; i++) {
8183 if ((i & (RFPL - 1)) == 0)
8184 cpu_fprintf(f, "FPR%02d", i);
8185 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
8186 if ((i & (RFPL - 1)) == (RFPL - 1))
8187 cpu_fprintf(f, "\n");
8188 }
8189 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
8190 #if !defined(CONFIG_USER_ONLY)
8191 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
8192 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
8193 #endif
8194
8195 #undef RGPL
8196 #undef RFPL
8197 }
8198
8199 void cpu_dump_statistics (CPUState *env, FILE*f,
8200 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8201 int flags)
8202 {
8203 #if defined(DO_PPC_STATISTICS)
8204 opc_handler_t **t1, **t2, **t3, *handler;
8205 int op1, op2, op3;
8206
8207 t1 = env->opcodes;
8208 for (op1 = 0; op1 < 64; op1++) {
8209 handler = t1[op1];
8210 if (is_indirect_opcode(handler)) {
8211 t2 = ind_table(handler);
8212 for (op2 = 0; op2 < 32; op2++) {
8213 handler = t2[op2];
8214 if (is_indirect_opcode(handler)) {
8215 t3 = ind_table(handler);
8216 for (op3 = 0; op3 < 32; op3++) {
8217 handler = t3[op3];
8218 if (handler->count == 0)
8219 continue;
8220 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8221 "%016llx %lld\n",
8222 op1, op2, op3, op1, (op3 << 5) | op2,
8223 handler->oname,
8224 handler->count, handler->count);
8225 }
8226 } else {
8227 if (handler->count == 0)
8228 continue;
8229 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8230 "%016llx %lld\n",
8231 op1, op2, op1, op2, handler->oname,
8232 handler->count, handler->count);
8233 }
8234 }
8235 } else {
8236 if (handler->count == 0)
8237 continue;
8238 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8239 op1, op1, handler->oname,
8240 handler->count, handler->count);
8241 }
8242 }
8243 #endif
8244 }
8245
8246 /*****************************************************************************/
8247 static always_inline void gen_intermediate_code_internal (CPUState *env,
8248 TranslationBlock *tb,
8249 int search_pc)
8250 {
8251 DisasContext ctx, *ctxp = &ctx;
8252 opc_handler_t **table, *handler;
8253 target_ulong pc_start;
8254 uint16_t *gen_opc_end;
8255 CPUBreakpoint *bp;
8256 int j, lj = -1;
8257 int num_insns;
8258 int max_insns;
8259
8260 pc_start = tb->pc;
8261 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8262 ctx.nip = pc_start;
8263 ctx.tb = tb;
8264 ctx.exception = POWERPC_EXCP_NONE;
8265 ctx.spr_cb = env->spr_cb;
8266 ctx.mem_idx = env->mmu_idx;
8267 ctx.access_type = -1;
8268 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
8269 #if defined(TARGET_PPC64)
8270 ctx.sf_mode = msr_sf;
8271 #endif
8272 ctx.fpu_enabled = msr_fp;
8273 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
8274 ctx.spe_enabled = msr_spe;
8275 else
8276 ctx.spe_enabled = 0;
8277 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8278 ctx.altivec_enabled = msr_vr;
8279 else
8280 ctx.altivec_enabled = 0;
8281 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8282 ctx.singlestep_enabled = CPU_SINGLE_STEP;
8283 else
8284 ctx.singlestep_enabled = 0;
8285 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8286 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8287 if (unlikely(env->singlestep_enabled))
8288 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
8289 #if defined (DO_SINGLE_STEP) && 0
8290 /* Single step trace mode */
8291 msr_se = 1;
8292 #endif
8293 num_insns = 0;
8294 max_insns = tb->cflags & CF_COUNT_MASK;
8295 if (max_insns == 0)
8296 max_insns = CF_COUNT_MASK;
8297
8298 gen_icount_start();
8299 /* Set env in case of segfault during code fetch */
8300 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
8301 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8302 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8303 if (bp->pc == ctx.nip) {
8304 gen_debug_exception(ctxp);
8305 break;
8306 }
8307 }
8308 }
8309 if (unlikely(search_pc)) {
8310 j = gen_opc_ptr - gen_opc_buf;
8311 if (lj < j) {
8312 lj++;
8313 while (lj < j)
8314 gen_opc_instr_start[lj++] = 0;
8315 gen_opc_pc[lj] = ctx.nip;
8316 gen_opc_instr_start[lj] = 1;
8317 gen_opc_icount[lj] = num_insns;
8318 }
8319 }
8320 LOG_DISAS("----------------\n");
8321 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8322 ctx.nip, ctx.mem_idx, (int)msr_ir);
8323 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8324 gen_io_start();
8325 if (unlikely(ctx.le_mode)) {
8326 ctx.opcode = bswap32(ldl_code(ctx.nip));
8327 } else {
8328 ctx.opcode = ldl_code(ctx.nip);
8329 }
8330 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
8331 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
8332 opc3(ctx.opcode), little_endian ? "little" : "big");
8333 ctx.nip += 4;
8334 table = env->opcodes;
8335 num_insns++;
8336 handler = table[opc1(ctx.opcode)];
8337 if (is_indirect_opcode(handler)) {
8338 table = ind_table(handler);
8339 handler = table[opc2(ctx.opcode)];
8340 if (is_indirect_opcode(handler)) {
8341 table = ind_table(handler);
8342 handler = table[opc3(ctx.opcode)];
8343 }
8344 }
8345 /* Is opcode *REALLY* valid ? */
8346 if (unlikely(handler->handler == &gen_invalid)) {
8347 if (qemu_log_enabled()) {
8348 qemu_log("invalid/unsupported opcode: "
8349 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8350 opc1(ctx.opcode), opc2(ctx.opcode),
8351 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8352 } else {
8353 printf("invalid/unsupported opcode: "
8354 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8355 opc1(ctx.opcode), opc2(ctx.opcode),
8356 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
8357 }
8358 } else {
8359 if (unlikely((ctx.opcode & handler->inval) != 0)) {
8360 if (qemu_log_enabled()) {
8361 qemu_log("invalid bits: %08x for opcode: "
8362 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8363 ctx.opcode & handler->inval, opc1(ctx.opcode),
8364 opc2(ctx.opcode), opc3(ctx.opcode),
8365 ctx.opcode, ctx.nip - 4);
8366 } else {
8367 printf("invalid bits: %08x for opcode: "
8368 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8369 ctx.opcode & handler->inval, opc1(ctx.opcode),
8370 opc2(ctx.opcode), opc3(ctx.opcode),
8371 ctx.opcode, ctx.nip - 4);
8372 }
8373 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
8374 break;
8375 }
8376 }
8377 (*(handler->handler))(&ctx);
8378 #if defined(DO_PPC_STATISTICS)
8379 handler->count++;
8380 #endif
8381 /* Check trace mode exceptions */
8382 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8383 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8384 ctx.exception != POWERPC_SYSCALL &&
8385 ctx.exception != POWERPC_EXCP_TRAP &&
8386 ctx.exception != POWERPC_EXCP_BRANCH)) {
8387 gen_exception(ctxp, POWERPC_EXCP_TRACE);
8388 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
8389 (env->singlestep_enabled) ||
8390 num_insns >= max_insns)) {
8391 /* if we reach a page boundary or are single stepping, stop
8392 * generation
8393 */
8394 break;
8395 }
8396 #if defined (DO_SINGLE_STEP)
8397 break;
8398 #endif
8399 }
8400 if (tb->cflags & CF_LAST_IO)
8401 gen_io_end();
8402 if (ctx.exception == POWERPC_EXCP_NONE) {
8403 gen_goto_tb(&ctx, 0, ctx.nip);
8404 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8405 if (unlikely(env->singlestep_enabled)) {
8406 gen_debug_exception(ctxp);
8407 }
8408 /* Generate the return instruction */
8409 tcg_gen_exit_tb(0);
8410 }
8411 gen_icount_end(tb, num_insns);
8412 *gen_opc_ptr = INDEX_op_end;
8413 if (unlikely(search_pc)) {
8414 j = gen_opc_ptr - gen_opc_buf;
8415 lj++;
8416 while (lj <= j)
8417 gen_opc_instr_start[lj++] = 0;
8418 } else {
8419 tb->size = ctx.nip - pc_start;
8420 tb->icount = num_insns;
8421 }
8422 #if defined(DEBUG_DISAS)
8423 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8424 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8425 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8426 int flags;
8427 flags = env->bfd_mach;
8428 flags |= ctx.le_mode << 16;
8429 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8430 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8431 qemu_log("\n");
8432 }
8433 #endif
8434 }
8435
8436 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8437 {
8438 gen_intermediate_code_internal(env, tb, 0);
8439 }
8440
8441 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8442 {
8443 gen_intermediate_code_internal(env, tb, 1);
8444 }
8445
8446 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8447 unsigned long searched_pc, int pc_pos, void *puc)
8448 {
8449 env->nip = gen_opc_pc[pc_pos];
8450 }