hw/mac_dbdma.c

   1 /*
   2  * PowerMac descriptor-based DMA emulation
   3  *
   4  * Copyright (c) 2005-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  * Copyright (c) 2009 Laurent Vivier
   7  *
   8  * some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h
   9  *
  10  *   Definitions for using the Apple Descriptor-Based DMA controller
  11  *   in Power Macintosh computers.
  12  *
  13  *   Copyright (C) 1996 Paul Mackerras.
  14  *
  15  * some parts from mol 0.9.71
  16  *
  17  *   Descriptor based DMA emulation
  18  *
  19  *   Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se)
  20  *
  21  * Permission is hereby granted, free of charge, to any person obtaining a copy
  22  * of this software and associated documentation files (the "Software"), to deal
  23  * in the Software without restriction, including without limitation the rights
  24  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  25  * copies of the Software, and to permit persons to whom the Software is
  26  * furnished to do so, subject to the following conditions:
  27  *
  28  * The above copyright notice and this permission notice shall be included in
  29  * all copies or substantial portions of the Software.
  30  *
  31  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  32  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  33  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  34  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  35  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  36  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  37  * THE SOFTWARE.
  38  */
  39 #include "hw.h"
  40 #include "isa.h"
  41 #include "mac_dbdma.h"
  42
  43 /* debug DBDMA */
  44 //#define DEBUG_DBDMA
  45
  46 #ifdef DEBUG_DBDMA
  47 #define DBDMA_DPRINTF(fmt, args...) \
  48 do { printf("DBDMA: " fmt , ##args); } while (0)
  49 #else
  50 #define DBDMA_DPRINTF(fmt, args...)
  51 #endif
  52
  53 /*
  54  */
  55
  56 /*
  57  * DBDMA control/status registers.  All little-endian.
  58  */
  59
  60 #define DBDMA_CONTROL         0x00
  61 #define DBDMA_STATUS          0x01
  62 #define DBDMA_CMDPTR_HI       0x02
  63 #define DBDMA_CMDPTR_LO       0x03
  64 #define DBDMA_INTR_SEL        0x04
  65 #define DBDMA_BRANCH_SEL      0x05
  66 #define DBDMA_WAIT_SEL        0x06
  67 #define DBDMA_XFER_MODE       0x07
  68 #define DBDMA_DATA2PTR_HI     0x08
  69 #define DBDMA_DATA2PTR_LO     0x09
  70 #define DBDMA_RES1            0x0A
  71 #define DBDMA_ADDRESS_HI      0x0B
  72 #define DBDMA_BRANCH_ADDR_HI  0x0C
  73 #define DBDMA_RES2            0x0D
  74 #define DBDMA_RES3            0x0E
  75 #define DBDMA_RES4            0x0F
  76
  77 #define DBDMA_REGS            16
  78 #define DBDMA_SIZE            (DBDMA_REGS * sizeof(uint32_t))
  79
  80 #define DBDMA_CHANNEL_SHIFT   7
  81 #define DBDMA_CHANNEL_SIZE    (1 << DBDMA_CHANNEL_SHIFT)
  82
  83 #define DBDMA_CHANNELS        (0x1000 >> DBDMA_CHANNEL_SHIFT)
  84
  85 /* Bits in control and status registers */
  86
  87 #define RUN     0x8000
  88 #define PAUSE   0x4000
  89 #define FLUSH   0x2000
  90 #define WAKE    0x1000
  91 #define DEAD    0x0800
  92 #define ACTIVE  0x0400
  93 #define BT      0x0100
  94 #define DEVSTAT 0x00ff
  95
  96 /*
  97  * DBDMA command structure.  These fields are all little-endian!
  98  */
  99
 100 typedef struct dbdma_cmd {
 101     uint16_t req_count;   /* requested byte transfer count */
 102     uint16_t command;     /* command word (has bit-fields) */
 103     uint32_t phy_addr;    /* physical data address */
 104     uint32_t cmd_dep;     /* command-dependent field */
 105     uint16_t res_count;   /* residual count after completion */
 106     uint16_t xfer_status; /* transfer status */
 107 } dbdma_cmd;
 108
 109 /* DBDMA command values in command field */
 110
 111 #define COMMAND_MASK    0xf000
 112 #define OUTPUT_MORE     0x0000  /* transfer memory data to stream */
 113 #define OUTPUT_LAST     0x1000  /* ditto followed by end marker */
 114 #define INPUT_MORE      0x2000  /* transfer stream data to memory */
 115 #define INPUT_LAST      0x3000  /* ditto, expect end marker */
 116 #define STORE_WORD      0x4000  /* write word (4 bytes) to device reg */
 117 #define LOAD_WORD       0x5000  /* read word (4 bytes) from device reg */
 118 #define DBDMA_NOP       0x6000  /* do nothing */
 119 #define DBDMA_STOP      0x7000  /* suspend processing */
 120
 121 /* Key values in command field */
 122
 123 #define KEY_MASK        0x0700
 124 #define KEY_STREAM0     0x0000  /* usual data stream */
 125 #define KEY_STREAM1     0x0100  /* control/status stream */
 126 #define KEY_STREAM2     0x0200  /* device-dependent stream */
 127 #define KEY_STREAM3     0x0300  /* device-dependent stream */
 128 #define KEY_STREAM4     0x0400  /* reserved */
 129 #define KEY_REGS        0x0500  /* device register space */
 130 #define KEY_SYSTEM      0x0600  /* system memory-mapped space */
 131 #define KEY_DEVICE      0x0700  /* device memory-mapped space */
 132
 133 /* Interrupt control values in command field */
 134
 135 #define INTR_MASK       0x0030
 136 #define INTR_NEVER      0x0000  /* don't interrupt */
 137 #define INTR_IFSET      0x0010  /* intr if condition bit is 1 */
 138 #define INTR_IFCLR      0x0020  /* intr if condition bit is 0 */
 139 #define INTR_ALWAYS     0x0030  /* always interrupt */
 140
 141 /* Branch control values in command field */
 142
 143 #define BR_MASK         0x000c
 144 #define BR_NEVER        0x0000  /* don't branch */
 145 #define BR_IFSET        0x0004  /* branch if condition bit is 1 */
 146 #define BR_IFCLR        0x0008  /* branch if condition bit is 0 */
 147 #define BR_ALWAYS       0x000c  /* always branch */
 148
 149 /* Wait control values in command field */
 150
 151 #define WAIT_MASK       0x0003
 152 #define WAIT_NEVER      0x0000  /* don't wait */
 153 #define WAIT_IFSET      0x0001  /* wait if condition bit is 1 */
 154 #define WAIT_IFCLR      0x0002  /* wait if condition bit is 0 */
 155 #define WAIT_ALWAYS     0x0003  /* always wait */
 156
 157 typedef struct DBDMA_channel {
 158     int channel;
 159     uint32_t regs[DBDMA_REGS];
 160     qemu_irq irq;
 161     DBDMA_io io;
 162     DBDMA_rw rw;
 163     dbdma_cmd current;
 164     int processing;
 165 } DBDMA_channel;
 166
 167 #ifdef DEBUG_DBDMA
 168 static void dump_dbdma_cmd(dbdma_cmd *cmd)
 169 {
 170     printf("dbdma_cmd %p\n", cmd);
 171     printf("    req_count 0x%04x\n", le16_to_cpu(cmd->req_count));
 172     printf("    command 0x%04x\n", le16_to_cpu(cmd->command));
 173     printf("    phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr));
 174     printf("    cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep));
 175     printf("    res_count 0x%04x\n", le16_to_cpu(cmd->res_count));
 176     printf("    xfer_status 0x%04x\n", le16_to_cpu(cmd->xfer_status));
 177 }
 178 #else
 179 static void dump_dbdma_cmd(dbdma_cmd *cmd)
 180 {
 181 }
 182 #endif
 183 static void dbdma_cmdptr_load(DBDMA_channel *ch)
 184 {
 185     DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
 186                   be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
 187     cpu_physical_memory_read(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
 188                              (uint8_t*)&ch->current, sizeof(dbdma_cmd));
 189 }
 190
 191 static void dbdma_cmdptr_save(DBDMA_channel *ch)
 192 {
 193     DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
 194                   be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
 195     DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
 196                   le16_to_cpu(ch->current.xfer_status),
 197                   le16_to_cpu(ch->current.res_count));
 198     cpu_physical_memory_write(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
 199                               (uint8_t*)&ch->current, sizeof(dbdma_cmd));
 200 }
 201
 202 static void kill_channel(DBDMA_channel *ch)
 203 {
 204     DBDMA_DPRINTF("kill_channel\n");
 205
 206     ch->regs[DBDMA_STATUS] |= cpu_to_be32(DEAD);
 207     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~ACTIVE);
 208
 209     qemu_irq_raise(ch->irq);
 210 }
 211
 212 static void conditional_interrupt(DBDMA_channel *ch)
 213 {
 214     dbdma_cmd *current = &ch->current;
 215     uint16_t intr;
 216     uint16_t sel_mask, sel_value;
 217     uint32_t status;
 218     int cond;
 219
 220     DBDMA_DPRINTF("conditional_interrupt\n");
 221
 222     intr = le16_to_cpu(current->command) & INTR_MASK;
 223
 224     switch(intr) {
 225     case INTR_NEVER:  /* don't interrupt */
 226         return;
 227     case INTR_ALWAYS: /* always interrupt */
 228         qemu_irq_raise(ch->irq);
 229         return;
 230     }
 231
 232     status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
 233
 234     sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;
 235     sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;
 236
 237     cond = (status & sel_mask) == (sel_value & sel_mask);
 238
 239     switch(intr) {
 240     case INTR_IFSET:  /* intr if condition bit is 1 */
 241         if (cond)
 242             qemu_irq_raise(ch->irq);
 243         return;
 244     case INTR_IFCLR:  /* intr if condition bit is 0 */
 245         if (!cond)
 246             qemu_irq_raise(ch->irq);
 247         return;
 248     }
 249 }
 250
 251 static int conditional_wait(DBDMA_channel *ch)
 252 {
 253     dbdma_cmd *current = &ch->current;
 254     uint16_t wait;
 255     uint16_t sel_mask, sel_value;
 256     uint32_t status;
 257     int cond;
 258
 259     DBDMA_DPRINTF("conditional_wait\n");
 260
 261     wait = le16_to_cpu(current->command) & WAIT_MASK;
 262
 263     switch(wait) {
 264     case WAIT_NEVER:  /* don't wait */
 265         return 0;
 266     case WAIT_ALWAYS: /* always wait */
 267         return 1;
 268     }
 269
 270     status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
 271
 272     sel_mask = (be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) >> 16) & 0x0f;
 273     sel_value = be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) & 0x0f;
 274
 275     cond = (status & sel_mask) == (sel_value & sel_mask);
 276
 277     switch(wait) {
 278     case WAIT_IFSET:  /* wait if condition bit is 1 */
 279         if (cond)
 280             return 1;
 281         return 0;
 282     case WAIT_IFCLR:  /* wait if condition bit is 0 */
 283         if (!cond)
 284             return 1;
 285         return 0;
 286     }
 287     return 0;
 288 }
 289
 290 static void next(DBDMA_channel *ch)
 291 {
 292     uint32_t cp;
 293
 294     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~BT);
 295
 296     cp = be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]);
 297     ch->regs[DBDMA_CMDPTR_LO] = cpu_to_be32(cp + sizeof(dbdma_cmd));
 298     dbdma_cmdptr_load(ch);
 299 }
 300
 301 static void branch(DBDMA_channel *ch)
 302 {
 303     dbdma_cmd *current = &ch->current;
 304
 305     ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep;
 306     ch->regs[DBDMA_STATUS] |= cpu_to_be32(BT);
 307     dbdma_cmdptr_load(ch);
 308 }
 309
 310 static void conditional_branch(DBDMA_channel *ch)
 311 {
 312     dbdma_cmd *current = &ch->current;
 313     uint16_t br;
 314     uint16_t sel_mask, sel_value;
 315     uint32_t status;
 316     int cond;
 317
 318     DBDMA_DPRINTF("conditional_branch\n");
 319
 320     /* check if we must branch */
 321
 322     br = le16_to_cpu(current->command) & BR_MASK;
 323
 324     switch(br) {
 325     case BR_NEVER:  /* don't branch */
 326         next(ch);
 327         return;
 328     case BR_ALWAYS: /* always branch */
 329         branch(ch);
 330         return;
 331     }
 332
 333     status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
 334
 335     sel_mask = (be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) >> 16) & 0x0f;
 336     sel_value = be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) & 0x0f;
 337
 338     cond = (status & sel_mask) == (sel_value & sel_mask);
 339
 340     switch(br) {
 341     case BR_IFSET:  /* branch if condition bit is 1 */
 342         if (cond)
 343             branch(ch);
 344         else
 345             next(ch);
 346         return;
 347     case BR_IFCLR:  /* branch if condition bit is 0 */
 348         if (!cond)
 349             branch(ch);
 350         else
 351             next(ch);
 352         return;
 353     }
 354 }
 355
 356 static QEMUBH *dbdma_bh;
 357 static void channel_run(DBDMA_channel *ch);
 358
 359 static void dbdma_end(DBDMA_io *io)
 360 {
 361     DBDMA_channel *ch = io->channel;
 362     dbdma_cmd *current = &ch->current;
 363
 364     if (conditional_wait(ch))
 365         goto wait;
 366
 367     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 368     current->res_count = cpu_to_le16(be32_to_cpu(io->len));
 369     dbdma_cmdptr_save(ch);
 370     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
 371
 372     conditional_interrupt(ch);
 373     conditional_branch(ch);
 374
 375 wait:
 376     ch->processing = 0;
 377     if ((ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN)) &&
 378         (ch->regs[DBDMA_STATUS] & cpu_to_be32(ACTIVE)))
 379         channel_run(ch);
 380 }
 381
 382 static void start_output(DBDMA_channel *ch, int key, uint32_t addr,
 383                         uint16_t req_count, int is_last)
 384 {
 385     DBDMA_DPRINTF("start_output\n");
 386
 387     /* KEY_REGS, KEY_DEVICE and KEY_STREAM
 388      * are not implemented in the mac-io chip
 389      */
 390
 391     DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key);
 392     if (!addr || key > KEY_STREAM3) {
 393         kill_channel(ch);
 394         return;
 395     }
 396
 397     ch->io.addr = addr;
 398     ch->io.len = req_count;
 399     ch->io.is_last = is_last;
 400     ch->io.dma_end = dbdma_end;
 401     ch->io.is_dma_out = 1;
 402     ch->processing = 1;
 403     ch->rw(&ch->io);
 404 }
 405
 406 static void start_input(DBDMA_channel *ch, int key, uint32_t addr,
 407                        uint16_t req_count, int is_last)
 408 {
 409     DBDMA_DPRINTF("start_input\n");
 410
 411     /* KEY_REGS, KEY_DEVICE and KEY_STREAM
 412      * are not implemented in the mac-io chip
 413      */
 414
 415     if (!addr || key > KEY_STREAM3) {
 416         kill_channel(ch);
 417         return;
 418     }
 419
 420     ch->io.addr = addr;
 421     ch->io.len = req_count;
 422     ch->io.is_last = is_last;
 423     ch->io.dma_end = dbdma_end;
 424     ch->io.is_dma_out = 0;
 425     ch->processing = 1;
 426     ch->rw(&ch->io);
 427 }
 428
 429 static void load_word(DBDMA_channel *ch, int key, uint32_t addr,
 430                      uint16_t len)
 431 {
 432     dbdma_cmd *current = &ch->current;
 433     uint32_t val;
 434
 435     DBDMA_DPRINTF("load_word\n");
 436
 437     /* only implements KEY_SYSTEM */
 438
 439     if (key != KEY_SYSTEM) {
 440         printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
 441         kill_channel(ch);
 442         return;
 443     }
 444
 445     cpu_physical_memory_read(addr, (uint8_t*)&val, len);
 446
 447     if (len == 2)
 448         val = (val << 16) | (current->cmd_dep & 0x0000ffff);
 449     else if (len == 1)
 450         val = (val << 24) | (current->cmd_dep & 0x00ffffff);
 451
 452     current->cmd_dep = val;
 453
 454     if (conditional_wait(ch))
 455         goto wait;
 456
 457     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 458     dbdma_cmdptr_save(ch);
 459     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
 460
 461     conditional_interrupt(ch);
 462     next(ch);
 463
 464 wait:
 465     qemu_bh_schedule(dbdma_bh);
 466 }
 467
 468 static void store_word(DBDMA_channel *ch, int key, uint32_t addr,
 469                       uint16_t len)
 470 {
 471     dbdma_cmd *current = &ch->current;
 472     uint32_t val;
 473
 474     DBDMA_DPRINTF("store_word\n");
 475
 476     /* only implements KEY_SYSTEM */
 477
 478     if (key != KEY_SYSTEM) {
 479         printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
 480         kill_channel(ch);
 481         return;
 482     }
 483
 484     val = current->cmd_dep;
 485     if (len == 2)
 486         val >>= 16;
 487     else if (len == 1)
 488         val >>= 24;
 489
 490     cpu_physical_memory_write(addr, (uint8_t*)&val, len);
 491
 492     if (conditional_wait(ch))
 493         goto wait;
 494
 495     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 496     dbdma_cmdptr_save(ch);
 497     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
 498
 499     conditional_interrupt(ch);
 500     next(ch);
 501
 502 wait:
 503     qemu_bh_schedule(dbdma_bh);
 504 }
 505
 506 static void nop(DBDMA_channel *ch)
 507 {
 508     dbdma_cmd *current = &ch->current;
 509
 510     if (conditional_wait(ch))
 511         goto wait;
 512
 513     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 514     dbdma_cmdptr_save(ch);
 515
 516     conditional_interrupt(ch);
 517     conditional_branch(ch);
 518
 519 wait:
 520     qemu_bh_schedule(dbdma_bh);
 521 }
 522
 523 static void stop(DBDMA_channel *ch)
 524 {
 525     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD|FLUSH));
 526
 527     /* the stop command does not increment command pointer */
 528 }
 529
 530 static void channel_run(DBDMA_channel *ch)
 531 {
 532     dbdma_cmd *current = &ch->current;
 533     uint16_t cmd, key;
 534     uint16_t req_count;
 535     uint32_t phy_addr;
 536
 537     DBDMA_DPRINTF("channel_run\n");
 538     dump_dbdma_cmd(current);
 539
 540     /* clear WAKE flag at command fetch */
 541
 542     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~WAKE);
 543
 544     cmd = le16_to_cpu(current->command) & COMMAND_MASK;
 545
 546     switch (cmd) {
 547     case DBDMA_NOP:
 548         nop(ch);
 549         return;
 550
 551     case DBDMA_STOP:
 552         stop(ch);
 553         return;
 554     }
 555
 556     key = le16_to_cpu(current->command) & 0x0700;
 557     req_count = le16_to_cpu(current->req_count);
 558     phy_addr = le32_to_cpu(current->phy_addr);
 559
 560     if (key == KEY_STREAM4) {
 561         printf("command %x, invalid key 4\n", cmd);
 562         kill_channel(ch);
 563         return;
 564     }
 565
 566     switch (cmd) {
 567     case OUTPUT_MORE:
 568         start_output(ch, key, phy_addr, req_count, 0);
 569         return;
 570
 571     case OUTPUT_LAST:
 572         start_output(ch, key, phy_addr, req_count, 1);
 573         return;
 574
 575     case INPUT_MORE:
 576         start_input(ch, key, phy_addr, req_count, 0);
 577         return;
 578
 579     case INPUT_LAST:
 580         start_input(ch, key, phy_addr, req_count, 1);
 581         return;
 582     }
 583
 584     if (key < KEY_REGS) {
 585         printf("command %x, invalid key %x\n", cmd, key);
 586         key = KEY_SYSTEM;
 587     }
 588
 589     /* for LOAD_WORD and STORE_WORD, req_count is on 3 bits
 590      * and BRANCH is invalid
 591      */
 592
 593     req_count = req_count & 0x0007;
 594     if (req_count & 0x4) {
 595         req_count = 4;
 596         phy_addr &= ~3;
 597     } else if (req_count & 0x2) {
 598         req_count = 2;
 599         phy_addr &= ~1;
 600     } else
 601         req_count = 1;
 602
 603     switch (cmd) {
 604     case LOAD_WORD:
 605         load_word(ch, key, phy_addr, req_count);
 606         return;
 607
 608     case STORE_WORD:
 609         store_word(ch, key, phy_addr, req_count);
 610         return;
 611     }
 612 }
 613
 614 static void DBDMA_run (DBDMA_channel *ch)
 615 {
 616     int channel;
 617
 618     for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
 619             uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
 620             if (!ch->processing && (status & RUN) && (status & ACTIVE))
 621                 channel_run(ch);
 622     }
 623 }
 624
 625 static void DBDMA_run_bh(void *opaque)
 626 {
 627     DBDMA_channel *ch = opaque;
 628
 629     DBDMA_DPRINTF("DBDMA_run_bh\n");
 630
 631     DBDMA_run(ch);
 632 }
 633
 634 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
 635                             DBDMA_rw rw,
 636                             void *opaque)
 637 {
 638     DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan;
 639
 640     DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
 641
 642     ch->irq = irq;
 643     ch->channel = nchan;
 644     ch->rw = rw;
 645     ch->io.opaque = opaque;
 646     ch->io.channel = ch;
 647 }
 648
 649 void DBDMA_schedule(void)
 650 {
 651     CPUState *env = cpu_single_env;
 652     if (env)
 653         cpu_interrupt(env, CPU_INTERRUPT_EXIT);
 654 }
 655
 656 static void
 657 dbdma_control_write(DBDMA_channel *ch)
 658 {
 659     uint16_t mask, value;
 660     uint32_t status;
 661
 662     mask = (be32_to_cpu(ch->regs[DBDMA_CONTROL]) >> 16) & 0xffff;
 663     value = be32_to_cpu(ch->regs[DBDMA_CONTROL]) & 0xffff;
 664
 665     value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT);
 666
 667     status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
 668
 669     status = (value & mask) | (status & ~mask);
 670
 671     if (status & WAKE)
 672         status |= ACTIVE;
 673     if (status & RUN) {
 674         status |= ACTIVE;
 675         status &= ~DEAD;
 676     }
 677     if (status & PAUSE)
 678         status &= ~ACTIVE;
 679     if ((be32_to_cpu(ch->regs[DBDMA_STATUS]) & RUN) && !(status & RUN)) {
 680         /* RUN is cleared */
 681         status &= ~(ACTIVE|DEAD);
 682     }
 683
 684     DBDMA_DPRINTF("    status 0x%08x\n", status);
 685
 686     ch->regs[DBDMA_STATUS] = cpu_to_be32(status);
 687
 688     if (status & ACTIVE)
 689         qemu_bh_schedule(dbdma_bh);
 690 }
 691
 692 static void dbdma_writel (void *opaque,
 693                           target_phys_addr_t addr, uint32_t value)
 694 {
 695     int channel = addr >> DBDMA_CHANNEL_SHIFT;
 696     DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
 697     int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
 698
 699     DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
 700     DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
 701                   (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
 702
 703     /* cmdptr cannot be modified if channel is RUN or ACTIVE */
 704
 705     if (reg == DBDMA_CMDPTR_LO &&
 706         (ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN | ACTIVE)))
 707         return;
 708
 709     ch->regs[reg] = value;
 710
 711     switch(reg) {
 712     case DBDMA_CONTROL:
 713         dbdma_control_write(ch);
 714         break;
 715     case DBDMA_CMDPTR_LO:
 716         /* 16-byte aligned */
 717         ch->regs[DBDMA_CMDPTR_LO] &= cpu_to_be32(~0xf);
 718         dbdma_cmdptr_load(ch);
 719         break;
 720     case DBDMA_STATUS:
 721     case DBDMA_INTR_SEL:
 722     case DBDMA_BRANCH_SEL:
 723     case DBDMA_WAIT_SEL:
 724         /* nothing to do */
 725         break;
 726     case DBDMA_XFER_MODE:
 727     case DBDMA_CMDPTR_HI:
 728     case DBDMA_DATA2PTR_HI:
 729     case DBDMA_DATA2PTR_LO:
 730     case DBDMA_ADDRESS_HI:
 731     case DBDMA_BRANCH_ADDR_HI:
 732     case DBDMA_RES1:
 733     case DBDMA_RES2:
 734     case DBDMA_RES3:
 735     case DBDMA_RES4:
 736         /* unused */
 737         break;
 738     }
 739 }
 740
 741 static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
 742 {
 743     uint32_t value;
 744     int channel = addr >> DBDMA_CHANNEL_SHIFT;
 745     DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
 746     int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
 747
 748     value = ch->regs[reg];
 749
 750     DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value);
 751     DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
 752                   (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
 753
 754     switch(reg) {
 755     case DBDMA_CONTROL:
 756         value = 0;
 757         break;
 758     case DBDMA_STATUS:
 759     case DBDMA_CMDPTR_LO:
 760     case DBDMA_INTR_SEL:
 761     case DBDMA_BRANCH_SEL:
 762     case DBDMA_WAIT_SEL:
 763         /* nothing to do */
 764         break;
 765     case DBDMA_XFER_MODE:
 766     case DBDMA_CMDPTR_HI:
 767     case DBDMA_DATA2PTR_HI:
 768     case DBDMA_DATA2PTR_LO:
 769     case DBDMA_ADDRESS_HI:
 770     case DBDMA_BRANCH_ADDR_HI:
 771         /* unused */
 772         value = 0;
 773         break;
 774     case DBDMA_RES1:
 775     case DBDMA_RES2:
 776     case DBDMA_RES3:
 777     case DBDMA_RES4:
 778         /* reserved */
 779         break;
 780     }
 781
 782     return value;
 783 }
 784
 785 static CPUWriteMemoryFunc *dbdma_write[] = {
 786     NULL,
 787     NULL,
 788     dbdma_writel,
 789 };
 790
 791 static CPUReadMemoryFunc *dbdma_read[] = {
 792     NULL,
 793     NULL,
 794     dbdma_readl,
 795 };
 796
 797 static void dbdma_save(QEMUFile *f, void *opaque)
 798 {
 799     DBDMA_channel *s = opaque;
 800     unsigned int i, j;
 801
 802     for (i = 0; i < DBDMA_CHANNELS; i++)
 803         for (j = 0; j < DBDMA_REGS; j++)
 804             qemu_put_be32s(f, &s[i].regs[j]);
 805 }
 806
 807 static int dbdma_load(QEMUFile *f, void *opaque, int version_id)
 808 {
 809     DBDMA_channel *s = opaque;
 810     unsigned int i, j;
 811
 812     if (version_id != 2)
 813         return -EINVAL;
 814
 815     for (i = 0; i < DBDMA_CHANNELS; i++)
 816         for (j = 0; j < DBDMA_REGS; j++)
 817             qemu_get_be32s(f, &s[i].regs[j]);
 818
 819     return 0;
 820 }
 821
 822 static void dbdma_reset(void *opaque)
 823 {
 824     DBDMA_channel *s = opaque;
 825     int i;
 826
 827     for (i = 0; i < DBDMA_CHANNELS; i++)
 828         memset(s[i].regs, 0, DBDMA_SIZE);
 829 }
 830
 831 void* DBDMA_init (int *dbdma_mem_index)
 832 {
 833     DBDMA_channel *s;
 834
 835     s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
 836
 837     *dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, s);
 838     register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
 839     qemu_register_reset(dbdma_reset, s);
 840     dbdma_reset(s);
 841
 842     dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
 843
 844     return s;
 845 }