target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25
  26 //#define DEBUG_KVM
  27
  28 #ifdef DEBUG_KVM
  29 #define dprintf(fmt, ...) \
  30     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  31 #else
  32 #define dprintf(fmt, ...) \
  33     do { } while (0)
  34 #endif
  35
  36 int kvm_arch_init_vcpu(CPUState *env)
  37 {
  38     struct {
  39         struct kvm_cpuid2 cpuid;
  40         struct kvm_cpuid_entry2 entries[100];
  41     } __attribute__((packed)) cpuid_data;
  42     uint32_t limit, i, j, cpuid_i;
  43     uint32_t eax, ebx, ecx, edx;
  44
  45     cpuid_i = 0;
  46
  47     cpu_x86_cpuid(env, 0, 0, &eax, &ebx, &ecx, &edx);
  48     limit = eax;
  49
  50     for (i = 0; i <= limit; i++) {
  51         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
  52
  53         switch (i) {
  54         case 2: {
  55             /* Keep reading function 2 till all the input is received */
  56             int times;
  57
  58             cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
  59             times = eax & 0xff;
  60
  61             c->function = i;
  62             c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
  63             c->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
  64             c->eax = eax;
  65             c->ebx = ebx;
  66             c->ecx = ecx;
  67             c->edx = edx;
  68
  69             for (j = 1; j < times; ++j) {
  70                 cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
  71                 c->function = i;
  72                 c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
  73                 c->eax = eax;
  74                 c->ebx = ebx;
  75                 c->ecx = ecx;
  76                 c->edx = edx;
  77             }
  78             break;
  79         }
  80         case 4:
  81         case 0xb:
  82         case 0xd:
  83             for (j = 0; ; j++) {
  84                 cpu_x86_cpuid(env, i, j, &eax, &ebx, &ecx, &edx);
  85                 c->function = i;
  86                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  87                 c->index = j;
  88                 c->eax = eax;
  89                 c->ebx = ebx;
  90                 c->ecx = ecx;
  91                 c->edx = edx;
  92                 c = &cpuid_data.entries[++cpuid_i];
  93
  94                 if (i == 4 && eax == 0)
  95                     break;
  96                 if (i == 0xb && !(ecx & 0xff00))
  97                     break;
  98                 if (i == 0xd && eax == 0)
  99                     break;
 100             }
 101             break;
 102         default:
 103             cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
 104             c->function = i;
 105             c->eax = eax;
 106             c->ebx = ebx;
 107             c->ecx = ecx;
 108             c->edx = edx;
 109             break;
 110         }
 111     }
 112     cpu_x86_cpuid(env, 0x80000000, 0, &eax, &ebx, &ecx, &edx);
 113     limit = eax;
 114
 115     for (i = 0x80000000; i <= limit; i++) {
 116         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 117
 118         cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
 119         c->function = i;
 120         c->eax = eax;
 121         c->ebx = ebx;
 122         c->ecx = ecx;
 123         c->edx = edx;
 124     }
 125
 126     cpuid_data.cpuid.nent = cpuid_i;
 127
 128     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 129 }
 130
 131 static int kvm_has_msr_star(CPUState *env)
 132 {
 133     static int has_msr_star;
 134     int ret;
 135
 136     /* first time */
 137     if (has_msr_star == 0) {
 138         struct kvm_msr_list msr_list, *kvm_msr_list;
 139
 140         has_msr_star = -1;
 141
 142         /* Obtain MSR list from KVM.  These are the MSRs that we must
 143          * save/restore */
 144         msr_list.nmsrs = 0;
 145         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 146         if (ret < 0)
 147             return 0;
 148
 149         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 150                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 151
 152         kvm_msr_list->nmsrs = msr_list.nmsrs;
 153         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 154         if (ret >= 0) {
 155             int i;
 156
 157             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 158                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 159                     has_msr_star = 1;
 160                     break;
 161                 }
 162             }
 163         }
 164
 165         free(kvm_msr_list);
 166     }
 167
 168     if (has_msr_star == 1)
 169         return 1;
 170     return 0;
 171 }
 172
 173 int kvm_arch_init(KVMState *s, int smp_cpus)
 174 {
 175     int ret;
 176
 177     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 178      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 179      * must be part of guest physical memory, we need to allocate it.  Older
 180      * versions of KVM just assumed that it would be at the end of physical
 181      * memory but that doesn't work with more than 4GB of memory.  We simply
 182      * refuse to work with those older versions of KVM. */
 183     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 184     if (ret <= 0) {
 185         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 186         return ret;
 187     }
 188
 189     /* this address is 3 pages before the bios, and the bios should present
 190      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 191      * this?
 192      */
 193     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 194 }
 195
 196 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 197 {
 198     lhs->selector = rhs->selector;
 199     lhs->base = rhs->base;
 200     lhs->limit = rhs->limit;
 201     lhs->type = 3;
 202     lhs->present = 1;
 203     lhs->dpl = 3;
 204     lhs->db = 0;
 205     lhs->s = 1;
 206     lhs->l = 0;
 207     lhs->g = 0;
 208     lhs->avl = 0;
 209     lhs->unusable = 0;
 210 }
 211
 212 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 213 {
 214     unsigned flags = rhs->flags;
 215     lhs->selector = rhs->selector;
 216     lhs->base = rhs->base;
 217     lhs->limit = rhs->limit;
 218     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 219     lhs->present = (flags & DESC_P_MASK) != 0;
 220     lhs->dpl = rhs->selector & 3;
 221     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 222     lhs->s = (flags & DESC_S_MASK) != 0;
 223     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 224     lhs->g = (flags & DESC_G_MASK) != 0;
 225     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 226     lhs->unusable = 0;
 227 }
 228
 229 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 230 {
 231     lhs->selector = rhs->selector;
 232     lhs->base = rhs->base;
 233     lhs->limit = rhs->limit;
 234     lhs->flags =
 235         (rhs->type << DESC_TYPE_SHIFT)
 236         | (rhs->present * DESC_P_MASK)
 237         | (rhs->dpl << DESC_DPL_SHIFT)
 238         | (rhs->db << DESC_B_SHIFT)
 239         | (rhs->s * DESC_S_MASK)
 240         | (rhs->l << DESC_L_SHIFT)
 241         | (rhs->g * DESC_G_MASK)
 242         | (rhs->avl * DESC_AVL_MASK);
 243 }
 244
 245 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 246 {
 247     if (set)
 248         *kvm_reg = *qemu_reg;
 249     else
 250         *qemu_reg = *kvm_reg;
 251 }
 252
 253 static int kvm_getput_regs(CPUState *env, int set)
 254 {
 255     struct kvm_regs regs;
 256     int ret = 0;
 257
 258     if (!set) {
 259         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 260         if (ret < 0)
 261             return ret;
 262     }
 263
 264     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 265     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 266     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 267     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 268     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 269     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 270     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 271     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 272 #ifdef TARGET_X86_64
 273     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 274     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 275     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 276     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 277     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 278     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 279     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 280     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 281 #endif
 282
 283     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 284     kvm_getput_reg(&regs.rip, &env->eip, set);
 285
 286     if (set)
 287         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 288
 289     return ret;
 290 }
 291
 292 static int kvm_put_fpu(CPUState *env)
 293 {
 294     struct kvm_fpu fpu;
 295     int i;
 296
 297     memset(&fpu, 0, sizeof fpu);
 298     fpu.fsw = env->fpus & ~(7 << 11);
 299     fpu.fsw |= (env->fpstt & 7) << 11;
 300     fpu.fcw = env->fpuc;
 301     for (i = 0; i < 8; ++i)
 302         fpu.ftwx |= (!env->fptags[i]) << i;
 303     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 304     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 305     fpu.mxcsr = env->mxcsr;
 306
 307     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 308 }
 309
 310 static int kvm_put_sregs(CPUState *env)
 311 {
 312     struct kvm_sregs sregs;
 313
 314     memcpy(sregs.interrupt_bitmap,
 315            env->interrupt_bitmap,
 316            sizeof(sregs.interrupt_bitmap));
 317
 318     if ((env->eflags & VM_MASK)) {
 319             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 320             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 321             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 322             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 323             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 324             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 325     } else {
 326             set_seg(&sregs.cs, &env->segs[R_CS]);
 327             set_seg(&sregs.ds, &env->segs[R_DS]);
 328             set_seg(&sregs.es, &env->segs[R_ES]);
 329             set_seg(&sregs.fs, &env->segs[R_FS]);
 330             set_seg(&sregs.gs, &env->segs[R_GS]);
 331             set_seg(&sregs.ss, &env->segs[R_SS]);
 332
 333             if (env->cr[0] & CR0_PE_MASK) {
 334                 /* force ss cpl to cs cpl */
 335                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 336                         (sregs.cs.selector & 3);
 337                 sregs.ss.dpl = sregs.ss.selector & 3;
 338             }
 339     }
 340
 341     set_seg(&sregs.tr, &env->tr);
 342     set_seg(&sregs.ldt, &env->ldt);
 343
 344     sregs.idt.limit = env->idt.limit;
 345     sregs.idt.base = env->idt.base;
 346     sregs.gdt.limit = env->gdt.limit;
 347     sregs.gdt.base = env->gdt.base;
 348
 349     sregs.cr0 = env->cr[0];
 350     sregs.cr2 = env->cr[2];
 351     sregs.cr3 = env->cr[3];
 352     sregs.cr4 = env->cr[4];
 353
 354     sregs.cr8 = cpu_get_apic_tpr(env);
 355     sregs.apic_base = cpu_get_apic_base(env);
 356
 357     sregs.efer = env->efer;
 358
 359     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 360 }
 361
 362 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 363                               uint32_t index, uint64_t value)
 364 {
 365     entry->index = index;
 366     entry->data = value;
 367 }
 368
 369 static int kvm_put_msrs(CPUState *env)
 370 {
 371     struct {
 372         struct kvm_msrs info;
 373         struct kvm_msr_entry entries[100];
 374     } msr_data;
 375     struct kvm_msr_entry *msrs = msr_data.entries;
 376     int n = 0;
 377
 378     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 379     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 380     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 381     if (kvm_has_msr_star(env))
 382         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 383     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 384 #ifdef TARGET_X86_64
 385     /* FIXME if lm capable */
 386     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 387     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 388     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 389     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 390 #endif
 391     msr_data.info.nmsrs = n;
 392
 393     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 394
 395 }
 396
 397
 398 static int kvm_get_fpu(CPUState *env)
 399 {
 400     struct kvm_fpu fpu;
 401     int i, ret;
 402
 403     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 404     if (ret < 0)
 405         return ret;
 406
 407     env->fpstt = (fpu.fsw >> 11) & 7;
 408     env->fpus = fpu.fsw;
 409     env->fpuc = fpu.fcw;
 410     for (i = 0; i < 8; ++i)
 411         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 412     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 413     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 414     env->mxcsr = fpu.mxcsr;
 415
 416     return 0;
 417 }
 418
 419 static int kvm_get_sregs(CPUState *env)
 420 {
 421     struct kvm_sregs sregs;
 422     uint32_t hflags;
 423     int ret;
 424
 425     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 426     if (ret < 0)
 427         return ret;
 428
 429     memcpy(env->interrupt_bitmap,
 430            sregs.interrupt_bitmap,
 431            sizeof(sregs.interrupt_bitmap));
 432
 433     get_seg(&env->segs[R_CS], &sregs.cs);
 434     get_seg(&env->segs[R_DS], &sregs.ds);
 435     get_seg(&env->segs[R_ES], &sregs.es);
 436     get_seg(&env->segs[R_FS], &sregs.fs);
 437     get_seg(&env->segs[R_GS], &sregs.gs);
 438     get_seg(&env->segs[R_SS], &sregs.ss);
 439
 440     get_seg(&env->tr, &sregs.tr);
 441     get_seg(&env->ldt, &sregs.ldt);
 442
 443     env->idt.limit = sregs.idt.limit;
 444     env->idt.base = sregs.idt.base;
 445     env->gdt.limit = sregs.gdt.limit;
 446     env->gdt.base = sregs.gdt.base;
 447
 448     env->cr[0] = sregs.cr0;
 449     env->cr[2] = sregs.cr2;
 450     env->cr[3] = sregs.cr3;
 451     env->cr[4] = sregs.cr4;
 452
 453     cpu_set_apic_base(env, sregs.apic_base);
 454
 455     env->efer = sregs.efer;
 456     //cpu_set_apic_tpr(env, sregs.cr8);
 457
 458 #define HFLAG_COPY_MASK ~( \
 459                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 460                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 461                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 462                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 463
 464
 465
 466     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 467     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 468     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 469             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 470     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 471     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 472             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 473
 474     if (env->efer & MSR_EFER_LMA) {
 475         hflags |= HF_LMA_MASK;
 476     }
 477
 478     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 479         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 480     } else {
 481         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 482                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 483         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 484                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 485         if (!(env->cr[0] & CR0_PE_MASK) ||
 486                    (env->eflags & VM_MASK) ||
 487                    !(hflags & HF_CS32_MASK)) {
 488                 hflags |= HF_ADDSEG_MASK;
 489             } else {
 490                 hflags |= ((env->segs[R_DS].base |
 491                                 env->segs[R_ES].base |
 492                                 env->segs[R_SS].base) != 0) <<
 493                     HF_ADDSEG_SHIFT;
 494             }
 495     }
 496     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 497
 498     return 0;
 499 }
 500
 501 static int kvm_get_msrs(CPUState *env)
 502 {
 503     struct {
 504         struct kvm_msrs info;
 505         struct kvm_msr_entry entries[100];
 506     } msr_data;
 507     struct kvm_msr_entry *msrs = msr_data.entries;
 508     int ret, i, n;
 509
 510     n = 0;
 511     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 512     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 513     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 514     if (kvm_has_msr_star(env))
 515         msrs[n++].index = MSR_STAR;
 516     msrs[n++].index = MSR_IA32_TSC;
 517 #ifdef TARGET_X86_64
 518     /* FIXME lm_capable_kernel */
 519     msrs[n++].index = MSR_CSTAR;
 520     msrs[n++].index = MSR_KERNELGSBASE;
 521     msrs[n++].index = MSR_FMASK;
 522     msrs[n++].index = MSR_LSTAR;
 523 #endif
 524     msr_data.info.nmsrs = n;
 525     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 526     if (ret < 0)
 527         return ret;
 528
 529     for (i = 0; i < ret; i++) {
 530         switch (msrs[i].index) {
 531         case MSR_IA32_SYSENTER_CS:
 532             env->sysenter_cs = msrs[i].data;
 533             break;
 534         case MSR_IA32_SYSENTER_ESP:
 535             env->sysenter_esp = msrs[i].data;
 536             break;
 537         case MSR_IA32_SYSENTER_EIP:
 538             env->sysenter_eip = msrs[i].data;
 539             break;
 540         case MSR_STAR:
 541             env->star = msrs[i].data;
 542             break;
 543 #ifdef TARGET_X86_64
 544         case MSR_CSTAR:
 545             env->cstar = msrs[i].data;
 546             break;
 547         case MSR_KERNELGSBASE:
 548             env->kernelgsbase = msrs[i].data;
 549             break;
 550         case MSR_FMASK:
 551             env->fmask = msrs[i].data;
 552             break;
 553         case MSR_LSTAR:
 554             env->lstar = msrs[i].data;
 555             break;
 556 #endif
 557         case MSR_IA32_TSC:
 558             env->tsc = msrs[i].data;
 559             break;
 560         }
 561     }
 562
 563     return 0;
 564 }
 565
 566 int kvm_arch_put_registers(CPUState *env)
 567 {
 568     int ret;
 569
 570     ret = kvm_getput_regs(env, 1);
 571     if (ret < 0)
 572         return ret;
 573
 574     ret = kvm_put_fpu(env);
 575     if (ret < 0)
 576         return ret;
 577
 578     ret = kvm_put_sregs(env);
 579     if (ret < 0)
 580         return ret;
 581
 582     ret = kvm_put_msrs(env);
 583     if (ret < 0)
 584         return ret;
 585
 586     return 0;
 587 }
 588
 589 int kvm_arch_get_registers(CPUState *env)
 590 {
 591     int ret;
 592
 593     ret = kvm_getput_regs(env, 0);
 594     if (ret < 0)
 595         return ret;
 596
 597     ret = kvm_get_fpu(env);
 598     if (ret < 0)
 599         return ret;
 600
 601     ret = kvm_get_sregs(env);
 602     if (ret < 0)
 603         return ret;
 604
 605     ret = kvm_get_msrs(env);
 606     if (ret < 0)
 607         return ret;
 608
 609     return 0;
 610 }
 611
 612 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 613 {
 614     /* Try to inject an interrupt if the guest can accept it */
 615     if (run->ready_for_interrupt_injection &&
 616         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 617         (env->eflags & IF_MASK)) {
 618         int irq;
 619
 620         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 621         irq = cpu_get_pic_interrupt(env);
 622         if (irq >= 0) {
 623             struct kvm_interrupt intr;
 624             intr.irq = irq;
 625             /* FIXME: errors */
 626             dprintf("injected interrupt %d\n", irq);
 627             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 628         }
 629     }
 630
 631     /* If we have an interrupt but the guest is not ready to receive an
 632      * interrupt, request an interrupt window exit.  This will
 633      * cause a return to userspace as soon as the guest is ready to
 634      * receive interrupts. */
 635     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 636         run->request_interrupt_window = 1;
 637     else
 638         run->request_interrupt_window = 0;
 639
 640     dprintf("setting tpr\n");
 641     run->cr8 = cpu_get_apic_tpr(env);
 642
 643     return 0;
 644 }
 645
 646 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 647 {
 648     if (run->if_flag)
 649         env->eflags |= IF_MASK;
 650     else
 651         env->eflags &= ~IF_MASK;
 652
 653     cpu_set_apic_tpr(env, run->cr8);
 654     cpu_set_apic_base(env, run->apic_base);
 655
 656     return 0;
 657 }
 658
 659 static int kvm_handle_halt(CPUState *env)
 660 {
 661     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 662           (env->eflags & IF_MASK)) &&
 663         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 664         env->halted = 1;
 665         env->exception_index = EXCP_HLT;
 666         return 0;
 667     }
 668
 669     return 1;
 670 }
 671
 672 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 673 {
 674     int ret = 0;
 675
 676     switch (run->exit_reason) {
 677     case KVM_EXIT_HLT:
 678         dprintf("handle_hlt\n");
 679         ret = kvm_handle_halt(env);
 680         break;
 681     }
 682
 683     return ret;
 684 }