add test.c
[qemu/mini2440/sniper_sniper_test.git] / hw / eepro100.c
blob2948d3c154943bde011bc601d4c65b96f7856edb
1 /*
2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 * Tested features (i82559):
24 * PXE boot (i386) no valid link
25 * Linux networking (i386) ok
27 * Untested:
28 * non-i386 platforms
29 * Windows networking
31 * References:
33 * Intel 8255x 10/100 Mbps Ethernet Controller Family
34 * Open Source Software Developer Manual
37 #if defined(TARGET_I386)
38 # warning "PXE boot still not working!"
39 #endif
41 #include <assert.h>
42 #include <stddef.h> /* offsetof */
43 #include "hw.h"
44 #include "pci.h"
45 #include "net.h"
46 #include "eeprom93xx.h"
48 /* Common declarations for all PCI devices. */
50 #define PCI_DEVICE_ID 0x02 /* 16 bits */
51 #define PCI_COMMAND 0x04 /* 16 bits */
52 #define PCI_STATUS 0x06 /* 16 bits */
54 #define PCI_REVISION_ID 0x08 /* 8 bits */
56 #define PCI_CONFIG_8(offset, value) \
57 (pci_conf[offset] = (value))
58 #define PCI_CONFIG_16(offset, value) \
59 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
60 #define PCI_CONFIG_32(offset, value) \
61 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
63 #define KiB 1024
65 /* debug EEPRO100 card */
66 //~ #define DEBUG_EEPRO100
68 #ifdef DEBUG_EEPRO100
69 #define logout(fmt, args...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ##args)
70 #else
71 #define logout(fmt, args...) ((void)0)
72 #endif
74 /* Set flags to 0 to disable debug output. */
75 #define MDI 0
77 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
79 #define missing(text) assert(!"feature is missing in this emulation: " text)
81 #define MAX_ETH_FRAME_SIZE 1514
83 /* This driver supports several different devices which are declared here. */
84 #define i82551 0x82551
85 #define i82557B 0x82557b
86 #define i82557C 0x82557c
87 #define i82558B 0x82558b
88 #define i82559C 0x82559c
89 #define i82559ER 0x82559e
90 #define i82562 0x82562
92 #define EEPROM_SIZE 64
94 #define PCI_MEM_SIZE (4 * KiB)
95 #define PCI_IO_SIZE 64
96 #define PCI_FLASH_SIZE (128 * KiB)
98 #define BIT(n) (1 << (n))
99 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
101 /* The SCB accepts the following controls for the Tx and Rx units: */
102 #define CU_NOP 0x0000 /* No operation. */
103 #define CU_START 0x0010 /* CU start. */
104 #define CU_RESUME 0x0020 /* CU resume. */
105 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
106 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
107 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
108 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
109 #define CU_SRESUME 0x00a0 /* CU static resume. */
111 #define RU_NOP 0x0000
112 #define RX_START 0x0001
113 #define RX_RESUME 0x0002
114 #define RX_ABORT 0x0004
115 #define RX_ADDR_LOAD 0x0006
116 #define RX_RESUMENR 0x0007
117 #define INT_MASK 0x0100
118 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
120 typedef unsigned char bool;
122 /* Offsets to the various registers.
123 All accesses need not be longword aligned. */
124 enum speedo_offsets {
125 SCBStatus = 0,
126 SCBAck = 1,
127 SCBCmd = 2, /* Rx/Command Unit command and status. */
128 SCBIntmask = 3,
129 SCBPointer = 4, /* General purpose pointer. */
130 SCBPort = 8, /* Misc. commands and operands. */
131 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
132 SCBCtrlMDI = 16, /* MDI interface control. */
133 SCBEarlyRx = 20, /* Early receive byte count. */
134 SCBFlow = 24,
137 /* A speedo3 transmit buffer descriptor with two buffers... */
138 typedef struct {
139 uint16_t status;
140 uint16_t command;
141 uint32_t link; /* void * */
142 uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
143 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
144 uint8_t tx_threshold; /* transmit threshold */
145 uint8_t tbd_count; /* TBD number */
146 //~ /* This constitutes two "TBD" entries: hdr and data */
147 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
148 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
149 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
150 //~ int32_t tx_buf_size1; /* Length of Tx data. */
151 } eepro100_tx_t;
153 /* Receive frame descriptor. */
154 typedef struct {
155 int16_t status;
156 uint16_t command;
157 uint32_t link; /* struct RxFD * */
158 uint32_t rx_buf_addr; /* void * */
159 uint16_t count;
160 uint16_t size;
161 char packet[MAX_ETH_FRAME_SIZE + 4];
162 } eepro100_rx_t;
164 typedef struct {
165 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
166 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
167 tx_multiple_collisions, tx_total_collisions;
168 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
169 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
170 rx_short_frame_errors;
171 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
172 uint16_t xmt_tco_frames, rcv_tco_frames;
173 uint32_t complete;
174 } eepro100_stats_t;
176 typedef enum {
177 cu_idle = 0,
178 cu_suspended = 1,
179 cu_active = 2,
180 cu_lpq_active = 2,
181 cu_hqp_active = 3
182 } cu_state_t;
184 typedef enum {
185 ru_idle = 0,
186 ru_suspended = 1,
187 ru_no_resources = 2,
188 ru_ready = 4
189 } ru_state_t;
191 typedef struct {
192 #if 1
193 uint8_t cmd;
194 uint32_t start;
195 uint32_t stop;
196 uint8_t boundary;
197 uint8_t tsr;
198 uint8_t tpsr;
199 uint16_t tcnt;
200 uint16_t rcnt;
201 uint32_t rsar;
202 uint8_t rsr;
203 uint8_t rxcr;
204 uint8_t isr;
205 uint8_t dcfg;
206 uint8_t imr;
207 uint8_t phys[6]; /* mac address */
208 uint8_t curpag;
209 uint8_t mult[8]; /* multicast mask array */
210 int mmio_index;
211 PCIDevice *pci_dev;
212 VLANClientState *vc;
213 #endif
214 uint8_t scb_stat; /* SCB stat/ack byte */
215 uint8_t int_stat; /* PCI interrupt status */
216 uint32_t region[3]; /* PCI region addresses */
217 uint8_t macaddr[6];
218 uint32_t statcounter[19];
219 uint16_t mdimem[32];
220 eeprom_t *eeprom;
221 uint32_t device; /* device variant */
222 uint32_t pointer;
223 /* (cu_base + cu_offset) address the next command block in the command block list. */
224 uint32_t cu_base; /* CU base address */
225 uint32_t cu_offset; /* CU address offset */
226 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
227 uint32_t ru_base; /* RU base address */
228 uint32_t ru_offset; /* RU address offset */
229 uint32_t statsaddr; /* pointer to eepro100_stats_t */
230 eepro100_stats_t statistics; /* statistical counters */
231 #if 0
232 uint16_t status;
233 #endif
235 /* Configuration bytes. */
236 uint8_t configuration[22];
238 /* Data in mem is always in the byte order of the controller (le). */
239 uint8_t mem[PCI_MEM_SIZE];
240 } EEPRO100State;
242 /* Default values for MDI (PHY) registers */
243 static const uint16_t eepro100_mdi_default[] = {
244 /* MDI Registers 0 - 6, 7 */
245 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
246 /* MDI Registers 8 - 15 */
247 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
248 /* MDI Registers 16 - 31 */
249 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
250 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
253 /* Readonly mask for MDI (PHY) registers */
254 static const uint16_t eepro100_mdi_mask[] = {
255 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
256 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
257 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
258 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
261 #define POLYNOMIAL 0x04c11db6
263 /* From FreeBSD */
264 /* XXX: optimize */
265 static int compute_mcast_idx(const uint8_t * ep)
267 uint32_t crc;
268 int carry, i, j;
269 uint8_t b;
271 crc = 0xffffffff;
272 for (i = 0; i < 6; i++) {
273 b = *ep++;
274 for (j = 0; j < 8; j++) {
275 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
276 crc <<= 1;
277 b >>= 1;
278 if (carry)
279 crc = ((crc ^ POLYNOMIAL) | carry);
282 return (crc >> 26);
285 #if defined(DEBUG_EEPRO100)
286 static const char *nic_dump(const uint8_t * buf, unsigned size)
288 static char dump[3 * 16 + 1];
289 char *p = &dump[0];
290 if (size > 16)
291 size = 16;
292 while (size-- > 0) {
293 p += sprintf(p, " %02x", *buf++);
295 return dump;
297 #endif /* DEBUG_EEPRO100 */
299 enum scb_stat_ack {
300 stat_ack_not_ours = 0x00,
301 stat_ack_sw_gen = 0x04,
302 stat_ack_rnr = 0x10,
303 stat_ack_cu_idle = 0x20,
304 stat_ack_frame_rx = 0x40,
305 stat_ack_cu_cmd_done = 0x80,
306 stat_ack_not_present = 0xFF,
307 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
308 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
311 static void disable_interrupt(EEPRO100State * s)
313 if (s->int_stat) {
314 logout("interrupt disabled\n");
315 qemu_irq_lower(s->pci_dev->irq[0]);
316 s->int_stat = 0;
320 static void enable_interrupt(EEPRO100State * s)
322 if (!s->int_stat) {
323 logout("interrupt enabled\n");
324 qemu_irq_raise(s->pci_dev->irq[0]);
325 s->int_stat = 1;
329 static void eepro100_acknowledge(EEPRO100State * s)
331 s->scb_stat &= ~s->mem[SCBAck];
332 s->mem[SCBAck] = s->scb_stat;
333 if (s->scb_stat == 0) {
334 disable_interrupt(s);
338 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
340 uint8_t mask = ~s->mem[SCBIntmask];
341 s->mem[SCBAck] |= stat;
342 stat = s->scb_stat = s->mem[SCBAck];
343 stat &= (mask | 0x0f);
344 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
345 if (stat && (mask & 0x01)) {
346 /* SCB mask and SCB Bit M do not disable interrupt. */
347 enable_interrupt(s);
348 } else if (s->int_stat) {
349 disable_interrupt(s);
353 static void eepro100_cx_interrupt(EEPRO100State * s)
355 /* CU completed action command. */
356 /* Transmit not ok (82557 only, not in emulation). */
357 eepro100_interrupt(s, 0x80);
360 static void eepro100_cna_interrupt(EEPRO100State * s)
362 /* CU left the active state. */
363 eepro100_interrupt(s, 0x20);
366 static void eepro100_fr_interrupt(EEPRO100State * s)
368 /* RU received a complete frame. */
369 eepro100_interrupt(s, 0x40);
372 #if 0
373 static void eepro100_rnr_interrupt(EEPRO100State * s)
375 /* RU is not ready. */
376 eepro100_interrupt(s, 0x10);
378 #endif
380 static void eepro100_mdi_interrupt(EEPRO100State * s)
382 /* MDI completed read or write cycle. */
383 eepro100_interrupt(s, 0x08);
386 static void eepro100_swi_interrupt(EEPRO100State * s)
388 /* Software has requested an interrupt. */
389 eepro100_interrupt(s, 0x04);
392 #if 0
393 static void eepro100_fcp_interrupt(EEPRO100State * s)
395 /* Flow control pause interrupt (82558 and later). */
396 eepro100_interrupt(s, 0x01);
398 #endif
400 static void pci_reset(EEPRO100State * s)
402 uint32_t device = s->device;
403 uint8_t *pci_conf = s->pci_dev->config;
405 logout("%p\n", s);
407 /* PCI Vendor ID */
408 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
409 /* PCI Device ID */
410 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
411 /* PCI Command */
412 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
413 /* PCI Status */
414 PCI_CONFIG_16(PCI_STATUS, 0x2800);
415 /* PCI Revision ID */
416 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
417 /* PCI Class Code */
418 PCI_CONFIG_8(0x09, 0x00);
419 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
420 /* PCI Cache Line Size */
421 /* check cache line size!!! */
422 //~ PCI_CONFIG_8(0x0c, 0x00);
423 /* PCI Latency Timer */
424 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
425 /* PCI Header Type */
426 /* BIST (built-in self test) */
427 #if defined(TARGET_I386)
428 // !!! workaround for buggy bios
429 //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
430 #endif
431 #if 0
432 /* PCI Base Address Registers */
433 /* CSR Memory Mapped Base Address */
434 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
435 PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH);
436 /* CSR I/O Mapped Base Address */
437 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO);
438 #if 0
439 /* Flash Memory Mapped Base Address */
440 PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM);
441 #endif
442 #endif
443 /* Expansion ROM Base Address (depends on boot disable!!!) */
444 PCI_CONFIG_32(0x30, 0x00000000);
445 /* Capability Pointer */
446 PCI_CONFIG_8(0x34, 0xdc);
447 /* Interrupt Pin */
448 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
449 /* Minimum Grant */
450 PCI_CONFIG_8(0x3e, 0x08);
451 /* Maximum Latency */
452 PCI_CONFIG_8(0x3f, 0x18);
453 /* Power Management Capabilities / Next Item Pointer / Capability ID */
454 PCI_CONFIG_32(0xdc, 0x7e210001);
456 switch (device) {
457 case i82551:
458 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
459 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
460 break;
461 case i82557B:
462 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
463 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
464 break;
465 case i82557C:
466 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
467 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
468 break;
469 case i82558B:
470 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
471 PCI_CONFIG_16(PCI_STATUS, 0x2810);
472 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
473 break;
474 case i82559C:
475 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
476 PCI_CONFIG_16(PCI_STATUS, 0x2810);
477 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
478 break;
479 case i82559ER:
480 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
481 PCI_CONFIG_16(PCI_STATUS, 0x2810);
482 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
483 break;
484 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
485 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
486 default:
487 logout("Device %X is undefined!\n", device);
490 if (device == i82557C || device == i82558B || device == i82559C) {
491 logout("Get device id and revision from EEPROM!!!\n");
495 static void nic_selective_reset(EEPRO100State * s)
497 size_t i;
498 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
499 //~ eeprom93xx_reset(s->eeprom);
500 memcpy(eeprom_contents, s->macaddr, 6);
501 eeprom_contents[0xa] = 0x4000;
502 uint16_t sum = 0;
503 for (i = 0; i < EEPROM_SIZE - 1; i++) {
504 sum += eeprom_contents[i];
506 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
508 memset(s->mem, 0, sizeof(s->mem));
509 uint32_t val = BIT(21);
510 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
512 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
513 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
516 static void nic_reset(void *opaque)
518 EEPRO100State *s = (EEPRO100State *) opaque;
519 logout("%p\n", s);
520 static int first;
521 if (!first) {
522 first = 1;
524 nic_selective_reset(s);
527 #if defined(DEBUG_EEPRO100)
528 static const char *reg[PCI_IO_SIZE / 4] = {
529 "Command/Status",
530 "General Pointer",
531 "Port",
532 "EEPROM/Flash Control",
533 "MDI Control",
534 "Receive DMA Byte Count",
535 "Flow control register",
536 "General Status/Control"
539 static char *regname(uint32_t addr)
541 static char buf[16];
542 if (addr < PCI_IO_SIZE) {
543 const char *r = reg[addr / 4];
544 if (r != 0) {
545 sprintf(buf, "%s+%u", r, addr % 4);
546 } else {
547 sprintf(buf, "0x%02x", addr);
549 } else {
550 sprintf(buf, "??? 0x%08x", addr);
552 return buf;
554 #endif /* DEBUG_EEPRO100 */
556 #if 0
557 static uint16_t eepro100_read_status(EEPRO100State * s)
559 uint16_t val = s->status;
560 logout("val=0x%04x\n", val);
561 return val;
564 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
566 logout("val=0x%04x\n", val);
567 s->status = val;
569 #endif
571 /*****************************************************************************
573 * Command emulation.
575 ****************************************************************************/
577 #if 0
578 static uint16_t eepro100_read_command(EEPRO100State * s)
580 uint16_t val = 0xffff;
581 //~ logout("val=0x%04x\n", val);
582 return val;
584 #endif
586 /* Commands that can be put in a command list entry. */
587 enum commands {
588 CmdNOp = 0,
589 CmdIASetup = 1,
590 CmdConfigure = 2,
591 CmdMulticastList = 3,
592 CmdTx = 4,
593 CmdTDR = 5, /* load microcode */
594 CmdDump = 6,
595 CmdDiagnose = 7,
597 /* And some extra flags: */
598 CmdSuspend = 0x4000, /* Suspend after completion. */
599 CmdIntr = 0x2000, /* Interrupt after completion. */
600 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
603 static cu_state_t get_cu_state(EEPRO100State * s)
605 return ((s->mem[SCBStatus] >> 6) & 0x03);
608 static void set_cu_state(EEPRO100State * s, cu_state_t state)
610 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
613 static ru_state_t get_ru_state(EEPRO100State * s)
615 return ((s->mem[SCBStatus] >> 2) & 0x0f);
618 static void set_ru_state(EEPRO100State * s, ru_state_t state)
620 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
623 static void dump_statistics(EEPRO100State * s)
625 /* Dump statistical data. Most data is never changed by the emulation
626 * and always 0, so we first just copy the whole block and then those
627 * values which really matter.
628 * Number of data should check configuration!!!
630 cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64);
631 stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
632 stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
633 stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
634 stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
635 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
636 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
637 //~ missing("CU dump statistical counters");
640 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
642 eepro100_tx_t tx;
643 uint32_t cb_address;
644 switch (val) {
645 case CU_NOP:
646 /* No operation. */
647 break;
648 case CU_START:
649 if (get_cu_state(s) != cu_idle) {
650 /* Intel documentation says that CU must be idle for the CU
651 * start command. Intel driver for Linux also starts the CU
652 * from suspended state. */
653 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
654 //~ assert(!"wrong CU state");
656 set_cu_state(s, cu_active);
657 s->cu_offset = s->pointer;
658 next_command:
659 cb_address = s->cu_base + s->cu_offset;
660 cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
661 uint16_t status = le16_to_cpu(tx.status);
662 uint16_t command = le16_to_cpu(tx.command);
663 logout
664 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
665 val, status, command, tx.link);
666 bool bit_el = ((command & 0x8000) != 0);
667 bool bit_s = ((command & 0x4000) != 0);
668 bool bit_i = ((command & 0x2000) != 0);
669 bool bit_nc = ((command & 0x0010) != 0);
670 //~ bool bit_sf = ((command & 0x0008) != 0);
671 uint16_t cmd = command & 0x0007;
672 s->cu_offset = le32_to_cpu(tx.link);
673 switch (cmd) {
674 case CmdNOp:
675 /* Do nothing. */
676 break;
677 case CmdIASetup:
678 cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6);
679 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
680 break;
681 case CmdConfigure:
682 cpu_physical_memory_read(cb_address + 8, &s->configuration[0],
683 sizeof(s->configuration));
684 logout("configuration: %s\n", nic_dump(&s->configuration[0], 16));
685 break;
686 case CmdMulticastList:
687 //~ missing("multicast list");
688 break;
689 case CmdTx:
690 (void)0;
691 uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr);
692 uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
693 logout
694 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
695 tbd_array, tcb_bytes, tx.tbd_count);
696 assert(!bit_nc);
697 //~ assert(!bit_sf);
698 assert(tcb_bytes <= 2600);
699 /* Next assertion fails for local configuration. */
700 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
701 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
702 logout
703 ("illegal values of TBD array address and TCB byte count!\n");
705 uint8_t buf[MAX_ETH_FRAME_SIZE + 4];
706 uint16_t size = 0;
707 uint32_t tbd_address = cb_address + 0x10;
708 assert(tcb_bytes <= sizeof(buf));
709 while (size < tcb_bytes) {
710 uint32_t tx_buffer_address = ldl_phys(tbd_address);
711 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
712 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
713 tbd_address += 8;
714 logout
715 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
716 tx_buffer_address, tx_buffer_size);
717 cpu_physical_memory_read(tx_buffer_address, &buf[size],
718 tx_buffer_size);
719 size += tx_buffer_size;
721 if (tbd_array == 0xffffffff) {
722 /* Simplified mode. Was already handled by code above. */
723 } else {
724 /* Flexible mode. */
725 uint8_t tbd_count = 0;
726 if (!(s->configuration[6] & BIT(4))) {
727 /* Extended TCB. */
728 assert(tcb_bytes == 0);
729 for (; tbd_count < 2; tbd_count++) {
730 uint32_t tx_buffer_address = ldl_phys(tbd_address);
731 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
732 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
733 tbd_address += 8;
734 logout
735 ("TBD (extended mode): buffer address 0x%08x, size 0x%04x\n",
736 tx_buffer_address, tx_buffer_size);
737 cpu_physical_memory_read(tx_buffer_address, &buf[size],
738 tx_buffer_size);
739 size += tx_buffer_size;
740 if (tx_buffer_el & 1) {
741 break;
745 tbd_address = tbd_array;
746 for (; tbd_count < tx.tbd_count; tbd_count++) {
747 uint32_t tx_buffer_address = ldl_phys(tbd_address);
748 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
749 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
750 tbd_address += 8;
751 logout
752 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
753 tx_buffer_address, tx_buffer_size);
754 cpu_physical_memory_read(tx_buffer_address, &buf[size],
755 tx_buffer_size);
756 size += tx_buffer_size;
757 if (tx_buffer_el & 1) {
758 break;
762 qemu_send_packet(s->vc, buf, size);
763 s->statistics.tx_good_frames++;
764 /* Transmit with bad status would raise an CX/TNO interrupt.
765 * (82557 only). Emulation never has bad status. */
766 //~ eepro100_cx_interrupt(s);
767 break;
768 case CmdTDR:
769 logout("load microcode\n");
770 /* Starting with offset 8, the command contains
771 * 64 dwords microcode which we just ignore here. */
772 break;
773 default:
774 missing("undefined command");
776 /* Write new status (success). */
777 stw_phys(cb_address, status | 0x8000 | 0x2000);
778 if (bit_i) {
779 /* CU completed action. */
780 eepro100_cx_interrupt(s);
782 if (bit_el) {
783 /* CU becomes idle. */
784 set_cu_state(s, cu_idle);
785 eepro100_cna_interrupt(s);
786 } else if (bit_s) {
787 /* CU becomes suspended. */
788 set_cu_state(s, cu_suspended);
789 eepro100_cna_interrupt(s);
790 } else {
791 /* More entries in list. */
792 logout("CU list with at least one more entry\n");
793 goto next_command;
795 logout("CU list empty\n");
796 /* List is empty. Now CU is idle or suspended. */
797 break;
798 case CU_RESUME:
799 if (get_cu_state(s) != cu_suspended) {
800 logout("bad CU resume from CU state %u\n", get_cu_state(s));
801 /* Workaround for bad Linux eepro100 driver which resumes
802 * from idle state. */
803 //~ missing("cu resume");
804 set_cu_state(s, cu_suspended);
806 if (get_cu_state(s) == cu_suspended) {
807 logout("CU resuming\n");
808 set_cu_state(s, cu_active);
809 goto next_command;
811 break;
812 case CU_STATSADDR:
813 /* Load dump counters address. */
814 s->statsaddr = s->pointer;
815 logout("val=0x%02x (status address)\n", val);
816 break;
817 case CU_SHOWSTATS:
818 /* Dump statistical counters. */
819 dump_statistics(s);
820 break;
821 case CU_CMD_BASE:
822 /* Load CU base. */
823 logout("val=0x%02x (CU base address)\n", val);
824 s->cu_base = s->pointer;
825 break;
826 case CU_DUMPSTATS:
827 /* Dump and reset statistical counters. */
828 dump_statistics(s);
829 memset(&s->statistics, 0, sizeof(s->statistics));
830 break;
831 case CU_SRESUME:
832 /* CU static resume. */
833 missing("CU static resume");
834 break;
835 default:
836 missing("Undefined CU command");
840 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
842 switch (val) {
843 case RU_NOP:
844 /* No operation. */
845 break;
846 case RX_START:
847 /* RU start. */
848 if (get_ru_state(s) != ru_idle) {
849 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
850 //~ assert(!"wrong RU state");
852 set_ru_state(s, ru_ready);
853 s->ru_offset = s->pointer;
854 logout("val=0x%02x (rx start)\n", val);
855 break;
856 case RX_RESUME:
857 /* Restart RU. */
858 if (get_ru_state(s) != ru_suspended) {
859 logout("RU state is %u, should be %u\n", get_ru_state(s),
860 ru_suspended);
861 //~ assert(!"wrong RU state");
863 set_ru_state(s, ru_ready);
864 break;
865 case RX_ADDR_LOAD:
866 /* Load RU base. */
867 logout("val=0x%02x (RU base address)\n", val);
868 s->ru_base = s->pointer;
869 break;
870 default:
871 logout("val=0x%02x (undefined RU command)\n", val);
872 missing("Undefined SU command");
876 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
878 eepro100_ru_command(s, val & 0x0f);
879 eepro100_cu_command(s, val & 0xf0);
880 if ((val) == 0) {
881 logout("val=0x%02x\n", val);
883 /* Clear command byte after command was accepted. */
884 s->mem[SCBCmd] = 0;
887 /*****************************************************************************
889 * EEPROM emulation.
891 ****************************************************************************/
893 #define EEPROM_CS 0x02
894 #define EEPROM_SK 0x01
895 #define EEPROM_DI 0x04
896 #define EEPROM_DO 0x08
898 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
900 uint16_t val;
901 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
902 if (eeprom93xx_read(s->eeprom)) {
903 val |= EEPROM_DO;
904 } else {
905 val &= ~EEPROM_DO;
907 return val;
910 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
912 logout("write val=0x%02x\n", val);
914 /* mask unwriteable bits */
915 //~ val = SET_MASKED(val, 0x31, eeprom->value);
917 int eecs = ((val & EEPROM_CS) != 0);
918 int eesk = ((val & EEPROM_SK) != 0);
919 int eedi = ((val & EEPROM_DI) != 0);
920 eeprom93xx_write(eeprom, eecs, eesk, eedi);
923 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
925 s->pointer = le32_to_cpu(val);
926 logout("val=0x%08x\n", val);
929 /*****************************************************************************
931 * MDI emulation.
933 ****************************************************************************/
935 #if defined(DEBUG_EEPRO100)
936 static const char *mdi_op_name[] = {
937 "opcode 0",
938 "write",
939 "read",
940 "opcode 3"
943 static const char *mdi_reg_name[] = {
944 "Control",
945 "Status",
946 "PHY Identification (Word 1)",
947 "PHY Identification (Word 2)",
948 "Auto-Negotiation Advertisement",
949 "Auto-Negotiation Link Partner Ability",
950 "Auto-Negotiation Expansion"
952 #endif /* DEBUG_EEPRO100 */
954 static uint32_t eepro100_read_mdi(EEPRO100State * s)
956 uint32_t val;
957 memcpy(&val, &s->mem[0x10], sizeof(val));
959 #ifdef DEBUG_EEPRO100
960 uint8_t raiseint = (val & BIT(29)) >> 29;
961 uint8_t opcode = (val & BITS(27, 26)) >> 26;
962 uint8_t phy = (val & BITS(25, 21)) >> 21;
963 uint8_t reg = (val & BITS(20, 16)) >> 16;
964 uint16_t data = (val & BITS(15, 0));
965 #endif
966 /* Emulation takes no time to finish MDI transaction. */
967 val |= BIT(28);
968 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
969 val, raiseint, mdi_op_name[opcode], phy,
970 mdi_reg_name[reg], data));
971 return val;
974 //~ #define BITS(val, upper, lower) (val & ???)
975 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
977 uint8_t raiseint = (val & BIT(29)) >> 29;
978 uint8_t opcode = (val & BITS(27, 26)) >> 26;
979 uint8_t phy = (val & BITS(25, 21)) >> 21;
980 uint8_t reg = (val & BITS(20, 16)) >> 16;
981 uint16_t data = (val & BITS(15, 0));
982 if (phy != 1) {
983 /* Unsupported PHY address. */
984 //~ logout("phy must be 1 but is %u\n", phy);
985 data = 0;
986 } else if (opcode != 1 && opcode != 2) {
987 /* Unsupported opcode. */
988 logout("opcode must be 1 or 2 but is %u\n", opcode);
989 data = 0;
990 } else if (reg > 6) {
991 /* Unsupported register. */
992 logout("register must be 0...6 but is %u\n", reg);
993 data = 0;
994 } else {
995 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
996 val, raiseint, mdi_op_name[opcode], phy,
997 mdi_reg_name[reg], data));
998 if (opcode == 1) {
999 /* MDI write */
1000 switch (reg) {
1001 case 0: /* Control Register */
1002 if (data & 0x8000) {
1003 /* Reset status and control registers to default. */
1004 s->mdimem[0] = eepro100_mdi_default[0];
1005 s->mdimem[1] = eepro100_mdi_default[1];
1006 data = s->mdimem[reg];
1007 } else {
1008 /* Restart Auto Configuration = Normal Operation */
1009 data &= ~0x0200;
1011 break;
1012 case 1: /* Status Register */
1013 missing("not writable");
1014 data = s->mdimem[reg];
1015 break;
1016 case 2: /* PHY Identification Register (Word 1) */
1017 case 3: /* PHY Identification Register (Word 2) */
1018 missing("not implemented");
1019 break;
1020 case 4: /* Auto-Negotiation Advertisement Register */
1021 case 5: /* Auto-Negotiation Link Partner Ability Register */
1022 break;
1023 case 6: /* Auto-Negotiation Expansion Register */
1024 default:
1025 missing("not implemented");
1027 s->mdimem[reg] = data;
1028 } else if (opcode == 2) {
1029 /* MDI read */
1030 switch (reg) {
1031 case 0: /* Control Register */
1032 if (data & 0x8000) {
1033 /* Reset status and control registers to default. */
1034 s->mdimem[0] = eepro100_mdi_default[0];
1035 s->mdimem[1] = eepro100_mdi_default[1];
1037 break;
1038 case 1: /* Status Register */
1039 s->mdimem[reg] |= 0x0020;
1040 break;
1041 case 2: /* PHY Identification Register (Word 1) */
1042 case 3: /* PHY Identification Register (Word 2) */
1043 case 4: /* Auto-Negotiation Advertisement Register */
1044 break;
1045 case 5: /* Auto-Negotiation Link Partner Ability Register */
1046 s->mdimem[reg] = 0x41fe;
1047 break;
1048 case 6: /* Auto-Negotiation Expansion Register */
1049 s->mdimem[reg] = 0x0001;
1050 break;
1052 data = s->mdimem[reg];
1054 /* Emulation takes no time to finish MDI transaction.
1055 * Set MDI bit in SCB status register. */
1056 s->mem[SCBAck] |= 0x08;
1057 val |= BIT(28);
1058 if (raiseint) {
1059 eepro100_mdi_interrupt(s);
1062 val = (val & 0xffff0000) + data;
1063 memcpy(&s->mem[0x10], &val, sizeof(val));
1066 /*****************************************************************************
1068 * Port emulation.
1070 ****************************************************************************/
1072 #define PORT_SOFTWARE_RESET 0
1073 #define PORT_SELFTEST 1
1074 #define PORT_SELECTIVE_RESET 2
1075 #define PORT_DUMP 3
1076 #define PORT_SELECTION_MASK 3
1078 typedef struct {
1079 uint32_t st_sign; /* Self Test Signature */
1080 uint32_t st_result; /* Self Test Results */
1081 } eepro100_selftest_t;
1083 static uint32_t eepro100_read_port(EEPRO100State * s)
1085 return 0;
1088 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1090 val = le32_to_cpu(val);
1091 uint32_t address = (val & ~PORT_SELECTION_MASK);
1092 uint8_t selection = (val & PORT_SELECTION_MASK);
1093 switch (selection) {
1094 case PORT_SOFTWARE_RESET:
1095 nic_reset(s);
1096 break;
1097 case PORT_SELFTEST:
1098 logout("selftest address=0x%08x\n", address);
1099 eepro100_selftest_t data;
1100 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1101 data.st_sign = 0xffffffff;
1102 data.st_result = 0;
1103 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1104 break;
1105 case PORT_SELECTIVE_RESET:
1106 logout("selective reset, selftest address=0x%08x\n", address);
1107 nic_selective_reset(s);
1108 break;
1109 default:
1110 logout("val=0x%08x\n", val);
1111 missing("unknown port selection");
1115 /*****************************************************************************
1117 * General hardware emulation.
1119 ****************************************************************************/
1121 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1123 uint8_t val;
1124 if (addr <= sizeof(s->mem) - sizeof(val)) {
1125 memcpy(&val, &s->mem[addr], sizeof(val));
1128 switch (addr) {
1129 case SCBStatus:
1130 //~ val = eepro100_read_status(s);
1131 logout("addr=%s val=0x%02x\n", regname(addr), val);
1132 break;
1133 case SCBAck:
1134 //~ val = eepro100_read_status(s);
1135 logout("addr=%s val=0x%02x\n", regname(addr), val);
1136 break;
1137 case SCBCmd:
1138 logout("addr=%s val=0x%02x\n", regname(addr), val);
1139 //~ val = eepro100_read_command(s);
1140 break;
1141 case SCBIntmask:
1142 logout("addr=%s val=0x%02x\n", regname(addr), val);
1143 break;
1144 case SCBPort + 3:
1145 logout("addr=%s val=0x%02x\n", regname(addr), val);
1146 break;
1147 case SCBeeprom:
1148 val = eepro100_read_eeprom(s);
1149 break;
1150 case 0x1b: /* PMDR (power management driver register) */
1151 val = 0;
1152 logout("addr=%s val=0x%02x\n", regname(addr), val);
1153 break;
1154 case 0x1d: /* general status register */
1155 /* 100 Mbps full duplex, valid link */
1156 val = 0x07;
1157 logout("addr=General Status val=%02x\n", val);
1158 break;
1159 default:
1160 logout("addr=%s val=0x%02x\n", regname(addr), val);
1161 missing("unknown byte read");
1163 return val;
1166 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1168 uint16_t val;
1169 if (addr <= sizeof(s->mem) - sizeof(val)) {
1170 memcpy(&val, &s->mem[addr], sizeof(val));
1173 logout("addr=%s val=0x%04x\n", regname(addr), val);
1175 switch (addr) {
1176 case SCBStatus:
1177 //~ val = eepro100_read_status(s);
1178 break;
1179 case SCBeeprom:
1180 val = eepro100_read_eeprom(s);
1181 break;
1182 default:
1183 logout("addr=%s val=0x%04x\n", regname(addr), val);
1184 missing("unknown word read");
1186 return val;
1189 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1191 uint32_t val;
1192 if (addr <= sizeof(s->mem) - sizeof(val)) {
1193 memcpy(&val, &s->mem[addr], sizeof(val));
1196 switch (addr) {
1197 case SCBStatus:
1198 //~ val = eepro100_read_status(s);
1199 logout("addr=%s val=0x%08x\n", regname(addr), val);
1200 break;
1201 case SCBPointer:
1202 //~ val = eepro100_read_pointer(s);
1203 logout("addr=%s val=0x%08x\n", regname(addr), val);
1204 break;
1205 case SCBPort:
1206 val = eepro100_read_port(s);
1207 logout("addr=%s val=0x%08x\n", regname(addr), val);
1208 break;
1209 case SCBCtrlMDI:
1210 val = eepro100_read_mdi(s);
1211 break;
1212 default:
1213 logout("addr=%s val=0x%08x\n", regname(addr), val);
1214 missing("unknown longword read");
1216 return val;
1219 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1221 if (addr <= sizeof(s->mem) - sizeof(val)) {
1222 memcpy(&s->mem[addr], &val, sizeof(val));
1225 logout("addr=%s val=0x%02x\n", regname(addr), val);
1227 switch (addr) {
1228 case SCBStatus:
1229 //~ eepro100_write_status(s, val);
1230 break;
1231 case SCBAck:
1232 eepro100_acknowledge(s);
1233 break;
1234 case SCBCmd:
1235 eepro100_write_command(s, val);
1236 break;
1237 case SCBIntmask:
1238 if (val & BIT(1)) {
1239 eepro100_swi_interrupt(s);
1241 eepro100_interrupt(s, 0);
1242 break;
1243 case SCBPort + 3:
1244 case SCBFlow:
1245 case SCBFlow + 1:
1246 case SCBFlow + 2:
1247 case SCBFlow + 3:
1248 logout("addr=%s val=0x%02x\n", regname(addr), val);
1249 break;
1250 case SCBeeprom:
1251 eepro100_write_eeprom(s->eeprom, val);
1252 break;
1253 default:
1254 logout("addr=%s val=0x%02x\n", regname(addr), val);
1255 missing("unknown byte write");
1259 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1261 if (addr <= sizeof(s->mem) - sizeof(val)) {
1262 memcpy(&s->mem[addr], &val, sizeof(val));
1265 logout("addr=%s val=0x%04x\n", regname(addr), val);
1267 switch (addr) {
1268 case SCBStatus:
1269 //~ eepro100_write_status(s, val);
1270 eepro100_acknowledge(s);
1271 break;
1272 case SCBCmd:
1273 eepro100_write_command(s, val);
1274 eepro100_write1(s, SCBIntmask, val >> 8);
1275 break;
1276 case SCBeeprom:
1277 eepro100_write_eeprom(s->eeprom, val);
1278 break;
1279 default:
1280 logout("addr=%s val=0x%04x\n", regname(addr), val);
1281 missing("unknown word write");
1285 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1287 if (addr <= sizeof(s->mem) - sizeof(val)) {
1288 memcpy(&s->mem[addr], &val, sizeof(val));
1291 switch (addr) {
1292 case SCBPointer:
1293 eepro100_write_pointer(s, val);
1294 break;
1295 case SCBPort:
1296 logout("addr=%s val=0x%08x\n", regname(addr), val);
1297 eepro100_write_port(s, val);
1298 break;
1299 case SCBCtrlMDI:
1300 eepro100_write_mdi(s, val);
1301 break;
1302 default:
1303 logout("addr=%s val=0x%08x\n", regname(addr), val);
1304 missing("unknown longword write");
1308 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1310 EEPRO100State *s = opaque;
1311 //~ logout("addr=%s\n", regname(addr));
1312 return eepro100_read1(s, addr - s->region[1]);
1315 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1317 EEPRO100State *s = opaque;
1318 return eepro100_read2(s, addr - s->region[1]);
1321 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1323 EEPRO100State *s = opaque;
1324 return eepro100_read4(s, addr - s->region[1]);
1327 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1329 EEPRO100State *s = opaque;
1330 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1331 eepro100_write1(s, addr - s->region[1], val);
1334 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1336 EEPRO100State *s = opaque;
1337 eepro100_write2(s, addr - s->region[1], val);
1340 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1342 EEPRO100State *s = opaque;
1343 eepro100_write4(s, addr - s->region[1], val);
1346 /***********************************************************/
1347 /* PCI EEPRO100 definitions */
1349 typedef struct PCIEEPRO100State {
1350 PCIDevice dev;
1351 EEPRO100State eepro100;
1352 } PCIEEPRO100State;
1354 static void pci_map(PCIDevice * pci_dev, int region_num,
1355 uint32_t addr, uint32_t size, int type)
1357 PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev;
1358 EEPRO100State *s = &d->eepro100;
1360 logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1361 region_num, addr, size, type);
1363 assert(region_num == 1);
1364 register_ioport_write(addr, size, 1, ioport_write1, s);
1365 register_ioport_read(addr, size, 1, ioport_read1, s);
1366 register_ioport_write(addr, size, 2, ioport_write2, s);
1367 register_ioport_read(addr, size, 2, ioport_read2, s);
1368 register_ioport_write(addr, size, 4, ioport_write4, s);
1369 register_ioport_read(addr, size, 4, ioport_read4, s);
1371 s->region[region_num] = addr;
1374 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1376 EEPRO100State *s = opaque;
1377 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1378 eepro100_write1(s, addr, val);
1381 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1383 EEPRO100State *s = opaque;
1384 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1385 eepro100_write2(s, addr, val);
1388 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1390 EEPRO100State *s = opaque;
1391 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1392 eepro100_write4(s, addr, val);
1395 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1397 EEPRO100State *s = opaque;
1398 //~ logout("addr=%s\n", regname(addr));
1399 return eepro100_read1(s, addr);
1402 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1404 EEPRO100State *s = opaque;
1405 //~ logout("addr=%s\n", regname(addr));
1406 return eepro100_read2(s, addr);
1409 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1411 EEPRO100State *s = opaque;
1412 //~ logout("addr=%s\n", regname(addr));
1413 return eepro100_read4(s, addr);
1416 static CPUWriteMemoryFunc *pci_mmio_write[] = {
1417 pci_mmio_writeb,
1418 pci_mmio_writew,
1419 pci_mmio_writel
1422 static CPUReadMemoryFunc *pci_mmio_read[] = {
1423 pci_mmio_readb,
1424 pci_mmio_readw,
1425 pci_mmio_readl
1428 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1429 uint32_t addr, uint32_t size, int type)
1431 PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev;
1433 logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1434 region_num, addr, size, type);
1436 if (region_num == 0) {
1437 /* Map control / status registers. */
1438 cpu_register_physical_memory(addr, size, d->eepro100.mmio_index);
1439 d->eepro100.region[region_num] = addr;
1443 static int nic_can_receive(void *opaque)
1445 EEPRO100State *s = opaque;
1446 logout("%p\n", s);
1447 return get_ru_state(s) == ru_ready;
1448 //~ return !eepro100_buffer_full(s);
1451 static void nic_receive(void *opaque, const uint8_t * buf, int size)
1453 /* TODO:
1454 * - Magic packets should set bit 30 in power management driver register.
1455 * - Interesting packets should set bit 29 in power management driver register.
1457 EEPRO100State *s = opaque;
1458 uint16_t rfd_status = 0xa000;
1459 static const uint8_t broadcast_macaddr[6] =
1460 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1462 /* TODO: check multiple IA bit. */
1463 assert(!(s->configuration[20] & BIT(6)));
1465 if (s->configuration[8] & 0x80) {
1466 /* CSMA is disabled. */
1467 logout("%p received while CSMA is disabled\n", s);
1468 return;
1469 } else if (size < 64 && (s->configuration[7] & 1)) {
1470 /* Short frame and configuration byte 7/0 (discard short receive) set:
1471 * Short frame is discarded */
1472 logout("%p received short frame (%d byte)\n", s, size);
1473 s->statistics.rx_short_frame_errors++;
1474 //~ return;
1475 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1476 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1477 * Long frames are discarded. */
1478 logout("%p received long frame (%d byte), ignored\n", s, size);
1479 return;
1480 } else if (memcmp(buf, s->macaddr, 6) == 0) { // !!!
1481 /* Frame matches individual address. */
1482 /* TODO: check configuration byte 15/4 (ignore U/L). */
1483 logout("%p received frame for me, len=%d\n", s, size);
1484 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1485 /* Broadcast frame. */
1486 logout("%p received broadcast, len=%d\n", s, size);
1487 rfd_status |= 0x0002;
1488 } else if (buf[0] & 0x01) { // !!!
1489 /* Multicast frame. */
1490 logout("%p received multicast, len=%d\n", s, size);
1491 /* TODO: check multicast all bit. */
1492 assert(!(s->configuration[21] & BIT(3)));
1493 int mcast_idx = compute_mcast_idx(buf);
1494 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
1495 return;
1497 rfd_status |= 0x0002;
1498 } else if (s->configuration[15] & 1) {
1499 /* Promiscuous: receive all. */
1500 logout("%p received frame in promiscuous mode, len=%d\n", s, size);
1501 rfd_status |= 0x0004;
1502 } else {
1503 logout("%p received frame, ignored, len=%d,%s\n", s, size,
1504 nic_dump(buf, size));
1505 return;
1508 if (get_ru_state(s) != ru_ready) {
1509 /* No ressources available. */
1510 logout("no ressources, state=%u\n", get_ru_state(s));
1511 s->statistics.rx_resource_errors++;
1512 //~ assert(!"no ressources");
1513 return;
1515 //~ !!!
1516 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1517 eepro100_rx_t rx;
1518 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1519 offsetof(eepro100_rx_t, packet));
1520 uint16_t rfd_command = le16_to_cpu(rx.command);
1521 uint16_t rfd_size = le16_to_cpu(rx.size);
1522 assert(size <= rfd_size);
1523 if (size < 64) {
1524 rfd_status |= 0x0080;
1526 logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command,
1527 rx.link, rx.rx_buf_addr, rfd_size);
1528 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1529 rfd_status);
1530 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1531 /* Early receive interrupt not supported. */
1532 //~ eepro100_er_interrupt(s);
1533 /* Receive CRC Transfer not supported. */
1534 assert(!(s->configuration[18] & 4));
1535 /* TODO: check stripping enable bit. */
1536 //~ assert(!(s->configuration[17] & 1));
1537 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1538 offsetof(eepro100_rx_t, packet), buf, size);
1539 s->statistics.rx_good_frames++;
1540 eepro100_fr_interrupt(s);
1541 s->ru_offset = le32_to_cpu(rx.link);
1542 if (rfd_command & 0x8000) {
1543 /* EL bit is set, so this was the last frame. */
1544 assert(0);
1546 if (rfd_command & 0x4000) {
1547 /* S bit is set. */
1548 set_ru_state(s, ru_suspended);
1552 static int nic_load(QEMUFile * f, void *opaque, int version_id)
1554 EEPRO100State *s = (EEPRO100State *) opaque;
1555 int i;
1556 int ret;
1558 if (version_id > 3)
1559 return -EINVAL;
1561 if (s->pci_dev && version_id >= 3) {
1562 ret = pci_device_load(s->pci_dev, f);
1563 if (ret < 0)
1564 return ret;
1567 if (version_id >= 2) {
1568 qemu_get_8s(f, &s->rxcr);
1569 } else {
1570 s->rxcr = 0x0c;
1573 qemu_get_8s(f, &s->cmd);
1574 qemu_get_be32s(f, &s->start);
1575 qemu_get_be32s(f, &s->stop);
1576 qemu_get_8s(f, &s->boundary);
1577 qemu_get_8s(f, &s->tsr);
1578 qemu_get_8s(f, &s->tpsr);
1579 qemu_get_be16s(f, &s->tcnt);
1580 qemu_get_be16s(f, &s->rcnt);
1581 qemu_get_be32s(f, &s->rsar);
1582 qemu_get_8s(f, &s->rsr);
1583 qemu_get_8s(f, &s->isr);
1584 qemu_get_8s(f, &s->dcfg);
1585 qemu_get_8s(f, &s->imr);
1586 qemu_get_buffer(f, s->phys, 6);
1587 qemu_get_8s(f, &s->curpag);
1588 qemu_get_buffer(f, s->mult, 8);
1589 qemu_get_buffer(f, s->mem, sizeof(s->mem));
1591 /* Restore all members of struct between scv_stat and mem */
1592 qemu_get_8s(f, &s->scb_stat);
1593 qemu_get_8s(f, &s->int_stat);
1594 for (i = 0; i < 3; i++)
1595 qemu_get_be32s(f, &s->region[i]);
1596 qemu_get_buffer(f, s->macaddr, 6);
1597 for (i = 0; i < 19; i++)
1598 qemu_get_be32s(f, &s->statcounter[i]);
1599 for (i = 0; i < 32; i++)
1600 qemu_get_be16s(f, &s->mdimem[i]);
1601 /* The eeprom should be saved and restored by its own routines */
1602 qemu_get_be32s(f, &s->device);
1603 qemu_get_be32s(f, &s->pointer);
1604 qemu_get_be32s(f, &s->cu_base);
1605 qemu_get_be32s(f, &s->cu_offset);
1606 qemu_get_be32s(f, &s->ru_base);
1607 qemu_get_be32s(f, &s->ru_offset);
1608 qemu_get_be32s(f, &s->statsaddr);
1609 /* Restore epro100_stats_t statistics */
1610 qemu_get_be32s(f, &s->statistics.tx_good_frames);
1611 qemu_get_be32s(f, &s->statistics.tx_max_collisions);
1612 qemu_get_be32s(f, &s->statistics.tx_late_collisions);
1613 qemu_get_be32s(f, &s->statistics.tx_underruns);
1614 qemu_get_be32s(f, &s->statistics.tx_lost_crs);
1615 qemu_get_be32s(f, &s->statistics.tx_deferred);
1616 qemu_get_be32s(f, &s->statistics.tx_single_collisions);
1617 qemu_get_be32s(f, &s->statistics.tx_multiple_collisions);
1618 qemu_get_be32s(f, &s->statistics.tx_total_collisions);
1619 qemu_get_be32s(f, &s->statistics.rx_good_frames);
1620 qemu_get_be32s(f, &s->statistics.rx_crc_errors);
1621 qemu_get_be32s(f, &s->statistics.rx_alignment_errors);
1622 qemu_get_be32s(f, &s->statistics.rx_resource_errors);
1623 qemu_get_be32s(f, &s->statistics.rx_overrun_errors);
1624 qemu_get_be32s(f, &s->statistics.rx_cdt_errors);
1625 qemu_get_be32s(f, &s->statistics.rx_short_frame_errors);
1626 qemu_get_be32s(f, &s->statistics.fc_xmt_pause);
1627 qemu_get_be32s(f, &s->statistics.fc_rcv_pause);
1628 qemu_get_be32s(f, &s->statistics.fc_rcv_unsupported);
1629 qemu_get_be16s(f, &s->statistics.xmt_tco_frames);
1630 qemu_get_be16s(f, &s->statistics.rcv_tco_frames);
1631 qemu_get_be32s(f, &s->statistics.complete);
1632 #if 0
1633 qemu_get_be16s(f, &s->status);
1634 #endif
1636 /* Configuration bytes. */
1637 qemu_get_buffer(f, s->configuration, sizeof(s->configuration));
1639 return 0;
1642 static void nic_save(QEMUFile * f, void *opaque)
1644 EEPRO100State *s = (EEPRO100State *) opaque;
1645 int i;
1647 if (s->pci_dev)
1648 pci_device_save(s->pci_dev, f);
1650 qemu_put_8s(f, &s->rxcr);
1652 qemu_put_8s(f, &s->cmd);
1653 qemu_put_be32s(f, &s->start);
1654 qemu_put_be32s(f, &s->stop);
1655 qemu_put_8s(f, &s->boundary);
1656 qemu_put_8s(f, &s->tsr);
1657 qemu_put_8s(f, &s->tpsr);
1658 qemu_put_be16s(f, &s->tcnt);
1659 qemu_put_be16s(f, &s->rcnt);
1660 qemu_put_be32s(f, &s->rsar);
1661 qemu_put_8s(f, &s->rsr);
1662 qemu_put_8s(f, &s->isr);
1663 qemu_put_8s(f, &s->dcfg);
1664 qemu_put_8s(f, &s->imr);
1665 qemu_put_buffer(f, s->phys, 6);
1666 qemu_put_8s(f, &s->curpag);
1667 qemu_put_buffer(f, s->mult, 8);
1668 qemu_put_buffer(f, s->mem, sizeof(s->mem));
1670 /* Save all members of struct between scv_stat and mem */
1671 qemu_put_8s(f, &s->scb_stat);
1672 qemu_put_8s(f, &s->int_stat);
1673 for (i = 0; i < 3; i++)
1674 qemu_put_be32s(f, &s->region[i]);
1675 qemu_put_buffer(f, s->macaddr, 6);
1676 for (i = 0; i < 19; i++)
1677 qemu_put_be32s(f, &s->statcounter[i]);
1678 for (i = 0; i < 32; i++)
1679 qemu_put_be16s(f, &s->mdimem[i]);
1680 /* The eeprom should be saved and restored by its own routines */
1681 qemu_put_be32s(f, &s->device);
1682 qemu_put_be32s(f, &s->pointer);
1683 qemu_put_be32s(f, &s->cu_base);
1684 qemu_put_be32s(f, &s->cu_offset);
1685 qemu_put_be32s(f, &s->ru_base);
1686 qemu_put_be32s(f, &s->ru_offset);
1687 qemu_put_be32s(f, &s->statsaddr);
1688 /* Save epro100_stats_t statistics */
1689 qemu_put_be32s(f, &s->statistics.tx_good_frames);
1690 qemu_put_be32s(f, &s->statistics.tx_max_collisions);
1691 qemu_put_be32s(f, &s->statistics.tx_late_collisions);
1692 qemu_put_be32s(f, &s->statistics.tx_underruns);
1693 qemu_put_be32s(f, &s->statistics.tx_lost_crs);
1694 qemu_put_be32s(f, &s->statistics.tx_deferred);
1695 qemu_put_be32s(f, &s->statistics.tx_single_collisions);
1696 qemu_put_be32s(f, &s->statistics.tx_multiple_collisions);
1697 qemu_put_be32s(f, &s->statistics.tx_total_collisions);
1698 qemu_put_be32s(f, &s->statistics.rx_good_frames);
1699 qemu_put_be32s(f, &s->statistics.rx_crc_errors);
1700 qemu_put_be32s(f, &s->statistics.rx_alignment_errors);
1701 qemu_put_be32s(f, &s->statistics.rx_resource_errors);
1702 qemu_put_be32s(f, &s->statistics.rx_overrun_errors);
1703 qemu_put_be32s(f, &s->statistics.rx_cdt_errors);
1704 qemu_put_be32s(f, &s->statistics.rx_short_frame_errors);
1705 qemu_put_be32s(f, &s->statistics.fc_xmt_pause);
1706 qemu_put_be32s(f, &s->statistics.fc_rcv_pause);
1707 qemu_put_be32s(f, &s->statistics.fc_rcv_unsupported);
1708 qemu_put_be16s(f, &s->statistics.xmt_tco_frames);
1709 qemu_put_be16s(f, &s->statistics.rcv_tco_frames);
1710 qemu_put_be32s(f, &s->statistics.complete);
1711 #if 0
1712 qemu_put_be16s(f, &s->status);
1713 #endif
1715 /* Configuration bytes. */
1716 qemu_put_buffer(f, s->configuration, sizeof(s->configuration));
1719 static PCIDevice *nic_init(PCIBus * bus, NICInfo * nd,
1720 const char *name, uint32_t device)
1722 PCIEEPRO100State *d;
1723 EEPRO100State *s;
1725 logout("\n");
1727 d = (PCIEEPRO100State *) pci_register_device(bus, name,
1728 sizeof(PCIEEPRO100State), -1,
1729 NULL, NULL);
1731 s = &d->eepro100;
1732 s->device = device;
1733 s->pci_dev = &d->dev;
1735 pci_reset(s);
1737 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1738 * i82559 and later support 64 or 256 word EEPROM. */
1739 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1741 /* Handler for memory-mapped I/O */
1742 d->eepro100.mmio_index =
1743 cpu_register_io_memory(0, pci_mmio_read, pci_mmio_write, s);
1745 pci_register_io_region(&d->dev, 0, PCI_MEM_SIZE,
1746 PCI_ADDRESS_SPACE_MEM |
1747 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map);
1748 pci_register_io_region(&d->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO,
1749 pci_map);
1750 pci_register_io_region(&d->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,
1751 pci_mmio_map);
1753 memcpy(s->macaddr, nd->macaddr, 6);
1754 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
1755 assert(s->region[1] == 0);
1757 nic_reset(s);
1759 s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
1760 nic_receive, nic_can_receive, s);
1762 qemu_format_nic_info_str(s->vc, s->macaddr);
1764 qemu_register_reset(nic_reset, s);
1766 register_savevm(name, -1, 3, nic_save, nic_load, s);
1767 return (PCIDevice *)d;
1770 PCIDevice *pci_i82551_init(PCIBus * bus, NICInfo * nd, int devfn)
1772 return nic_init(bus, nd, "i82551", i82551);
1773 //~ uint8_t *pci_conf = d->dev.config;
1776 PCIDevice *pci_i82557b_init(PCIBus * bus, NICInfo * nd, int devfn)
1778 return nic_init(bus, nd, "i82557b", i82557B);
1781 PCIDevice *pci_i82559er_init(PCIBus * bus, NICInfo * nd, int devfn)
1783 return nic_init(bus, nd, "i82559er", i82559ER);
1786 /* eof */