hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 /* PCI includes legacy ISA access.  */
   5 #include "isa.h"
   6
   7 /* PCI bus */
   8
   9 extern target_phys_addr_t pci_mem_base;
  10
  11 /* Device classes and subclasses */
  12
  13 #define PCI_CLASS_STORAGE_SCSI           0x0100
  14 #define PCI_CLASS_STORAGE_IDE            0x0101
  15 #define PCI_CLASS_STORAGE_OTHER          0x0180
  16
  17 #define PCI_CLASS_NETWORK_ETHERNET       0x0200
  18
  19 #define PCI_CLASS_DISPLAY_VGA            0x0300
  20 #define PCI_CLASS_DISPLAY_OTHER          0x0380
  21
  22 #define PCI_CLASS_MULTIMEDIA_AUDIO       0x0401
  23
  24 #define PCI_CLASS_MEMORY_RAM             0x0500
  25
  26 #define PCI_CLASS_SYSTEM_OTHER           0x0880
  27
  28 #define PCI_CLASS_SERIAL_USB             0x0c03
  29
  30 #define PCI_CLASS_BRIDGE_HOST            0x0600
  31 #define PCI_CLASS_BRIDGE_ISA             0x0601
  32 #define PCI_CLASS_BRIDGE_PCI             0x0604
  33 #define PCI_CLASS_BRIDGE_OTHER           0x0680
  34
  35 #define PCI_CLASS_PROCESSOR_CO           0x0b40
  36
  37 #define PCI_CLASS_OTHERS                 0xff
  38
  39 /* Vendors and devices. */
  40
  41 #define PCI_VENDOR_ID_LSI_LOGIC          0x1000
  42 #define PCI_DEVICE_ID_LSI_53C895A        0x0012
  43
  44 #define PCI_VENDOR_ID_DEC                0x1011
  45 #define PCI_DEVICE_ID_DEC_21154          0x0026
  46
  47 #define PCI_VENDOR_ID_CIRRUS             0x1013
  48
  49 #define PCI_VENDOR_ID_IBM                0x1014
  50 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  51
  52 #define PCI_VENDOR_ID_AMD                0x1022
  53 #define PCI_DEVICE_ID_AMD_LANCE          0x2000
  54
  55 #define PCI_VENDOR_ID_HITACHI            0x1054
  56
  57 #define PCI_VENDOR_ID_MOTOROLA           0x1057
  58 #define PCI_DEVICE_ID_MOTOROLA_MPC106    0x0002
  59 #define PCI_DEVICE_ID_MOTOROLA_RAVEN     0x4801
  60
  61 #define PCI_VENDOR_ID_APPLE              0x106b
  62 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  63 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  64 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  65 #define PCI_DEVICE_ID_APPLE_UNI_N_AGP    0x0020
  66 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  67
  68 #define PCI_VENDOR_ID_SUN                0x108e
  69 #define PCI_DEVICE_ID_SUN_EBUS           0x1000
  70 #define PCI_DEVICE_ID_SUN_SIMBA          0x5000
  71 #define PCI_DEVICE_ID_SUN_SABRE          0xa000
  72
  73 #define PCI_VENDOR_ID_CMD                0x1095
  74 #define PCI_DEVICE_ID_CMD_646            0x0646
  75
  76 #define PCI_VENDOR_ID_REALTEK            0x10ec
  77 #define PCI_DEVICE_ID_REALTEK_RTL8029    0x8029
  78 #define PCI_DEVICE_ID_REALTEK_8139       0x8139
  79
  80 #define PCI_VENDOR_ID_XILINX             0x10ee
  81
  82 #define PCI_VENDOR_ID_MARVELL            0x11ab
  83
  84 #define PCI_VENDOR_ID_QEMU               0x1234
  85 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  86
  87 #define PCI_VENDOR_ID_ENSONIQ            0x1274
  88 #define PCI_DEVICE_ID_ENSONIQ_ES1370     0x5000
  89
  90 #define PCI_VENDOR_ID_VMWARE             0x15ad
  91 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  92 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  93 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  94 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  95 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  96
  97 #define PCI_VENDOR_ID_INTEL              0x8086
  98 #define PCI_DEVICE_ID_INTEL_82441        0x1237
  99 #define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
 100 #define PCI_DEVICE_ID_INTEL_82371SB_0    0x7000
 101 #define PCI_DEVICE_ID_INTEL_82371SB_1    0x7010
 102 #define PCI_DEVICE_ID_INTEL_82371SB_2    0x7020
 103 #define PCI_DEVICE_ID_INTEL_82371AB_0    0x7110
 104 #define PCI_DEVICE_ID_INTEL_82371AB      0x7111
 105 #define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
 106 #define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113
 107
 108 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
 109 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
 110 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
 111 #define PCI_SUBDEVICE_ID_QEMU            0x1100
 112
 113 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
 114 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
 115 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
 116 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
 117
 118 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 119                                 uint32_t address, uint32_t data, int len);
 120 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 121                                    uint32_t address, int len);
 122 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 123                                 uint32_t addr, uint32_t size, int type);
 124
 125 #define PCI_ADDRESS_SPACE_MEM           0x00
 126 #define PCI_ADDRESS_SPACE_IO            0x01
 127 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
 128
 129 typedef struct PCIIORegion {
 130     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
 131     uint32_t size;
 132     uint8_t type;
 133     PCIMapIORegionFunc *map_func;
 134 } PCIIORegion;
 135
 136 #define PCI_ROM_SLOT 6
 137 #define PCI_NUM_REGIONS 7
 138
 139 #define PCI_DEVICES_MAX 64
 140
 141 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 142 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 143 #define PCI_COMMAND             0x04    /* 16 bits */
 144 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 145 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 146 #define PCI_REVISION            0x08
 147 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 148 #define PCI_SUBVENDOR_ID        0x2c    /* 16 bits */
 149 #define PCI_SUBDEVICE_ID        0x2e    /* 16 bits */
 150 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 151 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 152 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 153 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 154
 155 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 156 #define PCI_STATUS_RESERVED1    0x007
 157 #define PCI_STATUS_INT_STATUS   0x008
 158 #define PCI_STATUS_CAPABILITIES 0x010
 159 #define PCI_STATUS_66MHZ        0x020
 160 #define PCI_STATUS_RESERVED2    0x040
 161 #define PCI_STATUS_FAST_BACK    0x080
 162 #define PCI_STATUS_DEVSEL       0x600
 163
 164 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 165                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 166                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 167
 168 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 169
 170 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 171 #define PCI_COMMAND_RESERVED    0xf800
 172
 173 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 174
 175 struct PCIDevice {
 176     /* PCI config space */
 177     uint8_t config[256];
 178
 179     /* the following fields are read only */
 180     PCIBus *bus;
 181     int devfn;
 182     char name[64];
 183     PCIIORegion io_regions[PCI_NUM_REGIONS];
 184
 185     /* do not access the following fields */
 186     PCIConfigReadFunc *config_read;
 187     PCIConfigWriteFunc *config_write;
 188     /* ??? This is a PC-specific hack, and should be removed.  */
 189     int irq_index;
 190
 191     /* IRQ objects for the INTA-INTD pins.  */
 192     qemu_irq *irq;
 193
 194     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 195     int irq_state[4];
 196 };
 197
 198 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 199                                int instance_size, int devfn,
 200                                PCIConfigReadFunc *config_read,
 201                                PCIConfigWriteFunc *config_write);
 202
 203 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 204                             uint32_t size, int type,
 205                             PCIMapIORegionFunc *map_func);
 206
 207 uint32_t pci_default_read_config(PCIDevice *d,
 208                                  uint32_t address, int len);
 209 void pci_default_write_config(PCIDevice *d,
 210                               uint32_t address, uint32_t val, int len);
 211 void pci_device_save(PCIDevice *s, QEMUFile *f);
 212 int pci_device_load(PCIDevice *s, QEMUFile *f);
 213
 214 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 215 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 216 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 217                          qemu_irq *pic, int devfn_min, int nirq);
 218
 219 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 220                   const char *default_model);
 221 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 222 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 223 int pci_bus_num(PCIBus *s);
 224 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 225
 226 void pci_info(void);
 227 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 228                         pci_map_irq_fn map_irq, const char *name);
 229
 230 static inline void
 231 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 232 {
 233     cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
 234 }
 235
 236 static inline void
 237 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 238 {
 239     cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
 240 }
 241
 242 static inline void
 243 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 244 {
 245     cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
 246 }
 247
 248 /* lsi53c895a.c */
 249 #define LSI_MAX_DEVS 7
 250 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
 251 void *lsi_scsi_init(PCIBus *bus, int devfn);
 252
 253 /* vmware_vga.c */
 254 void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
 255                      unsigned long vga_ram_offset, int vga_ram_size);
 256
 257 /* usb-uhci.c */
 258 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 259 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 260
 261 /* usb-ohci.c */
 262 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 263
 264 /* eepro100.c */
 265
 266 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
 267 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
 268 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
 269
 270 /* ne2000.c */
 271
 272 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
 273
 274 /* rtl8139.c */
 275
 276 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
 277
 278 /* e1000.c */
 279 void pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);
 280
 281 /* pcnet.c */
 282 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
 283
 284 /* prep_pci.c */
 285 PCIBus *pci_prep_init(qemu_irq *pic);
 286
 287 /* apb_pci.c */
 288 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 289                      target_phys_addr_t mem_base,
 290                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
 291
 292 /* sh_pci.c */
 293 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 294                             qemu_irq *pic, int devfn_min, int nirq);
 295
 296 #endif