hw/unin_pci.c

   1 /*
   2  * QEMU Uninorth PCI host (for all Mac99 and newer machines)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc_mac.h"
  26 #include "pci.h"
  27
  28 /* debug UniNorth */
  29 //#define DEBUG_UNIN
  30
  31 #ifdef DEBUG_UNIN
  32 #define UNIN_DPRINTF(fmt, args...) \
  33 do { printf("UNIN: " fmt , ##args); } while (0)
  34 #else
  35 #define UNIN_DPRINTF(fmt, args...)
  36 #endif
  37
  38 typedef target_phys_addr_t pci_addr_t;
  39 #include "pci_host.h"
  40
  41 typedef PCIHostState UNINState;
  42
  43 static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
  44                                          uint32_t val)
  45 {
  46     UNINState *s = opaque;
  47     int i;
  48
  49     UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
  50 #ifdef TARGET_WORDS_BIGENDIAN
  51     val = bswap32(val);
  52 #endif
  53
  54     for (i = 11; i < 32; i++) {
  55         if ((val & (1 << i)) != 0)
  56             break;
  57     }
  58 #if 0
  59     s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
  60 #else
  61     s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
  62 #endif
  63 }
  64
  65 static uint32_t pci_unin_main_config_readl (void *opaque,
  66                                             target_phys_addr_t addr)
  67 {
  68     UNINState *s = opaque;
  69     uint32_t val;
  70     int devfn;
  71
  72     devfn = (s->config_reg >> 8) & 0xFF;
  73     val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
  74 #ifdef TARGET_WORDS_BIGENDIAN
  75     val = bswap32(val);
  76 #endif
  77     UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);
  78
  79     return val;
  80 }
  81
  82 static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
  83     &pci_unin_main_config_writel,
  84     &pci_unin_main_config_writel,
  85     &pci_unin_main_config_writel,
  86 };
  87
  88 static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
  89     &pci_unin_main_config_readl,
  90     &pci_unin_main_config_readl,
  91     &pci_unin_main_config_readl,
  92 };
  93
  94 static CPUWriteMemoryFunc *pci_unin_main_write[] = {
  95     &pci_host_data_writeb,
  96     &pci_host_data_writew,
  97     &pci_host_data_writel,
  98 };
  99
 100 static CPUReadMemoryFunc *pci_unin_main_read[] = {
 101     &pci_host_data_readb,
 102     &pci_host_data_readw,
 103     &pci_host_data_readl,
 104 };
 105
 106 #if 0
 107
 108 static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
 109                                     uint32_t val)
 110 {
 111     UNINState *s = opaque;
 112
 113 #ifdef TARGET_WORDS_BIGENDIAN
 114     val = bswap32(val);
 115 #endif
 116     s->config_reg = 0x80000000 | (val & ~0x00000001);
 117 }
 118
 119 static uint32_t pci_unin_config_readl (void *opaque,
 120                                        target_phys_addr_t addr)
 121 {
 122     UNINState *s = opaque;
 123     uint32_t val;
 124
 125     val = (s->config_reg | 0x00000001) & ~0x80000000;
 126 #ifdef TARGET_WORDS_BIGENDIAN
 127     val = bswap32(val);
 128 #endif
 129
 130     return val;
 131 }
 132
 133 static CPUWriteMemoryFunc *pci_unin_config_write[] = {
 134     &pci_unin_config_writel,
 135     &pci_unin_config_writel,
 136     &pci_unin_config_writel,
 137 };
 138
 139 static CPUReadMemoryFunc *pci_unin_config_read[] = {
 140     &pci_unin_config_readl,
 141     &pci_unin_config_readl,
 142     &pci_unin_config_readl,
 143 };
 144
 145 static CPUWriteMemoryFunc *pci_unin_write[] = {
 146     &pci_host_pci_writeb,
 147     &pci_host_pci_writew,
 148     &pci_host_pci_writel,
 149 };
 150
 151 static CPUReadMemoryFunc *pci_unin_read[] = {
 152     &pci_host_pci_readb,
 153     &pci_host_pci_readw,
 154     &pci_host_pci_readl,
 155 };
 156 #endif
 157
 158 /* Don't know if this matches real hardware, but it agrees with OHW.  */
 159 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
 160 {
 161     return (irq_num + (pci_dev->devfn >> 3)) & 3;
 162 }
 163
 164 static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level)
 165 {
 166     qemu_set_irq(pic[irq_num + 8], level);
 167 }
 168
 169 static void pci_unin_save(QEMUFile* f, void *opaque)
 170 {
 171     PCIDevice *d = opaque;
 172
 173     pci_device_save(d, f);
 174 }
 175
 176 static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
 177 {
 178     PCIDevice *d = opaque;
 179
 180     if (version_id != 1)
 181         return -EINVAL;
 182
 183     return pci_device_load(d, f);
 184 }
 185
 186 static void pci_unin_reset(void *opaque)
 187 {
 188 }
 189
 190 PCIBus *pci_pmac_init(qemu_irq *pic)
 191 {
 192     UNINState *s;
 193     PCIDevice *d;
 194     int pci_mem_config, pci_mem_data;
 195
 196     /* Use values found on a real PowerMac */
 197     /* Uninorth main bus */
 198     s = qemu_mallocz(sizeof(UNINState));
 199     s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq,
 200                               pic, 11 << 3, 4);
 201
 202     pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
 203                                             pci_unin_main_config_write, s);
 204     pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
 205                                           pci_unin_main_write, s);
 206     cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
 207     cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
 208     d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
 209                             11 << 3, NULL, NULL);
 210     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 211     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
 212     d->config[0x08] = 0x00; // revision
 213     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 214     d->config[0x0C] = 0x08; // cache_line_size
 215     d->config[0x0D] = 0x10; // latency_timer
 216     d->config[0x0E] = 0x00; // header_type
 217     d->config[0x34] = 0x00; // capabilities_pointer
 218
 219 #if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
 220     /* pci-to-pci bridge */
 221     d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
 222                             NULL, NULL);
 223     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
 224     pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
 225     d->config[0x08] = 0x05; // revision
 226     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
 227     d->config[0x0C] = 0x08; // cache_line_size
 228     d->config[0x0D] = 0x20; // latency_timer
 229     d->config[0x0E] = 0x01; // header_type
 230
 231     d->config[0x18] = 0x01; // primary_bus
 232     d->config[0x19] = 0x02; // secondary_bus
 233     d->config[0x1A] = 0x02; // subordinate_bus
 234     d->config[0x1B] = 0x20; // secondary_latency_timer
 235     d->config[0x1C] = 0x11; // io_base
 236     d->config[0x1D] = 0x01; // io_limit
 237     d->config[0x20] = 0x00; // memory_base
 238     d->config[0x21] = 0x80;
 239     d->config[0x22] = 0x00; // memory_limit
 240     d->config[0x23] = 0x80;
 241     d->config[0x24] = 0x01; // prefetchable_memory_base
 242     d->config[0x25] = 0x80;
 243     d->config[0x26] = 0xF1; // prefectchable_memory_limit
 244     d->config[0x27] = 0x7F;
 245     // d->config[0x34] = 0xdc // capabilities_pointer
 246 #endif
 247 #if 0 // XXX: not needed for now
 248     /* Uninorth AGP bus */
 249     s = &pci_bridge[1];
 250     pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
 251                                             pci_unin_config_write, s);
 252     pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
 253                                           pci_unin_write, s);
 254     cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
 255     cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
 256
 257     d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
 258                             NULL, NULL);
 259     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 260     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
 261     d->config[0x08] = 0x00; // revision
 262     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 263     d->config[0x0C] = 0x08; // cache_line_size
 264     d->config[0x0D] = 0x10; // latency_timer
 265     d->config[0x0E] = 0x00; // header_type
 266     //    d->config[0x34] = 0x80; // capabilities_pointer
 267 #endif
 268
 269 #if 0 // XXX: not needed for now
 270     /* Uninorth internal bus */
 271     s = &pci_bridge[2];
 272     pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
 273                                             pci_unin_config_write, s);
 274     pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
 275                                           pci_unin_write, s);
 276     cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
 277     cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
 278
 279     d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
 280                             3, 11 << 3, NULL, NULL);
 281     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
 282     pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
 283     d->config[0x08] = 0x00; // revision
 284     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 285     d->config[0x0C] = 0x08; // cache_line_size
 286     d->config[0x0D] = 0x10; // latency_timer
 287     d->config[0x0E] = 0x00; // header_type
 288     d->config[0x34] = 0x00; // capabilities_pointer
 289 #endif
 290     register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
 291     qemu_register_reset(pci_unin_reset, d);
 292     pci_unin_reset(d);
 293
 294     return s->bus;
 295 }