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nand: boot code cleanup
[qemu/mini2440.git] / target-i386 / translate.c
blobd45e9fe73089e56961e02ff487cbcea98435b97f
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31
32 #include "helper.h"
33 #define GEN_HELPER 1
34 #include "helper.h"
35
36 #define PREFIX_REPZ 0x01
37 #define PREFIX_REPNZ 0x02
38 #define PREFIX_LOCK 0x04
39 #define PREFIX_DATA 0x08
40 #define PREFIX_ADR 0x10
41
42 #ifdef TARGET_X86_64
43 #define X86_64_ONLY(x) x
44 #define X86_64_DEF(...) __VA_ARGS__
45 #define CODE64(s) ((s)->code64)
46 #define REX_X(s) ((s)->rex_x)
47 #define REX_B(s) ((s)->rex_b)
48 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
49 #if 1
50 #define BUGGY_64(x) NULL
51 #endif
52 #else
53 #define X86_64_ONLY(x) NULL
54 #define X86_64_DEF(...)
55 #define CODE64(s) 0
56 #define REX_X(s) 0
57 #define REX_B(s) 0
58 #endif
59
60 //#define MACRO_TEST 1
61
62 /* global register indexes */
63 static TCGv_ptr cpu_env;
64 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
65 static TCGv_i32 cpu_cc_op;
66 /* local temps */
67 static TCGv cpu_T[2], cpu_T3;
68 /* local register indexes (only used inside old micro ops) */
69 static TCGv cpu_tmp0, cpu_tmp4;
70 static TCGv_ptr cpu_ptr0, cpu_ptr1;
71 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
72 static TCGv_i64 cpu_tmp1_i64;
73 static TCGv cpu_tmp5, cpu_tmp6;
74
75 #include "gen-icount.h"
76
77 #ifdef TARGET_X86_64
78 static int x86_64_hregs;
79 #endif
80
81 typedef struct DisasContext {
82 /* current insn context */
83 int override; /* -1 if no override */
84 int prefix;
85 int aflag, dflag;
86 target_ulong pc; /* pc = eip + cs_base */
87 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
88 static state change (stop translation) */
89 /* current block context */
90 target_ulong cs_base; /* base of CS segment */
91 int pe; /* protected mode */
92 int code32; /* 32 bit code segment */
93 #ifdef TARGET_X86_64
94 int lma; /* long mode active */
95 int code64; /* 64 bit code segment */
96 int rex_x, rex_b;
97 #endif
98 int ss32; /* 32 bit stack segment */
99 int cc_op; /* current CC operation */
100 int addseg; /* non zero if either DS/ES/SS have a non zero base */
101 int f_st; /* currently unused */
102 int vm86; /* vm86 mode */
103 int cpl;
104 int iopl;
105 int tf; /* TF cpu flag */
106 int singlestep_enabled; /* "hardware" single step enabled */
107 int jmp_opt; /* use direct block chaining for direct jumps */
108 int mem_index; /* select memory access functions */
109 uint64_t flags; /* all execution flags */
110 struct TranslationBlock *tb;
111 int popl_esp_hack; /* for correct popl with esp base handling */
112 int rip_offset; /* only used in x86_64, but left for simplicity */
113 int cpuid_features;
114 int cpuid_ext_features;
115 int cpuid_ext2_features;
116 int cpuid_ext3_features;
117 } DisasContext;
118
119 static void gen_eob(DisasContext *s);
120 static void gen_jmp(DisasContext *s, target_ulong eip);
121 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
122
123 /* i386 arith/logic operations */
124 enum {
125 OP_ADDL,
126 OP_ORL,
127 OP_ADCL,
128 OP_SBBL,
129 OP_ANDL,
130 OP_SUBL,
131 OP_XORL,
132 OP_CMPL,
133 };
134
135 /* i386 shift ops */
136 enum {
137 OP_ROL,
138 OP_ROR,
139 OP_RCL,
140 OP_RCR,
141 OP_SHL,
142 OP_SHR,
143 OP_SHL1, /* undocumented */
144 OP_SAR = 7,
145 };
146
147 enum {
148 JCC_O,
149 JCC_B,
150 JCC_Z,
151 JCC_BE,
152 JCC_S,
153 JCC_P,
154 JCC_L,
155 JCC_LE,
156 };
157
158 /* operand size */
159 enum {
160 OT_BYTE = 0,
161 OT_WORD,
162 OT_LONG,
163 OT_QUAD,
164 };
165
166 enum {
167 /* I386 int registers */
168 OR_EAX, /* MUST be even numbered */
169 OR_ECX,
170 OR_EDX,
171 OR_EBX,
172 OR_ESP,
173 OR_EBP,
174 OR_ESI,
175 OR_EDI,
176
177 OR_TMP0 = 16, /* temporary operand register */
178 OR_TMP1,
179 OR_A0, /* temporary register used when doing address evaluation */
180 };
181
182 static inline void gen_op_movl_T0_0(void)
183 {
184 tcg_gen_movi_tl(cpu_T[0], 0);
185 }
186
187 static inline void gen_op_movl_T0_im(int32_t val)
188 {
189 tcg_gen_movi_tl(cpu_T[0], val);
190 }
191
192 static inline void gen_op_movl_T0_imu(uint32_t val)
193 {
194 tcg_gen_movi_tl(cpu_T[0], val);
195 }
196
197 static inline void gen_op_movl_T1_im(int32_t val)
198 {
199 tcg_gen_movi_tl(cpu_T[1], val);
200 }
201
202 static inline void gen_op_movl_T1_imu(uint32_t val)
203 {
204 tcg_gen_movi_tl(cpu_T[1], val);
205 }
206
207 static inline void gen_op_movl_A0_im(uint32_t val)
208 {
209 tcg_gen_movi_tl(cpu_A0, val);
210 }
211
212 #ifdef TARGET_X86_64
213 static inline void gen_op_movq_A0_im(int64_t val)
214 {
215 tcg_gen_movi_tl(cpu_A0, val);
216 }
217 #endif
218
219 static inline void gen_movtl_T0_im(target_ulong val)
220 {
221 tcg_gen_movi_tl(cpu_T[0], val);
222 }
223
224 static inline void gen_movtl_T1_im(target_ulong val)
225 {
226 tcg_gen_movi_tl(cpu_T[1], val);
227 }
228
229 static inline void gen_op_andl_T0_ffff(void)
230 {
231 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
232 }
233
234 static inline void gen_op_andl_T0_im(uint32_t val)
235 {
236 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
237 }
238
239 static inline void gen_op_movl_T0_T1(void)
240 {
241 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
242 }
243
244 static inline void gen_op_andl_A0_ffff(void)
245 {
246 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
247 }
248
249 #ifdef TARGET_X86_64
250
251 #define NB_OP_SIZES 4
252
253 #else /* !TARGET_X86_64 */
254
255 #define NB_OP_SIZES 3
256
257 #endif /* !TARGET_X86_64 */
258
259 #if defined(WORDS_BIGENDIAN)
260 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
261 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
262 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
263 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
264 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
265 #else
266 #define REG_B_OFFSET 0
267 #define REG_H_OFFSET 1
268 #define REG_W_OFFSET 0
269 #define REG_L_OFFSET 0
270 #define REG_LH_OFFSET 4
271 #endif
272
273 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
274 {
275 switch(ot) {
276 case OT_BYTE:
277 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
278 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
279 } else {
280 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
281 }
282 break;
283 case OT_WORD:
284 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
285 break;
286 #ifdef TARGET_X86_64
287 case OT_LONG:
288 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
289 /* high part of register set to zero */
290 tcg_gen_movi_tl(cpu_tmp0, 0);
291 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
292 break;
293 default:
294 case OT_QUAD:
295 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
296 break;
297 #else
298 default:
299 case OT_LONG:
300 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
301 break;
302 #endif
303 }
304 }
305
306 static inline void gen_op_mov_reg_T0(int ot, int reg)
307 {
308 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
309 }
310
311 static inline void gen_op_mov_reg_T1(int ot, int reg)
312 {
313 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
314 }
315
316 static inline void gen_op_mov_reg_A0(int size, int reg)
317 {
318 switch(size) {
319 case 0:
320 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
321 break;
322 #ifdef TARGET_X86_64
323 case 1:
324 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
325 /* high part of register set to zero */
326 tcg_gen_movi_tl(cpu_tmp0, 0);
327 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
328 break;
329 default:
330 case 2:
331 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
332 break;
333 #else
334 default:
335 case 1:
336 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
337 break;
338 #endif
339 }
340 }
341
342 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
343 {
344 switch(ot) {
345 case OT_BYTE:
346 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
347 goto std_case;
348 } else {
349 tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
350 }
351 break;
352 default:
353 std_case:
354 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
355 break;
356 }
357 }
358
359 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
360 {
361 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
362 }
363
364 static inline void gen_op_movl_A0_reg(int reg)
365 {
366 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
367 }
368
369 static inline void gen_op_addl_A0_im(int32_t val)
370 {
371 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
372 #ifdef TARGET_X86_64
373 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
374 #endif
375 }
376
377 #ifdef TARGET_X86_64
378 static inline void gen_op_addq_A0_im(int64_t val)
379 {
380 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
381 }
382 #endif
383
384 static void gen_add_A0_im(DisasContext *s, int val)
385 {
386 #ifdef TARGET_X86_64
387 if (CODE64(s))
388 gen_op_addq_A0_im(val);
389 else
390 #endif
391 gen_op_addl_A0_im(val);
392 }
393
394 static inline void gen_op_addl_T0_T1(void)
395 {
396 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
397 }
398
399 static inline void gen_op_jmp_T0(void)
400 {
401 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
402 }
403
404 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
405 {
406 switch(size) {
407 case 0:
408 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
409 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
410 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
411 break;
412 case 1:
413 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
414 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
415 #ifdef TARGET_X86_64
416 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
417 #endif
418 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
419 break;
420 #ifdef TARGET_X86_64
421 case 2:
422 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
423 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
424 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
425 break;
426 #endif
427 }
428 }
429
430 static inline void gen_op_add_reg_T0(int size, int reg)
431 {
432 switch(size) {
433 case 0:
434 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
435 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
436 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
437 break;
438 case 1:
439 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
440 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
441 #ifdef TARGET_X86_64
442 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
443 #endif
444 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
445 break;
446 #ifdef TARGET_X86_64
447 case 2:
448 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
449 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
450 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
451 break;
452 #endif
453 }
454 }
455
456 static inline void gen_op_set_cc_op(int32_t val)
457 {
458 tcg_gen_movi_i32(cpu_cc_op, val);
459 }
460
461 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
462 {
463 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
464 if (shift != 0)
465 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
466 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
467 #ifdef TARGET_X86_64
468 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
469 #endif
470 }
471
472 static inline void gen_op_movl_A0_seg(int reg)
473 {
474 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
475 }
476
477 static inline void gen_op_addl_A0_seg(int reg)
478 {
479 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
480 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
481 #ifdef TARGET_X86_64
482 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
483 #endif
484 }
485
486 #ifdef TARGET_X86_64
487 static inline void gen_op_movq_A0_seg(int reg)
488 {
489 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
490 }
491
492 static inline void gen_op_addq_A0_seg(int reg)
493 {
494 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
495 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
496 }
497
498 static inline void gen_op_movq_A0_reg(int reg)
499 {
500 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
501 }
502
503 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
504 {
505 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
506 if (shift != 0)
507 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
508 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
509 }
510 #endif
511
512 static inline void gen_op_lds_T0_A0(int idx)
513 {
514 int mem_index = (idx >> 2) - 1;
515 switch(idx & 3) {
516 case 0:
517 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
518 break;
519 case 1:
520 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
521 break;
522 default:
523 case 2:
524 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
525 break;
526 }
527 }
528
529 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
530 {
531 int mem_index = (idx >> 2) - 1;
532 switch(idx & 3) {
533 case 0:
534 tcg_gen_qemu_ld8u(t0, a0, mem_index);
535 break;
536 case 1:
537 tcg_gen_qemu_ld16u(t0, a0, mem_index);
538 break;
539 case 2:
540 tcg_gen_qemu_ld32u(t0, a0, mem_index);
541 break;
542 default:
543 case 3:
544 /* Should never happen on 32-bit targets. */
545 #ifdef TARGET_X86_64
546 tcg_gen_qemu_ld64(t0, a0, mem_index);
547 #endif
548 break;
549 }
550 }
551
552 /* XXX: always use ldu or lds */
553 static inline void gen_op_ld_T0_A0(int idx)
554 {
555 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
556 }
557
558 static inline void gen_op_ldu_T0_A0(int idx)
559 {
560 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
561 }
562
563 static inline void gen_op_ld_T1_A0(int idx)
564 {
565 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
566 }
567
568 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
569 {
570 int mem_index = (idx >> 2) - 1;
571 switch(idx & 3) {
572 case 0:
573 tcg_gen_qemu_st8(t0, a0, mem_index);
574 break;
575 case 1:
576 tcg_gen_qemu_st16(t0, a0, mem_index);
577 break;
578 case 2:
579 tcg_gen_qemu_st32(t0, a0, mem_index);
580 break;
581 default:
582 case 3:
583 /* Should never happen on 32-bit targets. */
584 #ifdef TARGET_X86_64
585 tcg_gen_qemu_st64(t0, a0, mem_index);
586 #endif
587 break;
588 }
589 }
590
591 static inline void gen_op_st_T0_A0(int idx)
592 {
593 gen_op_st_v(idx, cpu_T[0], cpu_A0);
594 }
595
596 static inline void gen_op_st_T1_A0(int idx)
597 {
598 gen_op_st_v(idx, cpu_T[1], cpu_A0);
599 }
600
601 static inline void gen_jmp_im(target_ulong pc)
602 {
603 tcg_gen_movi_tl(cpu_tmp0, pc);
604 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
605 }
606
607 static inline void gen_string_movl_A0_ESI(DisasContext *s)
608 {
609 int override;
610
611 override = s->override;
612 #ifdef TARGET_X86_64
613 if (s->aflag == 2) {
614 if (override >= 0) {
615 gen_op_movq_A0_seg(override);
616 gen_op_addq_A0_reg_sN(0, R_ESI);
617 } else {
618 gen_op_movq_A0_reg(R_ESI);
619 }
620 } else
621 #endif
622 if (s->aflag) {
623 /* 32 bit address */
624 if (s->addseg && override < 0)
625 override = R_DS;
626 if (override >= 0) {
627 gen_op_movl_A0_seg(override);
628 gen_op_addl_A0_reg_sN(0, R_ESI);
629 } else {
630 gen_op_movl_A0_reg(R_ESI);
631 }
632 } else {
633 /* 16 address, always override */
634 if (override < 0)
635 override = R_DS;
636 gen_op_movl_A0_reg(R_ESI);
637 gen_op_andl_A0_ffff();
638 gen_op_addl_A0_seg(override);
639 }
640 }
641
642 static inline void gen_string_movl_A0_EDI(DisasContext *s)
643 {
644 #ifdef TARGET_X86_64
645 if (s->aflag == 2) {
646 gen_op_movq_A0_reg(R_EDI);
647 } else
648 #endif
649 if (s->aflag) {
650 if (s->addseg) {
651 gen_op_movl_A0_seg(R_ES);
652 gen_op_addl_A0_reg_sN(0, R_EDI);
653 } else {
654 gen_op_movl_A0_reg(R_EDI);
655 }
656 } else {
657 gen_op_movl_A0_reg(R_EDI);
658 gen_op_andl_A0_ffff();
659 gen_op_addl_A0_seg(R_ES);
660 }
661 }
662
663 static inline void gen_op_movl_T0_Dshift(int ot)
664 {
665 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
666 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
667 };
668
669 static void gen_extu(int ot, TCGv reg)
670 {
671 switch(ot) {
672 case OT_BYTE:
673 tcg_gen_ext8u_tl(reg, reg);
674 break;
675 case OT_WORD:
676 tcg_gen_ext16u_tl(reg, reg);
677 break;
678 case OT_LONG:
679 tcg_gen_ext32u_tl(reg, reg);
680 break;
681 default:
682 break;
683 }
684 }
685
686 static void gen_exts(int ot, TCGv reg)
687 {
688 switch(ot) {
689 case OT_BYTE:
690 tcg_gen_ext8s_tl(reg, reg);
691 break;
692 case OT_WORD:
693 tcg_gen_ext16s_tl(reg, reg);
694 break;
695 case OT_LONG:
696 tcg_gen_ext32s_tl(reg, reg);
697 break;
698 default:
699 break;
700 }
701 }
702
703 static inline void gen_op_jnz_ecx(int size, int label1)
704 {
705 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
706 gen_extu(size + 1, cpu_tmp0);
707 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
708 }
709
710 static inline void gen_op_jz_ecx(int size, int label1)
711 {
712 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
713 gen_extu(size + 1, cpu_tmp0);
714 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
715 }
716
717 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
718 {
719 switch (ot) {
720 case 0: gen_helper_inb(v, n); break;
721 case 1: gen_helper_inw(v, n); break;
722 case 2: gen_helper_inl(v, n); break;
723 }
724
725 }
726
727 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
728 {
729 switch (ot) {
730 case 0: gen_helper_outb(v, n); break;
731 case 1: gen_helper_outw(v, n); break;
732 case 2: gen_helper_outl(v, n); break;
733 }
734
735 }
736
737 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
738 uint32_t svm_flags)
739 {
740 int state_saved;
741 target_ulong next_eip;
742
743 state_saved = 0;
744 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
745 if (s->cc_op != CC_OP_DYNAMIC)
746 gen_op_set_cc_op(s->cc_op);
747 gen_jmp_im(cur_eip);
748 state_saved = 1;
749 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
750 switch (ot) {
751 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
752 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
753 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
754 }
755 }
756 if(s->flags & HF_SVMI_MASK) {
757 if (!state_saved) {
758 if (s->cc_op != CC_OP_DYNAMIC)
759 gen_op_set_cc_op(s->cc_op);
760 gen_jmp_im(cur_eip);
761 state_saved = 1;
762 }
763 svm_flags |= (1 << (4 + ot));
764 next_eip = s->pc - s->cs_base;
765 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
766 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
767 tcg_const_i32(next_eip - cur_eip));
768 }
769 }
770
771 static inline void gen_movs(DisasContext *s, int ot)
772 {
773 gen_string_movl_A0_ESI(s);
774 gen_op_ld_T0_A0(ot + s->mem_index);
775 gen_string_movl_A0_EDI(s);
776 gen_op_st_T0_A0(ot + s->mem_index);
777 gen_op_movl_T0_Dshift(ot);
778 gen_op_add_reg_T0(s->aflag, R_ESI);
779 gen_op_add_reg_T0(s->aflag, R_EDI);
780 }
781
782 static inline void gen_update_cc_op(DisasContext *s)
783 {
784 if (s->cc_op != CC_OP_DYNAMIC) {
785 gen_op_set_cc_op(s->cc_op);
786 s->cc_op = CC_OP_DYNAMIC;
787 }
788 }
789
790 static void gen_op_update1_cc(void)
791 {
792 tcg_gen_discard_tl(cpu_cc_src);
793 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
794 }
795
796 static void gen_op_update2_cc(void)
797 {
798 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
799 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
800 }
801
802 static inline void gen_op_cmpl_T0_T1_cc(void)
803 {
804 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
805 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
806 }
807
808 static inline void gen_op_testl_T0_T1_cc(void)
809 {
810 tcg_gen_discard_tl(cpu_cc_src);
811 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
812 }
813
814 static void gen_op_update_neg_cc(void)
815 {
816 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
817 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
818 }
819
820 /* compute eflags.C to reg */
821 static void gen_compute_eflags_c(TCGv reg)
822 {
823 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
824 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
825 }
826
827 /* compute all eflags to cc_src */
828 static void gen_compute_eflags(TCGv reg)
829 {
830 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
831 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
832 }
833
834 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
835 {
836 if (s->cc_op != CC_OP_DYNAMIC)
837 gen_op_set_cc_op(s->cc_op);
838 switch(jcc_op) {
839 case JCC_O:
840 gen_compute_eflags(cpu_T[0]);
841 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
842 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
843 break;
844 case JCC_B:
845 gen_compute_eflags_c(cpu_T[0]);
846 break;
847 case JCC_Z:
848 gen_compute_eflags(cpu_T[0]);
849 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
850 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
851 break;
852 case JCC_BE:
853 gen_compute_eflags(cpu_tmp0);
854 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
855 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
856 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
857 break;
858 case JCC_S:
859 gen_compute_eflags(cpu_T[0]);
860 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
861 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
862 break;
863 case JCC_P:
864 gen_compute_eflags(cpu_T[0]);
865 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
866 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
867 break;
868 case JCC_L:
869 gen_compute_eflags(cpu_tmp0);
870 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
871 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
872 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
873 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
874 break;
875 default:
876 case JCC_LE:
877 gen_compute_eflags(cpu_tmp0);
878 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
879 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
880 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
881 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
882 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
883 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
884 break;
885 }
886 }
887
888 /* return true if setcc_slow is not needed (WARNING: must be kept in
889 sync with gen_jcc1) */
890 static int is_fast_jcc_case(DisasContext *s, int b)
891 {
892 int jcc_op;
893 jcc_op = (b >> 1) & 7;
894 switch(s->cc_op) {
895 /* we optimize the cmp/jcc case */
896 case CC_OP_SUBB:
897 case CC_OP_SUBW:
898 case CC_OP_SUBL:
899 case CC_OP_SUBQ:
900 if (jcc_op == JCC_O || jcc_op == JCC_P)
901 goto slow_jcc;
902 break;
903
904 /* some jumps are easy to compute */
905 case CC_OP_ADDB:
906 case CC_OP_ADDW:
907 case CC_OP_ADDL:
908 case CC_OP_ADDQ:
909
910 case CC_OP_LOGICB:
911 case CC_OP_LOGICW:
912 case CC_OP_LOGICL:
913 case CC_OP_LOGICQ:
914
915 case CC_OP_INCB:
916 case CC_OP_INCW:
917 case CC_OP_INCL:
918 case CC_OP_INCQ:
919
920 case CC_OP_DECB:
921 case CC_OP_DECW:
922 case CC_OP_DECL:
923 case CC_OP_DECQ:
924
925 case CC_OP_SHLB:
926 case CC_OP_SHLW:
927 case CC_OP_SHLL:
928 case CC_OP_SHLQ:
929 if (jcc_op != JCC_Z && jcc_op != JCC_S)
930 goto slow_jcc;
931 break;
932 default:
933 slow_jcc:
934 return 0;
935 }
936 return 1;
937 }
938
939 /* generate a conditional jump to label 'l1' according to jump opcode
940 value 'b'. In the fast case, T0 is guaranted not to be used. */
941 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
942 {
943 int inv, jcc_op, size, cond;
944 TCGv t0;
945
946 inv = b & 1;
947 jcc_op = (b >> 1) & 7;
948
949 switch(cc_op) {
950 /* we optimize the cmp/jcc case */
951 case CC_OP_SUBB:
952 case CC_OP_SUBW:
953 case CC_OP_SUBL:
954 case CC_OP_SUBQ:
955
956 size = cc_op - CC_OP_SUBB;
957 switch(jcc_op) {
958 case JCC_Z:
959 fast_jcc_z:
960 switch(size) {
961 case 0:
962 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
963 t0 = cpu_tmp0;
964 break;
965 case 1:
966 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
967 t0 = cpu_tmp0;
968 break;
969 #ifdef TARGET_X86_64
970 case 2:
971 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
972 t0 = cpu_tmp0;
973 break;
974 #endif
975 default:
976 t0 = cpu_cc_dst;
977 break;
978 }
979 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
980 break;
981 case JCC_S:
982 fast_jcc_s:
983 switch(size) {
984 case 0:
985 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
986 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
987 0, l1);
988 break;
989 case 1:
990 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
991 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
992 0, l1);
993 break;
994 #ifdef TARGET_X86_64
995 case 2:
996 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
997 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
998 0, l1);
999 break;
1000 #endif
1001 default:
1002 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1003 0, l1);
1004 break;
1005 }
1006 break;
1007
1008 case JCC_B:
1009 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1010 goto fast_jcc_b;
1011 case JCC_BE:
1012 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1013 fast_jcc_b:
1014 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1015 switch(size) {
1016 case 0:
1017 t0 = cpu_tmp0;
1018 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1019 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1020 break;
1021 case 1:
1022 t0 = cpu_tmp0;
1023 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1024 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1025 break;
1026 #ifdef TARGET_X86_64
1027 case 2:
1028 t0 = cpu_tmp0;
1029 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1030 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1031 break;
1032 #endif
1033 default:
1034 t0 = cpu_cc_src;
1035 break;
1036 }
1037 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1038 break;
1039
1040 case JCC_L:
1041 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1042 goto fast_jcc_l;
1043 case JCC_LE:
1044 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1045 fast_jcc_l:
1046 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1047 switch(size) {
1048 case 0:
1049 t0 = cpu_tmp0;
1050 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1051 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1052 break;
1053 case 1:
1054 t0 = cpu_tmp0;
1055 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1056 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1057 break;
1058 #ifdef TARGET_X86_64
1059 case 2:
1060 t0 = cpu_tmp0;
1061 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1062 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1063 break;
1064 #endif
1065 default:
1066 t0 = cpu_cc_src;
1067 break;
1068 }
1069 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1070 break;
1071
1072 default:
1073 goto slow_jcc;
1074 }
1075 break;
1076
1077 /* some jumps are easy to compute */
1078 case CC_OP_ADDB:
1079 case CC_OP_ADDW:
1080 case CC_OP_ADDL:
1081 case CC_OP_ADDQ:
1082
1083 case CC_OP_ADCB:
1084 case CC_OP_ADCW:
1085 case CC_OP_ADCL:
1086 case CC_OP_ADCQ:
1087
1088 case CC_OP_SBBB:
1089 case CC_OP_SBBW:
1090 case CC_OP_SBBL:
1091 case CC_OP_SBBQ:
1092
1093 case CC_OP_LOGICB:
1094 case CC_OP_LOGICW:
1095 case CC_OP_LOGICL:
1096 case CC_OP_LOGICQ:
1097
1098 case CC_OP_INCB:
1099 case CC_OP_INCW:
1100 case CC_OP_INCL:
1101 case CC_OP_INCQ:
1102
1103 case CC_OP_DECB:
1104 case CC_OP_DECW:
1105 case CC_OP_DECL:
1106 case CC_OP_DECQ:
1107
1108 case CC_OP_SHLB:
1109 case CC_OP_SHLW:
1110 case CC_OP_SHLL:
1111 case CC_OP_SHLQ:
1112
1113 case CC_OP_SARB:
1114 case CC_OP_SARW:
1115 case CC_OP_SARL:
1116 case CC_OP_SARQ:
1117 switch(jcc_op) {
1118 case JCC_Z:
1119 size = (cc_op - CC_OP_ADDB) & 3;
1120 goto fast_jcc_z;
1121 case JCC_S:
1122 size = (cc_op - CC_OP_ADDB) & 3;
1123 goto fast_jcc_s;
1124 default:
1125 goto slow_jcc;
1126 }
1127 break;
1128 default:
1129 slow_jcc:
1130 gen_setcc_slow_T0(s, jcc_op);
1131 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1132 cpu_T[0], 0, l1);
1133 break;
1134 }
1135 }
1136
1137 /* XXX: does not work with gdbstub "ice" single step - not a
1138 serious problem */
1139 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1140 {
1141 int l1, l2;
1142
1143 l1 = gen_new_label();
1144 l2 = gen_new_label();
1145 gen_op_jnz_ecx(s->aflag, l1);
1146 gen_set_label(l2);
1147 gen_jmp_tb(s, next_eip, 1);
1148 gen_set_label(l1);
1149 return l2;
1150 }
1151
1152 static inline void gen_stos(DisasContext *s, int ot)
1153 {
1154 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1155 gen_string_movl_A0_EDI(s);
1156 gen_op_st_T0_A0(ot + s->mem_index);
1157 gen_op_movl_T0_Dshift(ot);
1158 gen_op_add_reg_T0(s->aflag, R_EDI);
1159 }
1160
1161 static inline void gen_lods(DisasContext *s, int ot)
1162 {
1163 gen_string_movl_A0_ESI(s);
1164 gen_op_ld_T0_A0(ot + s->mem_index);
1165 gen_op_mov_reg_T0(ot, R_EAX);
1166 gen_op_movl_T0_Dshift(ot);
1167 gen_op_add_reg_T0(s->aflag, R_ESI);
1168 }
1169
1170 static inline void gen_scas(DisasContext *s, int ot)
1171 {
1172 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1173 gen_string_movl_A0_EDI(s);
1174 gen_op_ld_T1_A0(ot + s->mem_index);
1175 gen_op_cmpl_T0_T1_cc();
1176 gen_op_movl_T0_Dshift(ot);
1177 gen_op_add_reg_T0(s->aflag, R_EDI);
1178 }
1179
1180 static inline void gen_cmps(DisasContext *s, int ot)
1181 {
1182 gen_string_movl_A0_ESI(s);
1183 gen_op_ld_T0_A0(ot + s->mem_index);
1184 gen_string_movl_A0_EDI(s);
1185 gen_op_ld_T1_A0(ot + s->mem_index);
1186 gen_op_cmpl_T0_T1_cc();
1187 gen_op_movl_T0_Dshift(ot);
1188 gen_op_add_reg_T0(s->aflag, R_ESI);
1189 gen_op_add_reg_T0(s->aflag, R_EDI);
1190 }
1191
1192 static inline void gen_ins(DisasContext *s, int ot)
1193 {
1194 if (use_icount)
1195 gen_io_start();
1196 gen_string_movl_A0_EDI(s);
1197 /* Note: we must do this dummy write first to be restartable in
1198 case of page fault. */
1199 gen_op_movl_T0_0();
1200 gen_op_st_T0_A0(ot + s->mem_index);
1201 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1202 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1203 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1204 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1205 gen_op_st_T0_A0(ot + s->mem_index);
1206 gen_op_movl_T0_Dshift(ot);
1207 gen_op_add_reg_T0(s->aflag, R_EDI);
1208 if (use_icount)
1209 gen_io_end();
1210 }
1211
1212 static inline void gen_outs(DisasContext *s, int ot)
1213 {
1214 if (use_icount)
1215 gen_io_start();
1216 gen_string_movl_A0_ESI(s);
1217 gen_op_ld_T0_A0(ot + s->mem_index);
1218
1219 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1220 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1221 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1222 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1223 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1224
1225 gen_op_movl_T0_Dshift(ot);
1226 gen_op_add_reg_T0(s->aflag, R_ESI);
1227 if (use_icount)
1228 gen_io_end();
1229 }
1230
1231 /* same method as Valgrind : we generate jumps to current or next
1232 instruction */
1233 #define GEN_REPZ(op) \
1234 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1235 target_ulong cur_eip, target_ulong next_eip) \
1236 { \
1237 int l2;\
1238 gen_update_cc_op(s); \
1239 l2 = gen_jz_ecx_string(s, next_eip); \
1240 gen_ ## op(s, ot); \
1241 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1242 /* a loop would cause two single step exceptions if ECX = 1 \
1243 before rep string_insn */ \
1244 if (!s->jmp_opt) \
1245 gen_op_jz_ecx(s->aflag, l2); \
1246 gen_jmp(s, cur_eip); \
1247 }
1248
1249 #define GEN_REPZ2(op) \
1250 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1251 target_ulong cur_eip, \
1252 target_ulong next_eip, \
1253 int nz) \
1254 { \
1255 int l2;\
1256 gen_update_cc_op(s); \
1257 l2 = gen_jz_ecx_string(s, next_eip); \
1258 gen_ ## op(s, ot); \
1259 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1260 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1261 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1262 if (!s->jmp_opt) \
1263 gen_op_jz_ecx(s->aflag, l2); \
1264 gen_jmp(s, cur_eip); \
1265 }
1266
1267 GEN_REPZ(movs)
1268 GEN_REPZ(stos)
1269 GEN_REPZ(lods)
1270 GEN_REPZ(ins)
1271 GEN_REPZ(outs)
1272 GEN_REPZ2(scas)
1273 GEN_REPZ2(cmps)
1274
1275 static void gen_helper_fp_arith_ST0_FT0(int op)
1276 {
1277 switch (op) {
1278 case 0: gen_helper_fadd_ST0_FT0(); break;
1279 case 1: gen_helper_fmul_ST0_FT0(); break;
1280 case 2: gen_helper_fcom_ST0_FT0(); break;
1281 case 3: gen_helper_fcom_ST0_FT0(); break;
1282 case 4: gen_helper_fsub_ST0_FT0(); break;
1283 case 5: gen_helper_fsubr_ST0_FT0(); break;
1284 case 6: gen_helper_fdiv_ST0_FT0(); break;
1285 case 7: gen_helper_fdivr_ST0_FT0(); break;
1286 }
1287 }
1288
1289 /* NOTE the exception in "r" op ordering */
1290 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1291 {
1292 TCGv_i32 tmp = tcg_const_i32(opreg);
1293 switch (op) {
1294 case 0: gen_helper_fadd_STN_ST0(tmp); break;
1295 case 1: gen_helper_fmul_STN_ST0(tmp); break;
1296 case 4: gen_helper_fsubr_STN_ST0(tmp); break;
1297 case 5: gen_helper_fsub_STN_ST0(tmp); break;
1298 case 6: gen_helper_fdivr_STN_ST0(tmp); break;
1299 case 7: gen_helper_fdiv_STN_ST0(tmp); break;
1300 }
1301 }
1302
1303 /* if d == OR_TMP0, it means memory operand (address in A0) */
1304 static void gen_op(DisasContext *s1, int op, int ot, int d)
1305 {
1306 if (d != OR_TMP0) {
1307 gen_op_mov_TN_reg(ot, 0, d);
1308 } else {
1309 gen_op_ld_T0_A0(ot + s1->mem_index);
1310 }
1311 switch(op) {
1312 case OP_ADCL:
1313 if (s1->cc_op != CC_OP_DYNAMIC)
1314 gen_op_set_cc_op(s1->cc_op);
1315 gen_compute_eflags_c(cpu_tmp4);
1316 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1317 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1318 if (d != OR_TMP0)
1319 gen_op_mov_reg_T0(ot, d);
1320 else
1321 gen_op_st_T0_A0(ot + s1->mem_index);
1322 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1323 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1324 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1325 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1326 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1327 s1->cc_op = CC_OP_DYNAMIC;
1328 break;
1329 case OP_SBBL:
1330 if (s1->cc_op != CC_OP_DYNAMIC)
1331 gen_op_set_cc_op(s1->cc_op);
1332 gen_compute_eflags_c(cpu_tmp4);
1333 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1334 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1335 if (d != OR_TMP0)
1336 gen_op_mov_reg_T0(ot, d);
1337 else
1338 gen_op_st_T0_A0(ot + s1->mem_index);
1339 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1340 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1341 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1342 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1343 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1344 s1->cc_op = CC_OP_DYNAMIC;
1345 break;
1346 case OP_ADDL:
1347 gen_op_addl_T0_T1();
1348 if (d != OR_TMP0)
1349 gen_op_mov_reg_T0(ot, d);
1350 else
1351 gen_op_st_T0_A0(ot + s1->mem_index);
1352 gen_op_update2_cc();
1353 s1->cc_op = CC_OP_ADDB + ot;
1354 break;
1355 case OP_SUBL:
1356 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1357 if (d != OR_TMP0)
1358 gen_op_mov_reg_T0(ot, d);
1359 else
1360 gen_op_st_T0_A0(ot + s1->mem_index);
1361 gen_op_update2_cc();
1362 s1->cc_op = CC_OP_SUBB + ot;
1363 break;
1364 default:
1365 case OP_ANDL:
1366 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1367 if (d != OR_TMP0)
1368 gen_op_mov_reg_T0(ot, d);
1369 else
1370 gen_op_st_T0_A0(ot + s1->mem_index);
1371 gen_op_update1_cc();
1372 s1->cc_op = CC_OP_LOGICB + ot;
1373 break;
1374 case OP_ORL:
1375 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1376 if (d != OR_TMP0)
1377 gen_op_mov_reg_T0(ot, d);
1378 else
1379 gen_op_st_T0_A0(ot + s1->mem_index);
1380 gen_op_update1_cc();
1381 s1->cc_op = CC_OP_LOGICB + ot;
1382 break;
1383 case OP_XORL:
1384 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1385 if (d != OR_TMP0)
1386 gen_op_mov_reg_T0(ot, d);
1387 else
1388 gen_op_st_T0_A0(ot + s1->mem_index);
1389 gen_op_update1_cc();
1390 s1->cc_op = CC_OP_LOGICB + ot;
1391 break;
1392 case OP_CMPL:
1393 gen_op_cmpl_T0_T1_cc();
1394 s1->cc_op = CC_OP_SUBB + ot;
1395 break;
1396 }
1397 }
1398
1399 /* if d == OR_TMP0, it means memory operand (address in A0) */
1400 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1401 {
1402 if (d != OR_TMP0)
1403 gen_op_mov_TN_reg(ot, 0, d);
1404 else
1405 gen_op_ld_T0_A0(ot + s1->mem_index);
1406 if (s1->cc_op != CC_OP_DYNAMIC)
1407 gen_op_set_cc_op(s1->cc_op);
1408 if (c > 0) {
1409 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1410 s1->cc_op = CC_OP_INCB + ot;
1411 } else {
1412 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1413 s1->cc_op = CC_OP_DECB + ot;
1414 }
1415 if (d != OR_TMP0)
1416 gen_op_mov_reg_T0(ot, d);
1417 else
1418 gen_op_st_T0_A0(ot + s1->mem_index);
1419 gen_compute_eflags_c(cpu_cc_src);
1420 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1421 }
1422
1423 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1424 int is_right, int is_arith)
1425 {
1426 target_ulong mask;
1427 int shift_label;
1428 TCGv t0, t1;
1429
1430 if (ot == OT_QUAD)
1431 mask = 0x3f;
1432 else
1433 mask = 0x1f;
1434
1435 /* load */
1436 if (op1 == OR_TMP0)
1437 gen_op_ld_T0_A0(ot + s->mem_index);
1438 else
1439 gen_op_mov_TN_reg(ot, 0, op1);
1440
1441 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1442
1443 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1444
1445 if (is_right) {
1446 if (is_arith) {
1447 gen_exts(ot, cpu_T[0]);
1448 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1449 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1450 } else {
1451 gen_extu(ot, cpu_T[0]);
1452 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1453 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1454 }
1455 } else {
1456 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1457 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1458 }
1459
1460 /* store */
1461 if (op1 == OR_TMP0)
1462 gen_op_st_T0_A0(ot + s->mem_index);
1463 else
1464 gen_op_mov_reg_T0(ot, op1);
1465
1466 /* update eflags if non zero shift */
1467 if (s->cc_op != CC_OP_DYNAMIC)
1468 gen_op_set_cc_op(s->cc_op);
1469
1470 /* XXX: inefficient */
1471 t0 = tcg_temp_local_new();
1472 t1 = tcg_temp_local_new();
1473
1474 tcg_gen_mov_tl(t0, cpu_T[0]);
1475 tcg_gen_mov_tl(t1, cpu_T3);
1476
1477 shift_label = gen_new_label();
1478 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1479
1480 tcg_gen_mov_tl(cpu_cc_src, t1);
1481 tcg_gen_mov_tl(cpu_cc_dst, t0);
1482 if (is_right)
1483 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1484 else
1485 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1486
1487 gen_set_label(shift_label);
1488 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1489
1490 tcg_temp_free(t0);
1491 tcg_temp_free(t1);
1492 }
1493
1494 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1495 int is_right, int is_arith)
1496 {
1497 int mask;
1498
1499 if (ot == OT_QUAD)
1500 mask = 0x3f;
1501 else
1502 mask = 0x1f;
1503
1504 /* load */
1505 if (op1 == OR_TMP0)
1506 gen_op_ld_T0_A0(ot + s->mem_index);
1507 else
1508 gen_op_mov_TN_reg(ot, 0, op1);
1509
1510 op2 &= mask;
1511 if (op2 != 0) {
1512 if (is_right) {
1513 if (is_arith) {
1514 gen_exts(ot, cpu_T[0]);
1515 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1516 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1517 } else {
1518 gen_extu(ot, cpu_T[0]);
1519 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1520 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1521 }
1522 } else {
1523 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1524 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1525 }
1526 }
1527
1528 /* store */
1529 if (op1 == OR_TMP0)
1530 gen_op_st_T0_A0(ot + s->mem_index);
1531 else
1532 gen_op_mov_reg_T0(ot, op1);
1533
1534 /* update eflags if non zero shift */
1535 if (op2 != 0) {
1536 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1537 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1538 if (is_right)
1539 s->cc_op = CC_OP_SARB + ot;
1540 else
1541 s->cc_op = CC_OP_SHLB + ot;
1542 }
1543 }
1544
1545 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1546 {
1547 if (arg2 >= 0)
1548 tcg_gen_shli_tl(ret, arg1, arg2);
1549 else
1550 tcg_gen_shri_tl(ret, arg1, -arg2);
1551 }
1552
1553 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1554 int is_right)
1555 {
1556 target_ulong mask;
1557 int label1, label2, data_bits;
1558 TCGv t0, t1, t2, a0;
1559
1560 /* XXX: inefficient, but we must use local temps */
1561 t0 = tcg_temp_local_new();
1562 t1 = tcg_temp_local_new();
1563 t2 = tcg_temp_local_new();
1564 a0 = tcg_temp_local_new();
1565
1566 if (ot == OT_QUAD)
1567 mask = 0x3f;
1568 else
1569 mask = 0x1f;
1570
1571 /* load */
1572 if (op1 == OR_TMP0) {
1573 tcg_gen_mov_tl(a0, cpu_A0);
1574 gen_op_ld_v(ot + s->mem_index, t0, a0);
1575 } else {
1576 gen_op_mov_v_reg(ot, t0, op1);
1577 }
1578
1579 tcg_gen_mov_tl(t1, cpu_T[1]);
1580
1581 tcg_gen_andi_tl(t1, t1, mask);
1582
1583 /* Must test zero case to avoid using undefined behaviour in TCG
1584 shifts. */
1585 label1 = gen_new_label();
1586 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1587
1588 if (ot <= OT_WORD)
1589 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1590 else
1591 tcg_gen_mov_tl(cpu_tmp0, t1);
1592
1593 gen_extu(ot, t0);
1594 tcg_gen_mov_tl(t2, t0);
1595
1596 data_bits = 8 << ot;
1597 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1598 fix TCG definition) */
1599 if (is_right) {
1600 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1601 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1602 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1603 } else {
1604 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1605 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1606 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1607 }
1608 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1609
1610 gen_set_label(label1);
1611 /* store */
1612 if (op1 == OR_TMP0) {
1613 gen_op_st_v(ot + s->mem_index, t0, a0);
1614 } else {
1615 gen_op_mov_reg_v(ot, op1, t0);
1616 }
1617
1618 /* update eflags */
1619 if (s->cc_op != CC_OP_DYNAMIC)
1620 gen_op_set_cc_op(s->cc_op);
1621
1622 label2 = gen_new_label();
1623 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1624
1625 gen_compute_eflags(cpu_cc_src);
1626 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1627 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1628 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1629 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1630 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1631 if (is_right) {
1632 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1633 }
1634 tcg_gen_andi_tl(t0, t0, CC_C);
1635 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1636
1637 tcg_gen_discard_tl(cpu_cc_dst);
1638 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1639
1640 gen_set_label(label2);
1641 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1642
1643 tcg_temp_free(t0);
1644 tcg_temp_free(t1);
1645 tcg_temp_free(t2);
1646 tcg_temp_free(a0);
1647 }
1648
1649 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1650 int is_right)
1651 {
1652 int mask;
1653 int data_bits;
1654 TCGv t0, t1, a0;
1655
1656 /* XXX: inefficient, but we must use local temps */
1657 t0 = tcg_temp_local_new();
1658 t1 = tcg_temp_local_new();
1659 a0 = tcg_temp_local_new();
1660
1661 if (ot == OT_QUAD)
1662 mask = 0x3f;
1663 else
1664 mask = 0x1f;
1665
1666 /* load */
1667 if (op1 == OR_TMP0) {
1668 tcg_gen_mov_tl(a0, cpu_A0);
1669 gen_op_ld_v(ot + s->mem_index, t0, a0);
1670 } else {
1671 gen_op_mov_v_reg(ot, t0, op1);
1672 }
1673
1674 gen_extu(ot, t0);
1675 tcg_gen_mov_tl(t1, t0);
1676
1677 op2 &= mask;
1678 data_bits = 8 << ot;
1679 if (op2 != 0) {
1680 int shift = op2 & ((1 << (3 + ot)) - 1);
1681 if (is_right) {
1682 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1683 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1684 }
1685 else {
1686 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1687 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1688 }
1689 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1690 }
1691
1692 /* store */
1693 if (op1 == OR_TMP0) {
1694 gen_op_st_v(ot + s->mem_index, t0, a0);
1695 } else {
1696 gen_op_mov_reg_v(ot, op1, t0);
1697 }
1698
1699 if (op2 != 0) {
1700 /* update eflags */
1701 if (s->cc_op != CC_OP_DYNAMIC)
1702 gen_op_set_cc_op(s->cc_op);
1703
1704 gen_compute_eflags(cpu_cc_src);
1705 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1706 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1707 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1708 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1709 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1710 if (is_right) {
1711 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1712 }
1713 tcg_gen_andi_tl(t0, t0, CC_C);
1714 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1715
1716 tcg_gen_discard_tl(cpu_cc_dst);
1717 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1718 s->cc_op = CC_OP_EFLAGS;
1719 }
1720
1721 tcg_temp_free(t0);
1722 tcg_temp_free(t1);
1723 tcg_temp_free(a0);
1724 }
1725
1726 /* XXX: add faster immediate = 1 case */
1727 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1728 int is_right)
1729 {
1730 int label1;
1731
1732 if (s->cc_op != CC_OP_DYNAMIC)
1733 gen_op_set_cc_op(s->cc_op);
1734
1735 /* load */
1736 if (op1 == OR_TMP0)
1737 gen_op_ld_T0_A0(ot + s->mem_index);
1738 else
1739 gen_op_mov_TN_reg(ot, 0, op1);
1740
1741 if (is_right) {
1742 switch (ot) {
1743 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1744 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1745 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1746 #ifdef TARGET_X86_64
1747 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1748 #endif
1749 }
1750 } else {
1751 switch (ot) {
1752 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1753 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1754 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1755 #ifdef TARGET_X86_64
1756 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1757 #endif
1758 }
1759 }
1760 /* store */
1761 if (op1 == OR_TMP0)
1762 gen_op_st_T0_A0(ot + s->mem_index);
1763 else
1764 gen_op_mov_reg_T0(ot, op1);
1765
1766 /* update eflags */
1767 label1 = gen_new_label();
1768 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1769
1770 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1771 tcg_gen_discard_tl(cpu_cc_dst);
1772 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1773
1774 gen_set_label(label1);
1775 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1776 }
1777
1778 /* XXX: add faster immediate case */
1779 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1780 int is_right)
1781 {
1782 int label1, label2, data_bits;
1783 target_ulong mask;
1784 TCGv t0, t1, t2, a0;
1785
1786 t0 = tcg_temp_local_new();
1787 t1 = tcg_temp_local_new();
1788 t2 = tcg_temp_local_new();
1789 a0 = tcg_temp_local_new();
1790
1791 if (ot == OT_QUAD)
1792 mask = 0x3f;
1793 else
1794 mask = 0x1f;
1795
1796 /* load */
1797 if (op1 == OR_TMP0) {
1798 tcg_gen_mov_tl(a0, cpu_A0);
1799 gen_op_ld_v(ot + s->mem_index, t0, a0);
1800 } else {
1801 gen_op_mov_v_reg(ot, t0, op1);
1802 }
1803
1804 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1805
1806 tcg_gen_mov_tl(t1, cpu_T[1]);
1807 tcg_gen_mov_tl(t2, cpu_T3);
1808
1809 /* Must test zero case to avoid using undefined behaviour in TCG
1810 shifts. */
1811 label1 = gen_new_label();
1812 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1813
1814 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1815 if (ot == OT_WORD) {
1816 /* Note: we implement the Intel behaviour for shift count > 16 */
1817 if (is_right) {
1818 tcg_gen_andi_tl(t0, t0, 0xffff);
1819 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1820 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1821 tcg_gen_ext32u_tl(t0, t0);
1822
1823 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1824
1825 /* only needed if count > 16, but a test would complicate */
1826 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1827 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1828
1829 tcg_gen_shr_tl(t0, t0, t2);
1830
1831 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1832 } else {
1833 /* XXX: not optimal */
1834 tcg_gen_andi_tl(t0, t0, 0xffff);
1835 tcg_gen_shli_tl(t1, t1, 16);
1836 tcg_gen_or_tl(t1, t1, t0);
1837 tcg_gen_ext32u_tl(t1, t1);
1838
1839 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1840 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
1841 tcg_gen_shr_tl(cpu_tmp6, t1, cpu_tmp0);
1842 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);
1843
1844 tcg_gen_shl_tl(t0, t0, t2);
1845 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1846 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1847 tcg_gen_or_tl(t0, t0, t1);
1848 }
1849 } else {
1850 data_bits = 8 << ot;
1851 if (is_right) {
1852 if (ot == OT_LONG)
1853 tcg_gen_ext32u_tl(t0, t0);
1854
1855 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1856
1857 tcg_gen_shr_tl(t0, t0, t2);
1858 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1859 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1860 tcg_gen_or_tl(t0, t0, t1);
1861
1862 } else {
1863 if (ot == OT_LONG)
1864 tcg_gen_ext32u_tl(t1, t1);
1865
1866 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1867
1868 tcg_gen_shl_tl(t0, t0, t2);
1869 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1870 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1871 tcg_gen_or_tl(t0, t0, t1);
1872 }
1873 }
1874 tcg_gen_mov_tl(t1, cpu_tmp4);
1875
1876 gen_set_label(label1);
1877 /* store */
1878 if (op1 == OR_TMP0) {
1879 gen_op_st_v(ot + s->mem_index, t0, a0);
1880 } else {
1881 gen_op_mov_reg_v(ot, op1, t0);
1882 }
1883
1884 /* update eflags */
1885 if (s->cc_op != CC_OP_DYNAMIC)
1886 gen_op_set_cc_op(s->cc_op);
1887
1888 label2 = gen_new_label();
1889 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1890
1891 tcg_gen_mov_tl(cpu_cc_src, t1);
1892 tcg_gen_mov_tl(cpu_cc_dst, t0);
1893 if (is_right) {
1894 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1895 } else {
1896 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1897 }
1898 gen_set_label(label2);
1899 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1900
1901 tcg_temp_free(t0);
1902 tcg_temp_free(t1);
1903 tcg_temp_free(t2);
1904 tcg_temp_free(a0);
1905 }
1906
1907 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1908 {
1909 if (s != OR_TMP1)
1910 gen_op_mov_TN_reg(ot, 1, s);
1911 switch(op) {
1912 case OP_ROL:
1913 gen_rot_rm_T1(s1, ot, d, 0);
1914 break;
1915 case OP_ROR:
1916 gen_rot_rm_T1(s1, ot, d, 1);
1917 break;
1918 case OP_SHL:
1919 case OP_SHL1:
1920 gen_shift_rm_T1(s1, ot, d, 0, 0);
1921 break;
1922 case OP_SHR:
1923 gen_shift_rm_T1(s1, ot, d, 1, 0);
1924 break;
1925 case OP_SAR:
1926 gen_shift_rm_T1(s1, ot, d, 1, 1);
1927 break;
1928 case OP_RCL:
1929 gen_rotc_rm_T1(s1, ot, d, 0);
1930 break;
1931 case OP_RCR:
1932 gen_rotc_rm_T1(s1, ot, d, 1);
1933 break;
1934 }
1935 }
1936
1937 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1938 {
1939 switch(op) {
1940 case OP_ROL:
1941 gen_rot_rm_im(s1, ot, d, c, 0);
1942 break;
1943 case OP_ROR:
1944 gen_rot_rm_im(s1, ot, d, c, 1);
1945 break;
1946 case OP_SHL:
1947 case OP_SHL1:
1948 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1949 break;
1950 case OP_SHR:
1951 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1952 break;
1953 case OP_SAR:
1954 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1955 break;
1956 default:
1957 /* currently not optimized */
1958 gen_op_movl_T1_im(c);
1959 gen_shift(s1, op, ot, d, OR_TMP1);
1960 break;
1961 }
1962 }
1963
1964 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1965 {
1966 target_long disp;
1967 int havesib;
1968 int base;
1969 int index;
1970 int scale;
1971 int opreg;
1972 int mod, rm, code, override, must_add_seg;
1973
1974 override = s->override;
1975 must_add_seg = s->addseg;
1976 if (override >= 0)
1977 must_add_seg = 1;
1978 mod = (modrm >> 6) & 3;
1979 rm = modrm & 7;
1980
1981 if (s->aflag) {
1982
1983 havesib = 0;
1984 base = rm;
1985 index = 0;
1986 scale = 0;
1987
1988 if (base == 4) {
1989 havesib = 1;
1990 code = ldub_code(s->pc++);
1991 scale = (code >> 6) & 3;
1992 index = ((code >> 3) & 7) | REX_X(s);
1993 base = (code & 7);
1994 }
1995 base |= REX_B(s);
1996
1997 switch (mod) {
1998 case 0:
1999 if ((base & 7) == 5) {
2000 base = -1;
2001 disp = (int32_t)ldl_code(s->pc);
2002 s->pc += 4;
2003 if (CODE64(s) && !havesib) {
2004 disp += s->pc + s->rip_offset;
2005 }
2006 } else {
2007 disp = 0;
2008 }
2009 break;
2010 case 1:
2011 disp = (int8_t)ldub_code(s->pc++);
2012 break;
2013 default:
2014 case 2:
2015 disp = ldl_code(s->pc);
2016 s->pc += 4;
2017 break;
2018 }
2019
2020 if (base >= 0) {
2021 /* for correct popl handling with esp */
2022 if (base == 4 && s->popl_esp_hack)
2023 disp += s->popl_esp_hack;
2024 #ifdef TARGET_X86_64
2025 if (s->aflag == 2) {
2026 gen_op_movq_A0_reg(base);
2027 if (disp != 0) {
2028 gen_op_addq_A0_im(disp);
2029 }
2030 } else
2031 #endif
2032 {
2033 gen_op_movl_A0_reg(base);
2034 if (disp != 0)
2035 gen_op_addl_A0_im(disp);
2036 }
2037 } else {
2038 #ifdef TARGET_X86_64
2039 if (s->aflag == 2) {
2040 gen_op_movq_A0_im(disp);
2041 } else
2042 #endif
2043 {
2044 gen_op_movl_A0_im(disp);
2045 }
2046 }
2047 /* XXX: index == 4 is always invalid */
2048 if (havesib && (index != 4 || scale != 0)) {
2049 #ifdef TARGET_X86_64
2050 if (s->aflag == 2) {
2051 gen_op_addq_A0_reg_sN(scale, index);
2052 } else
2053 #endif
2054 {
2055 gen_op_addl_A0_reg_sN(scale, index);
2056 }
2057 }
2058 if (must_add_seg) {
2059 if (override < 0) {
2060 if (base == R_EBP || base == R_ESP)
2061 override = R_SS;
2062 else
2063 override = R_DS;
2064 }
2065 #ifdef TARGET_X86_64
2066 if (s->aflag == 2) {
2067 gen_op_addq_A0_seg(override);
2068 } else
2069 #endif
2070 {
2071 gen_op_addl_A0_seg(override);
2072 }
2073 }
2074 } else {
2075 switch (mod) {
2076 case 0:
2077 if (rm == 6) {
2078 disp = lduw_code(s->pc);
2079 s->pc += 2;
2080 gen_op_movl_A0_im(disp);
2081 rm = 0; /* avoid SS override */
2082 goto no_rm;
2083 } else {
2084 disp = 0;
2085 }
2086 break;
2087 case 1:
2088 disp = (int8_t)ldub_code(s->pc++);
2089 break;
2090 default:
2091 case 2:
2092 disp = lduw_code(s->pc);
2093 s->pc += 2;
2094 break;
2095 }
2096 switch(rm) {
2097 case 0:
2098 gen_op_movl_A0_reg(R_EBX);
2099 gen_op_addl_A0_reg_sN(0, R_ESI);
2100 break;
2101 case 1:
2102 gen_op_movl_A0_reg(R_EBX);
2103 gen_op_addl_A0_reg_sN(0, R_EDI);
2104 break;
2105 case 2:
2106 gen_op_movl_A0_reg(R_EBP);
2107 gen_op_addl_A0_reg_sN(0, R_ESI);
2108 break;
2109 case 3:
2110 gen_op_movl_A0_reg(R_EBP);
2111 gen_op_addl_A0_reg_sN(0, R_EDI);
2112 break;
2113 case 4:
2114 gen_op_movl_A0_reg(R_ESI);
2115 break;
2116 case 5:
2117 gen_op_movl_A0_reg(R_EDI);
2118 break;
2119 case 6:
2120 gen_op_movl_A0_reg(R_EBP);
2121 break;
2122 default:
2123 case 7:
2124 gen_op_movl_A0_reg(R_EBX);
2125 break;
2126 }
2127 if (disp != 0)
2128 gen_op_addl_A0_im(disp);
2129 gen_op_andl_A0_ffff();
2130 no_rm:
2131 if (must_add_seg) {
2132 if (override < 0) {
2133 if (rm == 2 || rm == 3 || rm == 6)
2134 override = R_SS;
2135 else
2136 override = R_DS;
2137 }
2138 gen_op_addl_A0_seg(override);
2139 }
2140 }
2141
2142 opreg = OR_A0;
2143 disp = 0;
2144 *reg_ptr = opreg;
2145 *offset_ptr = disp;
2146 }
2147
2148 static void gen_nop_modrm(DisasContext *s, int modrm)
2149 {
2150 int mod, rm, base, code;
2151
2152 mod = (modrm >> 6) & 3;
2153 if (mod == 3)
2154 return;
2155 rm = modrm & 7;
2156
2157 if (s->aflag) {
2158
2159 base = rm;
2160
2161 if (base == 4) {
2162 code = ldub_code(s->pc++);
2163 base = (code & 7);
2164 }
2165
2166 switch (mod) {
2167 case 0:
2168 if (base == 5) {
2169 s->pc += 4;
2170 }
2171 break;
2172 case 1:
2173 s->pc++;
2174 break;
2175 default:
2176 case 2:
2177 s->pc += 4;
2178 break;
2179 }
2180 } else {
2181 switch (mod) {
2182 case 0:
2183 if (rm == 6) {
2184 s->pc += 2;
2185 }
2186 break;
2187 case 1:
2188 s->pc++;
2189 break;
2190 default:
2191 case 2:
2192 s->pc += 2;
2193 break;
2194 }
2195 }
2196 }
2197
2198 /* used for LEA and MOV AX, mem */
2199 static void gen_add_A0_ds_seg(DisasContext *s)
2200 {
2201 int override, must_add_seg;
2202 must_add_seg = s->addseg;
2203 override = R_DS;
2204 if (s->override >= 0) {
2205 override = s->override;
2206 must_add_seg = 1;
2207 } else {
2208 override = R_DS;
2209 }
2210 if (must_add_seg) {
2211 #ifdef TARGET_X86_64
2212 if (CODE64(s)) {
2213 gen_op_addq_A0_seg(override);
2214 } else
2215 #endif
2216 {
2217 gen_op_addl_A0_seg(override);
2218 }
2219 }
2220 }
2221
2222 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2223 OR_TMP0 */
2224 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2225 {
2226 int mod, rm, opreg, disp;
2227
2228 mod = (modrm >> 6) & 3;
2229 rm = (modrm & 7) | REX_B(s);
2230 if (mod == 3) {
2231 if (is_store) {
2232 if (reg != OR_TMP0)
2233 gen_op_mov_TN_reg(ot, 0, reg);
2234 gen_op_mov_reg_T0(ot, rm);
2235 } else {
2236 gen_op_mov_TN_reg(ot, 0, rm);
2237 if (reg != OR_TMP0)
2238 gen_op_mov_reg_T0(ot, reg);
2239 }
2240 } else {
2241 gen_lea_modrm(s, modrm, &opreg, &disp);
2242 if (is_store) {
2243 if (reg != OR_TMP0)
2244 gen_op_mov_TN_reg(ot, 0, reg);
2245 gen_op_st_T0_A0(ot + s->mem_index);
2246 } else {
2247 gen_op_ld_T0_A0(ot + s->mem_index);
2248 if (reg != OR_TMP0)
2249 gen_op_mov_reg_T0(ot, reg);
2250 }
2251 }
2252 }
2253
2254 static inline uint32_t insn_get(DisasContext *s, int ot)
2255 {
2256 uint32_t ret;
2257
2258 switch(ot) {
2259 case OT_BYTE:
2260 ret = ldub_code(s->pc);
2261 s->pc++;
2262 break;
2263 case OT_WORD:
2264 ret = lduw_code(s->pc);
2265 s->pc += 2;
2266 break;
2267 default:
2268 case OT_LONG:
2269 ret = ldl_code(s->pc);
2270 s->pc += 4;
2271 break;
2272 }
2273 return ret;
2274 }
2275
2276 static inline int insn_const_size(unsigned int ot)
2277 {
2278 if (ot <= OT_LONG)
2279 return 1 << ot;
2280 else
2281 return 4;
2282 }
2283
2284 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2285 {
2286 TranslationBlock *tb;
2287 target_ulong pc;
2288
2289 pc = s->cs_base + eip;
2290 tb = s->tb;
2291 /* NOTE: we handle the case where the TB spans two pages here */
2292 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2293 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2294 /* jump to same page: we can use a direct jump */
2295 tcg_gen_goto_tb(tb_num);
2296 gen_jmp_im(eip);
2297 tcg_gen_exit_tb((long)tb + tb_num);
2298 } else {
2299 /* jump to another page: currently not optimized */
2300 gen_jmp_im(eip);
2301 gen_eob(s);
2302 }
2303 }
2304
2305 static inline void gen_jcc(DisasContext *s, int b,
2306 target_ulong val, target_ulong next_eip)
2307 {
2308 int l1, l2, cc_op;
2309
2310 cc_op = s->cc_op;
2311 if (s->cc_op != CC_OP_DYNAMIC) {
2312 gen_op_set_cc_op(s->cc_op);
2313 s->cc_op = CC_OP_DYNAMIC;
2314 }
2315 if (s->jmp_opt) {
2316 l1 = gen_new_label();
2317 gen_jcc1(s, cc_op, b, l1);
2318
2319 gen_goto_tb(s, 0, next_eip);
2320
2321 gen_set_label(l1);
2322 gen_goto_tb(s, 1, val);
2323 s->is_jmp = 3;
2324 } else {
2325
2326 l1 = gen_new_label();
2327 l2 = gen_new_label();
2328 gen_jcc1(s, cc_op, b, l1);
2329
2330 gen_jmp_im(next_eip);
2331 tcg_gen_br(l2);
2332
2333 gen_set_label(l1);
2334 gen_jmp_im(val);
2335 gen_set_label(l2);
2336 gen_eob(s);
2337 }
2338 }
2339
2340 static void gen_setcc(DisasContext *s, int b)
2341 {
2342 int inv, jcc_op, l1;
2343 TCGv t0;
2344
2345 if (is_fast_jcc_case(s, b)) {
2346 /* nominal case: we use a jump */
2347 /* XXX: make it faster by adding new instructions in TCG */
2348 t0 = tcg_temp_local_new();
2349 tcg_gen_movi_tl(t0, 0);
2350 l1 = gen_new_label();
2351 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2352 tcg_gen_movi_tl(t0, 1);
2353 gen_set_label(l1);
2354 tcg_gen_mov_tl(cpu_T[0], t0);
2355 tcg_temp_free(t0);
2356 } else {
2357 /* slow case: it is more efficient not to generate a jump,
2358 although it is questionnable whether this optimization is
2359 worth to */
2360 inv = b & 1;
2361 jcc_op = (b >> 1) & 7;
2362 gen_setcc_slow_T0(s, jcc_op);
2363 if (inv) {
2364 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2365 }
2366 }
2367 }
2368
2369 static inline void gen_op_movl_T0_seg(int seg_reg)
2370 {
2371 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2372 offsetof(CPUX86State,segs[seg_reg].selector));
2373 }
2374
2375 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2376 {
2377 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2378 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2379 offsetof(CPUX86State,segs[seg_reg].selector));
2380 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2381 tcg_gen_st_tl(cpu_T[0], cpu_env,
2382 offsetof(CPUX86State,segs[seg_reg].base));
2383 }
2384
2385 /* move T0 to seg_reg and compute if the CPU state may change. Never
2386 call this function with seg_reg == R_CS */
2387 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2388 {
2389 if (s->pe && !s->vm86) {
2390 /* XXX: optimize by finding processor state dynamically */
2391 if (s->cc_op != CC_OP_DYNAMIC)
2392 gen_op_set_cc_op(s->cc_op);
2393 gen_jmp_im(cur_eip);
2394 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2395 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2396 /* abort translation because the addseg value may change or
2397 because ss32 may change. For R_SS, translation must always
2398 stop as a special handling must be done to disable hardware
2399 interrupts for the next instruction */
2400 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2401 s->is_jmp = 3;
2402 } else {
2403 gen_op_movl_seg_T0_vm(seg_reg);
2404 if (seg_reg == R_SS)
2405 s->is_jmp = 3;
2406 }
2407 }
2408
2409 static inline int svm_is_rep(int prefixes)
2410 {
2411 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2412 }
2413
2414 static inline void
2415 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2416 uint32_t type, uint64_t param)
2417 {
2418 /* no SVM activated; fast case */
2419 if (likely(!(s->flags & HF_SVMI_MASK)))
2420 return;
2421 if (s->cc_op != CC_OP_DYNAMIC)
2422 gen_op_set_cc_op(s->cc_op);
2423 gen_jmp_im(pc_start - s->cs_base);
2424 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2425 tcg_const_i64(param));
2426 }
2427
2428 static inline void
2429 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2430 {
2431 gen_svm_check_intercept_param(s, pc_start, type, 0);
2432 }
2433
2434 static inline void gen_stack_update(DisasContext *s, int addend)
2435 {
2436 #ifdef TARGET_X86_64
2437 if (CODE64(s)) {
2438 gen_op_add_reg_im(2, R_ESP, addend);
2439 } else
2440 #endif
2441 if (s->ss32) {
2442 gen_op_add_reg_im(1, R_ESP, addend);
2443 } else {
2444 gen_op_add_reg_im(0, R_ESP, addend);
2445 }
2446 }
2447
2448 /* generate a push. It depends on ss32, addseg and dflag */
2449 static void gen_push_T0(DisasContext *s)
2450 {
2451 #ifdef TARGET_X86_64
2452 if (CODE64(s)) {
2453 gen_op_movq_A0_reg(R_ESP);
2454 if (s->dflag) {
2455 gen_op_addq_A0_im(-8);
2456 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2457 } else {
2458 gen_op_addq_A0_im(-2);
2459 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2460 }
2461 gen_op_mov_reg_A0(2, R_ESP);
2462 } else
2463 #endif
2464 {
2465 gen_op_movl_A0_reg(R_ESP);
2466 if (!s->dflag)
2467 gen_op_addl_A0_im(-2);
2468 else
2469 gen_op_addl_A0_im(-4);
2470 if (s->ss32) {
2471 if (s->addseg) {
2472 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2473 gen_op_addl_A0_seg(R_SS);
2474 }
2475 } else {
2476 gen_op_andl_A0_ffff();
2477 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2478 gen_op_addl_A0_seg(R_SS);
2479 }
2480 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2481 if (s->ss32 && !s->addseg)
2482 gen_op_mov_reg_A0(1, R_ESP);
2483 else
2484 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2485 }
2486 }
2487
2488 /* generate a push. It depends on ss32, addseg and dflag */
2489 /* slower version for T1, only used for call Ev */
2490 static void gen_push_T1(DisasContext *s)
2491 {
2492 #ifdef TARGET_X86_64
2493 if (CODE64(s)) {
2494 gen_op_movq_A0_reg(R_ESP);
2495 if (s->dflag) {
2496 gen_op_addq_A0_im(-8);
2497 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2498 } else {
2499 gen_op_addq_A0_im(-2);
2500 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2501 }
2502 gen_op_mov_reg_A0(2, R_ESP);
2503 } else
2504 #endif
2505 {
2506 gen_op_movl_A0_reg(R_ESP);
2507 if (!s->dflag)
2508 gen_op_addl_A0_im(-2);
2509 else
2510 gen_op_addl_A0_im(-4);
2511 if (s->ss32) {
2512 if (s->addseg) {
2513 gen_op_addl_A0_seg(R_SS);
2514 }
2515 } else {
2516 gen_op_andl_A0_ffff();
2517 gen_op_addl_A0_seg(R_SS);
2518 }
2519 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2520
2521 if (s->ss32 && !s->addseg)
2522 gen_op_mov_reg_A0(1, R_ESP);
2523 else
2524 gen_stack_update(s, (-2) << s->dflag);
2525 }
2526 }
2527
2528 /* two step pop is necessary for precise exceptions */
2529 static void gen_pop_T0(DisasContext *s)
2530 {
2531 #ifdef TARGET_X86_64
2532 if (CODE64(s)) {
2533 gen_op_movq_A0_reg(R_ESP);
2534 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2535 } else
2536 #endif
2537 {
2538 gen_op_movl_A0_reg(R_ESP);
2539 if (s->ss32) {
2540 if (s->addseg)
2541 gen_op_addl_A0_seg(R_SS);
2542 } else {
2543 gen_op_andl_A0_ffff();
2544 gen_op_addl_A0_seg(R_SS);
2545 }
2546 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2547 }
2548 }
2549
2550 static void gen_pop_update(DisasContext *s)
2551 {
2552 #ifdef TARGET_X86_64
2553 if (CODE64(s) && s->dflag) {
2554 gen_stack_update(s, 8);
2555 } else
2556 #endif
2557 {
2558 gen_stack_update(s, 2 << s->dflag);
2559 }
2560 }
2561
2562 static void gen_stack_A0(DisasContext *s)
2563 {
2564 gen_op_movl_A0_reg(R_ESP);
2565 if (!s->ss32)
2566 gen_op_andl_A0_ffff();
2567 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2568 if (s->addseg)
2569 gen_op_addl_A0_seg(R_SS);
2570 }
2571
2572 /* NOTE: wrap around in 16 bit not fully handled */
2573 static void gen_pusha(DisasContext *s)
2574 {
2575 int i;
2576 gen_op_movl_A0_reg(R_ESP);
2577 gen_op_addl_A0_im(-16 << s->dflag);
2578 if (!s->ss32)
2579 gen_op_andl_A0_ffff();
2580 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2581 if (s->addseg)
2582 gen_op_addl_A0_seg(R_SS);
2583 for(i = 0;i < 8; i++) {
2584 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2585 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2586 gen_op_addl_A0_im(2 << s->dflag);
2587 }
2588 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2589 }
2590
2591 /* NOTE: wrap around in 16 bit not fully handled */
2592 static void gen_popa(DisasContext *s)
2593 {
2594 int i;
2595 gen_op_movl_A0_reg(R_ESP);
2596 if (!s->ss32)
2597 gen_op_andl_A0_ffff();
2598 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2599 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2600 if (s->addseg)
2601 gen_op_addl_A0_seg(R_SS);
2602 for(i = 0;i < 8; i++) {
2603 /* ESP is not reloaded */
2604 if (i != 3) {
2605 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2606 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2607 }
2608 gen_op_addl_A0_im(2 << s->dflag);
2609 }
2610 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2611 }
2612
2613 static void gen_enter(DisasContext *s, int esp_addend, int level)
2614 {
2615 int ot, opsize;
2616
2617 level &= 0x1f;
2618 #ifdef TARGET_X86_64
2619 if (CODE64(s)) {
2620 ot = s->dflag ? OT_QUAD : OT_WORD;
2621 opsize = 1 << ot;
2622
2623 gen_op_movl_A0_reg(R_ESP);
2624 gen_op_addq_A0_im(-opsize);
2625 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2626
2627 /* push bp */
2628 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2629 gen_op_st_T0_A0(ot + s->mem_index);
2630 if (level) {
2631 /* XXX: must save state */
2632 gen_helper_enter64_level(tcg_const_i32(level),
2633 tcg_const_i32((ot == OT_QUAD)),
2634 cpu_T[1]);
2635 }
2636 gen_op_mov_reg_T1(ot, R_EBP);
2637 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2638 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2639 } else
2640 #endif
2641 {
2642 ot = s->dflag + OT_WORD;
2643 opsize = 2 << s->dflag;
2644
2645 gen_op_movl_A0_reg(R_ESP);
2646 gen_op_addl_A0_im(-opsize);
2647 if (!s->ss32)
2648 gen_op_andl_A0_ffff();
2649 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2650 if (s->addseg)
2651 gen_op_addl_A0_seg(R_SS);
2652 /* push bp */
2653 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2654 gen_op_st_T0_A0(ot + s->mem_index);
2655 if (level) {
2656 /* XXX: must save state */
2657 gen_helper_enter_level(tcg_const_i32(level),
2658 tcg_const_i32(s->dflag),
2659 cpu_T[1]);
2660 }
2661 gen_op_mov_reg_T1(ot, R_EBP);
2662 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2663 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2664 }
2665 }
2666
2667 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2668 {
2669 if (s->cc_op != CC_OP_DYNAMIC)
2670 gen_op_set_cc_op(s->cc_op);
2671 gen_jmp_im(cur_eip);
2672 gen_helper_raise_exception(tcg_const_i32(trapno));
2673 s->is_jmp = 3;
2674 }
2675
2676 /* an interrupt is different from an exception because of the
2677 privilege checks */
2678 static void gen_interrupt(DisasContext *s, int intno,
2679 target_ulong cur_eip, target_ulong next_eip)
2680 {
2681 if (s->cc_op != CC_OP_DYNAMIC)
2682 gen_op_set_cc_op(s->cc_op);
2683 gen_jmp_im(cur_eip);
2684 gen_helper_raise_interrupt(tcg_const_i32(intno),
2685 tcg_const_i32(next_eip - cur_eip));
2686 s->is_jmp = 3;
2687 }
2688
2689 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2690 {
2691 if (s->cc_op != CC_OP_DYNAMIC)
2692 gen_op_set_cc_op(s->cc_op);
2693 gen_jmp_im(cur_eip);
2694 gen_helper_debug();
2695 s->is_jmp = 3;
2696 }
2697
2698 /* generate a generic end of block. Trace exception is also generated
2699 if needed */
2700 static void gen_eob(DisasContext *s)
2701 {
2702 if (s->cc_op != CC_OP_DYNAMIC)
2703 gen_op_set_cc_op(s->cc_op);
2704 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2705 gen_helper_reset_inhibit_irq();
2706 }
2707 if (s->singlestep_enabled) {
2708 gen_helper_debug();
2709 } else if (s->tf) {
2710 gen_helper_single_step();
2711 } else {
2712 tcg_gen_exit_tb(0);
2713 }
2714 s->is_jmp = 3;
2715 }
2716
2717 /* generate a jump to eip. No segment change must happen before as a
2718 direct call to the next block may occur */
2719 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2720 {
2721 if (s->jmp_opt) {
2722 if (s->cc_op != CC_OP_DYNAMIC) {
2723 gen_op_set_cc_op(s->cc_op);
2724 s->cc_op = CC_OP_DYNAMIC;
2725 }
2726 gen_goto_tb(s, tb_num, eip);
2727 s->is_jmp = 3;
2728 } else {
2729 gen_jmp_im(eip);
2730 gen_eob(s);
2731 }
2732 }
2733
2734 static void gen_jmp(DisasContext *s, target_ulong eip)
2735 {
2736 gen_jmp_tb(s, eip, 0);
2737 }
2738
2739 static inline void gen_ldq_env_A0(int idx, int offset)
2740 {
2741 int mem_index = (idx >> 2) - 1;
2742 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2743 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2744 }
2745
2746 static inline void gen_stq_env_A0(int idx, int offset)
2747 {
2748 int mem_index = (idx >> 2) - 1;
2749 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2750 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2751 }
2752
2753 static inline void gen_ldo_env_A0(int idx, int offset)
2754 {
2755 int mem_index = (idx >> 2) - 1;
2756 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2757 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2758 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2759 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2760 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2761 }
2762
2763 static inline void gen_sto_env_A0(int idx, int offset)
2764 {
2765 int mem_index = (idx >> 2) - 1;
2766 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2767 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2768 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2769 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2770 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2771 }
2772
2773 static inline void gen_op_movo(int d_offset, int s_offset)
2774 {
2775 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2776 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2777 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2778 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2779 }
2780
2781 static inline void gen_op_movq(int d_offset, int s_offset)
2782 {
2783 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2784 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2785 }
2786
2787 static inline void gen_op_movl(int d_offset, int s_offset)
2788 {
2789 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2790 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2791 }
2792
2793 static inline void gen_op_movq_env_0(int d_offset)
2794 {
2795 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2796 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2797 }
2798
2799 #define SSE_SPECIAL ((void *)1)
2800 #define SSE_DUMMY ((void *)2)
2801
2802 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2803 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2804 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2805
2806 static void *sse_op_table1[256][4] = {
2807 /* 3DNow! extensions */
2808 [0x0e] = { SSE_DUMMY }, /* femms */
2809 [0x0f] = { SSE_DUMMY }, /* pf... */
2810 /* pure SSE operations */
2811 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2812 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2813 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2814 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2815 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2816 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2817 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2818 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2819
2820 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2821 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2822 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2823 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2824 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2825 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2826 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2827 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2828 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2829 [0x51] = SSE_FOP(sqrt),
2830 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2831 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2832 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2833 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2834 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2835 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2836 [0x58] = SSE_FOP(add),
2837 [0x59] = SSE_FOP(mul),
2838 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2839 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2840 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2841 [0x5c] = SSE_FOP(sub),
2842 [0x5d] = SSE_FOP(min),
2843 [0x5e] = SSE_FOP(div),
2844 [0x5f] = SSE_FOP(max),
2845
2846 [0xc2] = SSE_FOP(cmpeq),
2847 [0xc6] = { gen_helper_shufps, gen_helper_shufpd },
2848
2849 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2850 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2851
2852 /* MMX ops and their SSE extensions */
2853 [0x60] = MMX_OP2(punpcklbw),
2854 [0x61] = MMX_OP2(punpcklwd),
2855 [0x62] = MMX_OP2(punpckldq),
2856 [0x63] = MMX_OP2(packsswb),
2857 [0x64] = MMX_OP2(pcmpgtb),
2858 [0x65] = MMX_OP2(pcmpgtw),
2859 [0x66] = MMX_OP2(pcmpgtl),
2860 [0x67] = MMX_OP2(packuswb),
2861 [0x68] = MMX_OP2(punpckhbw),
2862 [0x69] = MMX_OP2(punpckhwd),
2863 [0x6a] = MMX_OP2(punpckhdq),
2864 [0x6b] = MMX_OP2(packssdw),
2865 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2866 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2867 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2868 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2869 [0x70] = { gen_helper_pshufw_mmx,
2870 gen_helper_pshufd_xmm,
2871 gen_helper_pshufhw_xmm,
2872 gen_helper_pshuflw_xmm },
2873 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2874 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2875 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2876 [0x74] = MMX_OP2(pcmpeqb),
2877 [0x75] = MMX_OP2(pcmpeqw),
2878 [0x76] = MMX_OP2(pcmpeql),
2879 [0x77] = { SSE_DUMMY }, /* emms */
2880 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2881 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2882 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2883 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2884 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2885 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2886 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2887 [0xd1] = MMX_OP2(psrlw),
2888 [0xd2] = MMX_OP2(psrld),
2889 [0xd3] = MMX_OP2(psrlq),
2890 [0xd4] = MMX_OP2(paddq),
2891 [0xd5] = MMX_OP2(pmullw),
2892 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2893 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2894 [0xd8] = MMX_OP2(psubusb),
2895 [0xd9] = MMX_OP2(psubusw),
2896 [0xda] = MMX_OP2(pminub),
2897 [0xdb] = MMX_OP2(pand),
2898 [0xdc] = MMX_OP2(paddusb),
2899 [0xdd] = MMX_OP2(paddusw),
2900 [0xde] = MMX_OP2(pmaxub),
2901 [0xdf] = MMX_OP2(pandn),
2902 [0xe0] = MMX_OP2(pavgb),
2903 [0xe1] = MMX_OP2(psraw),
2904 [0xe2] = MMX_OP2(psrad),
2905 [0xe3] = MMX_OP2(pavgw),
2906 [0xe4] = MMX_OP2(pmulhuw),
2907 [0xe5] = MMX_OP2(pmulhw),
2908 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2909 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2910 [0xe8] = MMX_OP2(psubsb),
2911 [0xe9] = MMX_OP2(psubsw),
2912 [0xea] = MMX_OP2(pminsw),
2913 [0xeb] = MMX_OP2(por),
2914 [0xec] = MMX_OP2(paddsb),
2915 [0xed] = MMX_OP2(paddsw),
2916 [0xee] = MMX_OP2(pmaxsw),
2917 [0xef] = MMX_OP2(pxor),
2918 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2919 [0xf1] = MMX_OP2(psllw),
2920 [0xf2] = MMX_OP2(pslld),
2921 [0xf3] = MMX_OP2(psllq),
2922 [0xf4] = MMX_OP2(pmuludq),
2923 [0xf5] = MMX_OP2(pmaddwd),
2924 [0xf6] = MMX_OP2(psadbw),
2925 [0xf7] = MMX_OP2(maskmov),
2926 [0xf8] = MMX_OP2(psubb),
2927 [0xf9] = MMX_OP2(psubw),
2928 [0xfa] = MMX_OP2(psubl),
2929 [0xfb] = MMX_OP2(psubq),
2930 [0xfc] = MMX_OP2(paddb),
2931 [0xfd] = MMX_OP2(paddw),
2932 [0xfe] = MMX_OP2(paddl),
2933 };
2934
2935 static void *sse_op_table2[3 * 8][2] = {
2936 [0 + 2] = MMX_OP2(psrlw),
2937 [0 + 4] = MMX_OP2(psraw),
2938 [0 + 6] = MMX_OP2(psllw),
2939 [8 + 2] = MMX_OP2(psrld),
2940 [8 + 4] = MMX_OP2(psrad),
2941 [8 + 6] = MMX_OP2(pslld),
2942 [16 + 2] = MMX_OP2(psrlq),
2943 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2944 [16 + 6] = MMX_OP2(psllq),
2945 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2946 };
2947
2948 static void *sse_op_table3[4 * 3] = {
2949 gen_helper_cvtsi2ss,
2950 gen_helper_cvtsi2sd,
2951 X86_64_ONLY(gen_helper_cvtsq2ss),
2952 X86_64_ONLY(gen_helper_cvtsq2sd),
2953
2954 gen_helper_cvttss2si,
2955 gen_helper_cvttsd2si,
2956 X86_64_ONLY(gen_helper_cvttss2sq),
2957 X86_64_ONLY(gen_helper_cvttsd2sq),
2958
2959 gen_helper_cvtss2si,
2960 gen_helper_cvtsd2si,
2961 X86_64_ONLY(gen_helper_cvtss2sq),
2962 X86_64_ONLY(gen_helper_cvtsd2sq),
2963 };
2964
2965 static void *sse_op_table4[8][4] = {
2966 SSE_FOP(cmpeq),
2967 SSE_FOP(cmplt),
2968 SSE_FOP(cmple),
2969 SSE_FOP(cmpunord),
2970 SSE_FOP(cmpneq),
2971 SSE_FOP(cmpnlt),
2972 SSE_FOP(cmpnle),
2973 SSE_FOP(cmpord),
2974 };
2975
2976 static void *sse_op_table5[256] = {
2977 [0x0c] = gen_helper_pi2fw,
2978 [0x0d] = gen_helper_pi2fd,
2979 [0x1c] = gen_helper_pf2iw,
2980 [0x1d] = gen_helper_pf2id,
2981 [0x8a] = gen_helper_pfnacc,
2982 [0x8e] = gen_helper_pfpnacc,
2983 [0x90] = gen_helper_pfcmpge,
2984 [0x94] = gen_helper_pfmin,
2985 [0x96] = gen_helper_pfrcp,
2986 [0x97] = gen_helper_pfrsqrt,
2987 [0x9a] = gen_helper_pfsub,
2988 [0x9e] = gen_helper_pfadd,
2989 [0xa0] = gen_helper_pfcmpgt,
2990 [0xa4] = gen_helper_pfmax,
2991 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
2992 [0xa7] = gen_helper_movq, /* pfrsqit1 */
2993 [0xaa] = gen_helper_pfsubr,
2994 [0xae] = gen_helper_pfacc,
2995 [0xb0] = gen_helper_pfcmpeq,
2996 [0xb4] = gen_helper_pfmul,
2997 [0xb6] = gen_helper_movq, /* pfrcpit2 */
2998 [0xb7] = gen_helper_pmulhrw_mmx,
2999 [0xbb] = gen_helper_pswapd,
3000 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3001 };
3002
3003 struct sse_op_helper_s {
3004 void *op[2]; uint32_t ext_mask;
3005 };
3006 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3007 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3008 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3009 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3010 static struct sse_op_helper_s sse_op_table6[256] = {
3011 [0x00] = SSSE3_OP(pshufb),
3012 [0x01] = SSSE3_OP(phaddw),
3013 [0x02] = SSSE3_OP(phaddd),
3014 [0x03] = SSSE3_OP(phaddsw),
3015 [0x04] = SSSE3_OP(pmaddubsw),
3016 [0x05] = SSSE3_OP(phsubw),
3017 [0x06] = SSSE3_OP(phsubd),
3018 [0x07] = SSSE3_OP(phsubsw),
3019 [0x08] = SSSE3_OP(psignb),
3020 [0x09] = SSSE3_OP(psignw),
3021 [0x0a] = SSSE3_OP(psignd),
3022 [0x0b] = SSSE3_OP(pmulhrsw),
3023 [0x10] = SSE41_OP(pblendvb),
3024 [0x14] = SSE41_OP(blendvps),
3025 [0x15] = SSE41_OP(blendvpd),
3026 [0x17] = SSE41_OP(ptest),
3027 [0x1c] = SSSE3_OP(pabsb),
3028 [0x1d] = SSSE3_OP(pabsw),
3029 [0x1e] = SSSE3_OP(pabsd),
3030 [0x20] = SSE41_OP(pmovsxbw),
3031 [0x21] = SSE41_OP(pmovsxbd),
3032 [0x22] = SSE41_OP(pmovsxbq),
3033 [0x23] = SSE41_OP(pmovsxwd),
3034 [0x24] = SSE41_OP(pmovsxwq),
3035 [0x25] = SSE41_OP(pmovsxdq),
3036 [0x28] = SSE41_OP(pmuldq),
3037 [0x29] = SSE41_OP(pcmpeqq),
3038 [0x2a] = SSE41_SPECIAL, /* movntqda */
3039 [0x2b] = SSE41_OP(packusdw),
3040 [0x30] = SSE41_OP(pmovzxbw),
3041 [0x31] = SSE41_OP(pmovzxbd),
3042 [0x32] = SSE41_OP(pmovzxbq),
3043 [0x33] = SSE41_OP(pmovzxwd),
3044 [0x34] = SSE41_OP(pmovzxwq),
3045 [0x35] = SSE41_OP(pmovzxdq),
3046 [0x37] = SSE42_OP(pcmpgtq),
3047 [0x38] = SSE41_OP(pminsb),
3048 [0x39] = SSE41_OP(pminsd),
3049 [0x3a] = SSE41_OP(pminuw),
3050 [0x3b] = SSE41_OP(pminud),
3051 [0x3c] = SSE41_OP(pmaxsb),
3052 [0x3d] = SSE41_OP(pmaxsd),
3053 [0x3e] = SSE41_OP(pmaxuw),
3054 [0x3f] = SSE41_OP(pmaxud),
3055 [0x40] = SSE41_OP(pmulld),
3056 [0x41] = SSE41_OP(phminposuw),
3057 };
3058
3059 static struct sse_op_helper_s sse_op_table7[256] = {
3060 [0x08] = SSE41_OP(roundps),
3061 [0x09] = SSE41_OP(roundpd),
3062 [0x0a] = SSE41_OP(roundss),
3063 [0x0b] = SSE41_OP(roundsd),
3064 [0x0c] = SSE41_OP(blendps),
3065 [0x0d] = SSE41_OP(blendpd),
3066 [0x0e] = SSE41_OP(pblendw),
3067 [0x0f] = SSSE3_OP(palignr),
3068 [0x14] = SSE41_SPECIAL, /* pextrb */
3069 [0x15] = SSE41_SPECIAL, /* pextrw */
3070 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3071 [0x17] = SSE41_SPECIAL, /* extractps */
3072 [0x20] = SSE41_SPECIAL, /* pinsrb */
3073 [0x21] = SSE41_SPECIAL, /* insertps */
3074 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3075 [0x40] = SSE41_OP(dpps),
3076 [0x41] = SSE41_OP(dppd),
3077 [0x42] = SSE41_OP(mpsadbw),
3078 [0x60] = SSE42_OP(pcmpestrm),
3079 [0x61] = SSE42_OP(pcmpestri),
3080 [0x62] = SSE42_OP(pcmpistrm),
3081 [0x63] = SSE42_OP(pcmpistri),
3082 };
3083
3084 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3085 {
3086 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3087 int modrm, mod, rm, reg, reg_addr, offset_addr;
3088 void *sse_op2;
3089
3090 b &= 0xff;
3091 if (s->prefix & PREFIX_DATA)
3092 b1 = 1;
3093 else if (s->prefix & PREFIX_REPZ)
3094 b1 = 2;
3095 else if (s->prefix & PREFIX_REPNZ)
3096 b1 = 3;
3097 else
3098 b1 = 0;
3099 sse_op2 = sse_op_table1[b][b1];
3100 if (!sse_op2)
3101 goto illegal_op;
3102 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3103 is_xmm = 1;
3104 } else {
3105 if (b1 == 0) {
3106 /* MMX case */
3107 is_xmm = 0;
3108 } else {
3109 is_xmm = 1;
3110 }
3111 }
3112 /* simple MMX/SSE operation */
3113 if (s->flags & HF_TS_MASK) {
3114 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3115 return;
3116 }
3117 if (s->flags & HF_EM_MASK) {
3118 illegal_op:
3119 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3120 return;
3121 }
3122 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3123 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3124 goto illegal_op;
3125 if (b == 0x0e) {
3126 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3127 goto illegal_op;
3128 /* femms */
3129 gen_helper_emms();
3130 return;
3131 }
3132 if (b == 0x77) {
3133 /* emms */
3134 gen_helper_emms();
3135 return;
3136 }
3137 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3138 the static cpu state) */
3139 if (!is_xmm) {
3140 gen_helper_enter_mmx();
3141 }
3142
3143 modrm = ldub_code(s->pc++);
3144 reg = ((modrm >> 3) & 7);
3145 if (is_xmm)
3146 reg |= rex_r;
3147 mod = (modrm >> 6) & 3;
3148 if (sse_op2 == SSE_SPECIAL) {
3149 b |= (b1 << 8);
3150 switch(b) {
3151 case 0x0e7: /* movntq */
3152 if (mod == 3)
3153 goto illegal_op;
3154 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3155 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3156 break;
3157 case 0x1e7: /* movntdq */
3158 case 0x02b: /* movntps */
3159 case 0x12b: /* movntps */
3160 case 0x3f0: /* lddqu */
3161 if (mod == 3)
3162 goto illegal_op;
3163 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3164 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3165 break;
3166 case 0x6e: /* movd mm, ea */
3167 #ifdef TARGET_X86_64
3168 if (s->dflag == 2) {
3169 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3170 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3171 } else
3172 #endif
3173 {
3174 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3175 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3176 offsetof(CPUX86State,fpregs[reg].mmx));
3177 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3178 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3179 }
3180 break;
3181 case 0x16e: /* movd xmm, ea */
3182 #ifdef TARGET_X86_64
3183 if (s->dflag == 2) {
3184 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3185 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3186 offsetof(CPUX86State,xmm_regs[reg]));
3187 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3188 } else
3189 #endif
3190 {
3191 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3192 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3193 offsetof(CPUX86State,xmm_regs[reg]));
3194 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3195 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3196 }
3197 break;
3198 case 0x6f: /* movq mm, ea */
3199 if (mod != 3) {
3200 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3201 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3202 } else {
3203 rm = (modrm & 7);
3204 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3205 offsetof(CPUX86State,fpregs[rm].mmx));
3206 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3207 offsetof(CPUX86State,fpregs[reg].mmx));
3208 }
3209 break;
3210 case 0x010: /* movups */
3211 case 0x110: /* movupd */
3212 case 0x028: /* movaps */
3213 case 0x128: /* movapd */
3214 case 0x16f: /* movdqa xmm, ea */
3215 case 0x26f: /* movdqu xmm, ea */
3216 if (mod != 3) {
3217 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3218 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3219 } else {
3220 rm = (modrm & 7) | REX_B(s);
3221 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3222 offsetof(CPUX86State,xmm_regs[rm]));
3223 }
3224 break;
3225 case 0x210: /* movss xmm, ea */
3226 if (mod != 3) {
3227 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3228 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3229 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3230 gen_op_movl_T0_0();
3231 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3232 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3233 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3234 } else {
3235 rm = (modrm & 7) | REX_B(s);
3236 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3237 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3238 }
3239 break;
3240 case 0x310: /* movsd xmm, ea */
3241 if (mod != 3) {
3242 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3243 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3244 gen_op_movl_T0_0();
3245 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3246 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3247 } else {
3248 rm = (modrm & 7) | REX_B(s);
3249 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3250 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3251 }
3252 break;
3253 case 0x012: /* movlps */
3254 case 0x112: /* movlpd */
3255 if (mod != 3) {
3256 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3257 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3258 } else {
3259 /* movhlps */
3260 rm = (modrm & 7) | REX_B(s);
3261 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3262 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3263 }
3264 break;
3265 case 0x212: /* movsldup */
3266 if (mod != 3) {
3267 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3268 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3269 } else {
3270 rm = (modrm & 7) | REX_B(s);
3271 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3272 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3273 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3274 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3275 }
3276 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3277 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3278 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3279 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3280 break;
3281 case 0x312: /* movddup */
3282 if (mod != 3) {
3283 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3284 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3285 } else {
3286 rm = (modrm & 7) | REX_B(s);
3287 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3288 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3289 }
3290 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3291 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3292 break;
3293 case 0x016: /* movhps */
3294 case 0x116: /* movhpd */
3295 if (mod != 3) {
3296 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3297 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3298 } else {
3299 /* movlhps */
3300 rm = (modrm & 7) | REX_B(s);
3301 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3302 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3303 }
3304 break;
3305 case 0x216: /* movshdup */
3306 if (mod != 3) {
3307 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3308 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3309 } else {
3310 rm = (modrm & 7) | REX_B(s);
3311 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3312 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3313 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3314 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3315 }
3316 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3317 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3318 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3319 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3320 break;
3321 case 0x7e: /* movd ea, mm */
3322 #ifdef TARGET_X86_64
3323 if (s->dflag == 2) {
3324 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3325 offsetof(CPUX86State,fpregs[reg].mmx));
3326 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3327 } else
3328 #endif
3329 {
3330 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3331 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3332 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3333 }
3334 break;
3335 case 0x17e: /* movd ea, xmm */
3336 #ifdef TARGET_X86_64
3337 if (s->dflag == 2) {
3338 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3339 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3340 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3341 } else
3342 #endif
3343 {
3344 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3345 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3346 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3347 }
3348 break;
3349 case 0x27e: /* movq xmm, ea */
3350 if (mod != 3) {
3351 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3352 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3353 } else {
3354 rm = (modrm & 7) | REX_B(s);
3355 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3356 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3357 }
3358 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3359 break;
3360 case 0x7f: /* movq ea, mm */
3361 if (mod != 3) {
3362 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3363 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3364 } else {
3365 rm = (modrm & 7);
3366 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3367 offsetof(CPUX86State,fpregs[reg].mmx));
3368 }
3369 break;
3370 case 0x011: /* movups */
3371 case 0x111: /* movupd */
3372 case 0x029: /* movaps */
3373 case 0x129: /* movapd */
3374 case 0x17f: /* movdqa ea, xmm */
3375 case 0x27f: /* movdqu ea, xmm */
3376 if (mod != 3) {
3377 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3378 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3379 } else {
3380 rm = (modrm & 7) | REX_B(s);
3381 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3382 offsetof(CPUX86State,xmm_regs[reg]));
3383 }
3384 break;
3385 case 0x211: /* movss ea, xmm */
3386 if (mod != 3) {
3387 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3388 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3389 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3390 } else {
3391 rm = (modrm & 7) | REX_B(s);
3392 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3393 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3394 }
3395 break;
3396 case 0x311: /* movsd ea, xmm */
3397 if (mod != 3) {
3398 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3399 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3400 } else {
3401 rm = (modrm & 7) | REX_B(s);
3402 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3403 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3404 }
3405 break;
3406 case 0x013: /* movlps */
3407 case 0x113: /* movlpd */
3408 if (mod != 3) {
3409 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3410 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3411 } else {
3412 goto illegal_op;
3413 }
3414 break;
3415 case 0x017: /* movhps */
3416 case 0x117: /* movhpd */
3417 if (mod != 3) {
3418 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3419 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3420 } else {
3421 goto illegal_op;
3422 }
3423 break;
3424 case 0x71: /* shift mm, im */
3425 case 0x72:
3426 case 0x73:
3427 case 0x171: /* shift xmm, im */
3428 case 0x172:
3429 case 0x173:
3430 val = ldub_code(s->pc++);
3431 if (is_xmm) {
3432 gen_op_movl_T0_im(val);
3433 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3434 gen_op_movl_T0_0();
3435 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3436 op1_offset = offsetof(CPUX86State,xmm_t0);
3437 } else {
3438 gen_op_movl_T0_im(val);
3439 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3440 gen_op_movl_T0_0();
3441 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3442 op1_offset = offsetof(CPUX86State,mmx_t0);
3443 }
3444 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3445 if (!sse_op2)
3446 goto illegal_op;
3447 if (is_xmm) {
3448 rm = (modrm & 7) | REX_B(s);
3449 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3450 } else {
3451 rm = (modrm & 7);
3452 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3453 }
3454 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3455 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3456 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3457 break;
3458 case 0x050: /* movmskps */
3459 rm = (modrm & 7) | REX_B(s);
3460 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3461 offsetof(CPUX86State,xmm_regs[rm]));
3462 gen_helper_movmskps(cpu_tmp2_i32, cpu_ptr0);
3463 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3464 gen_op_mov_reg_T0(OT_LONG, reg);
3465 break;
3466 case 0x150: /* movmskpd */
3467 rm = (modrm & 7) | REX_B(s);
3468 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3469 offsetof(CPUX86State,xmm_regs[rm]));
3470 gen_helper_movmskpd(cpu_tmp2_i32, cpu_ptr0);
3471 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3472 gen_op_mov_reg_T0(OT_LONG, reg);
3473 break;
3474 case 0x02a: /* cvtpi2ps */
3475 case 0x12a: /* cvtpi2pd */
3476 gen_helper_enter_mmx();
3477 if (mod != 3) {
3478 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3479 op2_offset = offsetof(CPUX86State,mmx_t0);
3480 gen_ldq_env_A0(s->mem_index, op2_offset);
3481 } else {
3482 rm = (modrm & 7);
3483 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3484 }
3485 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3486 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3487 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3488 switch(b >> 8) {
3489 case 0x0:
3490 gen_helper_cvtpi2ps(cpu_ptr0, cpu_ptr1);
3491 break;
3492 default:
3493 case 0x1:
3494 gen_helper_cvtpi2pd(cpu_ptr0, cpu_ptr1);
3495 break;
3496 }
3497 break;
3498 case 0x22a: /* cvtsi2ss */
3499 case 0x32a: /* cvtsi2sd */
3500 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3501 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3502 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3503 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3504 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3505 if (ot == OT_LONG) {
3506 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3507 ((void (*)(TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_tmp2_i32);
3508 } else {
3509 ((void (*)(TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_T[0]);
3510 }
3511 break;
3512 case 0x02c: /* cvttps2pi */
3513 case 0x12c: /* cvttpd2pi */
3514 case 0x02d: /* cvtps2pi */
3515 case 0x12d: /* cvtpd2pi */
3516 gen_helper_enter_mmx();
3517 if (mod != 3) {
3518 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3519 op2_offset = offsetof(CPUX86State,xmm_t0);
3520 gen_ldo_env_A0(s->mem_index, op2_offset);
3521 } else {
3522 rm = (modrm & 7) | REX_B(s);
3523 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3524 }
3525 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3526 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3527 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3528 switch(b) {
3529 case 0x02c:
3530 gen_helper_cvttps2pi(cpu_ptr0, cpu_ptr1);
3531 break;
3532 case 0x12c:
3533 gen_helper_cvttpd2pi(cpu_ptr0, cpu_ptr1);
3534 break;
3535 case 0x02d:
3536 gen_helper_cvtps2pi(cpu_ptr0, cpu_ptr1);
3537 break;
3538 case 0x12d:
3539 gen_helper_cvtpd2pi(cpu_ptr0, cpu_ptr1);
3540 break;
3541 }
3542 break;
3543 case 0x22c: /* cvttss2si */
3544 case 0x32c: /* cvttsd2si */
3545 case 0x22d: /* cvtss2si */
3546 case 0x32d: /* cvtsd2si */
3547 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3548 if (mod != 3) {
3549 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3550 if ((b >> 8) & 1) {
3551 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3552 } else {
3553 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3554 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3555 }
3556 op2_offset = offsetof(CPUX86State,xmm_t0);
3557 } else {
3558 rm = (modrm & 7) | REX_B(s);
3559 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3560 }
3561 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3562 (b & 1) * 4];
3563 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3564 if (ot == OT_LONG) {
3565 ((void (*)(TCGv_i32, TCGv_ptr))sse_op2)(cpu_tmp2_i32, cpu_ptr0);
3566 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3567 } else {
3568 ((void (*)(TCGv, TCGv_ptr))sse_op2)(cpu_T[0], cpu_ptr0);
3569 }
3570 gen_op_mov_reg_T0(ot, reg);
3571 break;
3572 case 0xc4: /* pinsrw */
3573 case 0x1c4:
3574 s->rip_offset = 1;
3575 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3576 val = ldub_code(s->pc++);
3577 if (b1) {
3578 val &= 7;
3579 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3580 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3581 } else {
3582 val &= 3;
3583 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3584 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3585 }
3586 break;
3587 case 0xc5: /* pextrw */
3588 case 0x1c5:
3589 if (mod != 3)
3590 goto illegal_op;
3591 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3592 val = ldub_code(s->pc++);
3593 if (b1) {
3594 val &= 7;
3595 rm = (modrm & 7) | REX_B(s);
3596 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3597 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3598 } else {
3599 val &= 3;
3600 rm = (modrm & 7);
3601 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3602 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3603 }
3604 reg = ((modrm >> 3) & 7) | rex_r;
3605 gen_op_mov_reg_T0(ot, reg);
3606 break;
3607 case 0x1d6: /* movq ea, xmm */
3608 if (mod != 3) {
3609 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3610 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3611 } else {
3612 rm = (modrm & 7) | REX_B(s);
3613 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3614 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3615 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3616 }
3617 break;
3618 case 0x2d6: /* movq2dq */
3619 gen_helper_enter_mmx();
3620 rm = (modrm & 7);
3621 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3622 offsetof(CPUX86State,fpregs[rm].mmx));
3623 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3624 break;
3625 case 0x3d6: /* movdq2q */
3626 gen_helper_enter_mmx();
3627 rm = (modrm & 7) | REX_B(s);
3628 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3629 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3630 break;
3631 case 0xd7: /* pmovmskb */
3632 case 0x1d7:
3633 if (mod != 3)
3634 goto illegal_op;
3635 if (b1) {
3636 rm = (modrm & 7) | REX_B(s);
3637 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3638 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_ptr0);
3639 } else {
3640 rm = (modrm & 7);
3641 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3642 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_ptr0);
3643 }
3644 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3645 reg = ((modrm >> 3) & 7) | rex_r;
3646 gen_op_mov_reg_T0(OT_LONG, reg);
3647 break;
3648 case 0x138:
3649 if (s->prefix & PREFIX_REPNZ)
3650 goto crc32;
3651 case 0x038:
3652 b = modrm;
3653 modrm = ldub_code(s->pc++);
3654 rm = modrm & 7;
3655 reg = ((modrm >> 3) & 7) | rex_r;
3656 mod = (modrm >> 6) & 3;
3657
3658 sse_op2 = sse_op_table6[b].op[b1];
3659 if (!sse_op2)
3660 goto illegal_op;
3661 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3662 goto illegal_op;
3663
3664 if (b1) {
3665 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3666 if (mod == 3) {
3667 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3668 } else {
3669 op2_offset = offsetof(CPUX86State,xmm_t0);
3670 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3671 switch (b) {
3672 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3673 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3674 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3675 gen_ldq_env_A0(s->mem_index, op2_offset +
3676 offsetof(XMMReg, XMM_Q(0)));
3677 break;
3678 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3679 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3680 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3681 (s->mem_index >> 2) - 1);
3682 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3683 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3684 offsetof(XMMReg, XMM_L(0)));
3685 break;
3686 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3687 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3688 (s->mem_index >> 2) - 1);
3689 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3690 offsetof(XMMReg, XMM_W(0)));
3691 break;
3692 case 0x2a: /* movntqda */
3693 gen_ldo_env_A0(s->mem_index, op1_offset);
3694 return;
3695 default:
3696 gen_ldo_env_A0(s->mem_index, op2_offset);
3697 }
3698 }
3699 } else {
3700 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3701 if (mod == 3) {
3702 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3703 } else {
3704 op2_offset = offsetof(CPUX86State,mmx_t0);
3705 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3706 gen_ldq_env_A0(s->mem_index, op2_offset);
3707 }
3708 }
3709 if (sse_op2 == SSE_SPECIAL)
3710 goto illegal_op;
3711
3712 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3713 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3714 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3715
3716 if (b == 0x17)
3717 s->cc_op = CC_OP_EFLAGS;
3718 break;
3719 case 0x338: /* crc32 */
3720 crc32:
3721 b = modrm;
3722 modrm = ldub_code(s->pc++);
3723 reg = ((modrm >> 3) & 7) | rex_r;
3724
3725 if (b != 0xf0 && b != 0xf1)
3726 goto illegal_op;
3727 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3728 goto illegal_op;
3729
3730 if (b == 0xf0)
3731 ot = OT_BYTE;
3732 else if (b == 0xf1 && s->dflag != 2)
3733 if (s->prefix & PREFIX_DATA)
3734 ot = OT_WORD;
3735 else
3736 ot = OT_LONG;
3737 else
3738 ot = OT_QUAD;
3739
3740 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3741 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3742 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3743 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3744 cpu_T[0], tcg_const_i32(8 << ot));
3745
3746 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3747 gen_op_mov_reg_T0(ot, reg);
3748 break;
3749 case 0x03a:
3750 case 0x13a:
3751 b = modrm;
3752 modrm = ldub_code(s->pc++);
3753 rm = modrm & 7;
3754 reg = ((modrm >> 3) & 7) | rex_r;
3755 mod = (modrm >> 6) & 3;
3756
3757 sse_op2 = sse_op_table7[b].op[b1];
3758 if (!sse_op2)
3759 goto illegal_op;
3760 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3761 goto illegal_op;
3762
3763 if (sse_op2 == SSE_SPECIAL) {
3764 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3765 rm = (modrm & 7) | REX_B(s);
3766 if (mod != 3)
3767 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3768 reg = ((modrm >> 3) & 7) | rex_r;
3769 val = ldub_code(s->pc++);
3770 switch (b) {
3771 case 0x14: /* pextrb */
3772 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3773 xmm_regs[reg].XMM_B(val & 15)));
3774 if (mod == 3)
3775 gen_op_mov_reg_T0(ot, rm);
3776 else
3777 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3778 (s->mem_index >> 2) - 1);
3779 break;
3780 case 0x15: /* pextrw */
3781 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3782 xmm_regs[reg].XMM_W(val & 7)));
3783 if (mod == 3)
3784 gen_op_mov_reg_T0(ot, rm);
3785 else
3786 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3787 (s->mem_index >> 2) - 1);
3788 break;
3789 case 0x16:
3790 if (ot == OT_LONG) { /* pextrd */
3791 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3792 offsetof(CPUX86State,
3793 xmm_regs[reg].XMM_L(val & 3)));
3794 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3795 if (mod == 3)
3796 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3797 else
3798 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3799 (s->mem_index >> 2) - 1);
3800 } else { /* pextrq */
3801 #ifdef TARGET_X86_64
3802 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3803 offsetof(CPUX86State,
3804 xmm_regs[reg].XMM_Q(val & 1)));
3805 if (mod == 3)
3806 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3807 else
3808 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3809 (s->mem_index >> 2) - 1);
3810 #else
3811 goto illegal_op;
3812 #endif
3813 }
3814 break;
3815 case 0x17: /* extractps */
3816 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3817 xmm_regs[reg].XMM_L(val & 3)));
3818 if (mod == 3)
3819 gen_op_mov_reg_T0(ot, rm);
3820 else
3821 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3822 (s->mem_index >> 2) - 1);
3823 break;
3824 case 0x20: /* pinsrb */
3825 if (mod == 3)
3826 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3827 else
3828 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3829 (s->mem_index >> 2) - 1);
3830 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3831 xmm_regs[reg].XMM_B(val & 15)));
3832 break;
3833 case 0x21: /* insertps */
3834 if (mod == 3) {
3835 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3836 offsetof(CPUX86State,xmm_regs[rm]
3837 .XMM_L((val >> 6) & 3)));
3838 } else {
3839 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3840 (s->mem_index >> 2) - 1);
3841 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3842 }
3843 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3844 offsetof(CPUX86State,xmm_regs[reg]
3845 .XMM_L((val >> 4) & 3)));
3846 if ((val >> 0) & 1)
3847 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3848 cpu_env, offsetof(CPUX86State,
3849 xmm_regs[reg].XMM_L(0)));
3850 if ((val >> 1) & 1)
3851 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3852 cpu_env, offsetof(CPUX86State,
3853 xmm_regs[reg].XMM_L(1)));
3854 if ((val >> 2) & 1)
3855 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3856 cpu_env, offsetof(CPUX86State,
3857 xmm_regs[reg].XMM_L(2)));
3858 if ((val >> 3) & 1)
3859 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3860 cpu_env, offsetof(CPUX86State,
3861 xmm_regs[reg].XMM_L(3)));
3862 break;
3863 case 0x22:
3864 if (ot == OT_LONG) { /* pinsrd */
3865 if (mod == 3)
3866 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3867 else
3868 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3869 (s->mem_index >> 2) - 1);
3870 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3871 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3872 offsetof(CPUX86State,
3873 xmm_regs[reg].XMM_L(val & 3)));
3874 } else { /* pinsrq */
3875 #ifdef TARGET_X86_64
3876 if (mod == 3)
3877 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3878 else
3879 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3880 (s->mem_index >> 2) - 1);
3881 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3882 offsetof(CPUX86State,
3883 xmm_regs[reg].XMM_Q(val & 1)));
3884 #else
3885 goto illegal_op;
3886 #endif
3887 }
3888 break;
3889 }
3890 return;
3891 }
3892
3893 if (b1) {
3894 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3895 if (mod == 3) {
3896 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3897 } else {
3898 op2_offset = offsetof(CPUX86State,xmm_t0);
3899 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3900 gen_ldo_env_A0(s->mem_index, op2_offset);
3901 }
3902 } else {
3903 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3904 if (mod == 3) {
3905 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3906 } else {
3907 op2_offset = offsetof(CPUX86State,mmx_t0);
3908 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3909 gen_ldq_env_A0(s->mem_index, op2_offset);
3910 }
3911 }
3912 val = ldub_code(s->pc++);
3913
3914 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
3915 s->cc_op = CC_OP_EFLAGS;
3916
3917 if (s->dflag == 2)
3918 /* The helper must use entire 64-bit gp registers */
3919 val |= 1 << 8;
3920 }
3921
3922 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3923 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3924 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3925 break;
3926 default:
3927 goto illegal_op;
3928 }
3929 } else {
3930 /* generic MMX or SSE operation */
3931 switch(b) {
3932 case 0x70: /* pshufx insn */
3933 case 0xc6: /* pshufx insn */
3934 case 0xc2: /* compare insns */
3935 s->rip_offset = 1;
3936 break;
3937 default:
3938 break;
3939 }
3940 if (is_xmm) {
3941 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3942 if (mod != 3) {
3943 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3944 op2_offset = offsetof(CPUX86State,xmm_t0);
3945 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3946 b == 0xc2)) {
3947 /* specific case for SSE single instructions */
3948 if (b1 == 2) {
3949 /* 32 bit access */
3950 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3951 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3952 } else {
3953 /* 64 bit access */
3954 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3955 }
3956 } else {
3957 gen_ldo_env_A0(s->mem_index, op2_offset);
3958 }
3959 } else {
3960 rm = (modrm & 7) | REX_B(s);
3961 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3962 }
3963 } else {
3964 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3965 if (mod != 3) {
3966 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3967 op2_offset = offsetof(CPUX86State,mmx_t0);
3968 gen_ldq_env_A0(s->mem_index, op2_offset);
3969 } else {
3970 rm = (modrm & 7);
3971 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3972 }
3973 }
3974 switch(b) {
3975 case 0x0f: /* 3DNow! data insns */
3976 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3977 goto illegal_op;
3978 val = ldub_code(s->pc++);
3979 sse_op2 = sse_op_table5[val];
3980 if (!sse_op2)
3981 goto illegal_op;
3982 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3983 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3984 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
3985 break;
3986 case 0x70: /* pshufx insn */
3987 case 0xc6: /* pshufx insn */
3988 val = ldub_code(s->pc++);
3989 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3990 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3991 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv_i32))sse_op2)(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3992 break;
3993 case 0xc2:
3994 /* compare insns */
3995 val = ldub_code(s->pc++);
3996 if (val >= 8)
3997 goto illegal_op;
3998 sse_op2 = sse_op_table4[val][b1];
3999 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4000 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4001 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4002 break;
4003 case 0xf7:
4004 /* maskmov : we must prepare A0 */
4005 if (mod != 3)
4006 goto illegal_op;
4007 #ifdef TARGET_X86_64
4008 if (s->aflag == 2) {
4009 gen_op_movq_A0_reg(R_EDI);
4010 } else
4011 #endif
4012 {
4013 gen_op_movl_A0_reg(R_EDI);
4014 if (s->aflag == 0)
4015 gen_op_andl_A0_ffff();
4016 }
4017 gen_add_A0_ds_seg(s);
4018
4019 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4020 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4021 ((void (*)(TCGv_ptr, TCGv_ptr, TCGv))sse_op2)(cpu_ptr0, cpu_ptr1, cpu_A0);
4022 break;
4023 default:
4024 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4025 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4026 ((void (*)(TCGv_ptr, TCGv_ptr))sse_op2)(cpu_ptr0, cpu_ptr1);
4027 break;
4028 }
4029 if (b == 0x2e || b == 0x2f) {
4030 s->cc_op = CC_OP_EFLAGS;
4031 }
4032 }
4033 }
4034
4035 /* convert one instruction. s->is_jmp is set if the translation must
4036 be stopped. Return the next pc value */
4037 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4038 {
4039 int b, prefixes, aflag, dflag;
4040 int shift, ot;
4041 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4042 target_ulong next_eip, tval;
4043 int rex_w, rex_r;
4044
4045 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4046 tcg_gen_debug_insn_start(pc_start);
4047 s->pc = pc_start;
4048 prefixes = 0;
4049 aflag = s->code32;
4050 dflag = s->code32;
4051 s->override = -1;
4052 rex_w = -1;
4053 rex_r = 0;
4054 #ifdef TARGET_X86_64
4055 s->rex_x = 0;
4056 s->rex_b = 0;
4057 x86_64_hregs = 0;
4058 #endif
4059 s->rip_offset = 0; /* for relative ip address */
4060 next_byte:
4061 b = ldub_code(s->pc);
4062 s->pc++;
4063 /* check prefixes */
4064 #ifdef TARGET_X86_64
4065 if (CODE64(s)) {
4066 switch (b) {
4067 case 0xf3:
4068 prefixes |= PREFIX_REPZ;
4069 goto next_byte;
4070 case 0xf2:
4071 prefixes |= PREFIX_REPNZ;
4072 goto next_byte;
4073 case 0xf0:
4074 prefixes |= PREFIX_LOCK;
4075 goto next_byte;
4076 case 0x2e:
4077 s->override = R_CS;
4078 goto next_byte;
4079 case 0x36:
4080 s->override = R_SS;
4081 goto next_byte;
4082 case 0x3e:
4083 s->override = R_DS;
4084 goto next_byte;
4085 case 0x26:
4086 s->override = R_ES;
4087 goto next_byte;
4088 case 0x64:
4089 s->override = R_FS;
4090 goto next_byte;
4091 case 0x65:
4092 s->override = R_GS;
4093 goto next_byte;
4094 case 0x66:
4095 prefixes |= PREFIX_DATA;
4096 goto next_byte;
4097 case 0x67:
4098 prefixes |= PREFIX_ADR;
4099 goto next_byte;
4100 case 0x40 ... 0x4f:
4101 /* REX prefix */
4102 rex_w = (b >> 3) & 1;
4103 rex_r = (b & 0x4) << 1;
4104 s->rex_x = (b & 0x2) << 2;
4105 REX_B(s) = (b & 0x1) << 3;
4106 x86_64_hregs = 1; /* select uniform byte register addressing */
4107 goto next_byte;
4108 }
4109 if (rex_w == 1) {
4110 /* 0x66 is ignored if rex.w is set */
4111 dflag = 2;
4112 } else {
4113 if (prefixes & PREFIX_DATA)
4114 dflag ^= 1;
4115 }
4116 if (!(prefixes & PREFIX_ADR))
4117 aflag = 2;
4118 } else
4119 #endif
4120 {
4121 switch (b) {
4122 case 0xf3:
4123 prefixes |= PREFIX_REPZ;
4124 goto next_byte;
4125 case 0xf2:
4126 prefixes |= PREFIX_REPNZ;
4127 goto next_byte;
4128 case 0xf0:
4129 prefixes |= PREFIX_LOCK;
4130 goto next_byte;
4131 case 0x2e:
4132 s->override = R_CS;
4133 goto next_byte;
4134 case 0x36:
4135 s->override = R_SS;
4136 goto next_byte;
4137 case 0x3e:
4138 s->override = R_DS;
4139 goto next_byte;
4140 case 0x26:
4141 s->override = R_ES;
4142 goto next_byte;
4143 case 0x64:
4144 s->override = R_FS;
4145 goto next_byte;
4146 case 0x65:
4147 s->override = R_GS;
4148 goto next_byte;
4149 case 0x66:
4150 prefixes |= PREFIX_DATA;
4151 goto next_byte;
4152 case 0x67:
4153 prefixes |= PREFIX_ADR;
4154 goto next_byte;
4155 }
4156 if (prefixes & PREFIX_DATA)
4157 dflag ^= 1;
4158 if (prefixes & PREFIX_ADR)
4159 aflag ^= 1;
4160 }
4161
4162 s->prefix = prefixes;
4163 s->aflag = aflag;
4164 s->dflag = dflag;
4165
4166 /* lock generation */
4167 if (prefixes & PREFIX_LOCK)
4168 gen_helper_lock();
4169
4170 /* now check op code */
4171 reswitch:
4172 switch(b) {
4173 case 0x0f:
4174 /**************************/
4175 /* extended op code */
4176 b = ldub_code(s->pc++) | 0x100;
4177 goto reswitch;
4178
4179 /**************************/
4180 /* arith & logic */
4181 case 0x00 ... 0x05:
4182 case 0x08 ... 0x0d:
4183 case 0x10 ... 0x15:
4184 case 0x18 ... 0x1d:
4185 case 0x20 ... 0x25:
4186 case 0x28 ... 0x2d:
4187 case 0x30 ... 0x35:
4188 case 0x38 ... 0x3d:
4189 {
4190 int op, f, val;
4191 op = (b >> 3) & 7;
4192 f = (b >> 1) & 3;
4193
4194 if ((b & 1) == 0)
4195 ot = OT_BYTE;
4196 else
4197 ot = dflag + OT_WORD;
4198
4199 switch(f) {
4200 case 0: /* OP Ev, Gv */
4201 modrm = ldub_code(s->pc++);
4202 reg = ((modrm >> 3) & 7) | rex_r;
4203 mod = (modrm >> 6) & 3;
4204 rm = (modrm & 7) | REX_B(s);
4205 if (mod != 3) {
4206 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4207 opreg = OR_TMP0;
4208 } else if (op == OP_XORL && rm == reg) {
4209 xor_zero:
4210 /* xor reg, reg optimisation */
4211 gen_op_movl_T0_0();
4212 s->cc_op = CC_OP_LOGICB + ot;
4213 gen_op_mov_reg_T0(ot, reg);
4214 gen_op_update1_cc();
4215 break;
4216 } else {
4217 opreg = rm;
4218 }
4219 gen_op_mov_TN_reg(ot, 1, reg);
4220 gen_op(s, op, ot, opreg);
4221 break;
4222 case 1: /* OP Gv, Ev */
4223 modrm = ldub_code(s->pc++);
4224 mod = (modrm >> 6) & 3;
4225 reg = ((modrm >> 3) & 7) | rex_r;
4226 rm = (modrm & 7) | REX_B(s);
4227 if (mod != 3) {
4228 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4229 gen_op_ld_T1_A0(ot + s->mem_index);
4230 } else if (op == OP_XORL && rm == reg) {
4231 goto xor_zero;
4232 } else {
4233 gen_op_mov_TN_reg(ot, 1, rm);
4234 }
4235 gen_op(s, op, ot, reg);
4236 break;
4237 case 2: /* OP A, Iv */
4238 val = insn_get(s, ot);
4239 gen_op_movl_T1_im(val);
4240 gen_op(s, op, ot, OR_EAX);
4241 break;
4242 }
4243 }
4244 break;
4245
4246 case 0x82:
4247 if (CODE64(s))
4248 goto illegal_op;
4249 case 0x80: /* GRP1 */
4250 case 0x81:
4251 case 0x83:
4252 {
4253 int val;
4254
4255 if ((b & 1) == 0)
4256 ot = OT_BYTE;
4257 else
4258 ot = dflag + OT_WORD;
4259
4260 modrm = ldub_code(s->pc++);
4261 mod = (modrm >> 6) & 3;
4262 rm = (modrm & 7) | REX_B(s);
4263 op = (modrm >> 3) & 7;
4264
4265 if (mod != 3) {
4266 if (b == 0x83)
4267 s->rip_offset = 1;
4268 else
4269 s->rip_offset = insn_const_size(ot);
4270 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4271 opreg = OR_TMP0;
4272 } else {
4273 opreg = rm;
4274 }
4275
4276 switch(b) {
4277 default:
4278 case 0x80:
4279 case 0x81:
4280 case 0x82:
4281 val = insn_get(s, ot);
4282 break;
4283 case 0x83:
4284 val = (int8_t)insn_get(s, OT_BYTE);
4285 break;
4286 }
4287 gen_op_movl_T1_im(val);
4288 gen_op(s, op, ot, opreg);
4289 }
4290 break;
4291
4292 /**************************/
4293 /* inc, dec, and other misc arith */
4294 case 0x40 ... 0x47: /* inc Gv */
4295 ot = dflag ? OT_LONG : OT_WORD;
4296 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4297 break;
4298 case 0x48 ... 0x4f: /* dec Gv */
4299 ot = dflag ? OT_LONG : OT_WORD;
4300 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4301 break;
4302 case 0xf6: /* GRP3 */
4303 case 0xf7:
4304 if ((b & 1) == 0)
4305 ot = OT_BYTE;
4306 else
4307 ot = dflag + OT_WORD;
4308
4309 modrm = ldub_code(s->pc++);
4310 mod = (modrm >> 6) & 3;
4311 rm = (modrm & 7) | REX_B(s);
4312 op = (modrm >> 3) & 7;
4313 if (mod != 3) {
4314 if (op == 0)
4315 s->rip_offset = insn_const_size(ot);
4316 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4317 gen_op_ld_T0_A0(ot + s->mem_index);
4318 } else {
4319 gen_op_mov_TN_reg(ot, 0, rm);
4320 }
4321
4322 switch(op) {
4323 case 0: /* test */
4324 val = insn_get(s, ot);
4325 gen_op_movl_T1_im(val);
4326 gen_op_testl_T0_T1_cc();
4327 s->cc_op = CC_OP_LOGICB + ot;
4328 break;
4329 case 2: /* not */
4330 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4331 if (mod != 3) {
4332 gen_op_st_T0_A0(ot + s->mem_index);
4333 } else {
4334 gen_op_mov_reg_T0(ot, rm);
4335 }
4336 break;
4337 case 3: /* neg */
4338 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4339 if (mod != 3) {
4340 gen_op_st_T0_A0(ot + s->mem_index);
4341 } else {
4342 gen_op_mov_reg_T0(ot, rm);
4343 }
4344 gen_op_update_neg_cc();
4345 s->cc_op = CC_OP_SUBB + ot;
4346 break;
4347 case 4: /* mul */
4348 switch(ot) {
4349 case OT_BYTE:
4350 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4351 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4352 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4353 /* XXX: use 32 bit mul which could be faster */
4354 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4355 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4356 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4357 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4358 s->cc_op = CC_OP_MULB;
4359 break;
4360 case OT_WORD:
4361 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4362 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4363 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4364 /* XXX: use 32 bit mul which could be faster */
4365 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4366 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4367 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4368 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4369 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4370 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4371 s->cc_op = CC_OP_MULW;
4372 break;
4373 default:
4374 case OT_LONG:
4375 #ifdef TARGET_X86_64
4376 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4377 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4378 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4379 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4380 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4381 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4382 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4383 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4384 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4385 #else
4386 {
4387 TCGv_i64 t0, t1;
4388 t0 = tcg_temp_new_i64();
4389 t1 = tcg_temp_new_i64();
4390 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4391 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4392 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4393 tcg_gen_mul_i64(t0, t0, t1);
4394 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4395 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4396 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4397 tcg_gen_shri_i64(t0, t0, 32);
4398 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4399 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4400 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4401 }
4402 #endif
4403 s->cc_op = CC_OP_MULL;
4404 break;
4405 #ifdef TARGET_X86_64
4406 case OT_QUAD:
4407 gen_helper_mulq_EAX_T0(cpu_T[0]);
4408 s->cc_op = CC_OP_MULQ;
4409 break;
4410 #endif
4411 }
4412 break;
4413 case 5: /* imul */
4414 switch(ot) {
4415 case OT_BYTE:
4416 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4417 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4418 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4419 /* XXX: use 32 bit mul which could be faster */
4420 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4421 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4422 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4423 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4424 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4425 s->cc_op = CC_OP_MULB;
4426 break;
4427 case OT_WORD:
4428 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4429 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4430 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4431 /* XXX: use 32 bit mul which could be faster */
4432 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4433 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4434 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4435 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4436 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4437 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4438 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4439 s->cc_op = CC_OP_MULW;
4440 break;
4441 default:
4442 case OT_LONG:
4443 #ifdef TARGET_X86_64
4444 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4445 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4446 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4447 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4448 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4449 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4450 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4451 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4452 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4453 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4454 #else
4455 {
4456 TCGv_i64 t0, t1;
4457 t0 = tcg_temp_new_i64();
4458 t1 = tcg_temp_new_i64();
4459 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4460 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4461 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4462 tcg_gen_mul_i64(t0, t0, t1);
4463 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4464 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4465 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4466 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4467 tcg_gen_shri_i64(t0, t0, 32);
4468 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4469 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4470 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4471 }
4472 #endif
4473 s->cc_op = CC_OP_MULL;
4474 break;
4475 #ifdef TARGET_X86_64
4476 case OT_QUAD:
4477 gen_helper_imulq_EAX_T0(cpu_T[0]);
4478 s->cc_op = CC_OP_MULQ;
4479 break;
4480 #endif
4481 }
4482 break;
4483 case 6: /* div */
4484 switch(ot) {
4485 case OT_BYTE:
4486 gen_jmp_im(pc_start - s->cs_base);
4487 gen_helper_divb_AL(cpu_T[0]);
4488 break;
4489 case OT_WORD:
4490 gen_jmp_im(pc_start - s->cs_base);
4491 gen_helper_divw_AX(cpu_T[0]);
4492 break;
4493 default:
4494 case OT_LONG:
4495 gen_jmp_im(pc_start - s->cs_base);
4496 gen_helper_divl_EAX(cpu_T[0]);
4497 break;
4498 #ifdef TARGET_X86_64
4499 case OT_QUAD:
4500 gen_jmp_im(pc_start - s->cs_base);
4501 gen_helper_divq_EAX(cpu_T[0]);
4502 break;
4503 #endif
4504 }
4505 break;
4506 case 7: /* idiv */
4507 switch(ot) {
4508 case OT_BYTE:
4509 gen_jmp_im(pc_start - s->cs_base);
4510 gen_helper_idivb_AL(cpu_T[0]);
4511 break;
4512 case OT_WORD:
4513 gen_jmp_im(pc_start - s->cs_base);
4514 gen_helper_idivw_AX(cpu_T[0]);
4515 break;
4516 default:
4517 case OT_LONG:
4518 gen_jmp_im(pc_start - s->cs_base);
4519 gen_helper_idivl_EAX(cpu_T[0]);
4520 break;
4521 #ifdef TARGET_X86_64
4522 case OT_QUAD:
4523 gen_jmp_im(pc_start - s->cs_base);
4524 gen_helper_idivq_EAX(cpu_T[0]);
4525 break;
4526 #endif
4527 }
4528 break;
4529 default:
4530 goto illegal_op;
4531 }
4532 break;
4533
4534 case 0xfe: /* GRP4 */
4535 case 0xff: /* GRP5 */
4536 if ((b & 1) == 0)
4537 ot = OT_BYTE;
4538 else
4539 ot = dflag + OT_WORD;
4540
4541 modrm = ldub_code(s->pc++);
4542 mod = (modrm >> 6) & 3;
4543 rm = (modrm & 7) | REX_B(s);
4544 op = (modrm >> 3) & 7;
4545 if (op >= 2 && b == 0xfe) {
4546 goto illegal_op;
4547 }
4548 if (CODE64(s)) {
4549 if (op == 2 || op == 4) {
4550 /* operand size for jumps is 64 bit */
4551 ot = OT_QUAD;
4552 } else if (op == 3 || op == 5) {
4553 /* for call calls, the operand is 16 or 32 bit, even
4554 in long mode */
4555 ot = dflag ? OT_LONG : OT_WORD;
4556 } else if (op == 6) {
4557 /* default push size is 64 bit */
4558 ot = dflag ? OT_QUAD : OT_WORD;
4559 }
4560 }
4561 if (mod != 3) {
4562 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4563 if (op >= 2 && op != 3 && op != 5)
4564 gen_op_ld_T0_A0(ot + s->mem_index);
4565 } else {
4566 gen_op_mov_TN_reg(ot, 0, rm);
4567 }
4568
4569 switch(op) {
4570 case 0: /* inc Ev */
4571 if (mod != 3)
4572 opreg = OR_TMP0;
4573 else
4574 opreg = rm;
4575 gen_inc(s, ot, opreg, 1);
4576 break;
4577 case 1: /* dec Ev */
4578 if (mod != 3)
4579 opreg = OR_TMP0;
4580 else
4581 opreg = rm;
4582 gen_inc(s, ot, opreg, -1);
4583 break;
4584 case 2: /* call Ev */
4585 /* XXX: optimize if memory (no 'and' is necessary) */
4586 if (s->dflag == 0)
4587 gen_op_andl_T0_ffff();
4588 next_eip = s->pc - s->cs_base;
4589 gen_movtl_T1_im(next_eip);
4590 gen_push_T1(s);
4591 gen_op_jmp_T0();
4592 gen_eob(s);
4593 break;
4594 case 3: /* lcall Ev */
4595 gen_op_ld_T1_A0(ot + s->mem_index);
4596 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4597 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4598 do_lcall:
4599 if (s->pe && !s->vm86) {
4600 if (s->cc_op != CC_OP_DYNAMIC)
4601 gen_op_set_cc_op(s->cc_op);
4602 gen_jmp_im(pc_start - s->cs_base);
4603 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4604 gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4605 tcg_const_i32(dflag),
4606 tcg_const_i32(s->pc - pc_start));
4607 } else {
4608 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4609 gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4610 tcg_const_i32(dflag),
4611 tcg_const_i32(s->pc - s->cs_base));
4612 }
4613 gen_eob(s);
4614 break;
4615 case 4: /* jmp Ev */
4616 if (s->dflag == 0)
4617 gen_op_andl_T0_ffff();
4618 gen_op_jmp_T0();
4619 gen_eob(s);
4620 break;
4621 case 5: /* ljmp Ev */
4622 gen_op_ld_T1_A0(ot + s->mem_index);
4623 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4624 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4625 do_ljmp:
4626 if (s->pe && !s->vm86) {
4627 if (s->cc_op != CC_OP_DYNAMIC)
4628 gen_op_set_cc_op(s->cc_op);
4629 gen_jmp_im(pc_start - s->cs_base);
4630 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4631 gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4632 tcg_const_i32(s->pc - pc_start));
4633 } else {
4634 gen_op_movl_seg_T0_vm(R_CS);
4635 gen_op_movl_T0_T1();
4636 gen_op_jmp_T0();
4637 }
4638 gen_eob(s);
4639 break;
4640 case 6: /* push Ev */
4641 gen_push_T0(s);
4642 break;
4643 default:
4644 goto illegal_op;
4645 }
4646 break;
4647
4648 case 0x84: /* test Ev, Gv */
4649 case 0x85:
4650 if ((b & 1) == 0)
4651 ot = OT_BYTE;
4652 else
4653 ot = dflag + OT_WORD;
4654
4655 modrm = ldub_code(s->pc++);
4656 mod = (modrm >> 6) & 3;
4657 rm = (modrm & 7) | REX_B(s);
4658 reg = ((modrm >> 3) & 7) | rex_r;
4659
4660 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4661 gen_op_mov_TN_reg(ot, 1, reg);
4662 gen_op_testl_T0_T1_cc();
4663 s->cc_op = CC_OP_LOGICB + ot;
4664 break;
4665
4666 case 0xa8: /* test eAX, Iv */
4667 case 0xa9:
4668 if ((b & 1) == 0)
4669 ot = OT_BYTE;
4670 else
4671 ot = dflag + OT_WORD;
4672 val = insn_get(s, ot);
4673
4674 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4675 gen_op_movl_T1_im(val);
4676 gen_op_testl_T0_T1_cc();
4677 s->cc_op = CC_OP_LOGICB + ot;
4678 break;
4679
4680 case 0x98: /* CWDE/CBW */
4681 #ifdef TARGET_X86_64
4682 if (dflag == 2) {
4683 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4684 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4685 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4686 } else
4687 #endif
4688 if (dflag == 1) {
4689 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4690 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4691 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4692 } else {
4693 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4694 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4695 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4696 }
4697 break;
4698 case 0x99: /* CDQ/CWD */
4699 #ifdef TARGET_X86_64
4700 if (dflag == 2) {
4701 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4702 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4703 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4704 } else
4705 #endif
4706 if (dflag == 1) {
4707 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4708 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4709 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4710 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4711 } else {
4712 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4713 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4714 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4715 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4716 }
4717 break;
4718 case 0x1af: /* imul Gv, Ev */
4719 case 0x69: /* imul Gv, Ev, I */
4720 case 0x6b:
4721 ot = dflag + OT_WORD;
4722 modrm = ldub_code(s->pc++);
4723 reg = ((modrm >> 3) & 7) | rex_r;
4724 if (b == 0x69)
4725 s->rip_offset = insn_const_size(ot);
4726 else if (b == 0x6b)
4727 s->rip_offset = 1;
4728 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4729 if (b == 0x69) {
4730 val = insn_get(s, ot);
4731 gen_op_movl_T1_im(val);
4732 } else if (b == 0x6b) {
4733 val = (int8_t)insn_get(s, OT_BYTE);
4734 gen_op_movl_T1_im(val);
4735 } else {
4736 gen_op_mov_TN_reg(ot, 1, reg);
4737 }
4738
4739 #ifdef TARGET_X86_64
4740 if (ot == OT_QUAD) {
4741 gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
4742 } else
4743 #endif
4744 if (ot == OT_LONG) {
4745 #ifdef TARGET_X86_64
4746 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4747 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4748 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4749 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4750 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4751 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4752 #else
4753 {
4754 TCGv_i64 t0, t1;
4755 t0 = tcg_temp_new_i64();
4756 t1 = tcg_temp_new_i64();
4757 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4758 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4759 tcg_gen_mul_i64(t0, t0, t1);
4760 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4761 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4762 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4763 tcg_gen_shri_i64(t0, t0, 32);
4764 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4765 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4766 }
4767 #endif
4768 } else {
4769 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4770 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4771 /* XXX: use 32 bit mul which could be faster */
4772 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4773 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4774 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4775 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4776 }
4777 gen_op_mov_reg_T0(ot, reg);
4778 s->cc_op = CC_OP_MULB + ot;
4779 break;
4780 case 0x1c0:
4781 case 0x1c1: /* xadd Ev, Gv */
4782 if ((b & 1) == 0)
4783 ot = OT_BYTE;
4784 else
4785 ot = dflag + OT_WORD;
4786 modrm = ldub_code(s->pc++);
4787 reg = ((modrm >> 3) & 7) | rex_r;
4788 mod = (modrm >> 6) & 3;
4789 if (mod == 3) {
4790 rm = (modrm & 7) | REX_B(s);
4791 gen_op_mov_TN_reg(ot, 0, reg);
4792 gen_op_mov_TN_reg(ot, 1, rm);
4793 gen_op_addl_T0_T1();
4794 gen_op_mov_reg_T1(ot, reg);
4795 gen_op_mov_reg_T0(ot, rm);
4796 } else {
4797 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4798 gen_op_mov_TN_reg(ot, 0, reg);
4799 gen_op_ld_T1_A0(ot + s->mem_index);
4800 gen_op_addl_T0_T1();
4801 gen_op_st_T0_A0(ot + s->mem_index);
4802 gen_op_mov_reg_T1(ot, reg);
4803 }
4804 gen_op_update2_cc();
4805 s->cc_op = CC_OP_ADDB + ot;
4806 break;
4807 case 0x1b0:
4808 case 0x1b1: /* cmpxchg Ev, Gv */
4809 {
4810 int label1, label2;
4811 TCGv t0, t1, t2, a0;
4812
4813 if ((b & 1) == 0)
4814 ot = OT_BYTE;
4815 else
4816 ot = dflag + OT_WORD;
4817 modrm = ldub_code(s->pc++);
4818 reg = ((modrm >> 3) & 7) | rex_r;
4819 mod = (modrm >> 6) & 3;
4820 t0 = tcg_temp_local_new();
4821 t1 = tcg_temp_local_new();
4822 t2 = tcg_temp_local_new();
4823 a0 = tcg_temp_local_new();
4824 gen_op_mov_v_reg(ot, t1, reg);
4825 if (mod == 3) {
4826 rm = (modrm & 7) | REX_B(s);
4827 gen_op_mov_v_reg(ot, t0, rm);
4828 } else {
4829 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4830 tcg_gen_mov_tl(a0, cpu_A0);
4831 gen_op_ld_v(ot + s->mem_index, t0, a0);
4832 rm = 0; /* avoid warning */
4833 }
4834 label1 = gen_new_label();
4835 tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX]));
4836 tcg_gen_sub_tl(t2, t2, t0);
4837 gen_extu(ot, t2);
4838 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4839 if (mod == 3) {
4840 label2 = gen_new_label();
4841 gen_op_mov_reg_v(ot, R_EAX, t0);
4842 tcg_gen_br(label2);
4843 gen_set_label(label1);
4844 gen_op_mov_reg_v(ot, rm, t1);
4845 gen_set_label(label2);
4846 } else {
4847 tcg_gen_mov_tl(t1, t0);
4848 gen_op_mov_reg_v(ot, R_EAX, t0);
4849 gen_set_label(label1);
4850 /* always store */
4851 gen_op_st_v(ot + s->mem_index, t1, a0);
4852 }
4853 tcg_gen_mov_tl(cpu_cc_src, t0);
4854 tcg_gen_mov_tl(cpu_cc_dst, t2);
4855 s->cc_op = CC_OP_SUBB + ot;
4856 tcg_temp_free(t0);
4857 tcg_temp_free(t1);
4858 tcg_temp_free(t2);
4859 tcg_temp_free(a0);
4860 }
4861 break;
4862 case 0x1c7: /* cmpxchg8b */
4863 modrm = ldub_code(s->pc++);
4864 mod = (modrm >> 6) & 3;
4865 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4866 goto illegal_op;
4867 #ifdef TARGET_X86_64
4868 if (dflag == 2) {
4869 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4870 goto illegal_op;
4871 gen_jmp_im(pc_start - s->cs_base);
4872 if (s->cc_op != CC_OP_DYNAMIC)
4873 gen_op_set_cc_op(s->cc_op);
4874 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4875 gen_helper_cmpxchg16b(cpu_A0);
4876 } else
4877 #endif
4878 {
4879 if (!(s->cpuid_features & CPUID_CX8))
4880 goto illegal_op;
4881 gen_jmp_im(pc_start - s->cs_base);
4882 if (s->cc_op != CC_OP_DYNAMIC)
4883 gen_op_set_cc_op(s->cc_op);
4884 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4885 gen_helper_cmpxchg8b(cpu_A0);
4886 }
4887 s->cc_op = CC_OP_EFLAGS;
4888 break;
4889
4890 /**************************/
4891 /* push/pop */
4892 case 0x50 ... 0x57: /* push */
4893 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4894 gen_push_T0(s);
4895 break;
4896 case 0x58 ... 0x5f: /* pop */
4897 if (CODE64(s)) {
4898 ot = dflag ? OT_QUAD : OT_WORD;
4899 } else {
4900 ot = dflag + OT_WORD;
4901 }
4902 gen_pop_T0(s);
4903 /* NOTE: order is important for pop %sp */
4904 gen_pop_update(s);
4905 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4906 break;
4907 case 0x60: /* pusha */
4908 if (CODE64(s))
4909 goto illegal_op;
4910 gen_pusha(s);
4911 break;
4912 case 0x61: /* popa */
4913 if (CODE64(s))
4914 goto illegal_op;
4915 gen_popa(s);
4916 break;
4917 case 0x68: /* push Iv */
4918 case 0x6a:
4919 if (CODE64(s)) {
4920 ot = dflag ? OT_QUAD : OT_WORD;
4921 } else {
4922 ot = dflag + OT_WORD;
4923 }
4924 if (b == 0x68)
4925 val = insn_get(s, ot);
4926 else
4927 val = (int8_t)insn_get(s, OT_BYTE);
4928 gen_op_movl_T0_im(val);
4929 gen_push_T0(s);
4930 break;
4931 case 0x8f: /* pop Ev */
4932 if (CODE64(s)) {
4933 ot = dflag ? OT_QUAD : OT_WORD;
4934 } else {
4935 ot = dflag + OT_WORD;
4936 }
4937 modrm = ldub_code(s->pc++);
4938 mod = (modrm >> 6) & 3;
4939 gen_pop_T0(s);
4940 if (mod == 3) {
4941 /* NOTE: order is important for pop %sp */
4942 gen_pop_update(s);
4943 rm = (modrm & 7) | REX_B(s);
4944 gen_op_mov_reg_T0(ot, rm);
4945 } else {
4946 /* NOTE: order is important too for MMU exceptions */
4947 s->popl_esp_hack = 1 << ot;
4948 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4949 s->popl_esp_hack = 0;
4950 gen_pop_update(s);
4951 }
4952 break;
4953 case 0xc8: /* enter */
4954 {
4955 int level;
4956 val = lduw_code(s->pc);
4957 s->pc += 2;
4958 level = ldub_code(s->pc++);
4959 gen_enter(s, val, level);
4960 }
4961 break;
4962 case 0xc9: /* leave */
4963 /* XXX: exception not precise (ESP is updated before potential exception) */
4964 if (CODE64(s)) {
4965 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
4966 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
4967 } else if (s->ss32) {
4968 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
4969 gen_op_mov_reg_T0(OT_LONG, R_ESP);
4970 } else {
4971 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
4972 gen_op_mov_reg_T0(OT_WORD, R_ESP);
4973 }
4974 gen_pop_T0(s);
4975 if (CODE64(s)) {
4976 ot = dflag ? OT_QUAD : OT_WORD;
4977 } else {
4978 ot = dflag + OT_WORD;
4979 }
4980 gen_op_mov_reg_T0(ot, R_EBP);
4981 gen_pop_update(s);
4982 break;
4983 case 0x06: /* push es */
4984 case 0x0e: /* push cs */
4985 case 0x16: /* push ss */
4986 case 0x1e: /* push ds */
4987 if (CODE64(s))
4988 goto illegal_op;
4989 gen_op_movl_T0_seg(b >> 3);
4990 gen_push_T0(s);
4991 break;
4992 case 0x1a0: /* push fs */
4993 case 0x1a8: /* push gs */
4994 gen_op_movl_T0_seg((b >> 3) & 7);
4995 gen_push_T0(s);
4996 break;
4997 case 0x07: /* pop es */
4998 case 0x17: /* pop ss */
4999 case 0x1f: /* pop ds */
5000 if (CODE64(s))
5001 goto illegal_op;
5002 reg = b >> 3;
5003 gen_pop_T0(s);
5004 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5005 gen_pop_update(s);
5006 if (reg == R_SS) {
5007 /* if reg == SS, inhibit interrupts/trace. */
5008 /* If several instructions disable interrupts, only the
5009 _first_ does it */
5010 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5011 gen_helper_set_inhibit_irq();
5012 s->tf = 0;
5013 }
5014 if (s->is_jmp) {
5015 gen_jmp_im(s->pc - s->cs_base);
5016 gen_eob(s);
5017 }
5018 break;
5019 case 0x1a1: /* pop fs */
5020 case 0x1a9: /* pop gs */
5021 gen_pop_T0(s);
5022 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5023 gen_pop_update(s);
5024 if (s->is_jmp) {
5025 gen_jmp_im(s->pc - s->cs_base);
5026 gen_eob(s);
5027 }
5028 break;
5029
5030 /**************************/
5031 /* mov */
5032 case 0x88:
5033 case 0x89: /* mov Gv, Ev */
5034 if ((b & 1) == 0)
5035 ot = OT_BYTE;
5036 else
5037 ot = dflag + OT_WORD;
5038 modrm = ldub_code(s->pc++);
5039 reg = ((modrm >> 3) & 7) | rex_r;
5040
5041 /* generate a generic store */
5042 gen_ldst_modrm(s, modrm, ot, reg, 1);
5043 break;
5044 case 0xc6:
5045 case 0xc7: /* mov Ev, Iv */
5046 if ((b & 1) == 0)
5047 ot = OT_BYTE;
5048 else
5049 ot = dflag + OT_WORD;
5050 modrm = ldub_code(s->pc++);
5051 mod = (modrm >> 6) & 3;
5052 if (mod != 3) {
5053 s->rip_offset = insn_const_size(ot);
5054 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5055 }
5056 val = insn_get(s, ot);
5057 gen_op_movl_T0_im(val);
5058 if (mod != 3)
5059 gen_op_st_T0_A0(ot + s->mem_index);
5060 else
5061 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5062 break;
5063 case 0x8a:
5064 case 0x8b: /* mov Ev, Gv */
5065 if ((b & 1) == 0)
5066 ot = OT_BYTE;
5067 else
5068 ot = OT_WORD + dflag;
5069 modrm = ldub_code(s->pc++);
5070 reg = ((modrm >> 3) & 7) | rex_r;
5071
5072 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5073 gen_op_mov_reg_T0(ot, reg);
5074 break;
5075 case 0x8e: /* mov seg, Gv */
5076 modrm = ldub_code(s->pc++);
5077 reg = (modrm >> 3) & 7;
5078 if (reg >= 6 || reg == R_CS)
5079 goto illegal_op;
5080 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5081 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5082 if (reg == R_SS) {
5083 /* if reg == SS, inhibit interrupts/trace */
5084 /* If several instructions disable interrupts, only the
5085 _first_ does it */
5086 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5087 gen_helper_set_inhibit_irq();
5088 s->tf = 0;
5089 }
5090 if (s->is_jmp) {
5091 gen_jmp_im(s->pc - s->cs_base);
5092 gen_eob(s);
5093 }
5094 break;
5095 case 0x8c: /* mov Gv, seg */
5096 modrm = ldub_code(s->pc++);
5097 reg = (modrm >> 3) & 7;
5098 mod = (modrm >> 6) & 3;
5099 if (reg >= 6)
5100 goto illegal_op;
5101 gen_op_movl_T0_seg(reg);
5102 if (mod == 3)
5103 ot = OT_WORD + dflag;
5104 else
5105 ot = OT_WORD;
5106 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5107 break;
5108
5109 case 0x1b6: /* movzbS Gv, Eb */
5110 case 0x1b7: /* movzwS Gv, Eb */
5111 case 0x1be: /* movsbS Gv, Eb */
5112 case 0x1bf: /* movswS Gv, Eb */
5113 {
5114 int d_ot;
5115 /* d_ot is the size of destination */
5116 d_ot = dflag + OT_WORD;
5117 /* ot is the size of source */
5118 ot = (b & 1) + OT_BYTE;
5119 modrm = ldub_code(s->pc++);
5120 reg = ((modrm >> 3) & 7) | rex_r;
5121 mod = (modrm >> 6) & 3;
5122 rm = (modrm & 7) | REX_B(s);
5123
5124 if (mod == 3) {
5125 gen_op_mov_TN_reg(ot, 0, rm);
5126 switch(ot | (b & 8)) {
5127 case OT_BYTE:
5128 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5129 break;
5130 case OT_BYTE | 8:
5131 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5132 break;
5133 case OT_WORD:
5134 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5135 break;
5136 default:
5137 case OT_WORD | 8:
5138 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5139 break;
5140 }
5141 gen_op_mov_reg_T0(d_ot, reg);
5142 } else {
5143 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5144 if (b & 8) {
5145 gen_op_lds_T0_A0(ot + s->mem_index);
5146 } else {
5147 gen_op_ldu_T0_A0(ot + s->mem_index);
5148 }
5149 gen_op_mov_reg_T0(d_ot, reg);
5150 }
5151 }
5152 break;
5153
5154 case 0x8d: /* lea */
5155 ot = dflag + OT_WORD;
5156 modrm = ldub_code(s->pc++);
5157 mod = (modrm >> 6) & 3;
5158 if (mod == 3)
5159 goto illegal_op;
5160 reg = ((modrm >> 3) & 7) | rex_r;
5161 /* we must ensure that no segment is added */
5162 s->override = -1;
5163 val = s->addseg;
5164 s->addseg = 0;
5165 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5166 s->addseg = val;
5167 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5168 break;
5169
5170 case 0xa0: /* mov EAX, Ov */
5171 case 0xa1:
5172 case 0xa2: /* mov Ov, EAX */
5173 case 0xa3:
5174 {
5175 target_ulong offset_addr;
5176
5177 if ((b & 1) == 0)
5178 ot = OT_BYTE;
5179 else
5180 ot = dflag + OT_WORD;
5181 #ifdef TARGET_X86_64
5182 if (s->aflag == 2) {
5183 offset_addr = ldq_code(s->pc);
5184 s->pc += 8;
5185 gen_op_movq_A0_im(offset_addr);
5186 } else
5187 #endif
5188 {
5189 if (s->aflag) {
5190 offset_addr = insn_get(s, OT_LONG);
5191 } else {
5192 offset_addr = insn_get(s, OT_WORD);
5193 }
5194 gen_op_movl_A0_im(offset_addr);
5195 }
5196 gen_add_A0_ds_seg(s);
5197 if ((b & 2) == 0) {
5198 gen_op_ld_T0_A0(ot + s->mem_index);
5199 gen_op_mov_reg_T0(ot, R_EAX);
5200 } else {
5201 gen_op_mov_TN_reg(ot, 0, R_EAX);
5202 gen_op_st_T0_A0(ot + s->mem_index);
5203 }
5204 }
5205 break;
5206 case 0xd7: /* xlat */
5207 #ifdef TARGET_X86_64
5208 if (s->aflag == 2) {
5209 gen_op_movq_A0_reg(R_EBX);
5210 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5211 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5212 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5213 } else
5214 #endif
5215 {
5216 gen_op_movl_A0_reg(R_EBX);
5217 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5218 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5219 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5220 if (s->aflag == 0)
5221 gen_op_andl_A0_ffff();
5222 else
5223 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5224 }
5225 gen_add_A0_ds_seg(s);
5226 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5227 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5228 break;
5229 case 0xb0 ... 0xb7: /* mov R, Ib */
5230 val = insn_get(s, OT_BYTE);
5231 gen_op_movl_T0_im(val);
5232 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5233 break;
5234 case 0xb8 ... 0xbf: /* mov R, Iv */
5235 #ifdef TARGET_X86_64
5236 if (dflag == 2) {
5237 uint64_t tmp;
5238 /* 64 bit case */
5239 tmp = ldq_code(s->pc);
5240 s->pc += 8;
5241 reg = (b & 7) | REX_B(s);
5242 gen_movtl_T0_im(tmp);
5243 gen_op_mov_reg_T0(OT_QUAD, reg);
5244 } else
5245 #endif
5246 {
5247 ot = dflag ? OT_LONG : OT_WORD;
5248 val = insn_get(s, ot);
5249 reg = (b & 7) | REX_B(s);
5250 gen_op_movl_T0_im(val);
5251 gen_op_mov_reg_T0(ot, reg);
5252 }
5253 break;
5254
5255 case 0x91 ... 0x97: /* xchg R, EAX */
5256 ot = dflag + OT_WORD;
5257 reg = (b & 7) | REX_B(s);
5258 rm = R_EAX;
5259 goto do_xchg_reg;
5260 case 0x86:
5261 case 0x87: /* xchg Ev, Gv */
5262 if ((b & 1) == 0)
5263 ot = OT_BYTE;
5264 else
5265 ot = dflag + OT_WORD;
5266 modrm = ldub_code(s->pc++);
5267 reg = ((modrm >> 3) & 7) | rex_r;
5268 mod = (modrm >> 6) & 3;
5269 if (mod == 3) {
5270 rm = (modrm & 7) | REX_B(s);
5271 do_xchg_reg:
5272 gen_op_mov_TN_reg(ot, 0, reg);
5273 gen_op_mov_TN_reg(ot, 1, rm);
5274 gen_op_mov_reg_T0(ot, rm);
5275 gen_op_mov_reg_T1(ot, reg);
5276 } else {
5277 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5278 gen_op_mov_TN_reg(ot, 0, reg);
5279 /* for xchg, lock is implicit */
5280 if (!(prefixes & PREFIX_LOCK))
5281 gen_helper_lock();
5282 gen_op_ld_T1_A0(ot + s->mem_index);
5283 gen_op_st_T0_A0(ot + s->mem_index);
5284 if (!(prefixes & PREFIX_LOCK))
5285 gen_helper_unlock();
5286 gen_op_mov_reg_T1(ot, reg);
5287 }
5288 break;
5289 case 0xc4: /* les Gv */
5290 if (CODE64(s))
5291 goto illegal_op;
5292 op = R_ES;
5293 goto do_lxx;
5294 case 0xc5: /* lds Gv */
5295 if (CODE64(s))
5296 goto illegal_op;
5297 op = R_DS;
5298 goto do_lxx;
5299 case 0x1b2: /* lss Gv */
5300 op = R_SS;
5301 goto do_lxx;
5302 case 0x1b4: /* lfs Gv */
5303 op = R_FS;
5304 goto do_lxx;
5305 case 0x1b5: /* lgs Gv */
5306 op = R_GS;
5307 do_lxx:
5308 ot = dflag ? OT_LONG : OT_WORD;
5309 modrm = ldub_code(s->pc++);
5310 reg = ((modrm >> 3) & 7) | rex_r;
5311 mod = (modrm >> 6) & 3;
5312 if (mod == 3)
5313 goto illegal_op;
5314 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5315 gen_op_ld_T1_A0(ot + s->mem_index);
5316 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5317 /* load the segment first to handle exceptions properly */
5318 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5319 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5320 /* then put the data */
5321 gen_op_mov_reg_T1(ot, reg);
5322 if (s->is_jmp) {
5323 gen_jmp_im(s->pc - s->cs_base);
5324 gen_eob(s);
5325 }
5326 break;
5327
5328 /************************/
5329 /* shifts */
5330 case 0xc0:
5331 case 0xc1:
5332 /* shift Ev,Ib */
5333 shift = 2;
5334 grp2:
5335 {
5336 if ((b & 1) == 0)
5337 ot = OT_BYTE;
5338 else
5339 ot = dflag + OT_WORD;
5340
5341 modrm = ldub_code(s->pc++);
5342 mod = (modrm >> 6) & 3;
5343 op = (modrm >> 3) & 7;
5344
5345 if (mod != 3) {
5346 if (shift == 2) {
5347 s->rip_offset = 1;
5348 }
5349 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5350 opreg = OR_TMP0;
5351 } else {
5352 opreg = (modrm & 7) | REX_B(s);
5353 }
5354
5355 /* simpler op */
5356 if (shift == 0) {
5357 gen_shift(s, op, ot, opreg, OR_ECX);
5358 } else {
5359 if (shift == 2) {
5360 shift = ldub_code(s->pc++);
5361 }
5362 gen_shifti(s, op, ot, opreg, shift);
5363 }
5364 }
5365 break;
5366 case 0xd0:
5367 case 0xd1:
5368 /* shift Ev,1 */
5369 shift = 1;
5370 goto grp2;
5371 case 0xd2:
5372 case 0xd3:
5373 /* shift Ev,cl */
5374 shift = 0;
5375 goto grp2;
5376
5377 case 0x1a4: /* shld imm */
5378 op = 0;
5379 shift = 1;
5380 goto do_shiftd;
5381 case 0x1a5: /* shld cl */
5382 op = 0;
5383 shift = 0;
5384 goto do_shiftd;
5385 case 0x1ac: /* shrd imm */
5386 op = 1;
5387 shift = 1;
5388 goto do_shiftd;
5389 case 0x1ad: /* shrd cl */
5390 op = 1;
5391 shift = 0;
5392 do_shiftd:
5393 ot = dflag + OT_WORD;
5394 modrm = ldub_code(s->pc++);
5395 mod = (modrm >> 6) & 3;
5396 rm = (modrm & 7) | REX_B(s);
5397 reg = ((modrm >> 3) & 7) | rex_r;
5398 if (mod != 3) {
5399 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5400 opreg = OR_TMP0;
5401 } else {
5402 opreg = rm;
5403 }
5404 gen_op_mov_TN_reg(ot, 1, reg);
5405
5406 if (shift) {
5407 val = ldub_code(s->pc++);
5408 tcg_gen_movi_tl(cpu_T3, val);
5409 } else {
5410 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
5411 }
5412 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5413 break;
5414
5415 /************************/
5416 /* floats */
5417 case 0xd8 ... 0xdf:
5418 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5419 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5420 /* XXX: what to do if illegal op ? */
5421 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5422 break;
5423 }
5424 modrm = ldub_code(s->pc++);
5425 mod = (modrm >> 6) & 3;
5426 rm = modrm & 7;
5427 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5428 if (mod != 3) {
5429 /* memory op */
5430 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5431 switch(op) {
5432 case 0x00 ... 0x07: /* fxxxs */
5433 case 0x10 ... 0x17: /* fixxxl */
5434 case 0x20 ... 0x27: /* fxxxl */
5435 case 0x30 ... 0x37: /* fixxx */
5436 {
5437 int op1;
5438 op1 = op & 7;
5439
5440 switch(op >> 4) {
5441 case 0:
5442 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5443 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5444 gen_helper_flds_FT0(cpu_tmp2_i32);
5445 break;
5446 case 1:
5447 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5448 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5449 gen_helper_fildl_FT0(cpu_tmp2_i32);
5450 break;
5451 case 2:
5452 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5453 (s->mem_index >> 2) - 1);
5454 gen_helper_fldl_FT0(cpu_tmp1_i64);
5455 break;
5456 case 3:
5457 default:
5458 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5459 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5460 gen_helper_fildl_FT0(cpu_tmp2_i32);
5461 break;
5462 }
5463
5464 gen_helper_fp_arith_ST0_FT0(op1);
5465 if (op1 == 3) {
5466 /* fcomp needs pop */
5467 gen_helper_fpop();
5468 }
5469 }
5470 break;
5471 case 0x08: /* flds */
5472 case 0x0a: /* fsts */
5473 case 0x0b: /* fstps */
5474 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5475 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5476 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5477 switch(op & 7) {
5478 case 0:
5479 switch(op >> 4) {
5480 case 0:
5481 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5482 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5483 gen_helper_flds_ST0(cpu_tmp2_i32);
5484 break;
5485 case 1:
5486 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5487 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5488 gen_helper_fildl_ST0(cpu_tmp2_i32);
5489 break;
5490 case 2:
5491 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5492 (s->mem_index >> 2) - 1);
5493 gen_helper_fldl_ST0(cpu_tmp1_i64);
5494 break;
5495 case 3:
5496 default:
5497 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5498 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5499 gen_helper_fildl_ST0(cpu_tmp2_i32);
5500 break;
5501 }
5502 break;
5503 case 1:
5504 /* XXX: the corresponding CPUID bit must be tested ! */
5505 switch(op >> 4) {
5506 case 1:
5507 gen_helper_fisttl_ST0(cpu_tmp2_i32);
5508 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5509 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5510 break;
5511 case 2:
5512 gen_helper_fisttll_ST0(cpu_tmp1_i64);
5513 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5514 (s->mem_index >> 2) - 1);
5515 break;
5516 case 3:
5517 default:
5518 gen_helper_fistt_ST0(cpu_tmp2_i32);
5519 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5520 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5521 break;
5522 }
5523 gen_helper_fpop();
5524 break;
5525 default:
5526 switch(op >> 4) {
5527 case 0:
5528 gen_helper_fsts_ST0(cpu_tmp2_i32);
5529 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5530 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5531 break;
5532 case 1:
5533 gen_helper_fistl_ST0(cpu_tmp2_i32);
5534 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5535 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5536 break;
5537 case 2:
5538 gen_helper_fstl_ST0(cpu_tmp1_i64);
5539 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5540 (s->mem_index >> 2) - 1);
5541 break;
5542 case 3:
5543 default:
5544 gen_helper_fist_ST0(cpu_tmp2_i32);
5545 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5546 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5547 break;
5548 }
5549 if ((op & 7) == 3)
5550 gen_helper_fpop();
5551 break;
5552 }
5553 break;
5554 case 0x0c: /* fldenv mem */
5555 if (s->cc_op != CC_OP_DYNAMIC)
5556 gen_op_set_cc_op(s->cc_op);
5557 gen_jmp_im(pc_start - s->cs_base);
5558 gen_helper_fldenv(
5559 cpu_A0, tcg_const_i32(s->dflag));
5560 break;
5561 case 0x0d: /* fldcw mem */
5562 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5563 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5564 gen_helper_fldcw(cpu_tmp2_i32);
5565 break;
5566 case 0x0e: /* fnstenv mem */
5567 if (s->cc_op != CC_OP_DYNAMIC)
5568 gen_op_set_cc_op(s->cc_op);
5569 gen_jmp_im(pc_start - s->cs_base);
5570 gen_helper_fstenv(cpu_A0, tcg_const_i32(s->dflag));
5571 break;
5572 case 0x0f: /* fnstcw mem */
5573 gen_helper_fnstcw(cpu_tmp2_i32);
5574 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5575 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5576 break;
5577 case 0x1d: /* fldt mem */
5578 if (s->cc_op != CC_OP_DYNAMIC)
5579 gen_op_set_cc_op(s->cc_op);
5580 gen_jmp_im(pc_start - s->cs_base);
5581 gen_helper_fldt_ST0(cpu_A0);
5582 break;
5583 case 0x1f: /* fstpt mem */
5584 if (s->cc_op != CC_OP_DYNAMIC)
5585 gen_op_set_cc_op(s->cc_op);
5586 gen_jmp_im(pc_start - s->cs_base);
5587 gen_helper_fstt_ST0(cpu_A0);
5588 gen_helper_fpop();
5589 break;
5590 case 0x2c: /* frstor mem */
5591 if (s->cc_op != CC_OP_DYNAMIC)
5592 gen_op_set_cc_op(s->cc_op);
5593 gen_jmp_im(pc_start - s->cs_base);
5594 gen_helper_frstor(cpu_A0, tcg_const_i32(s->dflag));
5595 break;
5596 case 0x2e: /* fnsave mem */
5597 if (s->cc_op != CC_OP_DYNAMIC)
5598 gen_op_set_cc_op(s->cc_op);
5599 gen_jmp_im(pc_start - s->cs_base);
5600 gen_helper_fsave(cpu_A0, tcg_const_i32(s->dflag));
5601 break;
5602 case 0x2f: /* fnstsw mem */
5603 gen_helper_fnstsw(cpu_tmp2_i32);
5604 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5605 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5606 break;
5607 case 0x3c: /* fbld */
5608 if (s->cc_op != CC_OP_DYNAMIC)
5609 gen_op_set_cc_op(s->cc_op);
5610 gen_jmp_im(pc_start - s->cs_base);
5611 gen_helper_fbld_ST0(cpu_A0);
5612 break;
5613 case 0x3e: /* fbstp */
5614 if (s->cc_op != CC_OP_DYNAMIC)
5615 gen_op_set_cc_op(s->cc_op);
5616 gen_jmp_im(pc_start - s->cs_base);
5617 gen_helper_fbst_ST0(cpu_A0);
5618 gen_helper_fpop();
5619 break;
5620 case 0x3d: /* fildll */
5621 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5622 (s->mem_index >> 2) - 1);
5623 gen_helper_fildll_ST0(cpu_tmp1_i64);
5624 break;
5625 case 0x3f: /* fistpll */
5626 gen_helper_fistll_ST0(cpu_tmp1_i64);
5627 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5628 (s->mem_index >> 2) - 1);
5629 gen_helper_fpop();
5630 break;
5631 default:
5632 goto illegal_op;
5633 }
5634 } else {
5635 /* register float ops */
5636 opreg = rm;
5637
5638 switch(op) {
5639 case 0x08: /* fld sti */
5640 gen_helper_fpush();
5641 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg + 1) & 7));
5642 break;
5643 case 0x09: /* fxchg sti */
5644 case 0x29: /* fxchg4 sti, undocumented op */
5645 case 0x39: /* fxchg7 sti, undocumented op */
5646 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg));
5647 break;
5648 case 0x0a: /* grp d9/2 */
5649 switch(rm) {
5650 case 0: /* fnop */
5651 /* check exceptions (FreeBSD FPU probe) */
5652 if (s->cc_op != CC_OP_DYNAMIC)
5653 gen_op_set_cc_op(s->cc_op);
5654 gen_jmp_im(pc_start - s->cs_base);
5655 gen_helper_fwait();
5656 break;
5657 default:
5658 goto illegal_op;
5659 }
5660 break;
5661 case 0x0c: /* grp d9/4 */
5662 switch(rm) {
5663 case 0: /* fchs */
5664 gen_helper_fchs_ST0();
5665 break;
5666 case 1: /* fabs */
5667 gen_helper_fabs_ST0();
5668 break;
5669 case 4: /* ftst */
5670 gen_helper_fldz_FT0();
5671 gen_helper_fcom_ST0_FT0();
5672 break;
5673 case 5: /* fxam */
5674 gen_helper_fxam_ST0();
5675 break;
5676 default:
5677 goto illegal_op;
5678 }
5679 break;
5680 case 0x0d: /* grp d9/5 */
5681 {
5682 switch(rm) {
5683 case 0:
5684 gen_helper_fpush();
5685 gen_helper_fld1_ST0();
5686 break;
5687 case 1:
5688 gen_helper_fpush();
5689 gen_helper_fldl2t_ST0();
5690 break;
5691 case 2:
5692 gen_helper_fpush();
5693 gen_helper_fldl2e_ST0();
5694 break;
5695 case 3:
5696 gen_helper_fpush();
5697 gen_helper_fldpi_ST0();
5698 break;
5699 case 4:
5700 gen_helper_fpush();
5701 gen_helper_fldlg2_ST0();
5702 break;
5703 case 5:
5704 gen_helper_fpush();
5705 gen_helper_fldln2_ST0();
5706 break;
5707 case 6:
5708 gen_helper_fpush();
5709 gen_helper_fldz_ST0();
5710 break;
5711 default:
5712 goto illegal_op;
5713 }
5714 }
5715 break;
5716 case 0x0e: /* grp d9/6 */
5717 switch(rm) {
5718 case 0: /* f2xm1 */
5719 gen_helper_f2xm1();
5720 break;
5721 case 1: /* fyl2x */
5722 gen_helper_fyl2x();
5723 break;
5724 case 2: /* fptan */
5725 gen_helper_fptan();
5726 break;
5727 case 3: /* fpatan */
5728 gen_helper_fpatan();
5729 break;
5730 case 4: /* fxtract */
5731 gen_helper_fxtract();
5732 break;
5733 case 5: /* fprem1 */
5734 gen_helper_fprem1();
5735 break;
5736 case 6: /* fdecstp */
5737 gen_helper_fdecstp();
5738 break;
5739 default:
5740 case 7: /* fincstp */
5741 gen_helper_fincstp();
5742 break;
5743 }
5744 break;
5745 case 0x0f: /* grp d9/7 */
5746 switch(rm) {
5747 case 0: /* fprem */
5748 gen_helper_fprem();
5749 break;
5750 case 1: /* fyl2xp1 */
5751 gen_helper_fyl2xp1();
5752 break;
5753 case 2: /* fsqrt */
5754 gen_helper_fsqrt();
5755 break;
5756 case 3: /* fsincos */
5757 gen_helper_fsincos();
5758 break;
5759 case 5: /* fscale */
5760 gen_helper_fscale();
5761 break;
5762 case 4: /* frndint */
5763 gen_helper_frndint();
5764 break;
5765 case 6: /* fsin */
5766 gen_helper_fsin();
5767 break;
5768 default:
5769 case 7: /* fcos */
5770 gen_helper_fcos();
5771 break;
5772 }
5773 break;
5774 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5775 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5776 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5777 {
5778 int op1;
5779
5780 op1 = op & 7;
5781 if (op >= 0x20) {
5782 gen_helper_fp_arith_STN_ST0(op1, opreg);
5783 if (op >= 0x30)
5784 gen_helper_fpop();
5785 } else {
5786 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5787 gen_helper_fp_arith_ST0_FT0(op1);
5788 }
5789 }
5790 break;
5791 case 0x02: /* fcom */
5792 case 0x22: /* fcom2, undocumented op */
5793 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5794 gen_helper_fcom_ST0_FT0();
5795 break;
5796 case 0x03: /* fcomp */
5797 case 0x23: /* fcomp3, undocumented op */
5798 case 0x32: /* fcomp5, undocumented op */
5799 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5800 gen_helper_fcom_ST0_FT0();
5801 gen_helper_fpop();
5802 break;
5803 case 0x15: /* da/5 */
5804 switch(rm) {
5805 case 1: /* fucompp */
5806 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5807 gen_helper_fucom_ST0_FT0();
5808 gen_helper_fpop();
5809 gen_helper_fpop();
5810 break;
5811 default:
5812 goto illegal_op;
5813 }
5814 break;
5815 case 0x1c:
5816 switch(rm) {
5817 case 0: /* feni (287 only, just do nop here) */
5818 break;
5819 case 1: /* fdisi (287 only, just do nop here) */
5820 break;
5821 case 2: /* fclex */
5822 gen_helper_fclex();
5823 break;
5824 case 3: /* fninit */
5825 gen_helper_fninit();
5826 break;
5827 case 4: /* fsetpm (287 only, just do nop here) */
5828 break;
5829 default:
5830 goto illegal_op;
5831 }
5832 break;
5833 case 0x1d: /* fucomi */
5834 if (s->cc_op != CC_OP_DYNAMIC)
5835 gen_op_set_cc_op(s->cc_op);
5836 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5837 gen_helper_fucomi_ST0_FT0();
5838 s->cc_op = CC_OP_EFLAGS;
5839 break;
5840 case 0x1e: /* fcomi */
5841 if (s->cc_op != CC_OP_DYNAMIC)
5842 gen_op_set_cc_op(s->cc_op);
5843 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5844 gen_helper_fcomi_ST0_FT0();
5845 s->cc_op = CC_OP_EFLAGS;
5846 break;
5847 case 0x28: /* ffree sti */
5848 gen_helper_ffree_STN(tcg_const_i32(opreg));
5849 break;
5850 case 0x2a: /* fst sti */
5851 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5852 break;
5853 case 0x2b: /* fstp sti */
5854 case 0x0b: /* fstp1 sti, undocumented op */
5855 case 0x3a: /* fstp8 sti, undocumented op */
5856 case 0x3b: /* fstp9 sti, undocumented op */
5857 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg));
5858 gen_helper_fpop();
5859 break;
5860 case 0x2c: /* fucom st(i) */
5861 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5862 gen_helper_fucom_ST0_FT0();
5863 break;
5864 case 0x2d: /* fucomp st(i) */
5865 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5866 gen_helper_fucom_ST0_FT0();
5867 gen_helper_fpop();
5868 break;
5869 case 0x33: /* de/3 */
5870 switch(rm) {
5871 case 1: /* fcompp */
5872 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5873 gen_helper_fcom_ST0_FT0();
5874 gen_helper_fpop();
5875 gen_helper_fpop();
5876 break;
5877 default:
5878 goto illegal_op;
5879 }
5880 break;
5881 case 0x38: /* ffreep sti, undocumented op */
5882 gen_helper_ffree_STN(tcg_const_i32(opreg));
5883 gen_helper_fpop();
5884 break;
5885 case 0x3c: /* df/4 */
5886 switch(rm) {
5887 case 0:
5888 gen_helper_fnstsw(cpu_tmp2_i32);
5889 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5890 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5891 break;
5892 default:
5893 goto illegal_op;
5894 }
5895 break;
5896 case 0x3d: /* fucomip */
5897 if (s->cc_op != CC_OP_DYNAMIC)
5898 gen_op_set_cc_op(s->cc_op);
5899 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5900 gen_helper_fucomi_ST0_FT0();
5901 gen_helper_fpop();
5902 s->cc_op = CC_OP_EFLAGS;
5903 break;
5904 case 0x3e: /* fcomip */
5905 if (s->cc_op != CC_OP_DYNAMIC)
5906 gen_op_set_cc_op(s->cc_op);
5907 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg));
5908 gen_helper_fcomi_ST0_FT0();
5909 gen_helper_fpop();
5910 s->cc_op = CC_OP_EFLAGS;
5911 break;
5912 case 0x10 ... 0x13: /* fcmovxx */
5913 case 0x18 ... 0x1b:
5914 {
5915 int op1, l1;
5916 static const uint8_t fcmov_cc[8] = {
5917 (JCC_B << 1),
5918 (JCC_Z << 1),
5919 (JCC_BE << 1),
5920 (JCC_P << 1),
5921 };
5922 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
5923 l1 = gen_new_label();
5924 gen_jcc1(s, s->cc_op, op1, l1);
5925 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg));
5926 gen_set_label(l1);
5927 }
5928 break;
5929 default:
5930 goto illegal_op;
5931 }
5932 }
5933 break;
5934 /************************/
5935 /* string ops */
5936
5937 case 0xa4: /* movsS */
5938 case 0xa5:
5939 if ((b & 1) == 0)
5940 ot = OT_BYTE;
5941 else
5942 ot = dflag + OT_WORD;
5943
5944 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5945 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5946 } else {
5947 gen_movs(s, ot);
5948 }
5949 break;
5950
5951 case 0xaa: /* stosS */
5952 case 0xab:
5953 if ((b & 1) == 0)
5954 ot = OT_BYTE;
5955 else
5956 ot = dflag + OT_WORD;
5957
5958 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5959 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5960 } else {
5961 gen_stos(s, ot);
5962 }
5963 break;
5964 case 0xac: /* lodsS */
5965 case 0xad:
5966 if ((b & 1) == 0)
5967 ot = OT_BYTE;
5968 else
5969 ot = dflag + OT_WORD;
5970 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5971 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5972 } else {
5973 gen_lods(s, ot);
5974 }
5975 break;
5976 case 0xae: /* scasS */
5977 case 0xaf:
5978 if ((b & 1) == 0)
5979 ot = OT_BYTE;
5980 else
5981 ot = dflag + OT_WORD;
5982 if (prefixes & PREFIX_REPNZ) {
5983 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5984 } else if (prefixes & PREFIX_REPZ) {
5985 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5986 } else {
5987 gen_scas(s, ot);
5988 s->cc_op = CC_OP_SUBB + ot;
5989 }
5990 break;
5991
5992 case 0xa6: /* cmpsS */
5993 case 0xa7:
5994 if ((b & 1) == 0)
5995 ot = OT_BYTE;
5996 else
5997 ot = dflag + OT_WORD;
5998 if (prefixes & PREFIX_REPNZ) {
5999 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6000 } else if (prefixes & PREFIX_REPZ) {
6001 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6002 } else {
6003 gen_cmps(s, ot);
6004 s->cc_op = CC_OP_SUBB + ot;
6005 }
6006 break;
6007 case 0x6c: /* insS */
6008 case 0x6d:
6009 if ((b & 1) == 0)
6010 ot = OT_BYTE;
6011 else
6012 ot = dflag ? OT_LONG : OT_WORD;
6013 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6014 gen_op_andl_T0_ffff();
6015 gen_check_io(s, ot, pc_start - s->cs_base,
6016 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6017 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6018 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6019 } else {
6020 gen_ins(s, ot);
6021 if (use_icount) {
6022 gen_jmp(s, s->pc - s->cs_base);
6023 }
6024 }
6025 break;
6026 case 0x6e: /* outsS */
6027 case 0x6f:
6028 if ((b & 1) == 0)
6029 ot = OT_BYTE;
6030 else
6031 ot = dflag ? OT_LONG : OT_WORD;
6032 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6033 gen_op_andl_T0_ffff();
6034 gen_check_io(s, ot, pc_start - s->cs_base,
6035 svm_is_rep(prefixes) | 4);
6036 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6037 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6038 } else {
6039 gen_outs(s, ot);
6040 if (use_icount) {
6041 gen_jmp(s, s->pc - s->cs_base);
6042 }
6043 }
6044 break;
6045
6046 /************************/
6047 /* port I/O */
6048
6049 case 0xe4:
6050 case 0xe5:
6051 if ((b & 1) == 0)
6052 ot = OT_BYTE;
6053 else
6054 ot = dflag ? OT_LONG : OT_WORD;
6055 val = ldub_code(s->pc++);
6056 gen_op_movl_T0_im(val);
6057 gen_check_io(s, ot, pc_start - s->cs_base,
6058 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6059 if (use_icount)
6060 gen_io_start();
6061 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6062 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6063 gen_op_mov_reg_T1(ot, R_EAX);
6064 if (use_icount) {
6065 gen_io_end();
6066 gen_jmp(s, s->pc - s->cs_base);
6067 }
6068 break;
6069 case 0xe6:
6070 case 0xe7:
6071 if ((b & 1) == 0)
6072 ot = OT_BYTE;
6073 else
6074 ot = dflag ? OT_LONG : OT_WORD;
6075 val = ldub_code(s->pc++);
6076 gen_op_movl_T0_im(val);
6077 gen_check_io(s, ot, pc_start - s->cs_base,
6078 svm_is_rep(prefixes));
6079 gen_op_mov_TN_reg(ot, 1, R_EAX);
6080
6081 if (use_icount)
6082 gen_io_start();
6083 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6084 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6085 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6086 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6087 if (use_icount) {
6088 gen_io_end();
6089 gen_jmp(s, s->pc - s->cs_base);
6090 }
6091 break;
6092 case 0xec:
6093 case 0xed:
6094 if ((b & 1) == 0)
6095 ot = OT_BYTE;
6096 else
6097 ot = dflag ? OT_LONG : OT_WORD;
6098 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6099 gen_op_andl_T0_ffff();
6100 gen_check_io(s, ot, pc_start - s->cs_base,
6101 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6102 if (use_icount)
6103 gen_io_start();
6104 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6105 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6106 gen_op_mov_reg_T1(ot, R_EAX);
6107 if (use_icount) {
6108 gen_io_end();
6109 gen_jmp(s, s->pc - s->cs_base);
6110 }
6111 break;
6112 case 0xee:
6113 case 0xef:
6114 if ((b & 1) == 0)
6115 ot = OT_BYTE;
6116 else
6117 ot = dflag ? OT_LONG : OT_WORD;
6118 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6119 gen_op_andl_T0_ffff();
6120 gen_check_io(s, ot, pc_start - s->cs_base,
6121 svm_is_rep(prefixes));
6122 gen_op_mov_TN_reg(ot, 1, R_EAX);
6123
6124 if (use_icount)
6125 gen_io_start();
6126 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6127 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6128 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6129 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6130 if (use_icount) {
6131 gen_io_end();
6132 gen_jmp(s, s->pc - s->cs_base);
6133 }
6134 break;
6135
6136 /************************/
6137 /* control */
6138 case 0xc2: /* ret im */
6139 val = ldsw_code(s->pc);
6140 s->pc += 2;
6141 gen_pop_T0(s);
6142 if (CODE64(s) && s->dflag)
6143 s->dflag = 2;
6144 gen_stack_update(s, val + (2 << s->dflag));
6145 if (s->dflag == 0)
6146 gen_op_andl_T0_ffff();
6147 gen_op_jmp_T0();
6148 gen_eob(s);
6149 break;
6150 case 0xc3: /* ret */
6151 gen_pop_T0(s);
6152 gen_pop_update(s);
6153 if (s->dflag == 0)
6154 gen_op_andl_T0_ffff();
6155 gen_op_jmp_T0();
6156 gen_eob(s);
6157 break;
6158 case 0xca: /* lret im */
6159 val = ldsw_code(s->pc);
6160 s->pc += 2;
6161 do_lret:
6162 if (s->pe && !s->vm86) {
6163 if (s->cc_op != CC_OP_DYNAMIC)
6164 gen_op_set_cc_op(s->cc_op);
6165 gen_jmp_im(pc_start - s->cs_base);
6166 gen_helper_lret_protected(tcg_const_i32(s->dflag),
6167 tcg_const_i32(val));
6168 } else {
6169 gen_stack_A0(s);
6170 /* pop offset */
6171 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6172 if (s->dflag == 0)
6173 gen_op_andl_T0_ffff();
6174 /* NOTE: keeping EIP updated is not a problem in case of
6175 exception */
6176 gen_op_jmp_T0();
6177 /* pop selector */
6178 gen_op_addl_A0_im(2 << s->dflag);
6179 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6180 gen_op_movl_seg_T0_vm(R_CS);
6181 /* add stack offset */
6182 gen_stack_update(s, val + (4 << s->dflag));
6183 }
6184 gen_eob(s);
6185 break;
6186 case 0xcb: /* lret */
6187 val = 0;
6188 goto do_lret;
6189 case 0xcf: /* iret */
6190 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6191 if (!s->pe) {
6192 /* real mode */
6193 gen_helper_iret_real(tcg_const_i32(s->dflag));
6194 s->cc_op = CC_OP_EFLAGS;
6195 } else if (s->vm86) {
6196 if (s->iopl != 3) {
6197 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6198 } else {
6199 gen_helper_iret_real(tcg_const_i32(s->dflag));
6200 s->cc_op = CC_OP_EFLAGS;
6201 }
6202 } else {
6203 if (s->cc_op != CC_OP_DYNAMIC)
6204 gen_op_set_cc_op(s->cc_op);
6205 gen_jmp_im(pc_start - s->cs_base);
6206 gen_helper_iret_protected(tcg_const_i32(s->dflag),
6207 tcg_const_i32(s->pc - s->cs_base));
6208 s->cc_op = CC_OP_EFLAGS;
6209 }
6210 gen_eob(s);
6211 break;
6212 case 0xe8: /* call im */
6213 {
6214 if (dflag)
6215 tval = (int32_t)insn_get(s, OT_LONG);
6216 else
6217 tval = (int16_t)insn_get(s, OT_WORD);
6218 next_eip = s->pc - s->cs_base;
6219 tval += next_eip;
6220 if (s->dflag == 0)
6221 tval &= 0xffff;
6222 gen_movtl_T0_im(next_eip);
6223 gen_push_T0(s);
6224 gen_jmp(s, tval);
6225 }
6226 break;
6227 case 0x9a: /* lcall im */
6228 {
6229 unsigned int selector, offset;
6230
6231 if (CODE64(s))
6232 goto illegal_op;
6233 ot = dflag ? OT_LONG : OT_WORD;
6234 offset = insn_get(s, ot);
6235 selector = insn_get(s, OT_WORD);
6236
6237 gen_op_movl_T0_im(selector);
6238 gen_op_movl_T1_imu(offset);
6239 }
6240 goto do_lcall;
6241 case 0xe9: /* jmp im */
6242 if (dflag)
6243 tval = (int32_t)insn_get(s, OT_LONG);
6244 else
6245 tval = (int16_t)insn_get(s, OT_WORD);
6246 tval += s->pc - s->cs_base;
6247 if (s->dflag == 0)
6248 tval &= 0xffff;
6249 else if(!CODE64(s))
6250 tval &= 0xffffffff;
6251 gen_jmp(s, tval);
6252 break;
6253 case 0xea: /* ljmp im */
6254 {
6255 unsigned int selector, offset;
6256
6257 if (CODE64(s))
6258 goto illegal_op;
6259 ot = dflag ? OT_LONG : OT_WORD;
6260 offset = insn_get(s, ot);
6261 selector = insn_get(s, OT_WORD);
6262
6263 gen_op_movl_T0_im(selector);
6264 gen_op_movl_T1_imu(offset);
6265 }
6266 goto do_ljmp;
6267 case 0xeb: /* jmp Jb */
6268 tval = (int8_t)insn_get(s, OT_BYTE);
6269 tval += s->pc - s->cs_base;
6270 if (s->dflag == 0)
6271 tval &= 0xffff;
6272 gen_jmp(s, tval);
6273 break;
6274 case 0x70 ... 0x7f: /* jcc Jb */
6275 tval = (int8_t)insn_get(s, OT_BYTE);
6276 goto do_jcc;
6277 case 0x180 ... 0x18f: /* jcc Jv */
6278 if (dflag) {
6279 tval = (int32_t)insn_get(s, OT_LONG);
6280 } else {
6281 tval = (int16_t)insn_get(s, OT_WORD);
6282 }
6283 do_jcc:
6284 next_eip = s->pc - s->cs_base;
6285 tval += next_eip;
6286 if (s->dflag == 0)
6287 tval &= 0xffff;
6288 gen_jcc(s, b, tval, next_eip);
6289 break;
6290
6291 case 0x190 ... 0x19f: /* setcc Gv */
6292 modrm = ldub_code(s->pc++);
6293 gen_setcc(s, b);
6294 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6295 break;
6296 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6297 {
6298 int l1;
6299 TCGv t0;
6300
6301 ot = dflag + OT_WORD;
6302 modrm = ldub_code(s->pc++);
6303 reg = ((modrm >> 3) & 7) | rex_r;
6304 mod = (modrm >> 6) & 3;
6305 t0 = tcg_temp_local_new();
6306 if (mod != 3) {
6307 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6308 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6309 } else {
6310 rm = (modrm & 7) | REX_B(s);
6311 gen_op_mov_v_reg(ot, t0, rm);
6312 }
6313 #ifdef TARGET_X86_64
6314 if (ot == OT_LONG) {
6315 /* XXX: specific Intel behaviour ? */
6316 l1 = gen_new_label();
6317 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6318 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
6319 gen_set_label(l1);
6320 tcg_gen_movi_tl(cpu_tmp0, 0);
6321 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
6322 } else
6323 #endif
6324 {
6325 l1 = gen_new_label();
6326 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6327 gen_op_mov_reg_v(ot, reg, t0);
6328 gen_set_label(l1);
6329 }
6330 tcg_temp_free(t0);
6331 }
6332 break;
6333
6334 /************************/
6335 /* flags */
6336 case 0x9c: /* pushf */
6337 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6338 if (s->vm86 && s->iopl != 3) {
6339 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6340 } else {
6341 if (s->cc_op != CC_OP_DYNAMIC)
6342 gen_op_set_cc_op(s->cc_op);
6343 gen_helper_read_eflags(cpu_T[0]);
6344 gen_push_T0(s);
6345 }
6346 break;
6347 case 0x9d: /* popf */
6348 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6349 if (s->vm86 && s->iopl != 3) {
6350 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6351 } else {
6352 gen_pop_T0(s);
6353 if (s->cpl == 0) {
6354 if (s->dflag) {
6355 gen_helper_write_eflags(cpu_T[0],
6356 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
6357 } else {
6358 gen_helper_write_eflags(cpu_T[0],
6359 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
6360 }
6361 } else {
6362 if (s->cpl <= s->iopl) {
6363 if (s->dflag) {
6364 gen_helper_write_eflags(cpu_T[0],
6365 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
6366 } else {
6367 gen_helper_write_eflags(cpu_T[0],
6368 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
6369 }
6370 } else {
6371 if (s->dflag) {
6372 gen_helper_write_eflags(cpu_T[0],
6373 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
6374 } else {
6375 gen_helper_write_eflags(cpu_T[0],
6376 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
6377 }
6378 }
6379 }
6380 gen_pop_update(s);
6381 s->cc_op = CC_OP_EFLAGS;
6382 /* abort translation because TF flag may change */
6383 gen_jmp_im(s->pc - s->cs_base);
6384 gen_eob(s);
6385 }
6386 break;
6387 case 0x9e: /* sahf */
6388 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6389 goto illegal_op;
6390 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6391 if (s->cc_op != CC_OP_DYNAMIC)
6392 gen_op_set_cc_op(s->cc_op);
6393 gen_compute_eflags(cpu_cc_src);
6394 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6395 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6396 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6397 s->cc_op = CC_OP_EFLAGS;
6398 break;
6399 case 0x9f: /* lahf */
6400 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6401 goto illegal_op;
6402 if (s->cc_op != CC_OP_DYNAMIC)
6403 gen_op_set_cc_op(s->cc_op);
6404 gen_compute_eflags(cpu_T[0]);
6405 /* Note: gen_compute_eflags() only gives the condition codes */
6406 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6407 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6408 break;
6409 case 0xf5: /* cmc */
6410 if (s->cc_op != CC_OP_DYNAMIC)
6411 gen_op_set_cc_op(s->cc_op);
6412 gen_compute_eflags(cpu_cc_src);
6413 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6414 s->cc_op = CC_OP_EFLAGS;
6415 break;
6416 case 0xf8: /* clc */
6417 if (s->cc_op != CC_OP_DYNAMIC)
6418 gen_op_set_cc_op(s->cc_op);
6419 gen_compute_eflags(cpu_cc_src);
6420 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6421 s->cc_op = CC_OP_EFLAGS;
6422 break;
6423 case 0xf9: /* stc */
6424 if (s->cc_op != CC_OP_DYNAMIC)
6425 gen_op_set_cc_op(s->cc_op);
6426 gen_compute_eflags(cpu_cc_src);
6427 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6428 s->cc_op = CC_OP_EFLAGS;
6429 break;
6430 case 0xfc: /* cld */
6431 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6432 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6433 break;
6434 case 0xfd: /* std */
6435 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6436 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6437 break;
6438
6439 /************************/
6440 /* bit operations */
6441 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6442 ot = dflag + OT_WORD;
6443 modrm = ldub_code(s->pc++);
6444 op = (modrm >> 3) & 7;
6445 mod = (modrm >> 6) & 3;
6446 rm = (modrm & 7) | REX_B(s);
6447 if (mod != 3) {
6448 s->rip_offset = 1;
6449 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6450 gen_op_ld_T0_A0(ot + s->mem_index);
6451 } else {
6452 gen_op_mov_TN_reg(ot, 0, rm);
6453 }
6454 /* load shift */
6455 val = ldub_code(s->pc++);
6456 gen_op_movl_T1_im(val);
6457 if (op < 4)
6458 goto illegal_op;
6459 op -= 4;
6460 goto bt_op;
6461 case 0x1a3: /* bt Gv, Ev */
6462 op = 0;
6463 goto do_btx;
6464 case 0x1ab: /* bts */
6465 op = 1;
6466 goto do_btx;
6467 case 0x1b3: /* btr */
6468 op = 2;
6469 goto do_btx;
6470 case 0x1bb: /* btc */
6471 op = 3;
6472 do_btx:
6473 ot = dflag + OT_WORD;
6474 modrm = ldub_code(s->pc++);
6475 reg = ((modrm >> 3) & 7) | rex_r;
6476 mod = (modrm >> 6) & 3;
6477 rm = (modrm & 7) | REX_B(s);
6478 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6479 if (mod != 3) {
6480 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6481 /* specific case: we need to add a displacement */
6482 gen_exts(ot, cpu_T[1]);
6483 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6484 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6485 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6486 gen_op_ld_T0_A0(ot + s->mem_index);
6487 } else {
6488 gen_op_mov_TN_reg(ot, 0, rm);
6489 }
6490 bt_op:
6491 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6492 switch(op) {
6493 case 0:
6494 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6495 tcg_gen_movi_tl(cpu_cc_dst, 0);
6496 break;
6497 case 1:
6498 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6499 tcg_gen_movi_tl(cpu_tmp0, 1);
6500 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6501 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6502 break;
6503 case 2:
6504 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6505 tcg_gen_movi_tl(cpu_tmp0, 1);
6506 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6507 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6508 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6509 break;
6510 default:
6511 case 3:
6512 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6513 tcg_gen_movi_tl(cpu_tmp0, 1);
6514 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6515 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6516 break;
6517 }
6518 s->cc_op = CC_OP_SARB + ot;
6519 if (op != 0) {
6520 if (mod != 3)
6521 gen_op_st_T0_A0(ot + s->mem_index);
6522 else
6523 gen_op_mov_reg_T0(ot, rm);
6524 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6525 tcg_gen_movi_tl(cpu_cc_dst, 0);
6526 }
6527 break;
6528 case 0x1bc: /* bsf */
6529 case 0x1bd: /* bsr */
6530 {
6531 int label1;
6532 TCGv t0;
6533
6534 ot = dflag + OT_WORD;
6535 modrm = ldub_code(s->pc++);
6536 reg = ((modrm >> 3) & 7) | rex_r;
6537 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
6538 gen_extu(ot, cpu_T[0]);
6539 label1 = gen_new_label();
6540 tcg_gen_movi_tl(cpu_cc_dst, 0);
6541 t0 = tcg_temp_local_new();
6542 tcg_gen_mov_tl(t0, cpu_T[0]);
6543 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6544 if (b & 1) {
6545 gen_helper_bsr(cpu_T[0], t0);
6546 } else {
6547 gen_helper_bsf(cpu_T[0], t0);
6548 }
6549 gen_op_mov_reg_T0(ot, reg);
6550 tcg_gen_movi_tl(cpu_cc_dst, 1);
6551 gen_set_label(label1);
6552 tcg_gen_discard_tl(cpu_cc_src);
6553 s->cc_op = CC_OP_LOGICB + ot;
6554 tcg_temp_free(t0);
6555 }
6556 break;
6557 /************************/
6558 /* bcd */
6559 case 0x27: /* daa */
6560 if (CODE64(s))
6561 goto illegal_op;
6562 if (s->cc_op != CC_OP_DYNAMIC)
6563 gen_op_set_cc_op(s->cc_op);
6564 gen_helper_daa();
6565 s->cc_op = CC_OP_EFLAGS;
6566 break;
6567 case 0x2f: /* das */
6568 if (CODE64(s))
6569 goto illegal_op;
6570 if (s->cc_op != CC_OP_DYNAMIC)
6571 gen_op_set_cc_op(s->cc_op);
6572 gen_helper_das();
6573 s->cc_op = CC_OP_EFLAGS;
6574 break;
6575 case 0x37: /* aaa */
6576 if (CODE64(s))
6577 goto illegal_op;
6578 if (s->cc_op != CC_OP_DYNAMIC)
6579 gen_op_set_cc_op(s->cc_op);
6580 gen_helper_aaa();
6581 s->cc_op = CC_OP_EFLAGS;
6582 break;
6583 case 0x3f: /* aas */
6584 if (CODE64(s))
6585 goto illegal_op;
6586 if (s->cc_op != CC_OP_DYNAMIC)
6587 gen_op_set_cc_op(s->cc_op);
6588 gen_helper_aas();
6589 s->cc_op = CC_OP_EFLAGS;
6590 break;
6591 case 0xd4: /* aam */
6592 if (CODE64(s))
6593 goto illegal_op;
6594 val = ldub_code(s->pc++);
6595 if (val == 0) {
6596 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6597 } else {
6598 gen_helper_aam(tcg_const_i32(val));
6599 s->cc_op = CC_OP_LOGICB;
6600 }
6601 break;
6602 case 0xd5: /* aad */
6603 if (CODE64(s))
6604 goto illegal_op;
6605 val = ldub_code(s->pc++);
6606 gen_helper_aad(tcg_const_i32(val));
6607 s->cc_op = CC_OP_LOGICB;
6608 break;
6609 /************************/
6610 /* misc */
6611 case 0x90: /* nop */
6612 /* XXX: xchg + rex handling */
6613 /* XXX: correct lock test for all insn */
6614 if (prefixes & PREFIX_LOCK)
6615 goto illegal_op;
6616 if (prefixes & PREFIX_REPZ) {
6617 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6618 }
6619 break;
6620 case 0x9b: /* fwait */
6621 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6622 (HF_MP_MASK | HF_TS_MASK)) {
6623 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6624 } else {
6625 if (s->cc_op != CC_OP_DYNAMIC)
6626 gen_op_set_cc_op(s->cc_op);
6627 gen_jmp_im(pc_start - s->cs_base);
6628 gen_helper_fwait();
6629 }
6630 break;
6631 case 0xcc: /* int3 */
6632 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6633 break;
6634 case 0xcd: /* int N */
6635 val = ldub_code(s->pc++);
6636 if (s->vm86 && s->iopl != 3) {
6637 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6638 } else {
6639 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6640 }
6641 break;
6642 case 0xce: /* into */
6643 if (CODE64(s))
6644 goto illegal_op;
6645 if (s->cc_op != CC_OP_DYNAMIC)
6646 gen_op_set_cc_op(s->cc_op);
6647 gen_jmp_im(pc_start - s->cs_base);
6648 gen_helper_into(tcg_const_i32(s->pc - pc_start));
6649 break;
6650 #ifdef WANT_ICEBP
6651 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6652 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6653 #if 1
6654 gen_debug(s, pc_start - s->cs_base);
6655 #else
6656 /* start debug */
6657 tb_flush(cpu_single_env);
6658 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6659 #endif
6660 break;
6661 #endif
6662 case 0xfa: /* cli */
6663 if (!s->vm86) {
6664 if (s->cpl <= s->iopl) {
6665 gen_helper_cli();
6666 } else {
6667 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6668 }
6669 } else {
6670 if (s->iopl == 3) {
6671 gen_helper_cli();
6672 } else {
6673 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6674 }
6675 }
6676 break;
6677 case 0xfb: /* sti */
6678 if (!s->vm86) {
6679 if (s->cpl <= s->iopl) {
6680 gen_sti:
6681 gen_helper_sti();
6682 /* interruptions are enabled only the first insn after sti */
6683 /* If several instructions disable interrupts, only the
6684 _first_ does it */
6685 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6686 gen_helper_set_inhibit_irq();
6687 /* give a chance to handle pending irqs */
6688 gen_jmp_im(s->pc - s->cs_base);
6689 gen_eob(s);
6690 } else {
6691 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6692 }
6693 } else {
6694 if (s->iopl == 3) {
6695 goto gen_sti;
6696 } else {
6697 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6698 }
6699 }
6700 break;
6701 case 0x62: /* bound */
6702 if (CODE64(s))
6703 goto illegal_op;
6704 ot = dflag ? OT_LONG : OT_WORD;
6705 modrm = ldub_code(s->pc++);
6706 reg = (modrm >> 3) & 7;
6707 mod = (modrm >> 6) & 3;
6708 if (mod == 3)
6709 goto illegal_op;
6710 gen_op_mov_TN_reg(ot, 0, reg);
6711 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6712 gen_jmp_im(pc_start - s->cs_base);
6713 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6714 if (ot == OT_WORD)
6715 gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
6716 else
6717 gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
6718 break;
6719 case 0x1c8 ... 0x1cf: /* bswap reg */
6720 reg = (b & 7) | REX_B(s);
6721 #ifdef TARGET_X86_64
6722 if (dflag == 2) {
6723 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6724 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6725 gen_op_mov_reg_T0(OT_QUAD, reg);
6726 } else
6727 #endif
6728 {
6729 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6730 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6731 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6732 gen_op_mov_reg_T0(OT_LONG, reg);
6733 }
6734 break;
6735 case 0xd6: /* salc */
6736 if (CODE64(s))
6737 goto illegal_op;
6738 if (s->cc_op != CC_OP_DYNAMIC)
6739 gen_op_set_cc_op(s->cc_op);
6740 gen_compute_eflags_c(cpu_T[0]);
6741 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6742 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6743 break;
6744 case 0xe0: /* loopnz */
6745 case 0xe1: /* loopz */
6746 case 0xe2: /* loop */
6747 case 0xe3: /* jecxz */
6748 {
6749 int l1, l2, l3;
6750
6751 tval = (int8_t)insn_get(s, OT_BYTE);
6752 next_eip = s->pc - s->cs_base;
6753 tval += next_eip;
6754 if (s->dflag == 0)
6755 tval &= 0xffff;
6756
6757 l1 = gen_new_label();
6758 l2 = gen_new_label();
6759 l3 = gen_new_label();
6760 b &= 3;
6761 switch(b) {
6762 case 0: /* loopnz */
6763 case 1: /* loopz */
6764 if (s->cc_op != CC_OP_DYNAMIC)
6765 gen_op_set_cc_op(s->cc_op);
6766 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6767 gen_op_jz_ecx(s->aflag, l3);
6768 gen_compute_eflags(cpu_tmp0);
6769 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6770 if (b == 0) {
6771 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6772 } else {
6773 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6774 }
6775 break;
6776 case 2: /* loop */
6777 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6778 gen_op_jnz_ecx(s->aflag, l1);
6779 break;
6780 default:
6781 case 3: /* jcxz */
6782 gen_op_jz_ecx(s->aflag, l1);
6783 break;
6784 }
6785
6786 gen_set_label(l3);
6787 gen_jmp_im(next_eip);
6788 tcg_gen_br(l2);
6789
6790 gen_set_label(l1);
6791 gen_jmp_im(tval);
6792 gen_set_label(l2);
6793 gen_eob(s);
6794 }
6795 break;
6796 case 0x130: /* wrmsr */
6797 case 0x132: /* rdmsr */
6798 if (s->cpl != 0) {
6799 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6800 } else {
6801 if (s->cc_op != CC_OP_DYNAMIC)
6802 gen_op_set_cc_op(s->cc_op);
6803 gen_jmp_im(pc_start - s->cs_base);
6804 if (b & 2) {
6805 gen_helper_rdmsr();
6806 } else {
6807 gen_helper_wrmsr();
6808 }
6809 }
6810 break;
6811 case 0x131: /* rdtsc */
6812 if (s->cc_op != CC_OP_DYNAMIC)
6813 gen_op_set_cc_op(s->cc_op);
6814 gen_jmp_im(pc_start - s->cs_base);
6815 if (use_icount)
6816 gen_io_start();
6817 gen_helper_rdtsc();
6818 if (use_icount) {
6819 gen_io_end();
6820 gen_jmp(s, s->pc - s->cs_base);
6821 }
6822 break;
6823 case 0x133: /* rdpmc */
6824 if (s->cc_op != CC_OP_DYNAMIC)
6825 gen_op_set_cc_op(s->cc_op);
6826 gen_jmp_im(pc_start - s->cs_base);
6827 gen_helper_rdpmc();
6828 break;
6829 case 0x134: /* sysenter */
6830 /* For Intel SYSENTER is valid on 64-bit */
6831 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6832 goto illegal_op;
6833 if (!s->pe) {
6834 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6835 } else {
6836 if (s->cc_op != CC_OP_DYNAMIC) {
6837 gen_op_set_cc_op(s->cc_op);
6838 s->cc_op = CC_OP_DYNAMIC;
6839 }
6840 gen_jmp_im(pc_start - s->cs_base);
6841 gen_helper_sysenter();
6842 gen_eob(s);
6843 }
6844 break;
6845 case 0x135: /* sysexit */
6846 /* For Intel SYSEXIT is valid on 64-bit */
6847 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6848 goto illegal_op;
6849 if (!s->pe) {
6850 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6851 } else {
6852 if (s->cc_op != CC_OP_DYNAMIC) {
6853 gen_op_set_cc_op(s->cc_op);
6854 s->cc_op = CC_OP_DYNAMIC;
6855 }
6856 gen_jmp_im(pc_start - s->cs_base);
6857 gen_helper_sysexit(tcg_const_i32(dflag));
6858 gen_eob(s);
6859 }
6860 break;
6861 #ifdef TARGET_X86_64
6862 case 0x105: /* syscall */
6863 /* XXX: is it usable in real mode ? */
6864 if (s->cc_op != CC_OP_DYNAMIC) {
6865 gen_op_set_cc_op(s->cc_op);
6866 s->cc_op = CC_OP_DYNAMIC;
6867 }
6868 gen_jmp_im(pc_start - s->cs_base);
6869 gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
6870 gen_eob(s);
6871 break;
6872 case 0x107: /* sysret */
6873 if (!s->pe) {
6874 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6875 } else {
6876 if (s->cc_op != CC_OP_DYNAMIC) {
6877 gen_op_set_cc_op(s->cc_op);
6878 s->cc_op = CC_OP_DYNAMIC;
6879 }
6880 gen_jmp_im(pc_start - s->cs_base);
6881 gen_helper_sysret(tcg_const_i32(s->dflag));
6882 /* condition codes are modified only in long mode */
6883 if (s->lma)
6884 s->cc_op = CC_OP_EFLAGS;
6885 gen_eob(s);
6886 }
6887 break;
6888 #endif
6889 case 0x1a2: /* cpuid */
6890 if (s->cc_op != CC_OP_DYNAMIC)
6891 gen_op_set_cc_op(s->cc_op);
6892 gen_jmp_im(pc_start - s->cs_base);
6893 gen_helper_cpuid();
6894 break;
6895 case 0xf4: /* hlt */
6896 if (s->cpl != 0) {
6897 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6898 } else {
6899 if (s->cc_op != CC_OP_DYNAMIC)
6900 gen_op_set_cc_op(s->cc_op);
6901 gen_jmp_im(pc_start - s->cs_base);
6902 gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
6903 s->is_jmp = 3;
6904 }
6905 break;
6906 case 0x100:
6907 modrm = ldub_code(s->pc++);
6908 mod = (modrm >> 6) & 3;
6909 op = (modrm >> 3) & 7;
6910 switch(op) {
6911 case 0: /* sldt */
6912 if (!s->pe || s->vm86)
6913 goto illegal_op;
6914 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
6915 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6916 ot = OT_WORD;
6917 if (mod == 3)
6918 ot += s->dflag;
6919 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6920 break;
6921 case 2: /* lldt */
6922 if (!s->pe || s->vm86)
6923 goto illegal_op;
6924 if (s->cpl != 0) {
6925 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6926 } else {
6927 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
6928 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6929 gen_jmp_im(pc_start - s->cs_base);
6930 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6931 gen_helper_lldt(cpu_tmp2_i32);
6932 }
6933 break;
6934 case 1: /* str */
6935 if (!s->pe || s->vm86)
6936 goto illegal_op;
6937 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
6938 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6939 ot = OT_WORD;
6940 if (mod == 3)
6941 ot += s->dflag;
6942 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6943 break;
6944 case 3: /* ltr */
6945 if (!s->pe || s->vm86)
6946 goto illegal_op;
6947 if (s->cpl != 0) {
6948 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6949 } else {
6950 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
6951 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6952 gen_jmp_im(pc_start - s->cs_base);
6953 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6954 gen_helper_ltr(cpu_tmp2_i32);
6955 }
6956 break;
6957 case 4: /* verr */
6958 case 5: /* verw */
6959 if (!s->pe || s->vm86)
6960 goto illegal_op;
6961 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6962 if (s->cc_op != CC_OP_DYNAMIC)
6963 gen_op_set_cc_op(s->cc_op);
6964 if (op == 4)
6965 gen_helper_verr(cpu_T[0]);
6966 else
6967 gen_helper_verw(cpu_T[0]);
6968 s->cc_op = CC_OP_EFLAGS;
6969 break;
6970 default:
6971 goto illegal_op;
6972 }
6973 break;
6974 case 0x101:
6975 modrm = ldub_code(s->pc++);
6976 mod = (modrm >> 6) & 3;
6977 op = (modrm >> 3) & 7;
6978 rm = modrm & 7;
6979 switch(op) {
6980 case 0: /* sgdt */
6981 if (mod == 3)
6982 goto illegal_op;
6983 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
6984 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6985 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
6986 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6987 gen_add_A0_im(s, 2);
6988 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
6989 if (!s->dflag)
6990 gen_op_andl_T0_im(0xffffff);
6991 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6992 break;
6993 case 1:
6994 if (mod == 3) {
6995 switch (rm) {
6996 case 0: /* monitor */
6997 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6998 s->cpl != 0)
6999 goto illegal_op;
7000 if (s->cc_op != CC_OP_DYNAMIC)
7001 gen_op_set_cc_op(s->cc_op);
7002 gen_jmp_im(pc_start - s->cs_base);
7003 #ifdef TARGET_X86_64
7004 if (s->aflag == 2) {
7005 gen_op_movq_A0_reg(R_EAX);
7006 } else
7007 #endif
7008 {
7009 gen_op_movl_A0_reg(R_EAX);
7010 if (s->aflag == 0)
7011 gen_op_andl_A0_ffff();
7012 }
7013 gen_add_A0_ds_seg(s);
7014 gen_helper_monitor(cpu_A0);
7015 break;
7016 case 1: /* mwait */
7017 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7018 s->cpl != 0)
7019 goto illegal_op;
7020 if (s->cc_op != CC_OP_DYNAMIC) {
7021 gen_op_set_cc_op(s->cc_op);
7022 s->cc_op = CC_OP_DYNAMIC;
7023 }
7024 gen_jmp_im(pc_start - s->cs_base);
7025 gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
7026 gen_eob(s);
7027 break;
7028 default:
7029 goto illegal_op;
7030 }
7031 } else { /* sidt */
7032 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7033 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7034 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7035 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7036 gen_add_A0_im(s, 2);
7037 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7038 if (!s->dflag)
7039 gen_op_andl_T0_im(0xffffff);
7040 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7041 }
7042 break;
7043 case 2: /* lgdt */
7044 case 3: /* lidt */
7045 if (mod == 3) {
7046 if (s->cc_op != CC_OP_DYNAMIC)
7047 gen_op_set_cc_op(s->cc_op);
7048 gen_jmp_im(pc_start - s->cs_base);
7049 switch(rm) {
7050 case 0: /* VMRUN */
7051 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7052 goto illegal_op;
7053 if (s->cpl != 0) {
7054 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7055 break;
7056 } else {
7057 gen_helper_vmrun(tcg_const_i32(s->aflag),
7058 tcg_const_i32(s->pc - pc_start));
7059 tcg_gen_exit_tb(0);
7060 s->is_jmp = 3;
7061 }
7062 break;
7063 case 1: /* VMMCALL */
7064 if (!(s->flags & HF_SVME_MASK))
7065 goto illegal_op;
7066 gen_helper_vmmcall();
7067 break;
7068 case 2: /* VMLOAD */
7069 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7070 goto illegal_op;
7071 if (s->cpl != 0) {
7072 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7073 break;
7074 } else {
7075 gen_helper_vmload(tcg_const_i32(s->aflag));
7076 }
7077 break;
7078 case 3: /* VMSAVE */
7079 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7080 goto illegal_op;
7081 if (s->cpl != 0) {
7082 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7083 break;
7084 } else {
7085 gen_helper_vmsave(tcg_const_i32(s->aflag));
7086 }
7087 break;
7088 case 4: /* STGI */
7089 if ((!(s->flags & HF_SVME_MASK) &&
7090 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7091 !s->pe)
7092 goto illegal_op;
7093 if (s->cpl != 0) {
7094 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7095 break;
7096 } else {
7097 gen_helper_stgi();
7098 }
7099 break;
7100 case 5: /* CLGI */
7101 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7102 goto illegal_op;
7103 if (s->cpl != 0) {
7104 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7105 break;
7106 } else {
7107 gen_helper_clgi();
7108 }
7109 break;
7110 case 6: /* SKINIT */
7111 if ((!(s->flags & HF_SVME_MASK) &&
7112 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7113 !s->pe)
7114 goto illegal_op;
7115 gen_helper_skinit();
7116 break;
7117 case 7: /* INVLPGA */
7118 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7119 goto illegal_op;
7120 if (s->cpl != 0) {
7121 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7122 break;
7123 } else {
7124 gen_helper_invlpga(tcg_const_i32(s->aflag));
7125 }
7126 break;
7127 default:
7128 goto illegal_op;
7129 }
7130 } else if (s->cpl != 0) {
7131 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7132 } else {
7133 gen_svm_check_intercept(s, pc_start,
7134 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7135 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7136 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7137 gen_add_A0_im(s, 2);
7138 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7139 if (!s->dflag)
7140 gen_op_andl_T0_im(0xffffff);
7141 if (op == 2) {
7142 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7143 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7144 } else {
7145 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7146 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7147 }
7148 }
7149 break;
7150 case 4: /* smsw */
7151 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7152 #if defined TARGET_X86_64 && defined WORDS_BIGENDIAN
7153 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7154 #else
7155 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7156 #endif
7157 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7158 break;
7159 case 6: /* lmsw */
7160 if (s->cpl != 0) {
7161 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7162 } else {
7163 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7164 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7165 gen_helper_lmsw(cpu_T[0]);
7166 gen_jmp_im(s->pc - s->cs_base);
7167 gen_eob(s);
7168 }
7169 break;
7170 case 7: /* invlpg */
7171 if (s->cpl != 0) {
7172 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7173 } else {
7174 if (mod == 3) {
7175 #ifdef TARGET_X86_64
7176 if (CODE64(s) && rm == 0) {
7177 /* swapgs */
7178 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
7179 tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
7180 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
7181 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
7182 } else
7183 #endif
7184 {
7185 goto illegal_op;
7186 }
7187 } else {
7188 if (s->cc_op != CC_OP_DYNAMIC)
7189 gen_op_set_cc_op(s->cc_op);
7190 gen_jmp_im(pc_start - s->cs_base);
7191 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7192 gen_helper_invlpg(cpu_A0);
7193 gen_jmp_im(s->pc - s->cs_base);
7194 gen_eob(s);
7195 }
7196 }
7197 break;
7198 default:
7199 goto illegal_op;
7200 }
7201 break;
7202 case 0x108: /* invd */
7203 case 0x109: /* wbinvd */
7204 if (s->cpl != 0) {
7205 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7206 } else {
7207 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7208 /* nothing to do */
7209 }
7210 break;
7211 case 0x63: /* arpl or movslS (x86_64) */
7212 #ifdef TARGET_X86_64
7213 if (CODE64(s)) {
7214 int d_ot;
7215 /* d_ot is the size of destination */
7216 d_ot = dflag + OT_WORD;
7217
7218 modrm = ldub_code(s->pc++);
7219 reg = ((modrm >> 3) & 7) | rex_r;
7220 mod = (modrm >> 6) & 3;
7221 rm = (modrm & 7) | REX_B(s);
7222
7223 if (mod == 3) {
7224 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7225 /* sign extend */
7226 if (d_ot == OT_QUAD)
7227 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7228 gen_op_mov_reg_T0(d_ot, reg);
7229 } else {
7230 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7231 if (d_ot == OT_QUAD) {
7232 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7233 } else {
7234 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7235 }
7236 gen_op_mov_reg_T0(d_ot, reg);
7237 }
7238 } else
7239 #endif
7240 {
7241 int label1;
7242 TCGv t0, t1, t2;
7243
7244 if (!s->pe || s->vm86)
7245 goto illegal_op;
7246 t0 = tcg_temp_local_new();
7247 t1 = tcg_temp_local_new();
7248 t2 = tcg_temp_local_new();
7249 ot = OT_WORD;
7250 modrm = ldub_code(s->pc++);
7251 reg = (modrm >> 3) & 7;
7252 mod = (modrm >> 6) & 3;
7253 rm = modrm & 7;
7254 if (mod != 3) {
7255 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7256 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7257 } else {
7258 gen_op_mov_v_reg(ot, t0, rm);
7259 }
7260 gen_op_mov_v_reg(ot, t1, reg);
7261 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7262 tcg_gen_andi_tl(t1, t1, 3);
7263 tcg_gen_movi_tl(t2, 0);
7264 label1 = gen_new_label();
7265 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7266 tcg_gen_andi_tl(t0, t0, ~3);
7267 tcg_gen_or_tl(t0, t0, t1);
7268 tcg_gen_movi_tl(t2, CC_Z);
7269 gen_set_label(label1);
7270 if (mod != 3) {
7271 gen_op_st_v(ot + s->mem_index, t0, cpu_A0);
7272 } else {
7273 gen_op_mov_reg_v(ot, rm, t0);
7274 }
7275 if (s->cc_op != CC_OP_DYNAMIC)
7276 gen_op_set_cc_op(s->cc_op);
7277 gen_compute_eflags(cpu_cc_src);
7278 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7279 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7280 s->cc_op = CC_OP_EFLAGS;
7281 tcg_temp_free(t0);
7282 tcg_temp_free(t1);
7283 tcg_temp_free(t2);
7284 }
7285 break;
7286 case 0x102: /* lar */
7287 case 0x103: /* lsl */
7288 {
7289 int label1;
7290 TCGv t0;
7291 if (!s->pe || s->vm86)
7292 goto illegal_op;
7293 ot = dflag ? OT_LONG : OT_WORD;
7294 modrm = ldub_code(s->pc++);
7295 reg = ((modrm >> 3) & 7) | rex_r;
7296 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7297 t0 = tcg_temp_local_new();
7298 if (s->cc_op != CC_OP_DYNAMIC)
7299 gen_op_set_cc_op(s->cc_op);
7300 if (b == 0x102)
7301 gen_helper_lar(t0, cpu_T[0]);
7302 else
7303 gen_helper_lsl(t0, cpu_T[0]);
7304 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7305 label1 = gen_new_label();
7306 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7307 gen_op_mov_reg_v(ot, reg, t0);
7308 gen_set_label(label1);
7309 s->cc_op = CC_OP_EFLAGS;
7310 tcg_temp_free(t0);
7311 }
7312 break;
7313 case 0x118:
7314 modrm = ldub_code(s->pc++);
7315 mod = (modrm >> 6) & 3;
7316 op = (modrm >> 3) & 7;
7317 switch(op) {
7318 case 0: /* prefetchnta */
7319 case 1: /* prefetchnt0 */
7320 case 2: /* prefetchnt0 */
7321 case 3: /* prefetchnt0 */
7322 if (mod == 3)
7323 goto illegal_op;
7324 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7325 /* nothing more to do */
7326 break;
7327 default: /* nop (multi byte) */
7328 gen_nop_modrm(s, modrm);
7329 break;
7330 }
7331 break;
7332 case 0x119 ... 0x11f: /* nop (multi byte) */
7333 modrm = ldub_code(s->pc++);
7334 gen_nop_modrm(s, modrm);
7335 break;
7336 case 0x120: /* mov reg, crN */
7337 case 0x122: /* mov crN, reg */
7338 if (s->cpl != 0) {
7339 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7340 } else {
7341 modrm = ldub_code(s->pc++);
7342 if ((modrm & 0xc0) != 0xc0)
7343 goto illegal_op;
7344 rm = (modrm & 7) | REX_B(s);
7345 reg = ((modrm >> 3) & 7) | rex_r;
7346 if (CODE64(s))
7347 ot = OT_QUAD;
7348 else
7349 ot = OT_LONG;
7350 switch(reg) {
7351 case 0:
7352 case 2:
7353 case 3:
7354 case 4:
7355 case 8:
7356 if (s->cc_op != CC_OP_DYNAMIC)
7357 gen_op_set_cc_op(s->cc_op);
7358 gen_jmp_im(pc_start - s->cs_base);
7359 if (b & 2) {
7360 gen_op_mov_TN_reg(ot, 0, rm);
7361 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
7362 gen_jmp_im(s->pc - s->cs_base);
7363 gen_eob(s);
7364 } else {
7365 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7366 gen_op_mov_reg_T0(ot, rm);
7367 }
7368 break;
7369 default:
7370 goto illegal_op;
7371 }
7372 }
7373 break;
7374 case 0x121: /* mov reg, drN */
7375 case 0x123: /* mov drN, reg */
7376 if (s->cpl != 0) {
7377 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7378 } else {
7379 modrm = ldub_code(s->pc++);
7380 if ((modrm & 0xc0) != 0xc0)
7381 goto illegal_op;
7382 rm = (modrm & 7) | REX_B(s);
7383 reg = ((modrm >> 3) & 7) | rex_r;
7384 if (CODE64(s))
7385 ot = OT_QUAD;
7386 else
7387 ot = OT_LONG;
7388 /* XXX: do it dynamically with CR4.DE bit */
7389 if (reg == 4 || reg == 5 || reg >= 8)
7390 goto illegal_op;
7391 if (b & 2) {
7392 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7393 gen_op_mov_TN_reg(ot, 0, rm);
7394 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
7395 gen_jmp_im(s->pc - s->cs_base);
7396 gen_eob(s);
7397 } else {
7398 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7399 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7400 gen_op_mov_reg_T0(ot, rm);
7401 }
7402 }
7403 break;
7404 case 0x106: /* clts */
7405 if (s->cpl != 0) {
7406 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7407 } else {
7408 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7409 gen_helper_clts();
7410 /* abort block because static cpu state changed */
7411 gen_jmp_im(s->pc - s->cs_base);
7412 gen_eob(s);
7413 }
7414 break;
7415 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7416 case 0x1c3: /* MOVNTI reg, mem */
7417 if (!(s->cpuid_features & CPUID_SSE2))
7418 goto illegal_op;
7419 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7420 modrm = ldub_code(s->pc++);
7421 mod = (modrm >> 6) & 3;
7422 if (mod == 3)
7423 goto illegal_op;
7424 reg = ((modrm >> 3) & 7) | rex_r;
7425 /* generate a generic store */
7426 gen_ldst_modrm(s, modrm, ot, reg, 1);
7427 break;
7428 case 0x1ae:
7429 modrm = ldub_code(s->pc++);
7430 mod = (modrm >> 6) & 3;
7431 op = (modrm >> 3) & 7;
7432 switch(op) {
7433 case 0: /* fxsave */
7434 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7435 (s->flags & HF_EM_MASK))
7436 goto illegal_op;
7437 if (s->flags & HF_TS_MASK) {
7438 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7439 break;
7440 }
7441 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7442 if (s->cc_op != CC_OP_DYNAMIC)
7443 gen_op_set_cc_op(s->cc_op);
7444 gen_jmp_im(pc_start - s->cs_base);
7445 gen_helper_fxsave(cpu_A0, tcg_const_i32((s->dflag == 2)));
7446 break;
7447 case 1: /* fxrstor */
7448 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7449 (s->flags & HF_EM_MASK))
7450 goto illegal_op;
7451 if (s->flags & HF_TS_MASK) {
7452 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7453 break;
7454 }
7455 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7456 if (s->cc_op != CC_OP_DYNAMIC)
7457 gen_op_set_cc_op(s->cc_op);
7458 gen_jmp_im(pc_start - s->cs_base);
7459 gen_helper_fxrstor(cpu_A0, tcg_const_i32((s->dflag == 2)));
7460 break;
7461 case 2: /* ldmxcsr */
7462 case 3: /* stmxcsr */
7463 if (s->flags & HF_TS_MASK) {
7464 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7465 break;
7466 }
7467 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7468 mod == 3)
7469 goto illegal_op;
7470 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7471 if (op == 2) {
7472 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7473 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7474 } else {
7475 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7476 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7477 }
7478 break;
7479 case 5: /* lfence */
7480 case 6: /* mfence */
7481 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
7482 goto illegal_op;
7483 break;
7484 case 7: /* sfence / clflush */
7485 if ((modrm & 0xc7) == 0xc0) {
7486 /* sfence */
7487 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7488 if (!(s->cpuid_features & CPUID_SSE))
7489 goto illegal_op;
7490 } else {
7491 /* clflush */
7492 if (!(s->cpuid_features & CPUID_CLFLUSH))
7493 goto illegal_op;
7494 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7495 }
7496 break;
7497 default:
7498 goto illegal_op;
7499 }
7500 break;
7501 case 0x10d: /* 3DNow! prefetch(w) */
7502 modrm = ldub_code(s->pc++);
7503 mod = (modrm >> 6) & 3;
7504 if (mod == 3)
7505 goto illegal_op;
7506 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7507 /* ignore for now */
7508 break;
7509 case 0x1aa: /* rsm */
7510 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7511 if (!(s->flags & HF_SMM_MASK))
7512 goto illegal_op;
7513 if (s->cc_op != CC_OP_DYNAMIC) {
7514 gen_op_set_cc_op(s->cc_op);
7515 s->cc_op = CC_OP_DYNAMIC;
7516 }
7517 gen_jmp_im(s->pc - s->cs_base);
7518 gen_helper_rsm();
7519 gen_eob(s);
7520 break;
7521 case 0x1b8: /* SSE4.2 popcnt */
7522 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7523 PREFIX_REPZ)
7524 goto illegal_op;
7525 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7526 goto illegal_op;
7527
7528 modrm = ldub_code(s->pc++);
7529 reg = ((modrm >> 3) & 7);
7530
7531 if (s->prefix & PREFIX_DATA)
7532 ot = OT_WORD;
7533 else if (s->dflag != 2)
7534 ot = OT_LONG;
7535 else
7536 ot = OT_QUAD;
7537
7538 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7539 gen_helper_popcnt(cpu_T[0], cpu_T[0], tcg_const_i32(ot));
7540 gen_op_mov_reg_T0(ot, reg);
7541
7542 s->cc_op = CC_OP_EFLAGS;
7543 break;
7544 case 0x10e ... 0x10f:
7545 /* 3DNow! instructions, ignore prefixes */
7546 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7547 case 0x110 ... 0x117:
7548 case 0x128 ... 0x12f:
7549 case 0x138 ... 0x13a:
7550 case 0x150 ... 0x177:
7551 case 0x17c ... 0x17f:
7552 case 0x1c2:
7553 case 0x1c4 ... 0x1c6:
7554 case 0x1d0 ... 0x1fe:
7555 gen_sse(s, b, pc_start, rex_r);
7556 break;
7557 default:
7558 goto illegal_op;
7559 }
7560 /* lock generation */
7561 if (s->prefix & PREFIX_LOCK)
7562 gen_helper_unlock();
7563 return s->pc;
7564 illegal_op:
7565 if (s->prefix & PREFIX_LOCK)
7566 gen_helper_unlock();
7567 /* XXX: ensure that no lock was generated */
7568 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7569 return s->pc;
7570 }
7571
7572 void optimize_flags_init(void)
7573 {
7574 #if TCG_TARGET_REG_BITS == 32
7575 assert(sizeof(CCTable) == (1 << 3));
7576 #else
7577 assert(sizeof(CCTable) == (1 << 4));
7578 #endif
7579 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7580 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7581 offsetof(CPUState, cc_op), "cc_op");
7582 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
7583 "cc_src");
7584 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
7585 "cc_dst");
7586 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
7587 "cc_tmp");
7588
7589 /* register helpers */
7590 #define GEN_HELPER 2
7591 #include "helper.h"
7592 }
7593
7594 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7595 basic block 'tb'. If search_pc is TRUE, also generate PC
7596 information for each intermediate instruction. */
7597 static inline void gen_intermediate_code_internal(CPUState *env,
7598 TranslationBlock *tb,
7599 int search_pc)
7600 {
7601 DisasContext dc1, *dc = &dc1;
7602 target_ulong pc_ptr;
7603 uint16_t *gen_opc_end;
7604 CPUBreakpoint *bp;
7605 int j, lj, cflags;
7606 uint64_t flags;
7607 target_ulong pc_start;
7608 target_ulong cs_base;
7609 int num_insns;
7610 int max_insns;
7611
7612 /* generate intermediate code */
7613 pc_start = tb->pc;
7614 cs_base = tb->cs_base;
7615 flags = tb->flags;
7616 cflags = tb->cflags;
7617
7618 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7619 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7620 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7621 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7622 dc->f_st = 0;
7623 dc->vm86 = (flags >> VM_SHIFT) & 1;
7624 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7625 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7626 dc->tf = (flags >> TF_SHIFT) & 1;
7627 dc->singlestep_enabled = env->singlestep_enabled;
7628 dc->cc_op = CC_OP_DYNAMIC;
7629 dc->cs_base = cs_base;
7630 dc->tb = tb;
7631 dc->popl_esp_hack = 0;
7632 /* select memory access functions */
7633 dc->mem_index = 0;
7634 if (flags & HF_SOFTMMU_MASK) {
7635 if (dc->cpl == 3)
7636 dc->mem_index = 2 * 4;
7637 else
7638 dc->mem_index = 1 * 4;
7639 }
7640 dc->cpuid_features = env->cpuid_features;
7641 dc->cpuid_ext_features = env->cpuid_ext_features;
7642 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7643 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7644 #ifdef TARGET_X86_64
7645 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7646 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7647 #endif
7648 dc->flags = flags;
7649 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7650 (flags & HF_INHIBIT_IRQ_MASK)
7651 #ifndef CONFIG_SOFTMMU
7652 || (flags & HF_SOFTMMU_MASK)
7653 #endif
7654 );
7655 #if 0
7656 /* check addseg logic */
7657 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7658 printf("ERROR addseg\n");
7659 #endif
7660
7661 cpu_T[0] = tcg_temp_new();
7662 cpu_T[1] = tcg_temp_new();
7663 cpu_A0 = tcg_temp_new();
7664 cpu_T3 = tcg_temp_new();
7665
7666 cpu_tmp0 = tcg_temp_new();
7667 cpu_tmp1_i64 = tcg_temp_new_i64();
7668 cpu_tmp2_i32 = tcg_temp_new_i32();
7669 cpu_tmp3_i32 = tcg_temp_new_i32();
7670 cpu_tmp4 = tcg_temp_new();
7671 cpu_tmp5 = tcg_temp_new();
7672 cpu_tmp6 = tcg_temp_new();
7673 cpu_ptr0 = tcg_temp_new_ptr();
7674 cpu_ptr1 = tcg_temp_new_ptr();
7675
7676 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7677
7678 dc->is_jmp = DISAS_NEXT;
7679 pc_ptr = pc_start;
7680 lj = -1;
7681 num_insns = 0;
7682 max_insns = tb->cflags & CF_COUNT_MASK;
7683 if (max_insns == 0)
7684 max_insns = CF_COUNT_MASK;
7685
7686 gen_icount_start();
7687 for(;;) {
7688 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
7689 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
7690 if (bp->pc == pc_ptr) {
7691 gen_debug(dc, pc_ptr - dc->cs_base);
7692 break;
7693 }
7694 }
7695 }
7696 if (search_pc) {
7697 j = gen_opc_ptr - gen_opc_buf;
7698 if (lj < j) {
7699 lj++;
7700 while (lj < j)
7701 gen_opc_instr_start[lj++] = 0;
7702 }
7703 gen_opc_pc[lj] = pc_ptr;
7704 gen_opc_cc_op[lj] = dc->cc_op;
7705 gen_opc_instr_start[lj] = 1;
7706 gen_opc_icount[lj] = num_insns;
7707 }
7708 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7709 gen_io_start();
7710
7711 pc_ptr = disas_insn(dc, pc_ptr);
7712 num_insns++;
7713 /* stop translation if indicated */
7714 if (dc->is_jmp)
7715 break;
7716 /* if single step mode, we generate only one instruction and
7717 generate an exception */
7718 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7719 the flag and abort the translation to give the irqs a
7720 change to be happen */
7721 if (dc->tf || dc->singlestep_enabled ||
7722 (flags & HF_INHIBIT_IRQ_MASK)) {
7723 gen_jmp_im(pc_ptr - dc->cs_base);
7724 gen_eob(dc);
7725 break;
7726 }
7727 /* if too long translation, stop generation too */
7728 if (gen_opc_ptr >= gen_opc_end ||
7729 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7730 num_insns >= max_insns) {
7731 gen_jmp_im(pc_ptr - dc->cs_base);
7732 gen_eob(dc);
7733 break;
7734 }
7735 if (singlestep) {
7736 gen_jmp_im(pc_ptr - dc->cs_base);
7737 gen_eob(dc);
7738 break;
7739 }
7740 }
7741 if (tb->cflags & CF_LAST_IO)
7742 gen_io_end();
7743 gen_icount_end(tb, num_insns);
7744 *gen_opc_ptr = INDEX_op_end;
7745 /* we don't forget to fill the last values */
7746 if (search_pc) {
7747 j = gen_opc_ptr - gen_opc_buf;
7748 lj++;
7749 while (lj <= j)
7750 gen_opc_instr_start[lj++] = 0;
7751 }
7752
7753 #ifdef DEBUG_DISAS
7754 log_cpu_state_mask(CPU_LOG_TB_CPU, env, X86_DUMP_CCOP);
7755 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
7756 int disas_flags;
7757 qemu_log("----------------\n");
7758 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7759 #ifdef TARGET_X86_64
7760 if (dc->code64)
7761 disas_flags = 2;
7762 else
7763 #endif
7764 disas_flags = !dc->code32;
7765 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7766 qemu_log("\n");
7767 }
7768 #endif
7769
7770 if (!search_pc) {
7771 tb->size = pc_ptr - pc_start;
7772 tb->icount = num_insns;
7773 }
7774 }
7775
7776 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7777 {
7778 gen_intermediate_code_internal(env, tb, 0);
7779 }
7780
7781 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7782 {
7783 gen_intermediate_code_internal(env, tb, 1);
7784 }
7785
7786 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7787 unsigned long searched_pc, int pc_pos, void *puc)
7788 {
7789 int cc_op;
7790 #ifdef DEBUG_DISAS
7791 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
7792 int i;
7793 qemu_log("RESTORE:\n");
7794 for(i = 0;i <= pc_pos; i++) {
7795 if (gen_opc_instr_start[i]) {
7796 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7797 }
7798 }
7799 qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7800 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7801 (uint32_t)tb->cs_base);
7802 }
7803 #endif
7804 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7805 cc_op = gen_opc_cc_op[pc_pos];
7806 if (cc_op != CC_OP_DYNAMIC)
7807 env->cc_op = cc_op;
7808 }
Samsung s3c2440 and arm920t support for the mini2440 dev board