target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26
  27 //#define DEBUG_KVM
  28
  29 #ifdef DEBUG_KVM
  30 #define dprintf(fmt, ...) \
  31     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  32 #else
  33 #define dprintf(fmt, ...) \
  34     do { } while (0)
  35 #endif
  36
  37 #ifdef KVM_CAP_EXT_CPUID
  38
  39 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  40 {
  41     struct kvm_cpuid2 *cpuid;
  42     int r, size;
  43
  44     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  45     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  46     cpuid->nent = max;
  47     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  48     if (r < 0) {
  49         if (r == -E2BIG) {
  50             qemu_free(cpuid);
  51             return NULL;
  52         } else {
  53             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  54                     strerror(-r));
  55             exit(1);
  56         }
  57     }
  58     return cpuid;
  59 }
  60
  61 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  62 {
  63     struct kvm_cpuid2 *cpuid;
  64     int i, max;
  65     uint32_t ret = 0;
  66     uint32_t cpuid_1_edx;
  67
  68     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  69         return -1U;
  70     }
  71
  72     max = 1;
  73     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  74         max *= 2;
  75     }
  76
  77     for (i = 0; i < cpuid->nent; ++i) {
  78         if (cpuid->entries[i].function == function) {
  79             switch (reg) {
  80             case R_EAX:
  81                 ret = cpuid->entries[i].eax;
  82                 break;
  83             case R_EBX:
  84                 ret = cpuid->entries[i].ebx;
  85                 break;
  86             case R_ECX:
  87                 ret = cpuid->entries[i].ecx;
  88                 break;
  89             case R_EDX:
  90                 ret = cpuid->entries[i].edx;
  91                 if (function == 0x80000001) {
  92                     /* On Intel, kvm returns cpuid according to the Intel spec,
  93                      * so add missing bits according to the AMD spec:
  94                      */
  95                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
  96                     ret |= cpuid_1_edx & 0xdfeff7ff;
  97                 }
  98                 break;
  99             }
 100         }
 101     }
 102
 103     qemu_free(cpuid);
 104
 105     return ret;
 106 }
 107
 108 #else
 109
 110 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 111 {
 112     return -1U;
 113 }
 114
 115 #endif
 116
 117 int kvm_arch_init_vcpu(CPUState *env)
 118 {
 119     struct {
 120         struct kvm_cpuid2 cpuid;
 121         struct kvm_cpuid_entry2 entries[100];
 122     } __attribute__((packed)) cpuid_data;
 123     uint32_t limit, i, j, cpuid_i;
 124     uint32_t unused;
 125
 126     cpuid_i = 0;
 127
 128     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 129
 130     for (i = 0; i <= limit; i++) {
 131         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 132
 133         switch (i) {
 134         case 2: {
 135             /* Keep reading function 2 till all the input is received */
 136             int times;
 137
 138             c->function = i;
 139             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 140                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 141             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 142             times = c->eax & 0xff;
 143
 144             for (j = 1; j < times; ++j) {
 145                 c = &cpuid_data.entries[cpuid_i++];
 146                 c->function = i;
 147                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 148                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 149             }
 150             break;
 151         }
 152         case 4:
 153         case 0xb:
 154         case 0xd:
 155             for (j = 0; ; j++) {
 156                 c->function = i;
 157                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 158                 c->index = j;
 159                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 160
 161                 if (i == 4 && c->eax == 0)
 162                     break;
 163                 if (i == 0xb && !(c->ecx & 0xff00))
 164                     break;
 165                 if (i == 0xd && c->eax == 0)
 166                     break;
 167
 168                 c = &cpuid_data.entries[cpuid_i++];
 169             }
 170             break;
 171         default:
 172             c->function = i;
 173             c->flags = 0;
 174             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 175             break;
 176         }
 177     }
 178     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 179
 180     for (i = 0x80000000; i <= limit; i++) {
 181         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 182
 183         c->function = i;
 184         c->flags = 0;
 185         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 186     }
 187
 188     cpuid_data.cpuid.nent = cpuid_i;
 189
 190     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 191 }
 192
 193 static int kvm_has_msr_star(CPUState *env)
 194 {
 195     static int has_msr_star;
 196     int ret;
 197
 198     /* first time */
 199     if (has_msr_star == 0) {
 200         struct kvm_msr_list msr_list, *kvm_msr_list;
 201
 202         has_msr_star = -1;
 203
 204         /* Obtain MSR list from KVM.  These are the MSRs that we must
 205          * save/restore */
 206         msr_list.nmsrs = 0;
 207         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 208         if (ret < 0)
 209             return 0;
 210
 211         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 212                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 213
 214         kvm_msr_list->nmsrs = msr_list.nmsrs;
 215         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 216         if (ret >= 0) {
 217             int i;
 218
 219             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 220                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 221                     has_msr_star = 1;
 222                     break;
 223                 }
 224             }
 225         }
 226
 227         free(kvm_msr_list);
 228     }
 229
 230     if (has_msr_star == 1)
 231         return 1;
 232     return 0;
 233 }
 234
 235 int kvm_arch_init(KVMState *s, int smp_cpus)
 236 {
 237     int ret;
 238
 239     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 240      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 241      * must be part of guest physical memory, we need to allocate it.  Older
 242      * versions of KVM just assumed that it would be at the end of physical
 243      * memory but that doesn't work with more than 4GB of memory.  We simply
 244      * refuse to work with those older versions of KVM. */
 245     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 246     if (ret <= 0) {
 247         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 248         return ret;
 249     }
 250
 251     /* this address is 3 pages before the bios, and the bios should present
 252      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 253      * this?
 254      */
 255     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 256 }
 257
 258 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 259 {
 260     lhs->selector = rhs->selector;
 261     lhs->base = rhs->base;
 262     lhs->limit = rhs->limit;
 263     lhs->type = 3;
 264     lhs->present = 1;
 265     lhs->dpl = 3;
 266     lhs->db = 0;
 267     lhs->s = 1;
 268     lhs->l = 0;
 269     lhs->g = 0;
 270     lhs->avl = 0;
 271     lhs->unusable = 0;
 272 }
 273
 274 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 275 {
 276     unsigned flags = rhs->flags;
 277     lhs->selector = rhs->selector;
 278     lhs->base = rhs->base;
 279     lhs->limit = rhs->limit;
 280     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 281     lhs->present = (flags & DESC_P_MASK) != 0;
 282     lhs->dpl = rhs->selector & 3;
 283     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 284     lhs->s = (flags & DESC_S_MASK) != 0;
 285     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 286     lhs->g = (flags & DESC_G_MASK) != 0;
 287     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 288     lhs->unusable = 0;
 289 }
 290
 291 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 292 {
 293     lhs->selector = rhs->selector;
 294     lhs->base = rhs->base;
 295     lhs->limit = rhs->limit;
 296     lhs->flags =
 297         (rhs->type << DESC_TYPE_SHIFT)
 298         | (rhs->present * DESC_P_MASK)
 299         | (rhs->dpl << DESC_DPL_SHIFT)
 300         | (rhs->db << DESC_B_SHIFT)
 301         | (rhs->s * DESC_S_MASK)
 302         | (rhs->l << DESC_L_SHIFT)
 303         | (rhs->g * DESC_G_MASK)
 304         | (rhs->avl * DESC_AVL_MASK);
 305 }
 306
 307 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 308 {
 309     if (set)
 310         *kvm_reg = *qemu_reg;
 311     else
 312         *qemu_reg = *kvm_reg;
 313 }
 314
 315 static int kvm_getput_regs(CPUState *env, int set)
 316 {
 317     struct kvm_regs regs;
 318     int ret = 0;
 319
 320     if (!set) {
 321         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 322         if (ret < 0)
 323             return ret;
 324     }
 325
 326     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 327     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 328     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 329     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 330     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 331     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 332     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 333     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 334 #ifdef TARGET_X86_64
 335     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 336     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 337     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 338     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 339     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 340     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 341     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 342     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 343 #endif
 344
 345     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 346     kvm_getput_reg(&regs.rip, &env->eip, set);
 347
 348     if (set)
 349         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 350
 351     return ret;
 352 }
 353
 354 static int kvm_put_fpu(CPUState *env)
 355 {
 356     struct kvm_fpu fpu;
 357     int i;
 358
 359     memset(&fpu, 0, sizeof fpu);
 360     fpu.fsw = env->fpus & ~(7 << 11);
 361     fpu.fsw |= (env->fpstt & 7) << 11;
 362     fpu.fcw = env->fpuc;
 363     for (i = 0; i < 8; ++i)
 364         fpu.ftwx |= (!env->fptags[i]) << i;
 365     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 366     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 367     fpu.mxcsr = env->mxcsr;
 368
 369     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 370 }
 371
 372 static int kvm_put_sregs(CPUState *env)
 373 {
 374     struct kvm_sregs sregs;
 375
 376     memcpy(sregs.interrupt_bitmap,
 377            env->interrupt_bitmap,
 378            sizeof(sregs.interrupt_bitmap));
 379
 380     if ((env->eflags & VM_MASK)) {
 381             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 382             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 383             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 384             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 385             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 386             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 387     } else {
 388             set_seg(&sregs.cs, &env->segs[R_CS]);
 389             set_seg(&sregs.ds, &env->segs[R_DS]);
 390             set_seg(&sregs.es, &env->segs[R_ES]);
 391             set_seg(&sregs.fs, &env->segs[R_FS]);
 392             set_seg(&sregs.gs, &env->segs[R_GS]);
 393             set_seg(&sregs.ss, &env->segs[R_SS]);
 394
 395             if (env->cr[0] & CR0_PE_MASK) {
 396                 /* force ss cpl to cs cpl */
 397                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 398                         (sregs.cs.selector & 3);
 399                 sregs.ss.dpl = sregs.ss.selector & 3;
 400             }
 401     }
 402
 403     set_seg(&sregs.tr, &env->tr);
 404     set_seg(&sregs.ldt, &env->ldt);
 405
 406     sregs.idt.limit = env->idt.limit;
 407     sregs.idt.base = env->idt.base;
 408     sregs.gdt.limit = env->gdt.limit;
 409     sregs.gdt.base = env->gdt.base;
 410
 411     sregs.cr0 = env->cr[0];
 412     sregs.cr2 = env->cr[2];
 413     sregs.cr3 = env->cr[3];
 414     sregs.cr4 = env->cr[4];
 415
 416     sregs.cr8 = cpu_get_apic_tpr(env);
 417     sregs.apic_base = cpu_get_apic_base(env);
 418
 419     sregs.efer = env->efer;
 420
 421     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 422 }
 423
 424 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 425                               uint32_t index, uint64_t value)
 426 {
 427     entry->index = index;
 428     entry->data = value;
 429 }
 430
 431 static int kvm_put_msrs(CPUState *env)
 432 {
 433     struct {
 434         struct kvm_msrs info;
 435         struct kvm_msr_entry entries[100];
 436     } msr_data;
 437     struct kvm_msr_entry *msrs = msr_data.entries;
 438     int n = 0;
 439
 440     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 441     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 442     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 443     if (kvm_has_msr_star(env))
 444         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 445     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 446 #ifdef TARGET_X86_64
 447     /* FIXME if lm capable */
 448     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 449     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 450     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 451     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 452 #endif
 453     msr_data.info.nmsrs = n;
 454
 455     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 456
 457 }
 458
 459
 460 static int kvm_get_fpu(CPUState *env)
 461 {
 462     struct kvm_fpu fpu;
 463     int i, ret;
 464
 465     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 466     if (ret < 0)
 467         return ret;
 468
 469     env->fpstt = (fpu.fsw >> 11) & 7;
 470     env->fpus = fpu.fsw;
 471     env->fpuc = fpu.fcw;
 472     for (i = 0; i < 8; ++i)
 473         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 474     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 475     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 476     env->mxcsr = fpu.mxcsr;
 477
 478     return 0;
 479 }
 480
 481 static int kvm_get_sregs(CPUState *env)
 482 {
 483     struct kvm_sregs sregs;
 484     uint32_t hflags;
 485     int ret;
 486
 487     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 488     if (ret < 0)
 489         return ret;
 490
 491     memcpy(env->interrupt_bitmap,
 492            sregs.interrupt_bitmap,
 493            sizeof(sregs.interrupt_bitmap));
 494
 495     get_seg(&env->segs[R_CS], &sregs.cs);
 496     get_seg(&env->segs[R_DS], &sregs.ds);
 497     get_seg(&env->segs[R_ES], &sregs.es);
 498     get_seg(&env->segs[R_FS], &sregs.fs);
 499     get_seg(&env->segs[R_GS], &sregs.gs);
 500     get_seg(&env->segs[R_SS], &sregs.ss);
 501
 502     get_seg(&env->tr, &sregs.tr);
 503     get_seg(&env->ldt, &sregs.ldt);
 504
 505     env->idt.limit = sregs.idt.limit;
 506     env->idt.base = sregs.idt.base;
 507     env->gdt.limit = sregs.gdt.limit;
 508     env->gdt.base = sregs.gdt.base;
 509
 510     env->cr[0] = sregs.cr0;
 511     env->cr[2] = sregs.cr2;
 512     env->cr[3] = sregs.cr3;
 513     env->cr[4] = sregs.cr4;
 514
 515     cpu_set_apic_base(env, sregs.apic_base);
 516
 517     env->efer = sregs.efer;
 518     //cpu_set_apic_tpr(env, sregs.cr8);
 519
 520 #define HFLAG_COPY_MASK ~( \
 521                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 522                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 523                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 524                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 525
 526
 527
 528     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 529     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 530     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 531             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 532     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 533     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 534             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 535
 536     if (env->efer & MSR_EFER_LMA) {
 537         hflags |= HF_LMA_MASK;
 538     }
 539
 540     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 541         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 542     } else {
 543         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 544                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 545         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 546                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 547         if (!(env->cr[0] & CR0_PE_MASK) ||
 548                    (env->eflags & VM_MASK) ||
 549                    !(hflags & HF_CS32_MASK)) {
 550                 hflags |= HF_ADDSEG_MASK;
 551             } else {
 552                 hflags |= ((env->segs[R_DS].base |
 553                                 env->segs[R_ES].base |
 554                                 env->segs[R_SS].base) != 0) <<
 555                     HF_ADDSEG_SHIFT;
 556             }
 557     }
 558     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 559
 560     return 0;
 561 }
 562
 563 static int kvm_get_msrs(CPUState *env)
 564 {
 565     struct {
 566         struct kvm_msrs info;
 567         struct kvm_msr_entry entries[100];
 568     } msr_data;
 569     struct kvm_msr_entry *msrs = msr_data.entries;
 570     int ret, i, n;
 571
 572     n = 0;
 573     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 574     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 575     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 576     if (kvm_has_msr_star(env))
 577         msrs[n++].index = MSR_STAR;
 578     msrs[n++].index = MSR_IA32_TSC;
 579 #ifdef TARGET_X86_64
 580     /* FIXME lm_capable_kernel */
 581     msrs[n++].index = MSR_CSTAR;
 582     msrs[n++].index = MSR_KERNELGSBASE;
 583     msrs[n++].index = MSR_FMASK;
 584     msrs[n++].index = MSR_LSTAR;
 585 #endif
 586     msr_data.info.nmsrs = n;
 587     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 588     if (ret < 0)
 589         return ret;
 590
 591     for (i = 0; i < ret; i++) {
 592         switch (msrs[i].index) {
 593         case MSR_IA32_SYSENTER_CS:
 594             env->sysenter_cs = msrs[i].data;
 595             break;
 596         case MSR_IA32_SYSENTER_ESP:
 597             env->sysenter_esp = msrs[i].data;
 598             break;
 599         case MSR_IA32_SYSENTER_EIP:
 600             env->sysenter_eip = msrs[i].data;
 601             break;
 602         case MSR_STAR:
 603             env->star = msrs[i].data;
 604             break;
 605 #ifdef TARGET_X86_64
 606         case MSR_CSTAR:
 607             env->cstar = msrs[i].data;
 608             break;
 609         case MSR_KERNELGSBASE:
 610             env->kernelgsbase = msrs[i].data;
 611             break;
 612         case MSR_FMASK:
 613             env->fmask = msrs[i].data;
 614             break;
 615         case MSR_LSTAR:
 616             env->lstar = msrs[i].data;
 617             break;
 618 #endif
 619         case MSR_IA32_TSC:
 620             env->tsc = msrs[i].data;
 621             break;
 622         }
 623     }
 624
 625     return 0;
 626 }
 627
 628 int kvm_arch_put_registers(CPUState *env)
 629 {
 630     int ret;
 631
 632     ret = kvm_getput_regs(env, 1);
 633     if (ret < 0)
 634         return ret;
 635
 636     ret = kvm_put_fpu(env);
 637     if (ret < 0)
 638         return ret;
 639
 640     ret = kvm_put_sregs(env);
 641     if (ret < 0)
 642         return ret;
 643
 644     ret = kvm_put_msrs(env);
 645     if (ret < 0)
 646         return ret;
 647
 648     return 0;
 649 }
 650
 651 int kvm_arch_get_registers(CPUState *env)
 652 {
 653     int ret;
 654
 655     ret = kvm_getput_regs(env, 0);
 656     if (ret < 0)
 657         return ret;
 658
 659     ret = kvm_get_fpu(env);
 660     if (ret < 0)
 661         return ret;
 662
 663     ret = kvm_get_sregs(env);
 664     if (ret < 0)
 665         return ret;
 666
 667     ret = kvm_get_msrs(env);
 668     if (ret < 0)
 669         return ret;
 670
 671     return 0;
 672 }
 673
 674 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 675 {
 676     /* Try to inject an interrupt if the guest can accept it */
 677     if (run->ready_for_interrupt_injection &&
 678         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 679         (env->eflags & IF_MASK)) {
 680         int irq;
 681
 682         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 683         irq = cpu_get_pic_interrupt(env);
 684         if (irq >= 0) {
 685             struct kvm_interrupt intr;
 686             intr.irq = irq;
 687             /* FIXME: errors */
 688             dprintf("injected interrupt %d\n", irq);
 689             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 690         }
 691     }
 692
 693     /* If we have an interrupt but the guest is not ready to receive an
 694      * interrupt, request an interrupt window exit.  This will
 695      * cause a return to userspace as soon as the guest is ready to
 696      * receive interrupts. */
 697     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 698         run->request_interrupt_window = 1;
 699     else
 700         run->request_interrupt_window = 0;
 701
 702     dprintf("setting tpr\n");
 703     run->cr8 = cpu_get_apic_tpr(env);
 704
 705     return 0;
 706 }
 707
 708 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 709 {
 710     if (run->if_flag)
 711         env->eflags |= IF_MASK;
 712     else
 713         env->eflags &= ~IF_MASK;
 714
 715     cpu_set_apic_tpr(env, run->cr8);
 716     cpu_set_apic_base(env, run->apic_base);
 717
 718     return 0;
 719 }
 720
 721 static int kvm_handle_halt(CPUState *env)
 722 {
 723     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 724           (env->eflags & IF_MASK)) &&
 725         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 726         env->halted = 1;
 727         env->exception_index = EXCP_HLT;
 728         return 0;
 729     }
 730
 731     return 1;
 732 }
 733
 734 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 735 {
 736     int ret = 0;
 737
 738     switch (run->exit_reason) {
 739     case KVM_EXIT_HLT:
 740         dprintf("handle_hlt\n");
 741         ret = kvm_handle_halt(env);
 742         break;
 743     }
 744
 745     return ret;
 746 }
 747
 748 #ifdef KVM_CAP_SET_GUEST_DEBUG
 749 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 750 {
 751     const static uint8_t int3 = 0xcc;
 752
 753     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 754         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 755         return -EINVAL;
 756     return 0;
 757 }
 758
 759 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 760 {
 761     uint8_t int3;
 762
 763     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 764         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 765         return -EINVAL;
 766     return 0;
 767 }
 768
 769 static struct {
 770     target_ulong addr;
 771     int len;
 772     int type;
 773 } hw_breakpoint[4];
 774
 775 static int nb_hw_breakpoint;
 776
 777 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 778 {
 779     int n;
 780
 781     for (n = 0; n < nb_hw_breakpoint; n++)
 782         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 783             (hw_breakpoint[n].len == len || len == -1))
 784             return n;
 785     return -1;
 786 }
 787
 788 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 789                                   target_ulong len, int type)
 790 {
 791     switch (type) {
 792     case GDB_BREAKPOINT_HW:
 793         len = 1;
 794         break;
 795     case GDB_WATCHPOINT_WRITE:
 796     case GDB_WATCHPOINT_ACCESS:
 797         switch (len) {
 798         case 1:
 799             break;
 800         case 2:
 801         case 4:
 802         case 8:
 803             if (addr & (len - 1))
 804                 return -EINVAL;
 805             break;
 806         default:
 807             return -EINVAL;
 808         }
 809         break;
 810     default:
 811         return -ENOSYS;
 812     }
 813
 814     if (nb_hw_breakpoint == 4)
 815         return -ENOBUFS;
 816
 817     if (find_hw_breakpoint(addr, len, type) >= 0)
 818         return -EEXIST;
 819
 820     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 821     hw_breakpoint[nb_hw_breakpoint].len = len;
 822     hw_breakpoint[nb_hw_breakpoint].type = type;
 823     nb_hw_breakpoint++;
 824
 825     return 0;
 826 }
 827
 828 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 829                                   target_ulong len, int type)
 830 {
 831     int n;
 832
 833     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 834     if (n < 0)
 835         return -ENOENT;
 836
 837     nb_hw_breakpoint--;
 838     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 839
 840     return 0;
 841 }
 842
 843 void kvm_arch_remove_all_hw_breakpoints(void)
 844 {
 845     nb_hw_breakpoint = 0;
 846 }
 847
 848 static CPUWatchpoint hw_watchpoint;
 849
 850 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 851 {
 852     int handle = 0;
 853     int n;
 854
 855     if (arch_info->exception == 1) {
 856         if (arch_info->dr6 & (1 << 14)) {
 857             if (cpu_single_env->singlestep_enabled)
 858                 handle = 1;
 859         } else {
 860             for (n = 0; n < 4; n++)
 861                 if (arch_info->dr6 & (1 << n))
 862                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 863                     case 0x0:
 864                         handle = 1;
 865                         break;
 866                     case 0x1:
 867                         handle = 1;
 868                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 869                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 870                         hw_watchpoint.flags = BP_MEM_WRITE;
 871                         break;
 872                     case 0x3:
 873                         handle = 1;
 874                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 875                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 876                         hw_watchpoint.flags = BP_MEM_ACCESS;
 877                         break;
 878                     }
 879         }
 880     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
 881         handle = 1;
 882
 883     if (!handle)
 884         kvm_update_guest_debug(cpu_single_env,
 885                         (arch_info->exception == 1) ?
 886                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 887
 888     return handle;
 889 }
 890
 891 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 892 {
 893     const uint8_t type_code[] = {
 894         [GDB_BREAKPOINT_HW] = 0x0,
 895         [GDB_WATCHPOINT_WRITE] = 0x1,
 896         [GDB_WATCHPOINT_ACCESS] = 0x3
 897     };
 898     const uint8_t len_code[] = {
 899         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 900     };
 901     int n;
 902
 903     if (kvm_sw_breakpoints_active(env))
 904         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 905
 906     if (nb_hw_breakpoint > 0) {
 907         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 908         dbg->arch.debugreg[7] = 0x0600;
 909         for (n = 0; n < nb_hw_breakpoint; n++) {
 910             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 911             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 912                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 913                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 914         }
 915     }
 916 }
 917 #endif /* KVM_CAP_SET_GUEST_DEBUG */