target-arm/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3
   4 void register_machines(void)
   5 {
   6     qemu_register_machine(&integratorcp_machine);
   7     qemu_register_machine(&versatilepb_machine);
   8     qemu_register_machine(&versatileab_machine);
   9     qemu_register_machine(&realview_machine);
  10     qemu_register_machine(&akitapda_machine);
  11     qemu_register_machine(&spitzpda_machine);
  12     qemu_register_machine(&borzoipda_machine);
  13     qemu_register_machine(&terrierpda_machine);
  14     qemu_register_machine(&sx1_machine_v1);
  15     qemu_register_machine(&sx1_machine_v2);
  16     qemu_register_machine(&palmte_machine);
  17     qemu_register_machine(&n800_machine);
  18     qemu_register_machine(&n810_machine);
  19     qemu_register_machine(&lm3s811evb_machine);
  20     qemu_register_machine(&lm3s6965evb_machine);
  21     qemu_register_machine(&connex_machine);
  22     qemu_register_machine(&verdex_machine);
  23     qemu_register_machine(&mainstone2_machine);
  24     qemu_register_machine(&musicpal_machine);
  25     qemu_register_machine(&tosapda_machine);
  26     qemu_register_machine(&mini2440_machine);
  27     qemu_register_machine(&syborg_machine);
  28 }
  29
  30 void cpu_save(QEMUFile *f, void *opaque)
  31 {
  32     int i;
  33     CPUARMState *env = (CPUARMState *)opaque;
  34
  35     for (i = 0; i < 16; i++) {
  36         qemu_put_be32(f, env->regs[i]);
  37     }
  38     qemu_put_be32(f, cpsr_read(env));
  39     qemu_put_be32(f, env->spsr);
  40     for (i = 0; i < 6; i++) {
  41         qemu_put_be32(f, env->banked_spsr[i]);
  42         qemu_put_be32(f, env->banked_r13[i]);
  43         qemu_put_be32(f, env->banked_r14[i]);
  44     }
  45     for (i = 0; i < 5; i++) {
  46         qemu_put_be32(f, env->usr_regs[i]);
  47         qemu_put_be32(f, env->fiq_regs[i]);
  48     }
  49     qemu_put_be32(f, env->cp15.c0_cpuid);
  50     qemu_put_be32(f, env->cp15.c0_cachetype);
  51     qemu_put_be32(f, env->cp15.c1_sys);
  52     qemu_put_be32(f, env->cp15.c1_coproc);
  53     qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
  54     qemu_put_be32(f, env->cp15.c2_base0);
  55     qemu_put_be32(f, env->cp15.c2_base1);
  56     qemu_put_be32(f, env->cp15.c2_mask);
  57     qemu_put_be32(f, env->cp15.c2_data);
  58     qemu_put_be32(f, env->cp15.c2_insn);
  59     qemu_put_be32(f, env->cp15.c3);
  60     qemu_put_be32(f, env->cp15.c5_insn);
  61     qemu_put_be32(f, env->cp15.c5_data);
  62     for (i = 0; i < 8; i++) {
  63         qemu_put_be32(f, env->cp15.c6_region[i]);
  64     }
  65     qemu_put_be32(f, env->cp15.c6_insn);
  66     qemu_put_be32(f, env->cp15.c6_data);
  67     qemu_put_be32(f, env->cp15.c9_insn);
  68     qemu_put_be32(f, env->cp15.c9_data);
  69     qemu_put_be32(f, env->cp15.c13_fcse);
  70     qemu_put_be32(f, env->cp15.c13_context);
  71     qemu_put_be32(f, env->cp15.c13_tls1);
  72     qemu_put_be32(f, env->cp15.c13_tls2);
  73     qemu_put_be32(f, env->cp15.c13_tls3);
  74     qemu_put_be32(f, env->cp15.c15_cpar);
  75
  76     qemu_put_be32(f, env->features);
  77
  78     if (arm_feature(env, ARM_FEATURE_VFP)) {
  79         for (i = 0;  i < 16; i++) {
  80             CPU_DoubleU u;
  81             u.d = env->vfp.regs[i];
  82             qemu_put_be32(f, u.l.upper);
  83             qemu_put_be32(f, u.l.lower);
  84         }
  85         for (i = 0; i < 16; i++) {
  86             qemu_put_be32(f, env->vfp.xregs[i]);
  87         }
  88
  89         /* TODO: Should use proper FPSCR access functions.  */
  90         qemu_put_be32(f, env->vfp.vec_len);
  91         qemu_put_be32(f, env->vfp.vec_stride);
  92
  93         if (arm_feature(env, ARM_FEATURE_VFP3)) {
  94             for (i = 16;  i < 32; i++) {
  95                 CPU_DoubleU u;
  96                 u.d = env->vfp.regs[i];
  97                 qemu_put_be32(f, u.l.upper);
  98                 qemu_put_be32(f, u.l.lower);
  99             }
 100         }
 101     }
 102
 103     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 104         for (i = 0; i < 16; i++) {
 105             qemu_put_be64(f, env->iwmmxt.regs[i]);
 106         }
 107         for (i = 0; i < 16; i++) {
 108             qemu_put_be32(f, env->iwmmxt.cregs[i]);
 109         }
 110     }
 111
 112     if (arm_feature(env, ARM_FEATURE_M)) {
 113         qemu_put_be32(f, env->v7m.other_sp);
 114         qemu_put_be32(f, env->v7m.vecbase);
 115         qemu_put_be32(f, env->v7m.basepri);
 116         qemu_put_be32(f, env->v7m.control);
 117         qemu_put_be32(f, env->v7m.current_sp);
 118         qemu_put_be32(f, env->v7m.exception);
 119     }
 120 }
 121
 122 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 123 {
 124     CPUARMState *env = (CPUARMState *)opaque;
 125     int i;
 126
 127     if (version_id != CPU_SAVE_VERSION)
 128         return -EINVAL;
 129
 130     for (i = 0; i < 16; i++) {
 131         env->regs[i] = qemu_get_be32(f);
 132     }
 133     cpsr_write(env, qemu_get_be32(f), 0xffffffff);
 134     env->spsr = qemu_get_be32(f);
 135     for (i = 0; i < 6; i++) {
 136         env->banked_spsr[i] = qemu_get_be32(f);
 137         env->banked_r13[i] = qemu_get_be32(f);
 138         env->banked_r14[i] = qemu_get_be32(f);
 139     }
 140     for (i = 0; i < 5; i++) {
 141         env->usr_regs[i] = qemu_get_be32(f);
 142         env->fiq_regs[i] = qemu_get_be32(f);
 143     }
 144     env->cp15.c0_cpuid = qemu_get_be32(f);
 145     env->cp15.c0_cachetype = qemu_get_be32(f);
 146     env->cp15.c1_sys = qemu_get_be32(f);
 147     env->cp15.c1_coproc = qemu_get_be32(f);
 148     env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
 149     env->cp15.c2_base0 = qemu_get_be32(f);
 150     env->cp15.c2_base1 = qemu_get_be32(f);
 151     env->cp15.c2_mask = qemu_get_be32(f);
 152     env->cp15.c2_data = qemu_get_be32(f);
 153     env->cp15.c2_insn = qemu_get_be32(f);
 154     env->cp15.c3 = qemu_get_be32(f);
 155     env->cp15.c5_insn = qemu_get_be32(f);
 156     env->cp15.c5_data = qemu_get_be32(f);
 157     for (i = 0; i < 8; i++) {
 158         env->cp15.c6_region[i] = qemu_get_be32(f);
 159     }
 160     env->cp15.c6_insn = qemu_get_be32(f);
 161     env->cp15.c6_data = qemu_get_be32(f);
 162     env->cp15.c9_insn = qemu_get_be32(f);
 163     env->cp15.c9_data = qemu_get_be32(f);
 164     env->cp15.c13_fcse = qemu_get_be32(f);
 165     env->cp15.c13_context = qemu_get_be32(f);
 166     env->cp15.c13_tls1 = qemu_get_be32(f);
 167     env->cp15.c13_tls2 = qemu_get_be32(f);
 168     env->cp15.c13_tls3 = qemu_get_be32(f);
 169     env->cp15.c15_cpar = qemu_get_be32(f);
 170
 171     env->features = qemu_get_be32(f);
 172
 173     if (arm_feature(env, ARM_FEATURE_VFP)) {
 174         for (i = 0;  i < 16; i++) {
 175             CPU_DoubleU u;
 176             u.l.upper = qemu_get_be32(f);
 177             u.l.lower = qemu_get_be32(f);
 178             env->vfp.regs[i] = u.d;
 179         }
 180         for (i = 0; i < 16; i++) {
 181             env->vfp.xregs[i] = qemu_get_be32(f);
 182         }
 183
 184         /* TODO: Should use proper FPSCR access functions.  */
 185         env->vfp.vec_len = qemu_get_be32(f);
 186         env->vfp.vec_stride = qemu_get_be32(f);
 187
 188         if (arm_feature(env, ARM_FEATURE_VFP3)) {
 189             for (i = 0;  i < 16; i++) {
 190                 CPU_DoubleU u;
 191                 u.l.upper = qemu_get_be32(f);
 192                 u.l.lower = qemu_get_be32(f);
 193                 env->vfp.regs[i] = u.d;
 194             }
 195         }
 196     }
 197
 198     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 199         for (i = 0; i < 16; i++) {
 200             env->iwmmxt.regs[i] = qemu_get_be64(f);
 201         }
 202         for (i = 0; i < 16; i++) {
 203             env->iwmmxt.cregs[i] = qemu_get_be32(f);
 204         }
 205     }
 206
 207     if (arm_feature(env, ARM_FEATURE_M)) {
 208         env->v7m.other_sp = qemu_get_be32(f);
 209         env->v7m.vecbase = qemu_get_be32(f);
 210         env->v7m.basepri = qemu_get_be32(f);
 211         env->v7m.control = qemu_get_be32(f);
 212         env->v7m.current_sp = qemu_get_be32(f);
 213         env->v7m.exception = qemu_get_be32(f);
 214     }
 215
 216     return 0;
 217 }