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Avoid clobbering input register in qemu_ld64+bswap+useronly case
[qemu/mini2440.git] / tcg / ppc / tcg-target.c
blobc5b4c18d45bff139f009d0ee24a8d15e48b66580
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #ifdef __APPLE__
28 #define LINKAGE_AREA_SIZE 24
29 #define BACK_CHAIN_OFFSET 8
30 #else
31 #define LINKAGE_AREA_SIZE 8
32 #define BACK_CHAIN_OFFSET 4
33 #endif
34
35 #define FAST_PATH
36 #if TARGET_PHYS_ADDR_BITS <= 32
37 #define ADDEND_OFFSET 0
38 #else
39 #define ADDEND_OFFSET 4
40 #endif
41
42 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
43 "r0",
44 "r1",
45 "rp",
46 "r3",
47 "r4",
48 "r5",
49 "r6",
50 "r7",
51 "r8",
52 "r9",
53 "r10",
54 "r11",
55 "r12",
56 "r13",
57 "r14",
58 "r15",
59 "r16",
60 "r17",
61 "r18",
62 "r19",
63 "r20",
64 "r21",
65 "r22",
66 "r23",
67 "r24",
68 "r25",
69 "r26",
70 "r27",
71 "r28",
72 "r29",
73 "r30",
74 "r31"
75 };
76
77 static const int tcg_target_reg_alloc_order[] = {
78 TCG_REG_R14,
79 TCG_REG_R15,
80 TCG_REG_R16,
81 TCG_REG_R17,
82 TCG_REG_R18,
83 TCG_REG_R19,
84 TCG_REG_R20,
85 TCG_REG_R21,
86 TCG_REG_R22,
87 TCG_REG_R23,
88 TCG_REG_R28,
89 TCG_REG_R29,
90 TCG_REG_R30,
91 TCG_REG_R31,
92 #ifdef __APPLE__
93 TCG_REG_R2,
94 #endif
95 TCG_REG_R3,
96 TCG_REG_R4,
97 TCG_REG_R5,
98 TCG_REG_R6,
99 TCG_REG_R7,
100 TCG_REG_R8,
101 TCG_REG_R9,
102 TCG_REG_R10,
103 #ifndef __APPLE__
104 TCG_REG_R11,
105 #endif
106 TCG_REG_R12,
107 TCG_REG_R13,
108 TCG_REG_R0,
109 TCG_REG_R1,
110 TCG_REG_R2,
111 TCG_REG_R24,
112 TCG_REG_R25,
113 TCG_REG_R26,
114 TCG_REG_R27
115 };
116
117 static const int tcg_target_call_iarg_regs[] = {
118 TCG_REG_R3,
119 TCG_REG_R4,
120 TCG_REG_R5,
121 TCG_REG_R6,
122 TCG_REG_R7,
123 TCG_REG_R8,
124 TCG_REG_R9,
125 TCG_REG_R10
126 };
127
128 static const int tcg_target_call_oarg_regs[2] = {
129 TCG_REG_R3,
130 TCG_REG_R4
131 };
132
133 static const int tcg_target_callee_save_regs[] = {
134 #ifdef __APPLE__
135 TCG_REG_R11,
136 TCG_REG_R13,
137 #endif
138 TCG_REG_R14,
139 TCG_REG_R15,
140 TCG_REG_R16,
141 TCG_REG_R17,
142 TCG_REG_R18,
143 TCG_REG_R19,
144 TCG_REG_R20,
145 TCG_REG_R21,
146 TCG_REG_R22,
147 TCG_REG_R23,
148 TCG_REG_R28,
149 TCG_REG_R29,
150 TCG_REG_R30,
151 TCG_REG_R31
152 };
153
154 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
155 {
156 tcg_target_long disp;
157
158 disp = target - (tcg_target_long) pc;
159 if ((disp << 6) >> 6 != disp)
160 tcg_abort ();
161
162 return disp & 0x3fffffc;
163 }
164
165 static void reloc_pc24 (void *pc, tcg_target_long target)
166 {
167 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
168 | reloc_pc24_val (pc, target);
169 }
170
171 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
172 {
173 tcg_target_long disp;
174
175 disp = target - (tcg_target_long) pc;
176 if (disp != (int16_t) disp)
177 tcg_abort ();
178
179 return disp & 0xfffc;
180 }
181
182 static void reloc_pc14 (void *pc, tcg_target_long target)
183 {
184 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
185 | reloc_pc14_val (pc, target);
186 }
187
188 static void patch_reloc(uint8_t *code_ptr, int type,
189 tcg_target_long value, tcg_target_long addend)
190 {
191 value += addend;
192 switch (type) {
193 case R_PPC_REL14:
194 reloc_pc14 (code_ptr, value);
195 break;
196 case R_PPC_REL24:
197 reloc_pc24 (code_ptr, value);
198 break;
199 default:
200 tcg_abort();
201 }
202 }
203
204 /* maximum number of register used for input function arguments */
205 static int tcg_target_get_call_iarg_regs_count(int flags)
206 {
207 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
208 }
209
210 /* parse target specific constraints */
211 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
212 {
213 const char *ct_str;
214
215 ct_str = *pct_str;
216 switch (ct_str[0]) {
217 case 'A': case 'B': case 'C': case 'D':
218 ct->ct |= TCG_CT_REG;
219 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
220 break;
221 case 'r':
222 ct->ct |= TCG_CT_REG;
223 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
224 break;
225 #ifdef CONFIG_SOFTMMU
226 case 'L': /* qemu_ld constraint */
227 ct->ct |= TCG_CT_REG;
228 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
229 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
230 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
231 break;
232 case 'K': /* qemu_st[8..32] constraint */
233 ct->ct |= TCG_CT_REG;
234 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
235 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
236 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
237 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
238 #if TARGET_LONG_BITS == 64
239 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
240 #endif
241 break;
242 case 'M': /* qemu_st64 constraint */
243 ct->ct |= TCG_CT_REG;
244 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
245 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
246 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
247 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
248 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
249 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
250 break;
251 #else
252 case 'L':
253 case 'K':
254 ct->ct |= TCG_CT_REG;
255 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
256 break;
257 case 'M':
258 ct->ct |= TCG_CT_REG;
259 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
260 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
261 break;
262 #endif
263 default:
264 return -1;
265 }
266 ct_str++;
267 *pct_str = ct_str;
268 return 0;
269 }
270
271 /* test if a constant matches the constraint */
272 static int tcg_target_const_match(tcg_target_long val,
273 const TCGArgConstraint *arg_ct)
274 {
275 int ct;
276
277 ct = arg_ct->ct;
278 if (ct & TCG_CT_CONST)
279 return 1;
280 return 0;
281 }
282
283 #define OPCD(opc) ((opc)<<26)
284 #define XO31(opc) (OPCD(31)|((opc)<<1))
285 #define XO19(opc) (OPCD(19)|((opc)<<1))
286
287 #define B OPCD(18)
288 #define BC OPCD(16)
289 #define LBZ OPCD(34)
290 #define LHZ OPCD(40)
291 #define LHA OPCD(42)
292 #define LWZ OPCD(32)
293 #define STB OPCD(38)
294 #define STH OPCD(44)
295 #define STW OPCD(36)
296
297 #define ADDI OPCD(14)
298 #define ADDIS OPCD(15)
299 #define ORI OPCD(24)
300 #define ORIS OPCD(25)
301 #define XORI OPCD(26)
302 #define XORIS OPCD(27)
303 #define ANDI OPCD(28)
304 #define ANDIS OPCD(29)
305 #define MULLI OPCD( 7)
306 #define CMPLI OPCD(10)
307 #define CMPI OPCD(11)
308
309 #define LWZU OPCD(33)
310 #define STWU OPCD(37)
311
312 #define RLWINM OPCD(21)
313
314 #define BCLR XO19( 16)
315 #define BCCTR XO19(528)
316 #define CRAND XO19(257)
317 #define CRANDC XO19(129)
318 #define CRNAND XO19(225)
319 #define CROR XO19(449)
320
321 #define EXTSB XO31(954)
322 #define EXTSH XO31(922)
323 #define ADD XO31(266)
324 #define ADDE XO31(138)
325 #define ADDC XO31( 10)
326 #define AND XO31( 28)
327 #define SUBF XO31( 40)
328 #define SUBFC XO31( 8)
329 #define SUBFE XO31(136)
330 #define OR XO31(444)
331 #define XOR XO31(316)
332 #define MULLW XO31(235)
333 #define MULHWU XO31( 11)
334 #define DIVW XO31(491)
335 #define DIVWU XO31(459)
336 #define CMP XO31( 0)
337 #define CMPL XO31( 32)
338 #define LHBRX XO31(790)
339 #define LWBRX XO31(534)
340 #define STHBRX XO31(918)
341 #define STWBRX XO31(662)
342 #define MFSPR XO31(339)
343 #define MTSPR XO31(467)
344 #define SRAWI XO31(824)
345 #define NEG XO31(104)
346
347 #define LBZX XO31( 87)
348 #define LHZX XO31(276)
349 #define LHAX XO31(343)
350 #define LWZX XO31( 23)
351 #define STBX XO31(215)
352 #define STHX XO31(407)
353 #define STWX XO31(151)
354
355 #define SPR(a,b) ((((a)<<5)|(b))<<11)
356 #define LR SPR(8, 0)
357 #define CTR SPR(9, 0)
358
359 #define SLW XO31( 24)
360 #define SRW XO31(536)
361 #define SRAW XO31(792)
362
363 #define LMW OPCD(46)
364 #define STMW OPCD(47)
365
366 #define TW XO31(4)
367 #define TRAP (TW | TO (31))
368
369 #define RT(r) ((r)<<21)
370 #define RS(r) ((r)<<21)
371 #define RA(r) ((r)<<16)
372 #define RB(r) ((r)<<11)
373 #define TO(t) ((t)<<21)
374 #define SH(s) ((s)<<11)
375 #define MB(b) ((b)<<6)
376 #define ME(e) ((e)<<1)
377 #define BO(o) ((o)<<21)
378
379 #define LK 1
380
381 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
382 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
383
384 #define BF(n) ((n)<<23)
385 #define BI(n, c) (((c)+((n)*4))<<16)
386 #define BT(n, c) (((c)+((n)*4))<<21)
387 #define BA(n, c) (((c)+((n)*4))<<16)
388 #define BB(n, c) (((c)+((n)*4))<<11)
389
390 #define BO_COND_TRUE BO (12)
391 #define BO_COND_FALSE BO (4)
392 #define BO_ALWAYS BO (20)
393
394 enum {
395 CR_LT,
396 CR_GT,
397 CR_EQ,
398 CR_SO
399 };
400
401 static const uint32_t tcg_to_bc[10] = {
402 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
403 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
404 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
405 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
406 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
407 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
408 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
409 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
410 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
411 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
412 };
413
414 static void tcg_out_mov(TCGContext *s, int ret, int arg)
415 {
416 tcg_out32 (s, OR | SAB (arg, ret, arg));
417 }
418
419 static void tcg_out_movi(TCGContext *s, TCGType type,
420 int ret, tcg_target_long arg)
421 {
422 if (arg == (int16_t) arg)
423 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
424 else {
425 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
426 if (arg & 0xffff)
427 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
428 }
429 }
430
431 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
432 int offset, int op1, int op2)
433 {
434 if (offset == (int16_t) offset)
435 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
436 else {
437 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
438 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
439 }
440 }
441
442 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
443 {
444 tcg_target_long disp;
445
446 disp = target - (tcg_target_long) s->code_ptr;
447 if ((disp << 6) >> 6 == disp)
448 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
449 else {
450 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
451 tcg_out32 (s, MTSPR | RS (0) | CTR);
452 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
453 }
454 }
455
456 #if defined(CONFIG_SOFTMMU)
457
458 #include "../../softmmu_defs.h"
459
460 static void *qemu_ld_helpers[4] = {
461 __ldb_mmu,
462 __ldw_mmu,
463 __ldl_mmu,
464 __ldq_mmu,
465 };
466
467 static void *qemu_st_helpers[4] = {
468 __stb_mmu,
469 __stw_mmu,
470 __stl_mmu,
471 __stq_mmu,
472 };
473 #endif
474
475 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
476 {
477 int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
478 #ifdef CONFIG_SOFTMMU
479 int r2;
480 void *label1_ptr, *label2_ptr;
481 #endif
482 #if TARGET_LONG_BITS == 64
483 int addr_reg2;
484 #endif
485
486 data_reg = *args++;
487 if (opc == 3)
488 data_reg2 = *args++;
489 else
490 data_reg2 = 0;
491 addr_reg = *args++;
492 #if TARGET_LONG_BITS == 64
493 addr_reg2 = *args++;
494 #endif
495 mem_index = *args;
496 s_bits = opc & 3;
497
498 #ifdef CONFIG_SOFTMMU
499 r0 = 3;
500 r1 = 4;
501 r2 = 0;
502
503 tcg_out32 (s, (RLWINM
504 | RA (r0)
505 | RS (addr_reg)
506 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
507 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
508 | ME (31 - CPU_TLB_ENTRY_BITS)
509 )
510 );
511 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
512 tcg_out32 (s, (LWZU
513 | RT (r1)
514 | RA (r0)
515 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
516 )
517 );
518 tcg_out32 (s, (RLWINM
519 | RA (r2)
520 | RS (addr_reg)
521 | SH (0)
522 | MB ((32 - s_bits) & 31)
523 | ME (31 - TARGET_PAGE_BITS)
524 )
525 );
526
527 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
528 #if TARGET_LONG_BITS == 64
529 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
530 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
531 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
532 #endif
533
534 label1_ptr = s->code_ptr;
535 #ifdef FAST_PATH
536 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
537 #endif
538
539 /* slow path */
540 #if TARGET_LONG_BITS == 32
541 tcg_out_mov (s, 3, addr_reg);
542 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
543 #else
544 tcg_out_mov (s, 3, addr_reg2);
545 tcg_out_mov (s, 4, addr_reg);
546 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
547 #endif
548
549 tcg_out_b (s, LK, (tcg_target_long) qemu_ld_helpers[s_bits]);
550 switch (opc) {
551 case 0|4:
552 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
553 break;
554 case 1|4:
555 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
556 break;
557 case 0:
558 case 1:
559 case 2:
560 if (data_reg != 3)
561 tcg_out_mov (s, data_reg, 3);
562 break;
563 case 3:
564 if (data_reg == 3) {
565 if (data_reg2 == 4) {
566 tcg_out_mov (s, 0, 4);
567 tcg_out_mov (s, 4, 3);
568 tcg_out_mov (s, 3, 0);
569 }
570 else {
571 tcg_out_mov (s, data_reg2, 3);
572 tcg_out_mov (s, 3, 4);
573 }
574 }
575 else {
576 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
577 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
578 }
579 break;
580 }
581 label2_ptr = s->code_ptr;
582 tcg_out32 (s, B);
583
584 /* label1: fast path */
585 #ifdef FAST_PATH
586 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
587 #endif
588
589 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
590 tcg_out32 (s, (LWZ
591 | RT (r0)
592 | RA (r0)
593 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
594 - offsetof (CPUTLBEntry, addr_read))
595 ));
596 /* r0 = env->tlb_table[mem_index][index].addend */
597 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
598 /* r0 = env->tlb_table[mem_index][index].addend + addr */
599
600 #else /* !CONFIG_SOFTMMU */
601 r0 = addr_reg;
602 r1 = 3;
603 #endif
604
605 #ifdef TARGET_WORDS_BIGENDIAN
606 bswap = 0;
607 #else
608 bswap = 1;
609 #endif
610 switch (opc) {
611 default:
612 case 0:
613 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
614 break;
615 case 0|4:
616 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
617 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
618 break;
619 case 1:
620 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
621 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
622 break;
623 case 1|4:
624 if (bswap) {
625 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
626 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
627 }
628 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
629 break;
630 case 2:
631 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
632 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
633 break;
634 case 3:
635 if (bswap) {
636 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
637 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
638 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r1));
639 }
640 else {
641 if (r0 == data_reg2) {
642 tcg_out32 (s, LWZ | RT (0) | RA (r0));
643 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
644 tcg_out_mov (s, data_reg2, 0);
645 }
646 else {
647 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
648 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
649 }
650 }
651 break;
652 }
653
654 #ifdef CONFIG_SOFTMMU
655 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
656 #endif
657 }
658
659 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
660 {
661 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap;
662 #ifdef CONFIG_SOFTMMU
663 int r2, ir;
664 void *label1_ptr, *label2_ptr;
665 #endif
666 #if TARGET_LONG_BITS == 64
667 int addr_reg2;
668 #endif
669
670 data_reg = *args++;
671 if (opc == 3)
672 data_reg2 = *args++;
673 else
674 data_reg2 = 0;
675 addr_reg = *args++;
676 #if TARGET_LONG_BITS == 64
677 addr_reg2 = *args++;
678 #endif
679 mem_index = *args;
680
681 #ifdef CONFIG_SOFTMMU
682 r0 = 3;
683 r1 = 4;
684 r2 = 0;
685
686 tcg_out32 (s, (RLWINM
687 | RA (r0)
688 | RS (addr_reg)
689 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
690 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
691 | ME (31 - CPU_TLB_ENTRY_BITS)
692 )
693 );
694 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
695 tcg_out32 (s, (LWZU
696 | RT (r1)
697 | RA (r0)
698 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
699 )
700 );
701 tcg_out32 (s, (RLWINM
702 | RA (r2)
703 | RS (addr_reg)
704 | SH (0)
705 | MB ((32 - opc) & 31)
706 | ME (31 - TARGET_PAGE_BITS)
707 )
708 );
709
710 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
711 #if TARGET_LONG_BITS == 64
712 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
713 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
714 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
715 #endif
716
717 label1_ptr = s->code_ptr;
718 #ifdef FAST_PATH
719 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
720 #endif
721
722 /* slow path */
723 #if TARGET_LONG_BITS == 32
724 tcg_out_mov (s, 3, addr_reg);
725 ir = 4;
726 #else
727 tcg_out_mov (s, 3, addr_reg2);
728 tcg_out_mov (s, 4, addr_reg);
729 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
730 ir = 5;
731 #else
732 ir = 4;
733 #endif
734 #endif
735
736 switch (opc) {
737 case 0:
738 tcg_out32 (s, (RLWINM
739 | RA (ir)
740 | RS (data_reg)
741 | SH (0)
742 | MB (24)
743 | ME (31)));
744 break;
745 case 1:
746 tcg_out32 (s, (RLWINM
747 | RA (ir)
748 | RS (data_reg)
749 | SH (0)
750 | MB (16)
751 | ME (31)));
752 break;
753 case 2:
754 tcg_out_mov (s, ir, data_reg);
755 break;
756 case 3:
757 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
758 ir = 5;
759 #endif
760 tcg_out_mov (s, ir++, data_reg2);
761 tcg_out_mov (s, ir, data_reg);
762 break;
763 }
764 ir++;
765
766 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
767 tcg_out_b (s, LK, (tcg_target_long) qemu_st_helpers[opc]);
768 label2_ptr = s->code_ptr;
769 tcg_out32 (s, B);
770
771 /* label1: fast path */
772 #ifdef FAST_PATH
773 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
774 #endif
775
776 tcg_out32 (s, (LWZ
777 | RT (r0)
778 | RA (r0)
779 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
780 - offsetof (CPUTLBEntry, addr_write))
781 ));
782 /* r0 = env->tlb_table[mem_index][index].addend */
783 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
784 /* r0 = env->tlb_table[mem_index][index].addend + addr */
785
786 #else /* !CONFIG_SOFTMMU */
787 r1 = 3;
788 r0 = addr_reg;
789 #endif
790
791 #ifdef TARGET_WORDS_BIGENDIAN
792 bswap = 0;
793 #else
794 bswap = 1;
795 #endif
796 switch (opc) {
797 case 0:
798 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
799 break;
800 case 1:
801 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
802 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
803 break;
804 case 2:
805 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
806 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
807 break;
808 case 3:
809 if (bswap) {
810 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
811 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
812 tcg_out32 (s, STWBRX | RS (data_reg2) | RA (0) | RB (r1));
813 }
814 else {
815 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
816 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
817 }
818 break;
819 }
820
821 #ifdef CONFIG_SOFTMMU
822 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
823 #endif
824 }
825
826 void tcg_target_qemu_prologue (TCGContext *s)
827 {
828 int i, frame_size;
829
830 frame_size = 0
831 + LINKAGE_AREA_SIZE
832 + TCG_STATIC_CALL_ARGS_SIZE
833 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
834 ;
835 frame_size = (frame_size + 15) & ~15;
836
837 tcg_out32 (s, MFSPR | RT (0) | LR);
838 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
839 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
840 tcg_out32 (s, (STW
841 | RS (tcg_target_callee_save_regs[i])
842 | RA (1)
843 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
844 )
845 );
846 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + BACK_CHAIN_OFFSET));
847
848 tcg_out32 (s, MTSPR | RS (3) | CTR);
849 tcg_out32 (s, BCCTR | BO_ALWAYS);
850 tb_ret_addr = s->code_ptr;
851
852 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
853 tcg_out32 (s, (LWZ
854 | RT (tcg_target_callee_save_regs[i])
855 | RA (1)
856 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
857 )
858 );
859 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + BACK_CHAIN_OFFSET));
860 tcg_out32 (s, MTSPR | RS (0) | LR);
861 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
862 tcg_out32 (s, BCLR | BO_ALWAYS);
863 }
864
865 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
866 tcg_target_long arg2)
867 {
868 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
869 }
870
871 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
872 tcg_target_long arg2)
873 {
874 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
875 }
876
877 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
878 {
879 if (!si && rt == ra)
880 return;
881
882 if (si == (int16_t) si)
883 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
884 else {
885 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
886 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
887 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
888 }
889 }
890
891 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
892 {
893 ppc_addi (s, reg, reg, val);
894 }
895
896 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
897 int const_arg2, int cr)
898 {
899 int imm;
900 uint32_t op;
901
902 switch (cond) {
903 case TCG_COND_EQ:
904 case TCG_COND_NE:
905 if (const_arg2) {
906 if ((int16_t) arg2 == arg2) {
907 op = CMPI;
908 imm = 1;
909 break;
910 }
911 else if ((uint16_t) arg2 == arg2) {
912 op = CMPLI;
913 imm = 1;
914 break;
915 }
916 }
917 op = CMPL;
918 imm = 0;
919 break;
920
921 case TCG_COND_LT:
922 case TCG_COND_GE:
923 case TCG_COND_LE:
924 case TCG_COND_GT:
925 if (const_arg2) {
926 if ((int16_t) arg2 == arg2) {
927 op = CMPI;
928 imm = 1;
929 break;
930 }
931 }
932 op = CMP;
933 imm = 0;
934 break;
935
936 case TCG_COND_LTU:
937 case TCG_COND_GEU:
938 case TCG_COND_LEU:
939 case TCG_COND_GTU:
940 if (const_arg2) {
941 if ((uint16_t) arg2 == arg2) {
942 op = CMPLI;
943 imm = 1;
944 break;
945 }
946 }
947 op = CMPL;
948 imm = 0;
949 break;
950
951 default:
952 tcg_abort ();
953 }
954 op |= BF (cr);
955
956 if (imm)
957 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
958 else {
959 if (const_arg2) {
960 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
961 tcg_out32 (s, op | RA (arg1) | RB (0));
962 }
963 else
964 tcg_out32 (s, op | RA (arg1) | RB (arg2));
965 }
966
967 }
968
969 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
970 {
971 TCGLabel *l = &s->labels[label_index];
972
973 if (l->has_value)
974 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
975 else {
976 uint16_t val = *(uint16_t *) &s->code_ptr[2];
977
978 /* Thanks to Andrzej Zaborowski */
979 tcg_out32 (s, bc | (val & 0xfffc));
980 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
981 }
982 }
983
984 static void tcg_out_brcond (TCGContext *s, int cond,
985 TCGArg arg1, TCGArg arg2, int const_arg2,
986 int label_index)
987 {
988 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
989 tcg_out_bc (s, tcg_to_bc[cond], label_index);
990 }
991
992 /* XXX: we implement it at the target level to avoid having to
993 handle cross basic blocks temporaries */
994 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
995 const int *const_args)
996 {
997 int cond = args[4], label_index = args[5], op;
998 struct { int bit1; int bit2; int cond2; } bits[] = {
999 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1000 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1001 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1002 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1003 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1004 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1005 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1006 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1007 }, *b = &bits[cond];
1008
1009 switch (cond) {
1010 case TCG_COND_EQ:
1011 case TCG_COND_NE:
1012 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1013 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1014 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1015 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1016 break;
1017 case TCG_COND_LT:
1018 case TCG_COND_LE:
1019 case TCG_COND_GT:
1020 case TCG_COND_GE:
1021 case TCG_COND_LTU:
1022 case TCG_COND_LEU:
1023 case TCG_COND_GTU:
1024 case TCG_COND_GEU:
1025 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1026 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1027 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1028 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1029 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1030 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1031 break;
1032 default:
1033 tcg_abort();
1034 }
1035
1036 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), label_index);
1037 }
1038
1039 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1040 {
1041 uint32_t *ptr;
1042 long disp = addr - jmp_addr;
1043 unsigned long patch_size;
1044
1045 ptr = (uint32_t *)jmp_addr;
1046
1047 if ((disp << 6) >> 6 != disp) {
1048 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1049 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1050 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1051 ptr[3] = 0x4e800420; /* brctr */
1052 patch_size = 16;
1053 } else {
1054 /* patch the branch destination */
1055 if (disp != 16) {
1056 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1057 patch_size = 4;
1058 } else {
1059 ptr[0] = 0x60000000; /* nop */
1060 ptr[1] = 0x60000000;
1061 ptr[2] = 0x60000000;
1062 ptr[3] = 0x60000000;
1063 patch_size = 16;
1064 }
1065 }
1066 /* flush icache */
1067 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1068 }
1069
1070 static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1071 const int *const_args)
1072 {
1073 switch (opc) {
1074 case INDEX_op_exit_tb:
1075 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1076 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1077 break;
1078 case INDEX_op_goto_tb:
1079 if (s->tb_jmp_offset) {
1080 /* direct jump method */
1081
1082 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1083 s->code_ptr += 16;
1084 }
1085 else {
1086 tcg_abort ();
1087 }
1088 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1089 break;
1090 case INDEX_op_br:
1091 {
1092 TCGLabel *l = &s->labels[args[0]];
1093
1094 if (l->has_value) {
1095 tcg_out_b (s, 0, l->u.value);
1096 }
1097 else {
1098 uint32_t val = *(uint32_t *) s->code_ptr;
1099
1100 /* Thanks to Andrzej Zaborowski */
1101 tcg_out32 (s, B | (val & 0x3fffffc));
1102 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1103 }
1104 }
1105 break;
1106 case INDEX_op_call:
1107 if (const_args[0]) {
1108 tcg_out_b (s, LK, args[0]);
1109 }
1110 else {
1111 tcg_out32 (s, MTSPR | RS (args[0]) | LR);
1112 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
1113 }
1114 break;
1115 case INDEX_op_jmp:
1116 if (const_args[0]) {
1117 tcg_out_b (s, 0, args[0]);
1118 }
1119 else {
1120 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1121 tcg_out32 (s, BCCTR | BO_ALWAYS);
1122 }
1123 break;
1124 case INDEX_op_movi_i32:
1125 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1126 break;
1127 case INDEX_op_ld8u_i32:
1128 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1129 break;
1130 case INDEX_op_ld8s_i32:
1131 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1132 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1133 break;
1134 case INDEX_op_ld16u_i32:
1135 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1136 break;
1137 case INDEX_op_ld16s_i32:
1138 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1139 break;
1140 case INDEX_op_ld_i32:
1141 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1142 break;
1143 case INDEX_op_st8_i32:
1144 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1145 break;
1146 case INDEX_op_st16_i32:
1147 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1148 break;
1149 case INDEX_op_st_i32:
1150 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1151 break;
1152
1153 case INDEX_op_add_i32:
1154 if (const_args[2])
1155 ppc_addi (s, args[0], args[1], args[2]);
1156 else
1157 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1158 break;
1159 case INDEX_op_sub_i32:
1160 if (const_args[2])
1161 ppc_addi (s, args[0], args[1], -args[2]);
1162 else
1163 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1164 break;
1165
1166 case INDEX_op_and_i32:
1167 if (const_args[2]) {
1168 if ((args[2] & 0xffff) == args[2])
1169 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1170 else if ((args[2] & 0xffff0000) == args[2])
1171 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1172 | ((args[2] >> 16) & 0xffff));
1173 else {
1174 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1175 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1176 }
1177 }
1178 else
1179 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1180 break;
1181 case INDEX_op_or_i32:
1182 if (const_args[2]) {
1183 if (args[2] & 0xffff) {
1184 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1185 | (args[2] & 0xffff));
1186 if (args[2] >> 16)
1187 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1188 | ((args[2] >> 16) & 0xffff));
1189 }
1190 else {
1191 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1192 | ((args[2] >> 16) & 0xffff));
1193 }
1194 }
1195 else
1196 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1197 break;
1198 case INDEX_op_xor_i32:
1199 if (const_args[2]) {
1200 if ((args[2] & 0xffff) == args[2])
1201 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1202 | (args[2] & 0xffff));
1203 else if ((args[2] & 0xffff0000) == args[2])
1204 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1205 | ((args[2] >> 16) & 0xffff));
1206 else {
1207 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1208 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1209 }
1210 }
1211 else
1212 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1213 break;
1214
1215 case INDEX_op_mul_i32:
1216 if (const_args[2]) {
1217 if (args[2] == (int16_t) args[2])
1218 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1219 | (args[2] & 0xffff));
1220 else {
1221 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1222 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1223 }
1224 }
1225 else
1226 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1227 break;
1228
1229 case INDEX_op_div_i32:
1230 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1231 break;
1232
1233 case INDEX_op_divu_i32:
1234 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1235 break;
1236
1237 case INDEX_op_rem_i32:
1238 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1239 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1240 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1241 break;
1242
1243 case INDEX_op_remu_i32:
1244 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1245 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1246 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1247 break;
1248
1249 case INDEX_op_mulu2_i32:
1250 if (args[0] == args[2] || args[0] == args[3]) {
1251 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1252 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1253 tcg_out_mov (s, args[0], 0);
1254 }
1255 else {
1256 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1257 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1258 }
1259 break;
1260
1261 case INDEX_op_shl_i32:
1262 if (const_args[2]) {
1263 tcg_out32 (s, (RLWINM
1264 | RA (args[0])
1265 | RS (args[1])
1266 | SH (args[2])
1267 | MB (0)
1268 | ME (31 - args[2])
1269 )
1270 );
1271 }
1272 else
1273 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1274 break;
1275 case INDEX_op_shr_i32:
1276 if (const_args[2]) {
1277 tcg_out32 (s, (RLWINM
1278 | RA (args[0])
1279 | RS (args[1])
1280 | SH (32 - args[2])
1281 | MB (args[2])
1282 | ME (31)
1283 )
1284 );
1285 }
1286 else
1287 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1288 break;
1289 case INDEX_op_sar_i32:
1290 if (const_args[2])
1291 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1292 else
1293 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1294 break;
1295
1296 case INDEX_op_add2_i32:
1297 if (args[0] == args[3] || args[0] == args[5]) {
1298 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1299 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1300 tcg_out_mov (s, args[0], 0);
1301 }
1302 else {
1303 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1304 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1305 }
1306 break;
1307 case INDEX_op_sub2_i32:
1308 if (args[0] == args[3] || args[0] == args[5]) {
1309 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1310 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1311 tcg_out_mov (s, args[0], 0);
1312 }
1313 else {
1314 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1315 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1316 }
1317 break;
1318
1319 case INDEX_op_brcond_i32:
1320 /*
1321 args[0] = r0
1322 args[1] = r1
1323 args[2] = cond
1324 args[3] = r1 is const
1325 args[4] = label_index
1326 */
1327 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1328 break;
1329 case INDEX_op_brcond2_i32:
1330 tcg_out_brcond2(s, args, const_args);
1331 break;
1332
1333 case INDEX_op_neg_i32:
1334 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1335 break;
1336
1337 case INDEX_op_qemu_ld8u:
1338 tcg_out_qemu_ld(s, args, 0);
1339 break;
1340 case INDEX_op_qemu_ld8s:
1341 tcg_out_qemu_ld(s, args, 0 | 4);
1342 break;
1343 case INDEX_op_qemu_ld16u:
1344 tcg_out_qemu_ld(s, args, 1);
1345 break;
1346 case INDEX_op_qemu_ld16s:
1347 tcg_out_qemu_ld(s, args, 1 | 4);
1348 break;
1349 case INDEX_op_qemu_ld32u:
1350 tcg_out_qemu_ld(s, args, 2);
1351 break;
1352 case INDEX_op_qemu_ld64:
1353 tcg_out_qemu_ld(s, args, 3);
1354 break;
1355 case INDEX_op_qemu_st8:
1356 tcg_out_qemu_st(s, args, 0);
1357 break;
1358 case INDEX_op_qemu_st16:
1359 tcg_out_qemu_st(s, args, 1);
1360 break;
1361 case INDEX_op_qemu_st32:
1362 tcg_out_qemu_st(s, args, 2);
1363 break;
1364 case INDEX_op_qemu_st64:
1365 tcg_out_qemu_st(s, args, 3);
1366 break;
1367
1368 case INDEX_op_ext8s_i32:
1369 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1370 break;
1371 case INDEX_op_ext16s_i32:
1372 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1373 break;
1374
1375 default:
1376 tcg_dump_ops (s, stderr);
1377 tcg_abort ();
1378 }
1379 }
1380
1381 static const TCGTargetOpDef ppc_op_defs[] = {
1382 { INDEX_op_exit_tb, { } },
1383 { INDEX_op_goto_tb, { } },
1384 { INDEX_op_call, { "ri" } },
1385 { INDEX_op_jmp, { "ri" } },
1386 { INDEX_op_br, { } },
1387
1388 { INDEX_op_mov_i32, { "r", "r" } },
1389 { INDEX_op_movi_i32, { "r" } },
1390 { INDEX_op_ld8u_i32, { "r", "r" } },
1391 { INDEX_op_ld8s_i32, { "r", "r" } },
1392 { INDEX_op_ld16u_i32, { "r", "r" } },
1393 { INDEX_op_ld16s_i32, { "r", "r" } },
1394 { INDEX_op_ld_i32, { "r", "r" } },
1395 { INDEX_op_st8_i32, { "r", "r" } },
1396 { INDEX_op_st16_i32, { "r", "r" } },
1397 { INDEX_op_st_i32, { "r", "r" } },
1398
1399 { INDEX_op_add_i32, { "r", "r", "ri" } },
1400 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1401 { INDEX_op_div_i32, { "r", "r", "r" } },
1402 { INDEX_op_divu_i32, { "r", "r", "r" } },
1403 { INDEX_op_rem_i32, { "r", "r", "r" } },
1404 { INDEX_op_remu_i32, { "r", "r", "r" } },
1405 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1406 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1407 { INDEX_op_and_i32, { "r", "r", "ri" } },
1408 { INDEX_op_or_i32, { "r", "r", "ri" } },
1409 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1410
1411 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1412 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1413 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1414
1415 { INDEX_op_brcond_i32, { "r", "ri" } },
1416
1417 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1418 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1419 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1420
1421 { INDEX_op_neg_i32, { "r", "r" } },
1422
1423 #if TARGET_LONG_BITS == 32
1424 { INDEX_op_qemu_ld8u, { "r", "L" } },
1425 { INDEX_op_qemu_ld8s, { "r", "L" } },
1426 { INDEX_op_qemu_ld16u, { "r", "L" } },
1427 { INDEX_op_qemu_ld16s, { "r", "L" } },
1428 { INDEX_op_qemu_ld32u, { "r", "L" } },
1429 { INDEX_op_qemu_ld32s, { "r", "L" } },
1430 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1431
1432 { INDEX_op_qemu_st8, { "K", "K" } },
1433 { INDEX_op_qemu_st16, { "K", "K" } },
1434 { INDEX_op_qemu_st32, { "K", "K" } },
1435 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1436 #else
1437 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1438 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1439 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1440 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1441 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1442 { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1443 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1444
1445 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1446 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1447 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1448 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1449 #endif
1450
1451 { INDEX_op_ext8s_i32, { "r", "r" } },
1452 { INDEX_op_ext16s_i32, { "r", "r" } },
1453
1454 { -1 },
1455 };
1456
1457 void tcg_target_init(TCGContext *s)
1458 {
1459 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1460 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1461 (1 << TCG_REG_R0) |
1462 #ifdef __APPLE__
1463 (1 << TCG_REG_R2) |
1464 #endif
1465 (1 << TCG_REG_R3) |
1466 (1 << TCG_REG_R4) |
1467 (1 << TCG_REG_R5) |
1468 (1 << TCG_REG_R6) |
1469 (1 << TCG_REG_R7) |
1470 (1 << TCG_REG_R8) |
1471 (1 << TCG_REG_R9) |
1472 (1 << TCG_REG_R10) |
1473 (1 << TCG_REG_R11) |
1474 (1 << TCG_REG_R12)
1475 );
1476
1477 tcg_regset_clear(s->reserved_regs);
1478 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1479 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1480 #ifndef __APPLE__
1481 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1482 #endif
1483
1484 tcg_add_target_add_op_defs(ppc_op_defs);
1485 }
Samsung s3c2440 and arm920t support for the mini2440 dev board