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Fix dots per clock value, cleanup and "optimize"
[qemu/mini2440.git] / hw / nseries.c
blobae87b3f52052da2a093c7362d5ef9d86b4e03750
1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23 #include "qemu-common.h"
24 #include "sysemu.h"
25 #include "omap.h"
26 #include "arm-misc.h"
27 #include "irq.h"
28 #include "console.h"
29 #include "boards.h"
30 #include "i2c.h"
31 #include "devices.h"
32 #include "flash.h"
33 #include "hw.h"
34
35 /* Nokia N8x0 support */
36 struct n800_s {
37 struct omap_mpu_state_s *cpu;
38
39 struct rfbi_chip_s blizzard;
40 struct {
41 void *opaque;
42 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
43 struct uwire_slave_s *chip;
44 } ts;
45 i2c_bus *i2c;
46
47 int keymap[0x80];
48 i2c_slave *kbd;
49
50 struct tusb_s *usb;
51 void *retu;
52 void *tahvo;
53 void *nand;
54 };
55
56 /* GPIO pins */
57 #define N8X0_TUSB_ENABLE_GPIO 0
58 #define N800_MMC2_WP_GPIO 8
59 #define N800_UNKNOWN_GPIO0 9 /* out */
60 #define N810_MMC2_VIOSD_GPIO 9
61 #define N810_HEADSET_AMP_GPIO 10
62 #define N800_CAM_TURN_GPIO 12
63 #define N810_GPS_RESET_GPIO 12
64 #define N800_BLIZZARD_POWERDOWN_GPIO 15
65 #define N800_MMC1_WP_GPIO 23
66 #define N810_MMC2_VSD_GPIO 23
67 #define N8X0_ONENAND_GPIO 26
68 #define N810_BLIZZARD_RESET_GPIO 30
69 #define N800_UNKNOWN_GPIO2 53 /* out */
70 #define N8X0_TUSB_INT_GPIO 58
71 #define N8X0_BT_WKUP_GPIO 61
72 #define N8X0_STI_GPIO 62
73 #define N8X0_CBUS_SEL_GPIO 64
74 #define N8X0_CBUS_DAT_GPIO 65
75 #define N8X0_CBUS_CLK_GPIO 66
76 #define N8X0_WLAN_IRQ_GPIO 87
77 #define N8X0_BT_RESET_GPIO 92
78 #define N8X0_TEA5761_CS_GPIO 93
79 #define N800_UNKNOWN_GPIO 94
80 #define N810_TSC_RESET_GPIO 94
81 #define N800_CAM_ACT_GPIO 95
82 #define N810_GPS_WAKEUP_GPIO 95
83 #define N8X0_MMC_CS_GPIO 96
84 #define N8X0_WLAN_PWR_GPIO 97
85 #define N8X0_BT_HOST_WKUP_GPIO 98
86 #define N810_SPEAKER_AMP_GPIO 101
87 #define N810_KB_LOCK_GPIO 102
88 #define N800_TSC_TS_GPIO 103
89 #define N810_TSC_TS_GPIO 106
90 #define N8X0_HEADPHONE_GPIO 107
91 #define N8X0_RETU_GPIO 108
92 #define N800_TSC_KP_IRQ_GPIO 109
93 #define N810_KEYBOARD_GPIO 109
94 #define N800_BAT_COVER_GPIO 110
95 #define N810_SLIDE_GPIO 110
96 #define N8X0_TAHVO_GPIO 111
97 #define N800_UNKNOWN_GPIO4 112 /* out */
98 #define N810_SLEEPX_LED_GPIO 112
99 #define N800_TSC_RESET_GPIO 118 /* ? */
100 #define N810_AIC33_RESET_GPIO 118
101 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
102 #define N8X0_TMP105_GPIO 125
103
104 /* Config */
105 #define BT_UART 0
106 #define XLDR_LL_UART 1
107
108 /* Addresses on the I2C bus 0 */
109 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
110 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
111 #define N810_LP5521_ADDR 0x32 /* LEDs */
112 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
113 #define N810_LM8323_ADDR 0x45 /* Keyboard */
114 /* Addresses on the I2C bus 1 */
115 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
116 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
117
118 /* Chipselects on GPMC NOR interface */
119 #define N8X0_ONENAND_CS 0
120 #define N8X0_USB_ASYNC_CS 1
121 #define N8X0_USB_SYNC_CS 4
122
123 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
124
125 typedef struct {
126 uint8_t b[6];
127 } __attribute__((packed)) bdaddr_t; /* XXX: move to BT headers */
128
129 static void n800_mmc_cs_cb(void *opaque, int line, int level)
130 {
131 /* TODO: this seems to actually be connected to the menelaus, to
132 * which also both MMC slots connect. */
133 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
134
135 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
136 }
137
138 static void n8x0_gpio_setup(struct n800_s *s)
139 {
140 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
141 omap2_gpio_out_set(s->cpu->gpif, N8X0_MMC_CS_GPIO, mmc_cs[0]);
142
143 qemu_irq_lower(omap2_gpio_in_get(s->cpu->gpif, N800_BAT_COVER_GPIO)[0]);
144 }
145
146 #define MAEMO_CAL_HEADER(...) \
147 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
148 __VA_ARGS__, \
149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
150
151 static const uint8_t n8x0_cal_wlan_mac[] = {
152 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
153 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
154 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
155 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
156 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
157 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
158 };
159
160 static const uint8_t n8x0_cal_bt_id[] = {
161 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
162 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
163 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
164 N8X0_BD_ADDR,
165 };
166
167 static void n8x0_nand_setup(struct n800_s *s)
168 {
169 char *otp_region;
170
171 /* Either ec40xx or ec48xx are OK for the ID */
172 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
173 onenand_base_unmap,
174 (s->nand = onenand_init(0xec4800, 1,
175 omap2_gpio_in_get(s->cpu->gpif,
176 N8X0_ONENAND_GPIO)[0])));
177 otp_region = onenand_raw_otp(s->nand);
178
179 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
180 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
181 /* XXX: in theory should also update the OOB for both pages */
182 }
183
184 static void n8x0_i2c_setup(struct n800_s *s)
185 {
186 qemu_irq tmp_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TMP105_GPIO)[0];
187
188 /* Attach the CPU on one end of our I2C bus. */
189 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
190
191 /* Attach a menelaus PM chip */
192 i2c_set_slave_address(
193 twl92230_init(s->i2c,
194 s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]),
195 N8X0_MENELAUS_ADDR);
196
197 /* Attach a TMP105 PM chip (A0 wired to ground) */
198 i2c_set_slave_address(tmp105_init(s->i2c, tmp_irq), N8X0_TMP105_ADDR);
199 }
200
201 /* Touchscreen and keypad controller */
202 static struct mouse_transform_info_s n800_pointercal = {
203 .x = 800,
204 .y = 480,
205 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
206 };
207
208 static struct mouse_transform_info_s n810_pointercal = {
209 .x = 800,
210 .y = 480,
211 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
212 };
213
214 #define RETU_KEYCODE 61 /* F3 */
215
216 static void n800_key_event(void *opaque, int keycode)
217 {
218 struct n800_s *s = (struct n800_s *) opaque;
219 int code = s->keymap[keycode & 0x7f];
220
221 if (code == -1) {
222 if ((keycode & 0x7f) == RETU_KEYCODE)
223 retu_key_event(s->retu, !(keycode & 0x80));
224 return;
225 }
226
227 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
228 }
229
230 static const int n800_keys[16] = {
231 -1,
232 72, /* Up */
233 63, /* Home (F5) */
234 -1,
235 75, /* Left */
236 28, /* Enter */
237 77, /* Right */
238 -1,
239 1, /* Cycle (ESC) */
240 80, /* Down */
241 62, /* Menu (F4) */
242 -1,
243 66, /* Zoom- (F8) */
244 64, /* FullScreen (F6) */
245 65, /* Zoom+ (F7) */
246 -1,
247 };
248
249 static void n800_tsc_kbd_setup(struct n800_s *s)
250 {
251 int i;
252
253 /* XXX: are the three pins inverted inside the chip between the
254 * tsc and the cpu (N4111)? */
255 qemu_irq penirq = 0; /* NC */
256 qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0];
257 qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0];
258
259 s->ts.chip = tsc2301_init(penirq, kbirq, dav, 0);
260 s->ts.opaque = s->ts.chip->opaque;
261 s->ts.txrx = tsc210x_txrx;
262
263 for (i = 0; i < 0x80; i ++)
264 s->keymap[i] = -1;
265 for (i = 0; i < 0x10; i ++)
266 if (n800_keys[i] >= 0)
267 s->keymap[n800_keys[i]] = i;
268
269 qemu_add_kbd_event_handler(n800_key_event, s);
270
271 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
272 }
273
274 static void n810_tsc_setup(struct n800_s *s)
275 {
276 qemu_irq pintdav = omap2_gpio_in_get(s->cpu->gpif, N810_TSC_TS_GPIO)[0];
277
278 s->ts.opaque = tsc2005_init(pintdav);
279 s->ts.txrx = tsc2005_txrx;
280
281 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
282 }
283
284 /* N810 Keyboard controller */
285 static void n810_key_event(void *opaque, int keycode)
286 {
287 struct n800_s *s = (struct n800_s *) opaque;
288 int code = s->keymap[keycode & 0x7f];
289
290 if (code == -1) {
291 if ((keycode & 0x7f) == RETU_KEYCODE)
292 retu_key_event(s->retu, !(keycode & 0x80));
293 return;
294 }
295
296 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
297 }
298
299 #define M 0
300
301 static int n810_keys[0x80] = {
302 [0x01] = 16, /* Q */
303 [0x02] = 37, /* K */
304 [0x03] = 24, /* O */
305 [0x04] = 25, /* P */
306 [0x05] = 14, /* Backspace */
307 [0x06] = 30, /* A */
308 [0x07] = 31, /* S */
309 [0x08] = 32, /* D */
310 [0x09] = 33, /* F */
311 [0x0a] = 34, /* G */
312 [0x0b] = 35, /* H */
313 [0x0c] = 36, /* J */
314
315 [0x11] = 17, /* W */
316 [0x12] = 62, /* Menu (F4) */
317 [0x13] = 38, /* L */
318 [0x14] = 40, /* ' (Apostrophe) */
319 [0x16] = 44, /* Z */
320 [0x17] = 45, /* X */
321 [0x18] = 46, /* C */
322 [0x19] = 47, /* V */
323 [0x1a] = 48, /* B */
324 [0x1b] = 49, /* N */
325 [0x1c] = 42, /* Shift (Left shift) */
326 [0x1f] = 65, /* Zoom+ (F7) */
327
328 [0x21] = 18, /* E */
329 [0x22] = 39, /* ; (Semicolon) */
330 [0x23] = 12, /* - (Minus) */
331 [0x24] = 13, /* = (Equal) */
332 [0x2b] = 56, /* Fn (Left Alt) */
333 [0x2c] = 50, /* M */
334 [0x2f] = 66, /* Zoom- (F8) */
335
336 [0x31] = 19, /* R */
337 [0x32] = 29 | M, /* Right Ctrl */
338 [0x34] = 57, /* Space */
339 [0x35] = 51, /* , (Comma) */
340 [0x37] = 72 | M, /* Up */
341 [0x3c] = 82 | M, /* Compose (Insert) */
342 [0x3f] = 64, /* FullScreen (F6) */
343
344 [0x41] = 20, /* T */
345 [0x44] = 52, /* . (Dot) */
346 [0x46] = 77 | M, /* Right */
347 [0x4f] = 63, /* Home (F5) */
348 [0x51] = 21, /* Y */
349 [0x53] = 80 | M, /* Down */
350 [0x55] = 28, /* Enter */
351 [0x5f] = 1, /* Cycle (ESC) */
352
353 [0x61] = 22, /* U */
354 [0x64] = 75 | M, /* Left */
355
356 [0x71] = 23, /* I */
357 #if 0
358 [0x75] = 28 | M, /* KP Enter (KP Enter) */
359 #else
360 [0x75] = 15, /* KP Enter (Tab) */
361 #endif
362 };
363
364 #undef M
365
366 static void n810_kbd_setup(struct n800_s *s)
367 {
368 qemu_irq kbd_irq = omap2_gpio_in_get(s->cpu->gpif, N810_KEYBOARD_GPIO)[0];
369 int i;
370
371 for (i = 0; i < 0x80; i ++)
372 s->keymap[i] = -1;
373 for (i = 0; i < 0x80; i ++)
374 if (n810_keys[i] > 0)
375 s->keymap[n810_keys[i]] = i;
376
377 qemu_add_kbd_event_handler(n810_key_event, s);
378
379 /* Attach the LM8322 keyboard to the I2C bus,
380 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
381 s->kbd = lm8323_init(s->i2c, kbd_irq);
382 i2c_set_slave_address(s->kbd, N810_LM8323_ADDR);
383 }
384
385 /* LCD MIPI DBI-C controller (URAL) */
386 struct mipid_s {
387 int resp[4];
388 int param[4];
389 int p;
390 int pm;
391 int cmd;
392
393 int sleep;
394 int booster;
395 int te;
396 int selfcheck;
397 int partial;
398 int normal;
399 int vscr;
400 int invert;
401 int onoff;
402 int gamma;
403 uint32_t id;
404 };
405
406 static void mipid_reset(struct mipid_s *s)
407 {
408 if (!s->sleep)
409 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
410
411 s->pm = 0;
412 s->cmd = 0;
413
414 s->sleep = 1;
415 s->booster = 0;
416 s->selfcheck =
417 (1 << 7) | /* Register loading OK. */
418 (1 << 5) | /* The chip is attached. */
419 (1 << 4); /* Display glass still in one piece. */
420 s->te = 0;
421 s->partial = 0;
422 s->normal = 1;
423 s->vscr = 0;
424 s->invert = 0;
425 s->onoff = 1;
426 s->gamma = 0;
427 }
428
429 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
430 {
431 struct mipid_s *s = (struct mipid_s *) opaque;
432 uint8_t ret;
433
434 if (len > 9)
435 cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n",
436 __FUNCTION__, len);
437
438 if (s->p >= sizeof(s->resp) / sizeof(*s->resp))
439 ret = 0;
440 else
441 ret = s->resp[s->p ++];
442 if (s->pm --> 0)
443 s->param[s->pm] = cmd;
444 else
445 s->cmd = cmd;
446
447 switch (s->cmd) {
448 case 0x00: /* NOP */
449 break;
450
451 case 0x01: /* SWRESET */
452 mipid_reset(s);
453 break;
454
455 case 0x02: /* BSTROFF */
456 s->booster = 0;
457 break;
458 case 0x03: /* BSTRON */
459 s->booster = 1;
460 break;
461
462 case 0x04: /* RDDID */
463 s->p = 0;
464 s->resp[0] = (s->id >> 16) & 0xff;
465 s->resp[1] = (s->id >> 8) & 0xff;
466 s->resp[2] = (s->id >> 0) & 0xff;
467 break;
468
469 case 0x06: /* RD_RED */
470 case 0x07: /* RD_GREEN */
471 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
472 * for the bootloader one needs to change this. */
473 case 0x08: /* RD_BLUE */
474 s->p = 0;
475 /* TODO: return first pixel components */
476 s->resp[0] = 0x01;
477 break;
478
479 case 0x09: /* RDDST */
480 s->p = 0;
481 s->resp[0] = s->booster << 7;
482 s->resp[1] = (5 << 4) | (s->partial << 2) |
483 (s->sleep << 1) | s->normal;
484 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
485 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
486 s->resp[3] = s->gamma << 6;
487 break;
488
489 case 0x0a: /* RDDPM */
490 s->p = 0;
491 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
492 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
493 break;
494 case 0x0b: /* RDDMADCTR */
495 s->p = 0;
496 s->resp[0] = 0;
497 break;
498 case 0x0c: /* RDDCOLMOD */
499 s->p = 0;
500 s->resp[0] = 5; /* 65K colours */
501 break;
502 case 0x0d: /* RDDIM */
503 s->p = 0;
504 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
505 break;
506 case 0x0e: /* RDDSM */
507 s->p = 0;
508 s->resp[0] = s->te << 7;
509 break;
510 case 0x0f: /* RDDSDR */
511 s->p = 0;
512 s->resp[0] = s->selfcheck;
513 break;
514
515 case 0x10: /* SLPIN */
516 s->sleep = 1;
517 break;
518 case 0x11: /* SLPOUT */
519 s->sleep = 0;
520 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
521 break;
522
523 case 0x12: /* PTLON */
524 s->partial = 1;
525 s->normal = 0;
526 s->vscr = 0;
527 break;
528 case 0x13: /* NORON */
529 s->partial = 0;
530 s->normal = 1;
531 s->vscr = 0;
532 break;
533
534 case 0x20: /* INVOFF */
535 s->invert = 0;
536 break;
537 case 0x21: /* INVON */
538 s->invert = 1;
539 break;
540
541 case 0x22: /* APOFF */
542 case 0x23: /* APON */
543 goto bad_cmd;
544
545 case 0x25: /* WRCNTR */
546 if (s->pm < 0)
547 s->pm = 1;
548 goto bad_cmd;
549
550 case 0x26: /* GAMSET */
551 if (!s->pm)
552 s->gamma = ffs(s->param[0] & 0xf) - 1;
553 else if (s->pm < 0)
554 s->pm = 1;
555 break;
556
557 case 0x28: /* DISPOFF */
558 s->onoff = 0;
559 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
560 break;
561 case 0x29: /* DISPON */
562 s->onoff = 1;
563 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
564 break;
565
566 case 0x2a: /* CASET */
567 case 0x2b: /* RASET */
568 case 0x2c: /* RAMWR */
569 case 0x2d: /* RGBSET */
570 case 0x2e: /* RAMRD */
571 case 0x30: /* PTLAR */
572 case 0x33: /* SCRLAR */
573 goto bad_cmd;
574
575 case 0x34: /* TEOFF */
576 s->te = 0;
577 break;
578 case 0x35: /* TEON */
579 if (!s->pm)
580 s->te = 1;
581 else if (s->pm < 0)
582 s->pm = 1;
583 break;
584
585 case 0x36: /* MADCTR */
586 goto bad_cmd;
587
588 case 0x37: /* VSCSAD */
589 s->partial = 0;
590 s->normal = 0;
591 s->vscr = 1;
592 break;
593
594 case 0x38: /* IDMOFF */
595 case 0x39: /* IDMON */
596 case 0x3a: /* COLMOD */
597 goto bad_cmd;
598
599 case 0xb0: /* CLKINT / DISCTL */
600 case 0xb1: /* CLKEXT */
601 if (s->pm < 0)
602 s->pm = 2;
603 break;
604
605 case 0xb4: /* FRMSEL */
606 break;
607
608 case 0xb5: /* FRM8SEL */
609 case 0xb6: /* TMPRNG / INIESC */
610 case 0xb7: /* TMPHIS / NOP2 */
611 case 0xb8: /* TMPREAD / MADCTL */
612 case 0xba: /* DISTCTR */
613 case 0xbb: /* EPVOL */
614 goto bad_cmd;
615
616 case 0xbd: /* Unknown */
617 s->p = 0;
618 s->resp[0] = 0;
619 s->resp[1] = 1;
620 break;
621
622 case 0xc2: /* IFMOD */
623 if (s->pm < 0)
624 s->pm = 2;
625 break;
626
627 case 0xc6: /* PWRCTL */
628 case 0xc7: /* PPWRCTL */
629 case 0xd0: /* EPWROUT */
630 case 0xd1: /* EPWRIN */
631 case 0xd4: /* RDEV */
632 case 0xd5: /* RDRR */
633 goto bad_cmd;
634
635 case 0xda: /* RDID1 */
636 s->p = 0;
637 s->resp[0] = (s->id >> 16) & 0xff;
638 break;
639 case 0xdb: /* RDID2 */
640 s->p = 0;
641 s->resp[0] = (s->id >> 8) & 0xff;
642 break;
643 case 0xdc: /* RDID3 */
644 s->p = 0;
645 s->resp[0] = (s->id >> 0) & 0xff;
646 break;
647
648 default:
649 bad_cmd:
650 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
651 break;
652 }
653
654 return ret;
655 }
656
657 static void *mipid_init(void)
658 {
659 struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s));
660
661 s->id = 0x838f03;
662 mipid_reset(s);
663
664 return s;
665 }
666
667 static void n8x0_spi_setup(struct n800_s *s)
668 {
669 void *tsc = s->ts.opaque;
670 void *mipid = mipid_init();
671
672 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
673 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
674 }
675
676 /* This task is normally performed by the bootloader. If we're loading
677 * a kernel directly, we need to enable the Blizzard ourselves. */
678 static void n800_dss_init(struct rfbi_chip_s *chip)
679 {
680 uint8_t *fb_blank;
681
682 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
683 chip->write(chip->opaque, 1, 0x64);
684 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
685 chip->write(chip->opaque, 1, 0x1e);
686 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
687 chip->write(chip->opaque, 1, 0xe0);
688 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
689 chip->write(chip->opaque, 1, 0x01);
690 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
691 chip->write(chip->opaque, 1, 0x06);
692 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
693 chip->write(chip->opaque, 1, 1); /* Enable bit */
694
695 chip->write(chip->opaque, 0, 0x6c);
696 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
697 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
698 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
699 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
700 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
701 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
702 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
703 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
704 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
705 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
706 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
707 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
708 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
709 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
710 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
711 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
712 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
713 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
714
715 fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
716 /* Display Memory Data Port */
717 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
718 free(fb_blank);
719 }
720
721 static void n8x0_dss_setup(struct n800_s *s, DisplayState *ds)
722 {
723 s->blizzard.opaque = s1d13745_init(0, ds);
724 s->blizzard.block = s1d13745_write_block;
725 s->blizzard.write = s1d13745_write;
726 s->blizzard.read = s1d13745_read;
727
728 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
729 }
730
731 static void n8x0_cbus_setup(struct n800_s *s)
732 {
733 qemu_irq dat_out = omap2_gpio_in_get(s->cpu->gpif, N8X0_CBUS_DAT_GPIO)[0];
734 qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0];
735 qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0];
736
737 struct cbus_s *cbus = cbus_init(dat_out);
738
739 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk);
740 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat);
741 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_SEL_GPIO, cbus->sel);
742
743 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
744 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
745 }
746
747 static void n8x0_usb_power_cb(void *opaque, int line, int level)
748 {
749 struct n800_s *s = opaque;
750
751 tusb6010_power(s->usb, level);
752 }
753
754 static void n8x0_usb_setup(struct n800_s *s)
755 {
756 qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0];
757 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
758 struct tusb_s *tusb = tusb6010_init(tusb_irq);
759
760 /* Using the NOR interface */
761 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
762 tusb6010_async_io(tusb), 0, 0, tusb);
763 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
764 tusb6010_sync_io(tusb), 0, 0, tusb);
765
766 s->usb = tusb;
767 omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
768 }
769
770 /* Setup done before the main bootloader starts by some early setup code
771 * - used when we want to run the main bootloader in emulation. This
772 * isn't documented. */
773 static uint32_t n800_pinout[104] = {
774 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
775 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
776 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
777 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
778 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
779 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
780 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
781 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
782 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
783 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
784 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
785 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
786 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
787 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
788 0x00000000, 0x00000038, 0x00340000, 0x00000000,
789 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
790 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
791 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
792 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
793 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
794 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
795 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
796 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
797 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
798 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
799 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
800 };
801
802 static void n800_setup_nolo_tags(void *sram_base)
803 {
804 int i;
805 uint32_t *p = sram_base + 0x8000;
806 uint32_t *v = sram_base + 0xa000;
807
808 memset(p, 0, 0x3000);
809
810 strcpy((void *) (p + 0), "QEMU N800");
811
812 strcpy((void *) (p + 8), "F5");
813
814 stl_raw(p + 10, 0x04f70000);
815 strcpy((void *) (p + 9), "RX-34");
816
817 /* RAM size in MB? */
818 stl_raw(p + 12, 0x80);
819
820 /* Pointer to the list of tags */
821 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
822
823 /* The NOLO tags start here */
824 p = sram_base + 0x9000;
825 #define ADD_TAG(tag, len) \
826 stw_raw((uint16_t *) p + 0, tag); \
827 stw_raw((uint16_t *) p + 1, len); p ++; \
828 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
829
830 /* OMAP STI console? Pin out settings? */
831 ADD_TAG(0x6e01, 414);
832 for (i = 0; i < sizeof(n800_pinout) / 4; i ++)
833 stl_raw(v ++, n800_pinout[i]);
834
835 /* Kernel memsize? */
836 ADD_TAG(0x6e05, 1);
837 stl_raw(v ++, 2);
838
839 /* NOLO serial console */
840 ADD_TAG(0x6e02, 4);
841 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
842
843 #if 0
844 /* CBUS settings (Retu/AVilma) */
845 ADD_TAG(0x6e03, 6);
846 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
847 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
848 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
849 v += 2;
850 #endif
851
852 /* Nokia ASIC BB5 (Retu/Tahvo) */
853 ADD_TAG(0x6e0a, 4);
854 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
855 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
856 v ++;
857
858 /* LCD console? */
859 ADD_TAG(0x6e04, 4);
860 stw_raw((uint16_t *) v + 0, 30); /* ??? */
861 stw_raw((uint16_t *) v + 1, 24); /* ??? */
862 v ++;
863
864 #if 0
865 /* LCD settings */
866 ADD_TAG(0x6e06, 2);
867 stw_raw((uint16_t *) (v ++), 15); /* ??? */
868 #endif
869
870 /* I^2C (Menelaus) */
871 ADD_TAG(0x6e07, 4);
872 stl_raw(v ++, 0x00720000); /* ??? */
873
874 /* Unknown */
875 ADD_TAG(0x6e0b, 6);
876 stw_raw((uint16_t *) v + 0, 94); /* ??? */
877 stw_raw((uint16_t *) v + 1, 23); /* ??? */
878 stw_raw((uint16_t *) v + 2, 0); /* ??? */
879 v += 2;
880
881 /* OMAP gpio switch info */
882 ADD_TAG(0x6e0c, 80);
883 strcpy((void *) v, "bat_cover"); v += 3;
884 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
885 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
886 v += 2;
887 strcpy((void *) v, "cam_act"); v += 3;
888 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
889 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
890 v += 2;
891 strcpy((void *) v, "cam_turn"); v += 3;
892 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
893 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
894 v += 2;
895 strcpy((void *) v, "headphone"); v += 3;
896 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
897 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
898 v += 2;
899
900 /* Bluetooth */
901 ADD_TAG(0x6e0e, 12);
902 stl_raw(v ++, 0x5c623d01); /* ??? */
903 stl_raw(v ++, 0x00000201); /* ??? */
904 stl_raw(v ++, 0x00000000); /* ??? */
905
906 /* CX3110x WLAN settings */
907 ADD_TAG(0x6e0f, 8);
908 stl_raw(v ++, 0x00610025); /* ??? */
909 stl_raw(v ++, 0xffff0057); /* ??? */
910
911 /* MMC host settings */
912 ADD_TAG(0x6e10, 12);
913 stl_raw(v ++, 0xffff000f); /* ??? */
914 stl_raw(v ++, 0xffffffff); /* ??? */
915 stl_raw(v ++, 0x00000060); /* ??? */
916
917 /* OneNAND chip select */
918 ADD_TAG(0x6e11, 10);
919 stl_raw(v ++, 0x00000401); /* ??? */
920 stl_raw(v ++, 0x0002003a); /* ??? */
921 stl_raw(v ++, 0x00000002); /* ??? */
922
923 /* TEA5761 sensor settings */
924 ADD_TAG(0x6e12, 2);
925 stl_raw(v ++, 93); /* GPIO num ??? */
926
927 #if 0
928 /* Unknown tag */
929 ADD_TAG(6e09, 0);
930
931 /* Kernel UART / console */
932 ADD_TAG(6e12, 0);
933 #endif
934
935 /* End of the list */
936 stl_raw(p ++, 0x00000000);
937 stl_raw(p ++, 0x00000000);
938 }
939
940 /* This task is normally performed by the bootloader. If we're loading
941 * a kernel directly, we need to set up GPMC mappings ourselves. */
942 static void n800_gpmc_init(struct n800_s *s)
943 {
944 uint32_t config7 =
945 (0xf << 8) | /* MASKADDRESS */
946 (1 << 6) | /* CSVALID */
947 (4 << 0); /* BASEADDRESS */
948
949 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
950 (void *) &config7, sizeof(config7));
951 }
952
953 /* Setup sequence done by the bootloader */
954 static void n8x0_boot_init(void *opaque)
955 {
956 struct n800_s *s = (struct n800_s *) opaque;
957 uint32_t buf;
958
959 /* PRCM setup */
960 #define omap_writel(addr, val) \
961 buf = (val); \
962 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
963
964 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
965 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
966 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
967 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
968 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
969 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
970 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
971 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
972 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
973 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
974 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
975 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
976 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
977 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
978 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
979 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
980 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
981 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
982 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
983 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
984 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
985 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
986 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
987 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
988 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
989 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
990 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
991 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
992 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
993 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
994 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
995 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
996 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
997 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
998 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
999 (0x78 << 12) | (6 << 8));
1000 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1001
1002 /* GPMC setup */
1003 n800_gpmc_init(s);
1004
1005 /* Video setup */
1006 n800_dss_init(&s->blizzard);
1007
1008 /* CPU setup */
1009 s->cpu->env->regs[15] = s->cpu->env->boot_info->loader_start;
1010 s->cpu->env->GE = 0x5;
1011
1012 /* If the machine has a slided keyboard, open it */
1013 if (s->kbd)
1014 qemu_irq_raise(omap2_gpio_in_get(s->cpu->gpif, N810_SLIDE_GPIO)[0]);
1015 }
1016
1017 #define OMAP_TAG_NOKIA_BT 0x4e01
1018 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1019 #define OMAP_TAG_CBUS 0x4e03
1020 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1021
1022 static struct omap_gpiosw_info_s {
1023 const char *name;
1024 int line;
1025 int type;
1026 } n800_gpiosw_info[] = {
1027 {
1028 "bat_cover", N800_BAT_COVER_GPIO,
1029 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1030 }, {
1031 "cam_act", N800_CAM_ACT_GPIO,
1032 OMAP_GPIOSW_TYPE_ACTIVITY,
1033 }, {
1034 "cam_turn", N800_CAM_TURN_GPIO,
1035 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1036 }, {
1037 "headphone", N8X0_HEADPHONE_GPIO,
1038 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1039 },
1040 { 0 }
1041 }, n810_gpiosw_info[] = {
1042 {
1043 "gps_reset", N810_GPS_RESET_GPIO,
1044 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1045 }, {
1046 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1047 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1048 }, {
1049 "headphone", N8X0_HEADPHONE_GPIO,
1050 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1051 }, {
1052 "kb_lock", N810_KB_LOCK_GPIO,
1053 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1054 }, {
1055 "sleepx_led", N810_SLEEPX_LED_GPIO,
1056 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1057 }, {
1058 "slide", N810_SLIDE_GPIO,
1059 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1060 },
1061 { 0 }
1062 };
1063
1064 static struct omap_partition_info_s {
1065 uint32_t offset;
1066 uint32_t size;
1067 int mask;
1068 const char *name;
1069 } n800_part_info[] = {
1070 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1071 { 0x00020000, 0x00060000, 0x0, "config" },
1072 { 0x00080000, 0x00200000, 0x0, "kernel" },
1073 { 0x00280000, 0x00200000, 0x3, "initfs" },
1074 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1075
1076 { 0, 0, 0, 0 }
1077 }, n810_part_info[] = {
1078 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1079 { 0x00020000, 0x00060000, 0x0, "config" },
1080 { 0x00080000, 0x00220000, 0x0, "kernel" },
1081 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1082 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1083
1084 { 0, 0, 0, 0 }
1085 };
1086
1087 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1088
1089 static int n8x0_atag_setup(void *p, int model)
1090 {
1091 uint8_t *b;
1092 uint16_t *w;
1093 uint32_t *l;
1094 struct omap_gpiosw_info_s *gpiosw;
1095 struct omap_partition_info_s *partition;
1096 const char *tag;
1097
1098 w = p;
1099
1100 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1101 stw_raw(w ++, 4); /* u16 len */
1102 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1103 w ++;
1104
1105 #if 0
1106 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1107 stw_raw(w ++, 4); /* u16 len */
1108 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1109 stw_raw(w ++, 115200); /* u32 console_speed */
1110 #endif
1111
1112 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1113 stw_raw(w ++, 36); /* u16 len */
1114 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1115 w += 8;
1116 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1117 w += 8;
1118 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1119 stw_raw(w ++, 24); /* u8 data_lines */
1120
1121 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1122 stw_raw(w ++, 8); /* u16 len */
1123 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1124 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1125 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1126 w ++;
1127
1128 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1129 stw_raw(w ++, 4); /* u16 len */
1130 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1131 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1132
1133 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1134 for (; gpiosw->name; gpiosw ++) {
1135 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1136 stw_raw(w ++, 20); /* u16 len */
1137 strcpy((void *) w, gpiosw->name); /* char name[12] */
1138 w += 6;
1139 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1140 stw_raw(w ++, gpiosw->type);
1141 stw_raw(w ++, 0);
1142 stw_raw(w ++, 0);
1143 }
1144
1145 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1146 stw_raw(w ++, 12); /* u16 len */
1147 b = (void *) w;
1148 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1149 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1150 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1151 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1152 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1153 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1154 b += 6;
1155 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1156 w = (void *) b;
1157
1158 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1159 stw_raw(w ++, 8); /* u16 len */
1160 stw_raw(w ++, 0x25); /* u8 chip_type */
1161 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1162 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1163 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1164
1165 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1166 stw_raw(w ++, 16); /* u16 len */
1167 if (model == 810) {
1168 stw_raw(w ++, 0x23f); /* unsigned flags */
1169 stw_raw(w ++, -1); /* s16 power_pin */
1170 stw_raw(w ++, -1); /* s16 switch_pin */
1171 stw_raw(w ++, -1); /* s16 wp_pin */
1172 stw_raw(w ++, 0x240); /* unsigned flags */
1173 stw_raw(w ++, 0xc000); /* s16 power_pin */
1174 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1175 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1176 } else {
1177 stw_raw(w ++, 0xf); /* unsigned flags */
1178 stw_raw(w ++, -1); /* s16 power_pin */
1179 stw_raw(w ++, -1); /* s16 switch_pin */
1180 stw_raw(w ++, -1); /* s16 wp_pin */
1181 stw_raw(w ++, 0); /* unsigned flags */
1182 stw_raw(w ++, 0); /* s16 power_pin */
1183 stw_raw(w ++, 0); /* s16 switch_pin */
1184 stw_raw(w ++, 0); /* s16 wp_pin */
1185 }
1186
1187 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1188 stw_raw(w ++, 4); /* u16 len */
1189 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1190 w ++;
1191
1192 partition = (model == 810) ? n810_part_info : n800_part_info;
1193 for (; partition->name; partition ++) {
1194 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1195 stw_raw(w ++, 28); /* u16 len */
1196 strcpy((void *) w, partition->name); /* char name[16] */
1197 l = (void *) (w + 8);
1198 stl_raw(l ++, partition->size); /* unsigned int size */
1199 stl_raw(l ++, partition->offset); /* unsigned int offset */
1200 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1201 w = (void *) l;
1202 }
1203
1204 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1205 stw_raw(w ++, 12); /* u16 len */
1206 #if 0
1207 strcpy((void *) w, "por"); /* char reason_str[12] */
1208 strcpy((void *) w, "charger"); /* char reason_str[12] */
1209 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1210 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1211 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1212 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1213 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1214 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1215 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1216 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1217 #else
1218 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1219 #endif
1220 w += 6;
1221
1222 tag = (model == 810) ? "RX-44" : "RX-34";
1223 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1224 stw_raw(w ++, 24); /* u16 len */
1225 strcpy((void *) w, "product"); /* char component[12] */
1226 w += 6;
1227 strcpy((void *) w, tag); /* char version[12] */
1228 w += 6;
1229
1230 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1231 stw_raw(w ++, 24); /* u16 len */
1232 strcpy((void *) w, "hw-build"); /* char component[12] */
1233 w += 6;
1234 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
1235 w += 6;
1236
1237 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1238 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1239 stw_raw(w ++, 24); /* u16 len */
1240 strcpy((void *) w, "nolo"); /* char component[12] */
1241 w += 6;
1242 strcpy((void *) w, tag); /* char version[12] */
1243 w += 6;
1244
1245 return (void *) w - p;
1246 }
1247
1248 static int n800_atag_setup(struct arm_boot_info *info, void *p)
1249 {
1250 return n8x0_atag_setup(p, 800);
1251 }
1252
1253 static int n810_atag_setup(struct arm_boot_info *info, void *p)
1254 {
1255 return n8x0_atag_setup(p, 810);
1256 }
1257
1258 static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1259 DisplayState *ds, const char *kernel_filename,
1260 const char *kernel_cmdline, const char *initrd_filename,
1261 const char *cpu_model, struct arm_boot_info *binfo, int model)
1262 {
1263 struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
1264 int sdram_size = binfo->ram_size;
1265 int onenandram_size = 0x00010000;
1266
1267 if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) {
1268 fprintf(stderr, "This architecture uses %i bytes of memory\n",
1269 sdram_size + onenandram_size + OMAP242X_SRAM_SIZE);
1270 exit(1);
1271 }
1272
1273 s->cpu = omap2420_mpu_init(sdram_size, NULL, cpu_model);
1274
1275 /* Setup peripherals
1276 *
1277 * Believed external peripherals layout in the N810:
1278 * (spi bus 1)
1279 * tsc2005
1280 * lcd_mipid
1281 * (spi bus 2)
1282 * Conexant cx3110x (WLAN)
1283 * optional: pc2400m (WiMAX)
1284 * (i2c bus 0)
1285 * TLV320AIC33 (audio codec)
1286 * TCM825x (camera by Toshiba)
1287 * lp5521 (clever LEDs)
1288 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1289 * lm8323 (keypad, manf 00, rev 04)
1290 * (i2c bus 1)
1291 * tmp105 (temperature sensor, hwmon)
1292 * menelaus (pm)
1293 * (somewhere on i2c - maybe N800-only)
1294 * tea5761 (FM tuner)
1295 * (serial 0)
1296 * GPS
1297 * (some serial port)
1298 * csr41814 (Bluetooth)
1299 */
1300 n8x0_gpio_setup(s);
1301 n8x0_nand_setup(s);
1302 n8x0_i2c_setup(s);
1303 if (model == 800)
1304 n800_tsc_kbd_setup(s);
1305 else if (model == 810) {
1306 n810_tsc_setup(s);
1307 n810_kbd_setup(s);
1308 }
1309 n8x0_spi_setup(s);
1310 n8x0_dss_setup(s, ds);
1311 n8x0_cbus_setup(s);
1312 if (usb_enabled)
1313 n8x0_usb_setup(s);
1314
1315 /* Setup initial (reset) machine state */
1316
1317 /* Start at the OneNAND bootloader. */
1318 s->cpu->env->regs[15] = 0;
1319
1320 if (kernel_filename) {
1321 /* Or at the linux loader. */
1322 binfo->kernel_filename = kernel_filename;
1323 binfo->kernel_cmdline = kernel_cmdline;
1324 binfo->initrd_filename = initrd_filename;
1325 arm_load_kernel(s->cpu->env, binfo);
1326
1327 qemu_register_reset(n8x0_boot_init, s);
1328 n8x0_boot_init(s);
1329 }
1330
1331 if (option_rom[0] && (boot_device[0] == 'n' || !kernel_filename)) {
1332 /* No, wait, better start at the ROM. */
1333 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1334
1335 /* This is intended for loading the `secondary.bin' program from
1336 * Nokia images (the NOLO bootloader). The entry point seems
1337 * to be at OMAP2_Q2_BASE + 0x400000.
1338 *
1339 * The `2nd.bin' files contain some kind of earlier boot code and
1340 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1341 *
1342 * The code above is for loading the `zImage' file from Nokia
1343 * images. */
1344 printf("%i bytes of image loaded\n", load_image(option_rom[0],
1345 phys_ram_base + 0x400000));
1346
1347 n800_setup_nolo_tags(phys_ram_base + sdram_size);
1348 }
1349 /* FIXME: We shouldn't really be doing this here. The LCD controller
1350 will set the size once configured, so this just sets an initial
1351 size until the guest activates the display. */
1352 dpy_resize(ds, 800, 480);
1353 }
1354
1355 static struct arm_boot_info n800_binfo = {
1356 .loader_start = OMAP2_Q2_BASE,
1357 /* Actually two chips of 0x4000000 bytes each */
1358 .ram_size = 0x08000000,
1359 .board_id = 0x4f7,
1360 .atag_board = n800_atag_setup,
1361 };
1362
1363 static struct arm_boot_info n810_binfo = {
1364 .loader_start = OMAP2_Q2_BASE,
1365 /* Actually two chips of 0x4000000 bytes each */
1366 .ram_size = 0x08000000,
1367 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1368 * used by some older versions of the bootloader and 5555 is used
1369 * instead (including versions that shipped with many devices). */
1370 .board_id = 0x60c,
1371 .atag_board = n810_atag_setup,
1372 };
1373
1374 static void n800_init(ram_addr_t ram_size, int vga_ram_size,
1375 const char *boot_device, DisplayState *ds,
1376 const char *kernel_filename, const char *kernel_cmdline,
1377 const char *initrd_filename, const char *cpu_model)
1378 {
1379 return n8x0_init(ram_size, boot_device, ds,
1380 kernel_filename, kernel_cmdline, initrd_filename,
1381 cpu_model, &n800_binfo, 800);
1382 }
1383
1384 static void n810_init(ram_addr_t ram_size, int vga_ram_size,
1385 const char *boot_device, DisplayState *ds,
1386 const char *kernel_filename, const char *kernel_cmdline,
1387 const char *initrd_filename, const char *cpu_model)
1388 {
1389 return n8x0_init(ram_size, boot_device, ds,
1390 kernel_filename, kernel_cmdline, initrd_filename,
1391 cpu_model, &n810_binfo, 810);
1392 }
1393
1394 QEMUMachine n800_machine = {
1395 "n800",
1396 "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1397 n800_init,
1398 (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED,
1399 };
1400
1401 QEMUMachine n810_machine = {
1402 "n810",
1403 "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1404 n810_init,
1405 (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | RAMSIZE_FIXED,
1406 };
Samsung s3c2440 and arm920t support for the mini2440 dev board