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Support out-of-the-tree building of tests
[qemu/mini2440.git] / target-sh4 / translate.c
blob4614c8674b8497d8ecd5121f718f3352ea2dac0b
1 /*
2 * SH4 translation
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <assert.h>
26
27 #define DEBUG_DISAS
28 #define SH4_DEBUG_DISAS
29 //#define SH4_SINGLE_STEP
30
31 #include "cpu.h"
32 #include "exec-all.h"
33 #include "disas.h"
34 #include "helper.h"
35 #include "tcg-op.h"
36 #include "qemu-common.h"
37
38 typedef struct DisasContext {
39 struct TranslationBlock *tb;
40 target_ulong pc;
41 uint32_t sr;
42 uint32_t fpscr;
43 uint16_t opcode;
44 uint32_t flags;
45 int bstate;
46 int memidx;
47 uint32_t delayed_pc;
48 int singlestep_enabled;
49 } DisasContext;
50
51 #if defined(CONFIG_USER_ONLY)
52 #define IS_USER(ctx) 1
53 #else
54 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
55 #endif
56
57 enum {
58 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
59 * exception condition
60 */
61 BS_STOP = 1, /* We want to stop translation for any reason */
62 BS_BRANCH = 2, /* We reached a branch condition */
63 BS_EXCP = 3, /* We reached an exception condition */
64 };
65
66 /* global register indexes */
67 static TCGv cpu_env;
68 static TCGv cpu_gregs[24];
69 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
70 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
71 static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
72
73 /* internal register indexes */
74 static TCGv cpu_flags, cpu_delayed_pc;
75
76 #include "gen-icount.h"
77
78 static void sh4_translate_init(void)
79 {
80 int i;
81 static int done_init = 0;
82 static const char * const gregnames[24] = {
83 "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
84 "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
85 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
86 "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
87 "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
88 };
89
90 if (done_init)
91 return;
92
93 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
94
95 for (i = 0; i < 24; i++)
96 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
97 offsetof(CPUState, gregs[i]),
98 gregnames[i]);
99
100 cpu_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
101 offsetof(CPUState, pc), "PC");
102 cpu_sr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
103 offsetof(CPUState, sr), "SR");
104 cpu_ssr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
105 offsetof(CPUState, ssr), "SSR");
106 cpu_spc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
107 offsetof(CPUState, spc), "SPC");
108 cpu_gbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
109 offsetof(CPUState, gbr), "GBR");
110 cpu_vbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
111 offsetof(CPUState, vbr), "VBR");
112 cpu_sgr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
113 offsetof(CPUState, sgr), "SGR");
114 cpu_dbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
115 offsetof(CPUState, dbr), "DBR");
116 cpu_mach = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
117 offsetof(CPUState, mach), "MACH");
118 cpu_macl = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
119 offsetof(CPUState, macl), "MACL");
120 cpu_pr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
121 offsetof(CPUState, pr), "PR");
122 cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
123 offsetof(CPUState, fpscr), "FPSCR");
124 cpu_fpul = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
125 offsetof(CPUState, fpul), "FPUL");
126
127 cpu_flags = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
128 offsetof(CPUState, flags), "_flags_");
129 cpu_delayed_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
130 offsetof(CPUState, delayed_pc),
131 "_delayed_pc_");
132
133 /* register helpers */
134 #undef DEF_HELPER
135 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
136 #include "helper.h"
137
138 done_init = 1;
139 }
140
141 void cpu_dump_state(CPUState * env, FILE * f,
142 int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
143 int flags)
144 {
145 int i;
146 cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
147 env->pc, env->sr, env->pr, env->fpscr);
148 cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
149 env->spc, env->ssr, env->gbr, env->vbr);
150 cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
151 env->sgr, env->dbr, env->delayed_pc, env->fpul);
152 for (i = 0; i < 24; i += 4) {
153 cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
154 i, env->gregs[i], i + 1, env->gregs[i + 1],
155 i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
156 }
157 if (env->flags & DELAY_SLOT) {
158 cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
159 env->delayed_pc);
160 } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
161 cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
162 env->delayed_pc);
163 }
164 }
165
166 void cpu_sh4_reset(CPUSH4State * env)
167 {
168 #if defined(CONFIG_USER_ONLY)
169 env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */
170 #else
171 env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */
172 #endif
173 env->vbr = 0;
174 env->pc = 0xA0000000;
175 #if defined(CONFIG_USER_ONLY)
176 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
177 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
178 #else
179 env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
180 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
181 #endif
182 env->mmucr = 0;
183 }
184
185 typedef struct {
186 const char *name;
187 int id;
188 uint32_t pvr;
189 uint32_t prr;
190 uint32_t cvr;
191 } sh4_def_t;
192
193 static sh4_def_t sh4_defs[] = {
194 {
195 .name = "SH7750R",
196 .id = SH_CPU_SH7750R,
197 .pvr = 0x00050000,
198 .prr = 0x00000100,
199 .cvr = 0x00110000,
200 }, {
201 .name = "SH7751R",
202 .id = SH_CPU_SH7751R,
203 .pvr = 0x04050005,
204 .prr = 0x00000113,
205 .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
206 },
207 };
208
209 static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
210 {
211 int i;
212
213 if (strcasecmp(name, "any") == 0)
214 return &sh4_defs[0];
215
216 for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
217 if (strcasecmp(name, sh4_defs[i].name) == 0)
218 return &sh4_defs[i];
219
220 return NULL;
221 }
222
223 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
224 {
225 int i;
226
227 for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
228 (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
229 }
230
231 static int cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def)
232 {
233 env->pvr = def->pvr;
234 env->prr = def->prr;
235 env->cvr = def->cvr;
236 env->id = def->id;
237 }
238
239 CPUSH4State *cpu_sh4_init(const char *cpu_model)
240 {
241 CPUSH4State *env;
242 const sh4_def_t *def;
243
244 def = cpu_sh4_find_by_name(cpu_model);
245 if (!def)
246 return NULL;
247 env = qemu_mallocz(sizeof(CPUSH4State));
248 if (!env)
249 return NULL;
250 cpu_exec_init(env);
251 sh4_translate_init();
252 env->cpu_model_str = cpu_model;
253 cpu_sh4_reset(env);
254 cpu_sh4_register(env, def);
255 tlb_flush(env, 1);
256 return env;
257 }
258
259 static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
260 {
261 TranslationBlock *tb;
262 tb = ctx->tb;
263
264 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
265 !ctx->singlestep_enabled) {
266 /* Use a direct jump if in same page and singlestep not enabled */
267 tcg_gen_goto_tb(n);
268 tcg_gen_movi_i32(cpu_pc, dest);
269 tcg_gen_exit_tb((long) tb + n);
270 } else {
271 tcg_gen_movi_i32(cpu_pc, dest);
272 if (ctx->singlestep_enabled)
273 tcg_gen_helper_0_0(helper_debug);
274 tcg_gen_exit_tb(0);
275 }
276 }
277
278 static void gen_jump(DisasContext * ctx)
279 {
280 if (ctx->delayed_pc == (uint32_t) - 1) {
281 /* Target is not statically known, it comes necessarily from a
282 delayed jump as immediate jump are conditinal jumps */
283 tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
284 if (ctx->singlestep_enabled)
285 tcg_gen_helper_0_0(helper_debug);
286 tcg_gen_exit_tb(0);
287 } else {
288 gen_goto_tb(ctx, 0, ctx->delayed_pc);
289 }
290 }
291
292 static inline void gen_branch_slot(uint32_t delayed_pc, int t)
293 {
294 TCGv sr;
295 int label = gen_new_label();
296 tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
297 sr = tcg_temp_new(TCG_TYPE_I32);
298 tcg_gen_andi_i32(sr, cpu_sr, SR_T);
299 tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
300 tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
301 gen_set_label(label);
302 }
303
304 /* Immediate conditional jump (bt or bf) */
305 static void gen_conditional_jump(DisasContext * ctx,
306 target_ulong ift, target_ulong ifnott)
307 {
308 int l1;
309 TCGv sr;
310
311 l1 = gen_new_label();
312 sr = tcg_temp_new(TCG_TYPE_I32);
313 tcg_gen_andi_i32(sr, cpu_sr, SR_T);
314 tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);
315 gen_goto_tb(ctx, 0, ifnott);
316 gen_set_label(l1);
317 gen_goto_tb(ctx, 1, ift);
318 }
319
320 /* Delayed conditional jump (bt or bf) */
321 static void gen_delayed_conditional_jump(DisasContext * ctx)
322 {
323 int l1;
324 TCGv ds;
325
326 l1 = gen_new_label();
327 ds = tcg_temp_new(TCG_TYPE_I32);
328 tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
329 tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);
330 gen_goto_tb(ctx, 1, ctx->pc + 2);
331 gen_set_label(l1);
332 tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
333 gen_jump(ctx);
334 }
335
336 static inline void gen_set_t(void)
337 {
338 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
339 }
340
341 static inline void gen_clr_t(void)
342 {
343 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
344 }
345
346 static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
347 {
348 int label1 = gen_new_label();
349 int label2 = gen_new_label();
350 tcg_gen_brcond_i32(cond, t1, t0, label1);
351 gen_clr_t();
352 tcg_gen_br(label2);
353 gen_set_label(label1);
354 gen_set_t();
355 gen_set_label(label2);
356 }
357
358 static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
359 {
360 int label1 = gen_new_label();
361 int label2 = gen_new_label();
362 tcg_gen_brcondi_i32(cond, t0, imm, label1);
363 gen_clr_t();
364 tcg_gen_br(label2);
365 gen_set_label(label1);
366 gen_set_t();
367 gen_set_label(label2);
368 }
369
370 static inline void gen_store_flags(uint32_t flags)
371 {
372 tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
373 tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);
374 }
375
376 static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
377 {
378 TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
379
380 p0 &= 0x1f;
381 p1 &= 0x1f;
382
383 tcg_gen_andi_i32(tmp, t1, (1 << p1));
384 tcg_gen_andi_i32(t0, t0, ~(1 << p0));
385 if (p0 < p1)
386 tcg_gen_shri_i32(tmp, tmp, p1 - p0);
387 else if (p0 > p1)
388 tcg_gen_shli_i32(tmp, tmp, p0 - p1);
389 tcg_gen_or_i32(t0, t0, tmp);
390
391 tcg_temp_free(tmp);
392 }
393
394
395 static inline void gen_load_fpr32(TCGv t, int reg)
396 {
397 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
398 }
399
400 static inline void gen_load_fpr64(TCGv t, int reg)
401 {
402 TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32);
403 TCGv tmp2 = tcg_temp_new(TCG_TYPE_I32);
404
405 tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg]));
406 tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1]));
407 tcg_gen_concat_i32_i64(t, tmp2, tmp1);
408 tcg_temp_free(tmp1);
409 tcg_temp_free(tmp2);
410 }
411
412 static inline void gen_store_fpr32(TCGv t, int reg)
413 {
414 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
415 }
416
417 static inline void gen_store_fpr64 (TCGv t, int reg)
418 {
419 TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
420
421 tcg_gen_trunc_i64_i32(tmp, t);
422 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1]));
423 tcg_gen_shri_i64(t, t, 32);
424 tcg_gen_trunc_i64_i32(tmp, t);
425 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg]));
426 tcg_temp_free(tmp);
427 }
428
429 #define B3_0 (ctx->opcode & 0xf)
430 #define B6_4 ((ctx->opcode >> 4) & 0x7)
431 #define B7_4 ((ctx->opcode >> 4) & 0xf)
432 #define B7_0 (ctx->opcode & 0xff)
433 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
434 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
435 (ctx->opcode & 0xfff))
436 #define B11_8 ((ctx->opcode >> 8) & 0xf)
437 #define B15_12 ((ctx->opcode >> 12) & 0xf)
438
439 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
440 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
441
442 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
443 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
444
445 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
446 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
447 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
448 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
449
450 #define CHECK_NOT_DELAY_SLOT \
451 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
452 {tcg_gen_helper_0_0(helper_raise_slot_illegal_instruction); ctx->bstate = BS_EXCP; \
453 return;}
454
455 #define CHECK_PRIVILEGED \
456 if (IS_USER(ctx)) { \
457 tcg_gen_helper_0_0(helper_raise_illegal_instruction); \
458 ctx->bstate = BS_EXCP; \
459 return; \
460 }
461
462 void _decode_opc(DisasContext * ctx)
463 {
464 #if 0
465 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
466 #endif
467 switch (ctx->opcode) {
468 case 0x0019: /* div0u */
469 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
470 return;
471 case 0x000b: /* rts */
472 CHECK_NOT_DELAY_SLOT
473 tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
474 ctx->flags |= DELAY_SLOT;
475 ctx->delayed_pc = (uint32_t) - 1;
476 return;
477 case 0x0028: /* clrmac */
478 tcg_gen_movi_i32(cpu_mach, 0);
479 tcg_gen_movi_i32(cpu_macl, 0);
480 return;
481 case 0x0048: /* clrs */
482 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
483 return;
484 case 0x0008: /* clrt */
485 gen_clr_t();
486 return;
487 case 0x0038: /* ldtlb */
488 CHECK_PRIVILEGED
489 tcg_gen_helper_0_0(helper_ldtlb);
490 return;
491 case 0x002b: /* rte */
492 CHECK_PRIVILEGED
493 CHECK_NOT_DELAY_SLOT
494 tcg_gen_mov_i32(cpu_sr, cpu_ssr);
495 tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
496 ctx->flags |= DELAY_SLOT;
497 ctx->delayed_pc = (uint32_t) - 1;
498 return;
499 case 0x0058: /* sets */
500 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
501 return;
502 case 0x0018: /* sett */
503 gen_set_t();
504 return;
505 case 0xfbfd: /* frchg */
506 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
507 ctx->bstate = BS_STOP;
508 return;
509 case 0xf3fd: /* fschg */
510 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
511 ctx->bstate = BS_STOP;
512 return;
513 case 0x0009: /* nop */
514 return;
515 case 0x001b: /* sleep */
516 CHECK_PRIVILEGED
517 tcg_gen_helper_0_1(helper_sleep, tcg_const_i32(ctx->pc + 2));
518 return;
519 }
520
521 switch (ctx->opcode & 0xf000) {
522 case 0x1000: /* mov.l Rm,@(disp,Rn) */
523 {
524 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
525 tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
526 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
527 tcg_temp_free(addr);
528 }
529 return;
530 case 0x5000: /* mov.l @(disp,Rm),Rn */
531 {
532 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
533 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
534 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
535 tcg_temp_free(addr);
536 }
537 return;
538 case 0xe000: /* mov #imm,Rn */
539 tcg_gen_movi_i32(REG(B11_8), B7_0s);
540 return;
541 case 0x9000: /* mov.w @(disp,PC),Rn */
542 {
543 TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
544 tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
545 tcg_temp_free(addr);
546 }
547 return;
548 case 0xd000: /* mov.l @(disp,PC),Rn */
549 {
550 TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
551 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
552 tcg_temp_free(addr);
553 }
554 return;
555 case 0x7000: /* add #imm,Rn */
556 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
557 return;
558 case 0xa000: /* bra disp */
559 CHECK_NOT_DELAY_SLOT
560 ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
561 tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
562 ctx->flags |= DELAY_SLOT;
563 return;
564 case 0xb000: /* bsr disp */
565 CHECK_NOT_DELAY_SLOT
566 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
567 ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
568 tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
569 ctx->flags |= DELAY_SLOT;
570 return;
571 }
572
573 switch (ctx->opcode & 0xf00f) {
574 case 0x6003: /* mov Rm,Rn */
575 tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
576 return;
577 case 0x2000: /* mov.b Rm,@Rn */
578 tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
579 return;
580 case 0x2001: /* mov.w Rm,@Rn */
581 tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
582 return;
583 case 0x2002: /* mov.l Rm,@Rn */
584 tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
585 return;
586 case 0x6000: /* mov.b @Rm,Rn */
587 tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
588 return;
589 case 0x6001: /* mov.w @Rm,Rn */
590 tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
591 return;
592 case 0x6002: /* mov.l @Rm,Rn */
593 tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
594 return;
595 case 0x2004: /* mov.b Rm,@-Rn */
596 {
597 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
598 tcg_gen_subi_i32(addr, REG(B11_8), 1);
599 tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
600 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */
601 tcg_temp_free(addr);
602 }
603 return;
604 case 0x2005: /* mov.w Rm,@-Rn */
605 {
606 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
607 tcg_gen_subi_i32(addr, REG(B11_8), 2);
608 tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
609 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
610 tcg_temp_free(addr);
611 }
612 return;
613 case 0x2006: /* mov.l Rm,@-Rn */
614 {
615 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
616 tcg_gen_subi_i32(addr, REG(B11_8), 4);
617 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
618 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
619 }
620 return;
621 case 0x6004: /* mov.b @Rm+,Rn */
622 tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
623 if ( B11_8 != B7_4 )
624 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
625 return;
626 case 0x6005: /* mov.w @Rm+,Rn */
627 tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
628 if ( B11_8 != B7_4 )
629 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
630 return;
631 case 0x6006: /* mov.l @Rm+,Rn */
632 tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
633 if ( B11_8 != B7_4 )
634 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
635 return;
636 case 0x0004: /* mov.b Rm,@(R0,Rn) */
637 {
638 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
639 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
640 tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
641 tcg_temp_free(addr);
642 }
643 return;
644 case 0x0005: /* mov.w Rm,@(R0,Rn) */
645 {
646 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
647 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
648 tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
649 tcg_temp_free(addr);
650 }
651 return;
652 case 0x0006: /* mov.l Rm,@(R0,Rn) */
653 {
654 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
655 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
656 tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
657 tcg_temp_free(addr);
658 }
659 return;
660 case 0x000c: /* mov.b @(R0,Rm),Rn */
661 {
662 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
663 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
664 tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
665 tcg_temp_free(addr);
666 }
667 return;
668 case 0x000d: /* mov.w @(R0,Rm),Rn */
669 {
670 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
671 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
672 tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
673 tcg_temp_free(addr);
674 }
675 return;
676 case 0x000e: /* mov.l @(R0,Rm),Rn */
677 {
678 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
679 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
680 tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
681 tcg_temp_free(addr);
682 }
683 return;
684 case 0x6008: /* swap.b Rm,Rn */
685 {
686 TCGv high, low;
687 high = tcg_temp_new(TCG_TYPE_I32);
688 tcg_gen_ext8u_i32(high, REG(B7_4));
689 tcg_gen_shli_i32(high, high, 8);
690 low = tcg_temp_new(TCG_TYPE_I32);
691 tcg_gen_shri_i32(low, REG(B7_4), 8);
692 tcg_gen_ext8u_i32(low, low);
693 tcg_gen_or_i32(REG(B11_8), high, low);
694 tcg_temp_free(low);
695 tcg_temp_free(high);
696 }
697 return;
698 case 0x6009: /* swap.w Rm,Rn */
699 {
700 TCGv high, low;
701 high = tcg_temp_new(TCG_TYPE_I32);
702 tcg_gen_ext16u_i32(high, REG(B7_4));
703 tcg_gen_shli_i32(high, high, 16);
704 low = tcg_temp_new(TCG_TYPE_I32);
705 tcg_gen_shri_i32(low, REG(B7_4), 16);
706 tcg_gen_ext16u_i32(low, low);
707 tcg_gen_or_i32(REG(B11_8), high, low);
708 tcg_temp_free(low);
709 tcg_temp_free(high);
710 }
711 return;
712 case 0x200d: /* xtrct Rm,Rn */
713 {
714 TCGv high, low;
715 high = tcg_temp_new(TCG_TYPE_I32);
716 tcg_gen_ext16u_i32(high, REG(B7_4));
717 tcg_gen_shli_i32(high, high, 16);
718 low = tcg_temp_new(TCG_TYPE_I32);
719 tcg_gen_shri_i32(low, REG(B11_8), 16);
720 tcg_gen_ext16u_i32(low, low);
721 tcg_gen_or_i32(REG(B11_8), high, low);
722 tcg_temp_free(low);
723 tcg_temp_free(high);
724 }
725 return;
726 case 0x300c: /* add Rm,Rn */
727 tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
728 return;
729 case 0x300e: /* addc Rm,Rn */
730 tcg_gen_helper_1_2(helper_addc, REG(B11_8), REG(B7_4), REG(B11_8));
731 return;
732 case 0x300f: /* addv Rm,Rn */
733 tcg_gen_helper_1_2(helper_addv, REG(B11_8), REG(B7_4), REG(B11_8));
734 return;
735 case 0x2009: /* and Rm,Rn */
736 tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
737 return;
738 case 0x3000: /* cmp/eq Rm,Rn */
739 gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));
740 return;
741 case 0x3003: /* cmp/ge Rm,Rn */
742 gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));
743 return;
744 case 0x3007: /* cmp/gt Rm,Rn */
745 gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));
746 return;
747 case 0x3006: /* cmp/hi Rm,Rn */
748 gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));
749 return;
750 case 0x3002: /* cmp/hs Rm,Rn */
751 gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));
752 return;
753 case 0x200c: /* cmp/str Rm,Rn */
754 {
755 int label1 = gen_new_label();
756 int label2 = gen_new_label();
757 TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32);
758 TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32);
759 tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
760 tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
761 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
762 tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
763 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
764 tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
765 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
766 tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
767 tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
768 tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
769 tcg_gen_br(label2);
770 gen_set_label(label1);
771 tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
772 gen_set_label(label2);
773 tcg_temp_free(cmp2);
774 tcg_temp_free(cmp1);
775 }
776 return;
777 case 0x2007: /* div0s Rm,Rn */
778 {
779 gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */
780 gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */
781 TCGv val = tcg_temp_new(TCG_TYPE_I32);
782 tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));
783 gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */
784 tcg_temp_free(val);
785 }
786 return;
787 case 0x3004: /* div1 Rm,Rn */
788 tcg_gen_helper_1_2(helper_div1, REG(B11_8), REG(B7_4), REG(B11_8));
789 return;
790 case 0x300d: /* dmuls.l Rm,Rn */
791 {
792 TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
793 TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
794
795 tcg_gen_ext_i32_i64(tmp1, REG(B7_4));
796 tcg_gen_ext_i32_i64(tmp2, REG(B11_8));
797 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
798 tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
799 tcg_gen_shri_i64(tmp1, tmp1, 32);
800 tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
801
802 tcg_temp_free(tmp2);
803 tcg_temp_free(tmp1);
804 }
805 return;
806 case 0x3005: /* dmulu.l Rm,Rn */
807 {
808 TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
809 TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
810
811 tcg_gen_extu_i32_i64(tmp1, REG(B7_4));
812 tcg_gen_extu_i32_i64(tmp2, REG(B11_8));
813 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
814 tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
815 tcg_gen_shri_i64(tmp1, tmp1, 32);
816 tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
817
818 tcg_temp_free(tmp2);
819 tcg_temp_free(tmp1);
820 }
821 return;
822 case 0x600e: /* exts.b Rm,Rn */
823 tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));
824 return;
825 case 0x600f: /* exts.w Rm,Rn */
826 tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));
827 return;
828 case 0x600c: /* extu.b Rm,Rn */
829 tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));
830 return;
831 case 0x600d: /* extu.w Rm,Rn */
832 tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));
833 return;
834 case 0x000f: /* mac.l @Rm+,@Rn+ */
835 {
836 TCGv arg0, arg1;
837 arg0 = tcg_temp_new(TCG_TYPE_I32);
838 tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
839 arg1 = tcg_temp_new(TCG_TYPE_I32);
840 tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
841 tcg_gen_helper_0_2(helper_macl, arg0, arg1);
842 tcg_temp_free(arg1);
843 tcg_temp_free(arg0);
844 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
845 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
846 }
847 return;
848 case 0x400f: /* mac.w @Rm+,@Rn+ */
849 {
850 TCGv arg0, arg1;
851 arg0 = tcg_temp_new(TCG_TYPE_I32);
852 tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
853 arg1 = tcg_temp_new(TCG_TYPE_I32);
854 tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
855 tcg_gen_helper_0_2(helper_macw, arg0, arg1);
856 tcg_temp_free(arg1);
857 tcg_temp_free(arg0);
858 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
859 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
860 }
861 return;
862 case 0x0007: /* mul.l Rm,Rn */
863 tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
864 return;
865 case 0x200f: /* muls.w Rm,Rn */
866 {
867 TCGv arg0, arg1;
868 arg0 = tcg_temp_new(TCG_TYPE_I32);
869 tcg_gen_ext16s_i32(arg0, REG(B7_4));
870 arg1 = tcg_temp_new(TCG_TYPE_I32);
871 tcg_gen_ext16s_i32(arg1, REG(B11_8));
872 tcg_gen_mul_i32(cpu_macl, arg0, arg1);
873 tcg_temp_free(arg1);
874 tcg_temp_free(arg0);
875 }
876 return;
877 case 0x200e: /* mulu.w Rm,Rn */
878 {
879 TCGv arg0, arg1;
880 arg0 = tcg_temp_new(TCG_TYPE_I32);
881 tcg_gen_ext16u_i32(arg0, REG(B7_4));
882 arg1 = tcg_temp_new(TCG_TYPE_I32);
883 tcg_gen_ext16u_i32(arg1, REG(B11_8));
884 tcg_gen_mul_i32(cpu_macl, arg0, arg1);
885 tcg_temp_free(arg1);
886 tcg_temp_free(arg0);
887 }
888 return;
889 case 0x600b: /* neg Rm,Rn */
890 tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
891 return;
892 case 0x600a: /* negc Rm,Rn */
893 tcg_gen_helper_1_1(helper_negc, REG(B11_8), REG(B7_4));
894 return;
895 case 0x6007: /* not Rm,Rn */
896 tcg_gen_not_i32(REG(B11_8), REG(B7_4));
897 return;
898 case 0x200b: /* or Rm,Rn */
899 tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
900 return;
901 case 0x400c: /* shad Rm,Rn */
902 {
903 int label1 = gen_new_label();
904 int label2 = gen_new_label();
905 int label3 = gen_new_label();
906 int label4 = gen_new_label();
907 TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
908 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
909 /* Rm positive, shift to the left */
910 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
911 tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
912 tcg_gen_br(label4);
913 /* Rm negative, shift to the right */
914 gen_set_label(label1);
915 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
916 tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
917 tcg_gen_not_i32(shift, REG(B7_4));
918 tcg_gen_andi_i32(shift, shift, 0x1f);
919 tcg_gen_addi_i32(shift, shift, 1);
920 tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
921 tcg_gen_br(label4);
922 /* Rm = -32 */
923 gen_set_label(label2);
924 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
925 tcg_gen_movi_i32(REG(B11_8), 0);
926 tcg_gen_br(label4);
927 gen_set_label(label3);
928 tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
929 gen_set_label(label4);
930 tcg_temp_free(shift);
931 }
932 return;
933 case 0x400d: /* shld Rm,Rn */
934 {
935 int label1 = gen_new_label();
936 int label2 = gen_new_label();
937 int label3 = gen_new_label();
938 TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
939 tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
940 /* Rm positive, shift to the left */
941 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
942 tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
943 tcg_gen_br(label3);
944 /* Rm negative, shift to the right */
945 gen_set_label(label1);
946 tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
947 tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
948 tcg_gen_not_i32(shift, REG(B7_4));
949 tcg_gen_andi_i32(shift, shift, 0x1f);
950 tcg_gen_addi_i32(shift, shift, 1);
951 tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
952 tcg_gen_br(label3);
953 /* Rm = -32 */
954 gen_set_label(label2);
955 tcg_gen_movi_i32(REG(B11_8), 0);
956 gen_set_label(label3);
957 tcg_temp_free(shift);
958 }
959 return;
960 case 0x3008: /* sub Rm,Rn */
961 tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
962 return;
963 case 0x300a: /* subc Rm,Rn */
964 tcg_gen_helper_1_2(helper_subc, REG(B11_8), REG(B7_4), REG(B11_8));
965 return;
966 case 0x300b: /* subv Rm,Rn */
967 tcg_gen_helper_1_2(helper_subv, REG(B11_8), REG(B7_4), REG(B11_8));
968 return;
969 case 0x2008: /* tst Rm,Rn */
970 {
971 TCGv val = tcg_temp_new(TCG_TYPE_I32);
972 tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
973 gen_cmp_imm(TCG_COND_EQ, val, 0);
974 tcg_temp_free(val);
975 }
976 return;
977 case 0x200a: /* xor Rm,Rn */
978 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
979 return;
980 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
981 if (ctx->fpscr & FPSCR_SZ) {
982 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
983 gen_load_fpr64(fp, XREG(B7_4));
984 gen_store_fpr64(fp, XREG(B11_8));
985 tcg_temp_free(fp);
986 } else {
987 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
988 gen_load_fpr32(fp, FREG(B7_4));
989 gen_store_fpr32(fp, FREG(B11_8));
990 tcg_temp_free(fp);
991 }
992 return;
993 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
994 if (ctx->fpscr & FPSCR_SZ) {
995 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
996 gen_load_fpr64(fp, XREG(B7_4));
997 tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
998 tcg_temp_free(fp);
999 } else {
1000 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1001 gen_load_fpr32(fp, FREG(B7_4));
1002 tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx);
1003 tcg_temp_free(fp);
1004 }
1005 return;
1006 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1007 if (ctx->fpscr & FPSCR_SZ) {
1008 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1009 tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
1010 gen_store_fpr64(fp, XREG(B11_8));
1011 tcg_temp_free(fp);
1012 } else {
1013 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1014 tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
1015 gen_store_fpr32(fp, FREG(B11_8));
1016 tcg_temp_free(fp);
1017 }
1018 return;
1019 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1020 if (ctx->fpscr & FPSCR_SZ) {
1021 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1022 tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
1023 gen_store_fpr64(fp, XREG(B11_8));
1024 tcg_temp_free(fp);
1025 tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
1026 } else {
1027 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1028 tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
1029 gen_store_fpr32(fp, FREG(B11_8));
1030 tcg_temp_free(fp);
1031 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
1032 }
1033 return;
1034 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1035 if (ctx->fpscr & FPSCR_SZ) {
1036 TCGv addr, fp;
1037 addr = tcg_temp_new(TCG_TYPE_I32);
1038 tcg_gen_subi_i32(addr, REG(B11_8), 8);
1039 fp = tcg_temp_new(TCG_TYPE_I64);
1040 gen_load_fpr64(fp, XREG(B7_4));
1041 tcg_gen_qemu_st64(fp, addr, ctx->memidx);
1042 tcg_temp_free(fp);
1043 tcg_temp_free(addr);
1044 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
1045 } else {
1046 TCGv addr, fp;
1047 addr = tcg_temp_new(TCG_TYPE_I32);
1048 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1049 fp = tcg_temp_new(TCG_TYPE_I32);
1050 gen_load_fpr32(fp, FREG(B7_4));
1051 tcg_gen_qemu_st32(fp, addr, ctx->memidx);
1052 tcg_temp_free(fp);
1053 tcg_temp_free(addr);
1054 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1055 }
1056 return;
1057 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1058 {
1059 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1060 tcg_gen_add_i32(addr, REG(B7_4), REG(0));
1061 if (ctx->fpscr & FPSCR_SZ) {
1062 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1063 tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
1064 gen_store_fpr64(fp, XREG(B11_8));
1065 tcg_temp_free(fp);
1066 } else {
1067 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1068 tcg_gen_qemu_ld32u(fp, addr, ctx->memidx);
1069 gen_store_fpr32(fp, FREG(B11_8));
1070 tcg_temp_free(fp);
1071 }
1072 tcg_temp_free(addr);
1073 }
1074 return;
1075 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1076 {
1077 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1078 tcg_gen_add_i32(addr, REG(B11_8), REG(0));
1079 if (ctx->fpscr & FPSCR_SZ) {
1080 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1081 gen_load_fpr64(fp, XREG(B7_4));
1082 tcg_gen_qemu_st64(fp, addr, ctx->memidx);
1083 tcg_temp_free(fp);
1084 } else {
1085 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1086 gen_load_fpr32(fp, FREG(B7_4));
1087 tcg_gen_qemu_st32(fp, addr, ctx->memidx);
1088 tcg_temp_free(fp);
1089 }
1090 tcg_temp_free(addr);
1091 }
1092 return;
1093 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1094 case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1095 case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1096 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1097 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1098 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1099 {
1100 TCGv fp0, fp1;
1101
1102 if (ctx->fpscr & FPSCR_PR) {
1103 if (ctx->opcode & 0x0110)
1104 break; /* illegal instruction */
1105 fp0 = tcg_temp_new(TCG_TYPE_I64);
1106 fp1 = tcg_temp_new(TCG_TYPE_I64);
1107 gen_load_fpr64(fp0, DREG(B11_8));
1108 gen_load_fpr64(fp1, DREG(B7_4));
1109 }
1110 else {
1111 fp0 = tcg_temp_new(TCG_TYPE_I32);
1112 fp1 = tcg_temp_new(TCG_TYPE_I32);
1113 gen_load_fpr32(fp0, FREG(B11_8));
1114 gen_load_fpr32(fp1, FREG(B7_4));
1115 }
1116
1117 switch (ctx->opcode & 0xf00f) {
1118 case 0xf000: /* fadd Rm,Rn */
1119 if (ctx->fpscr & FPSCR_PR)
1120 tcg_gen_helper_1_2(helper_fadd_DT, fp0, fp0, fp1);
1121 else
1122 tcg_gen_helper_1_2(helper_fadd_FT, fp0, fp0, fp1);
1123 break;
1124 case 0xf001: /* fsub Rm,Rn */
1125 if (ctx->fpscr & FPSCR_PR)
1126 tcg_gen_helper_1_2(helper_fsub_DT, fp0, fp0, fp1);
1127 else
1128 tcg_gen_helper_1_2(helper_fsub_FT, fp0, fp0, fp1);
1129 break;
1130 case 0xf002: /* fmul Rm,Rn */
1131 if (ctx->fpscr & FPSCR_PR)
1132 tcg_gen_helper_1_2(helper_fmul_DT, fp0, fp0, fp1);
1133 else
1134 tcg_gen_helper_1_2(helper_fmul_FT, fp0, fp0, fp1);
1135 break;
1136 case 0xf003: /* fdiv Rm,Rn */
1137 if (ctx->fpscr & FPSCR_PR)
1138 tcg_gen_helper_1_2(helper_fdiv_DT, fp0, fp0, fp1);
1139 else
1140 tcg_gen_helper_1_2(helper_fdiv_FT, fp0, fp0, fp1);
1141 break;
1142 case 0xf004: /* fcmp/eq Rm,Rn */
1143 if (ctx->fpscr & FPSCR_PR)
1144 tcg_gen_helper_0_2(helper_fcmp_eq_DT, fp0, fp1);
1145 else
1146 tcg_gen_helper_0_2(helper_fcmp_eq_FT, fp0, fp1);
1147 return;
1148 case 0xf005: /* fcmp/gt Rm,Rn */
1149 if (ctx->fpscr & FPSCR_PR)
1150 tcg_gen_helper_0_2(helper_fcmp_gt_DT, fp0, fp1);
1151 else
1152 tcg_gen_helper_0_2(helper_fcmp_gt_FT, fp0, fp1);
1153 return;
1154 }
1155
1156 if (ctx->fpscr & FPSCR_PR) {
1157 gen_store_fpr64(fp0, DREG(B11_8));
1158 }
1159 else {
1160 gen_store_fpr32(fp0, FREG(B11_8));
1161 }
1162 tcg_temp_free(fp1);
1163 tcg_temp_free(fp0);
1164 }
1165 return;
1166 }
1167
1168 switch (ctx->opcode & 0xff00) {
1169 case 0xc900: /* and #imm,R0 */
1170 tcg_gen_andi_i32(REG(0), REG(0), B7_0);
1171 return;
1172 case 0xcd00: /* and.b #imm,@(R0,GBR) */
1173 {
1174 TCGv addr, val;
1175 addr = tcg_temp_new(TCG_TYPE_I32);
1176 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1177 val = tcg_temp_new(TCG_TYPE_I32);
1178 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1179 tcg_gen_andi_i32(val, val, B7_0);
1180 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1181 tcg_temp_free(val);
1182 tcg_temp_free(addr);
1183 }
1184 return;
1185 case 0x8b00: /* bf label */
1186 CHECK_NOT_DELAY_SLOT
1187 gen_conditional_jump(ctx, ctx->pc + 2,
1188 ctx->pc + 4 + B7_0s * 2);
1189 ctx->bstate = BS_BRANCH;
1190 return;
1191 case 0x8f00: /* bf/s label */
1192 CHECK_NOT_DELAY_SLOT
1193 gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);
1194 ctx->flags |= DELAY_SLOT_CONDITIONAL;
1195 return;
1196 case 0x8900: /* bt label */
1197 CHECK_NOT_DELAY_SLOT
1198 gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
1199 ctx->pc + 2);
1200 ctx->bstate = BS_BRANCH;
1201 return;
1202 case 0x8d00: /* bt/s label */
1203 CHECK_NOT_DELAY_SLOT
1204 gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);
1205 ctx->flags |= DELAY_SLOT_CONDITIONAL;
1206 return;
1207 case 0x8800: /* cmp/eq #imm,R0 */
1208 gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
1209 return;
1210 case 0xc400: /* mov.b @(disp,GBR),R0 */
1211 {
1212 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1213 tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1214 tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1215 tcg_temp_free(addr);
1216 }
1217 return;
1218 case 0xc500: /* mov.w @(disp,GBR),R0 */
1219 {
1220 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1221 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1222 tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1223 tcg_temp_free(addr);
1224 }
1225 return;
1226 case 0xc600: /* mov.l @(disp,GBR),R0 */
1227 {
1228 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1229 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1230 tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
1231 tcg_temp_free(addr);
1232 }
1233 return;
1234 case 0xc000: /* mov.b R0,@(disp,GBR) */
1235 {
1236 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1237 tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1238 tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1239 tcg_temp_free(addr);
1240 }
1241 return;
1242 case 0xc100: /* mov.w R0,@(disp,GBR) */
1243 {
1244 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1245 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1246 tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1247 tcg_temp_free(addr);
1248 }
1249 return;
1250 case 0xc200: /* mov.l R0,@(disp,GBR) */
1251 {
1252 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1253 tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1254 tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
1255 tcg_temp_free(addr);
1256 }
1257 return;
1258 case 0x8000: /* mov.b R0,@(disp,Rn) */
1259 {
1260 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1261 tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1262 tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1263 tcg_temp_free(addr);
1264 }
1265 return;
1266 case 0x8100: /* mov.w R0,@(disp,Rn) */
1267 {
1268 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1269 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1270 tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1271 tcg_temp_free(addr);
1272 }
1273 return;
1274 case 0x8400: /* mov.b @(disp,Rn),R0 */
1275 {
1276 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1277 tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1278 tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1279 tcg_temp_free(addr);
1280 }
1281 return;
1282 case 0x8500: /* mov.w @(disp,Rn),R0 */
1283 {
1284 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1285 tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1286 tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1287 tcg_temp_free(addr);
1288 }
1289 return;
1290 case 0xc700: /* mova @(disp,PC),R0 */
1291 tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
1292 return;
1293 case 0xcb00: /* or #imm,R0 */
1294 tcg_gen_ori_i32(REG(0), REG(0), B7_0);
1295 return;
1296 case 0xcf00: /* or.b #imm,@(R0,GBR) */
1297 {
1298 TCGv addr, val;
1299 addr = tcg_temp_new(TCG_TYPE_I32);
1300 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1301 val = tcg_temp_new(TCG_TYPE_I32);
1302 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1303 tcg_gen_ori_i32(val, val, B7_0);
1304 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1305 tcg_temp_free(val);
1306 tcg_temp_free(addr);
1307 }
1308 return;
1309 case 0xc300: /* trapa #imm */
1310 {
1311 TCGv imm;
1312 CHECK_NOT_DELAY_SLOT
1313 tcg_gen_movi_i32(cpu_pc, ctx->pc);
1314 imm = tcg_const_i32(B7_0);
1315 tcg_gen_helper_0_1(helper_trapa, imm);
1316 tcg_temp_free(imm);
1317 ctx->bstate = BS_BRANCH;
1318 }
1319 return;
1320 case 0xc800: /* tst #imm,R0 */
1321 {
1322 TCGv val = tcg_temp_new(TCG_TYPE_I32);
1323 tcg_gen_andi_i32(val, REG(0), B7_0);
1324 gen_cmp_imm(TCG_COND_EQ, val, 0);
1325 tcg_temp_free(val);
1326 }
1327 return;
1328 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
1329 {
1330 TCGv val = tcg_temp_new(TCG_TYPE_I32);
1331 tcg_gen_add_i32(val, REG(0), cpu_gbr);
1332 tcg_gen_qemu_ld8u(val, val, ctx->memidx);
1333 tcg_gen_andi_i32(val, val, B7_0);
1334 gen_cmp_imm(TCG_COND_EQ, val, 0);
1335 tcg_temp_free(val);
1336 }
1337 return;
1338 case 0xca00: /* xor #imm,R0 */
1339 tcg_gen_xori_i32(REG(0), REG(0), B7_0);
1340 return;
1341 case 0xce00: /* xor.b #imm,@(R0,GBR) */
1342 {
1343 TCGv addr, val;
1344 addr = tcg_temp_new(TCG_TYPE_I32);
1345 tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1346 val = tcg_temp_new(TCG_TYPE_I32);
1347 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1348 tcg_gen_xori_i32(val, val, B7_0);
1349 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1350 tcg_temp_free(val);
1351 tcg_temp_free(addr);
1352 }
1353 return;
1354 }
1355
1356 switch (ctx->opcode & 0xf08f) {
1357 case 0x408e: /* ldc Rm,Rn_BANK */
1358 CHECK_PRIVILEGED
1359 tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8));
1360 return;
1361 case 0x4087: /* ldc.l @Rm+,Rn_BANK */
1362 CHECK_PRIVILEGED
1363 tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
1364 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1365 return;
1366 case 0x0082: /* stc Rm_BANK,Rn */
1367 CHECK_PRIVILEGED
1368 tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4));
1369 return;
1370 case 0x4083: /* stc.l Rm_BANK,@-Rn */
1371 CHECK_PRIVILEGED
1372 {
1373 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1374 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1375 tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
1376 tcg_temp_free(addr);
1377 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1378 }
1379 return;
1380 }
1381
1382 switch (ctx->opcode & 0xf0ff) {
1383 case 0x0023: /* braf Rn */
1384 CHECK_NOT_DELAY_SLOT
1385 tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
1386 ctx->flags |= DELAY_SLOT;
1387 ctx->delayed_pc = (uint32_t) - 1;
1388 return;
1389 case 0x0003: /* bsrf Rn */
1390 CHECK_NOT_DELAY_SLOT
1391 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1392 tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
1393 ctx->flags |= DELAY_SLOT;
1394 ctx->delayed_pc = (uint32_t) - 1;
1395 return;
1396 case 0x4015: /* cmp/pl Rn */
1397 gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
1398 return;
1399 case 0x4011: /* cmp/pz Rn */
1400 gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
1401 return;
1402 case 0x4010: /* dt Rn */
1403 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
1404 gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
1405 return;
1406 case 0x402b: /* jmp @Rn */
1407 CHECK_NOT_DELAY_SLOT
1408 tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1409 ctx->flags |= DELAY_SLOT;
1410 ctx->delayed_pc = (uint32_t) - 1;
1411 return;
1412 case 0x400b: /* jsr @Rn */
1413 CHECK_NOT_DELAY_SLOT
1414 tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1415 tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1416 ctx->flags |= DELAY_SLOT;
1417 ctx->delayed_pc = (uint32_t) - 1;
1418 return;
1419 case 0x400e: /* ldc Rm,SR */
1420 CHECK_PRIVILEGED
1421 tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
1422 ctx->bstate = BS_STOP;
1423 return;
1424 case 0x4007: /* ldc.l @Rm+,SR */
1425 CHECK_PRIVILEGED
1426 {
1427 TCGv val = tcg_temp_new(TCG_TYPE_I32);
1428 tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
1429 tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
1430 tcg_temp_free(val);
1431 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1432 ctx->bstate = BS_STOP;
1433 }
1434 return;
1435 case 0x0002: /* stc SR,Rn */
1436 CHECK_PRIVILEGED
1437 tcg_gen_mov_i32(REG(B11_8), cpu_sr);
1438 return;
1439 case 0x4003: /* stc SR,@-Rn */
1440 CHECK_PRIVILEGED
1441 {
1442 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1443 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1444 tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
1445 tcg_temp_free(addr);
1446 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1447 }
1448 return;
1449 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
1450 case ldnum: \
1451 prechk \
1452 tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \
1453 return; \
1454 case ldpnum: \
1455 prechk \
1456 tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \
1457 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
1458 return; \
1459 case stnum: \
1460 prechk \
1461 tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \
1462 return; \
1463 case stpnum: \
1464 prechk \
1465 { \
1466 TCGv addr = tcg_temp_new(TCG_TYPE_I32); \
1467 tcg_gen_subi_i32(addr, REG(B11_8), 4); \
1468 tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
1469 tcg_temp_free(addr); \
1470 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
1471 } \
1472 return;
1473 LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {})
1474 LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
1475 LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
1476 LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
1477 LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
1478 LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
1479 LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
1480 LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {})
1481 LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {})
1482 case 0x406a: /* lds Rm,FPSCR */
1483 tcg_gen_helper_0_1(helper_ld_fpscr, REG(B11_8));
1484 ctx->bstate = BS_STOP;
1485 return;
1486 case 0x4066: /* lds.l @Rm+,FPSCR */
1487 {
1488 TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1489 tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
1490 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1491 tcg_gen_helper_0_1(helper_ld_fpscr, addr);
1492 tcg_temp_free(addr);
1493 ctx->bstate = BS_STOP;
1494 }
1495 return;
1496 case 0x006a: /* sts FPSCR,Rn */
1497 tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
1498 return;
1499 case 0x4062: /* sts FPSCR,@-Rn */
1500 {
1501 TCGv addr, val;
1502 val = tcg_temp_new(TCG_TYPE_I32);
1503 tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
1504 addr = tcg_temp_new(TCG_TYPE_I32);
1505 tcg_gen_subi_i32(addr, REG(B11_8), 4);
1506 tcg_gen_qemu_st32(val, addr, ctx->memidx);
1507 tcg_temp_free(addr);
1508 tcg_temp_free(val);
1509 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1510 }
1511 return;
1512 case 0x00c3: /* movca.l R0,@Rm */
1513 tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
1514 return;
1515 case 0x0029: /* movt Rn */
1516 tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
1517 return;
1518 case 0x0093: /* ocbi @Rn */
1519 {
1520 TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
1521 tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1522 tcg_temp_free(dummy);
1523 }
1524 return;
1525 case 0x00a3: /* ocbp @Rn */
1526 {
1527 TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
1528 tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1529 tcg_temp_free(dummy);
1530 }
1531 return;
1532 case 0x00b3: /* ocbwb @Rn */
1533 {
1534 TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
1535 tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1536 tcg_temp_free(dummy);
1537 }
1538 return;
1539 case 0x0083: /* pref @Rn */
1540 return;
1541 case 0x4024: /* rotcl Rn */
1542 {
1543 TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
1544 tcg_gen_mov_i32(tmp, cpu_sr);
1545 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1546 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1547 gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);
1548 tcg_temp_free(tmp);
1549 }
1550 return;
1551 case 0x4025: /* rotcr Rn */
1552 {
1553 TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
1554 tcg_gen_mov_i32(tmp, cpu_sr);
1555 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1556 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1557 gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);
1558 tcg_temp_free(tmp);
1559 }
1560 return;
1561 case 0x4004: /* rotl Rn */
1562 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1563 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1564 gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
1565 return;
1566 case 0x4005: /* rotr Rn */
1567 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1568 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1569 gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
1570 return;
1571 case 0x4000: /* shll Rn */
1572 case 0x4020: /* shal Rn */
1573 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1574 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1575 return;
1576 case 0x4021: /* shar Rn */
1577 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1578 tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
1579 return;
1580 case 0x4001: /* shlr Rn */
1581 gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1582 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1583 return;
1584 case 0x4008: /* shll2 Rn */
1585 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
1586 return;
1587 case 0x4018: /* shll8 Rn */
1588 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
1589 return;
1590 case 0x4028: /* shll16 Rn */
1591 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
1592 return;
1593 case 0x4009: /* shlr2 Rn */
1594 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
1595 return;
1596 case 0x4019: /* shlr8 Rn */
1597 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
1598 return;
1599 case 0x4029: /* shlr16 Rn */
1600 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
1601 return;
1602 case 0x401b: /* tas.b @Rn */
1603 {
1604 TCGv addr, val;
1605 addr = tcg_temp_local_new(TCG_TYPE_I32);
1606 tcg_gen_mov_i32(addr, REG(B11_8));
1607 val = tcg_temp_local_new(TCG_TYPE_I32);
1608 tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1609 gen_cmp_imm(TCG_COND_EQ, val, 0);
1610 tcg_gen_ori_i32(val, val, 0x80);
1611 tcg_gen_qemu_st8(val, addr, ctx->memidx);
1612 tcg_temp_free(val);
1613 tcg_temp_free(addr);
1614 }
1615 return;
1616 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1617 {
1618 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1619 tcg_gen_mov_i32(fp, cpu_fpul);
1620 gen_store_fpr32(fp, FREG(B11_8));
1621 tcg_temp_free(fp);
1622 }
1623 return;
1624 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1625 {
1626 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1627 gen_load_fpr32(fp, FREG(B11_8));
1628 tcg_gen_mov_i32(cpu_fpul, fp);
1629 tcg_temp_free(fp);
1630 }
1631 return;
1632 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1633 if (ctx->fpscr & FPSCR_PR) {
1634 TCGv fp;
1635 if (ctx->opcode & 0x0100)
1636 break; /* illegal instruction */
1637 fp = tcg_temp_new(TCG_TYPE_I64);
1638 tcg_gen_helper_1_1(helper_float_DT, fp, cpu_fpul);
1639 gen_store_fpr64(fp, DREG(B11_8));
1640 tcg_temp_free(fp);
1641 }
1642 else {
1643 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1644 tcg_gen_helper_1_1(helper_float_FT, fp, cpu_fpul);
1645 gen_store_fpr32(fp, FREG(B11_8));
1646 tcg_temp_free(fp);
1647 }
1648 return;
1649 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1650 if (ctx->fpscr & FPSCR_PR) {
1651 TCGv fp;
1652 if (ctx->opcode & 0x0100)
1653 break; /* illegal instruction */
1654 fp = tcg_temp_new(TCG_TYPE_I64);
1655 gen_load_fpr64(fp, DREG(B11_8));
1656 tcg_gen_helper_1_1(helper_ftrc_DT, cpu_fpul, fp);
1657 tcg_temp_free(fp);
1658 }
1659 else {
1660 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1661 gen_load_fpr32(fp, FREG(B11_8));
1662 tcg_gen_helper_1_1(helper_ftrc_FT, cpu_fpul, fp);
1663 tcg_temp_free(fp);
1664 }
1665 return;
1666 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1667 {
1668 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1669 gen_load_fpr32(fp, FREG(B11_8));
1670 tcg_gen_helper_1_1(helper_fneg_T, fp, fp);
1671 gen_store_fpr32(fp, FREG(B11_8));
1672 tcg_temp_free(fp);
1673 }
1674 return;
1675 case 0xf05d: /* fabs FRn/DRn */
1676 if (ctx->fpscr & FPSCR_PR) {
1677 if (ctx->opcode & 0x0100)
1678 break; /* illegal instruction */
1679 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1680 gen_load_fpr64(fp, DREG(B11_8));
1681 tcg_gen_helper_1_1(helper_fabs_DT, fp, fp);
1682 gen_store_fpr64(fp, DREG(B11_8));
1683 tcg_temp_free(fp);
1684 } else {
1685 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1686 gen_load_fpr32(fp, FREG(B11_8));
1687 tcg_gen_helper_1_1(helper_fabs_FT, fp, fp);
1688 gen_store_fpr32(fp, FREG(B11_8));
1689 tcg_temp_free(fp);
1690 }
1691 return;
1692 case 0xf06d: /* fsqrt FRn */
1693 if (ctx->fpscr & FPSCR_PR) {
1694 if (ctx->opcode & 0x0100)
1695 break; /* illegal instruction */
1696 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1697 gen_load_fpr64(fp, DREG(B11_8));
1698 tcg_gen_helper_1_1(helper_fsqrt_DT, fp, fp);
1699 gen_store_fpr64(fp, DREG(B11_8));
1700 tcg_temp_free(fp);
1701 } else {
1702 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1703 gen_load_fpr32(fp, FREG(B11_8));
1704 tcg_gen_helper_1_1(helper_fsqrt_FT, fp, fp);
1705 gen_store_fpr32(fp, FREG(B11_8));
1706 tcg_temp_free(fp);
1707 }
1708 return;
1709 case 0xf07d: /* fsrra FRn */
1710 break;
1711 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1712 if (!(ctx->fpscr & FPSCR_PR)) {
1713 TCGv val = tcg_const_i32(0);
1714 gen_load_fpr32(val, FREG(B11_8));
1715 tcg_temp_free(val);
1716 return;
1717 }
1718 break;
1719 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1720 if (!(ctx->fpscr & FPSCR_PR)) {
1721 TCGv val = tcg_const_i32(0x3f800000);
1722 gen_load_fpr32(val, FREG(B11_8));
1723 tcg_temp_free(val);
1724 return;
1725 }
1726 break;
1727 case 0xf0ad: /* fcnvsd FPUL,DRn */
1728 {
1729 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1730 tcg_gen_helper_1_1(helper_fcnvsd_FT_DT, fp, cpu_fpul);
1731 gen_store_fpr64(fp, DREG(B11_8));
1732 tcg_temp_free(fp);
1733 }
1734 return;
1735 case 0xf0bd: /* fcnvds DRn,FPUL */
1736 {
1737 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1738 gen_load_fpr64(fp, DREG(B11_8));
1739 tcg_gen_helper_1_1(helper_fcnvds_DT_FT, cpu_fpul, fp);
1740 tcg_temp_free(fp);
1741 }
1742 return;
1743 }
1744
1745 fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
1746 ctx->opcode, ctx->pc);
1747 tcg_gen_helper_0_0(helper_raise_illegal_instruction);
1748 ctx->bstate = BS_EXCP;
1749 }
1750
1751 void decode_opc(DisasContext * ctx)
1752 {
1753 uint32_t old_flags = ctx->flags;
1754
1755 _decode_opc(ctx);
1756
1757 if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
1758 if (ctx->flags & DELAY_SLOT_CLEARME) {
1759 gen_store_flags(0);
1760 } else {
1761 /* go out of the delay slot */
1762 uint32_t new_flags = ctx->flags;
1763 new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
1764 gen_store_flags(new_flags);
1765 }
1766 ctx->flags = 0;
1767 ctx->bstate = BS_BRANCH;
1768 if (old_flags & DELAY_SLOT_CONDITIONAL) {
1769 gen_delayed_conditional_jump(ctx);
1770 } else if (old_flags & DELAY_SLOT) {
1771 gen_jump(ctx);
1772 }
1773
1774 }
1775
1776 /* go into a delay slot */
1777 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
1778 gen_store_flags(ctx->flags);
1779 }
1780
1781 static inline void
1782 gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1783 int search_pc)
1784 {
1785 DisasContext ctx;
1786 target_ulong pc_start;
1787 static uint16_t *gen_opc_end;
1788 int i, ii;
1789 int num_insns;
1790 int max_insns;
1791
1792 pc_start = tb->pc;
1793 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1794 ctx.pc = pc_start;
1795 ctx.flags = (uint32_t)tb->flags;
1796 ctx.bstate = BS_NONE;
1797 ctx.sr = env->sr;
1798 ctx.fpscr = env->fpscr;
1799 ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
1800 /* We don't know if the delayed pc came from a dynamic or static branch,
1801 so assume it is a dynamic branch. */
1802 ctx.delayed_pc = -1; /* use delayed pc from env pointer */
1803 ctx.tb = tb;
1804 ctx.singlestep_enabled = env->singlestep_enabled;
1805
1806 #ifdef DEBUG_DISAS
1807 if (loglevel & CPU_LOG_TB_CPU) {
1808 fprintf(logfile,
1809 "------------------------------------------------\n");
1810 cpu_dump_state(env, logfile, fprintf, 0);
1811 }
1812 #endif
1813
1814 ii = -1;
1815 num_insns = 0;
1816 max_insns = tb->cflags & CF_COUNT_MASK;
1817 if (max_insns == 0)
1818 max_insns = CF_COUNT_MASK;
1819 gen_icount_start();
1820 while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1821 if (env->nb_breakpoints > 0) {
1822 for (i = 0; i < env->nb_breakpoints; i++) {
1823 if (ctx.pc == env->breakpoints[i]) {
1824 /* We have hit a breakpoint - make sure PC is up-to-date */
1825 tcg_gen_movi_i32(cpu_pc, ctx.pc);
1826 tcg_gen_helper_0_0(helper_debug);
1827 ctx.bstate = BS_EXCP;
1828 break;
1829 }
1830 }
1831 }
1832 if (search_pc) {
1833 i = gen_opc_ptr - gen_opc_buf;
1834 if (ii < i) {
1835 ii++;
1836 while (ii < i)
1837 gen_opc_instr_start[ii++] = 0;
1838 }
1839 gen_opc_pc[ii] = ctx.pc;
1840 gen_opc_hflags[ii] = ctx.flags;
1841 gen_opc_instr_start[ii] = 1;
1842 gen_opc_icount[ii] = num_insns;
1843 }
1844 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1845 gen_io_start();
1846 #if 0
1847 fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
1848 fflush(stderr);
1849 #endif
1850 ctx.opcode = lduw_code(ctx.pc);
1851 decode_opc(&ctx);
1852 num_insns++;
1853 ctx.pc += 2;
1854 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1855 break;
1856 if (env->singlestep_enabled)
1857 break;
1858 if (num_insns >= max_insns)
1859 break;
1860 #ifdef SH4_SINGLE_STEP
1861 break;
1862 #endif
1863 }
1864 if (tb->cflags & CF_LAST_IO)
1865 gen_io_end();
1866 if (env->singlestep_enabled) {
1867 tcg_gen_helper_0_0(helper_debug);
1868 } else {
1869 switch (ctx.bstate) {
1870 case BS_STOP:
1871 /* gen_op_interrupt_restart(); */
1872 /* fall through */
1873 case BS_NONE:
1874 if (ctx.flags) {
1875 gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
1876 }
1877 gen_goto_tb(&ctx, 0, ctx.pc);
1878 break;
1879 case BS_EXCP:
1880 /* gen_op_interrupt_restart(); */
1881 tcg_gen_exit_tb(0);
1882 break;
1883 case BS_BRANCH:
1884 default:
1885 break;
1886 }
1887 }
1888
1889 gen_icount_end(tb, num_insns);
1890 *gen_opc_ptr = INDEX_op_end;
1891 if (search_pc) {
1892 i = gen_opc_ptr - gen_opc_buf;
1893 ii++;
1894 while (ii <= i)
1895 gen_opc_instr_start[ii++] = 0;
1896 } else {
1897 tb->size = ctx.pc - pc_start;
1898 tb->icount = num_insns;
1899 }
1900
1901 #ifdef DEBUG_DISAS
1902 #ifdef SH4_DEBUG_DISAS
1903 if (loglevel & CPU_LOG_TB_IN_ASM)
1904 fprintf(logfile, "\n");
1905 #endif
1906 if (loglevel & CPU_LOG_TB_IN_ASM) {
1907 fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */
1908 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
1909 fprintf(logfile, "\n");
1910 }
1911 #endif
1912 }
1913
1914 void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
1915 {
1916 gen_intermediate_code_internal(env, tb, 0);
1917 }
1918
1919 void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
1920 {
1921 gen_intermediate_code_internal(env, tb, 1);
1922 }
1923
1924 void gen_pc_load(CPUState *env, TranslationBlock *tb,
1925 unsigned long searched_pc, int pc_pos, void *puc)
1926 {
1927 env->pc = gen_opc_pc[pc_pos];
1928 env->flags = gen_opc_hflags[pc_pos];
1929 }
Samsung s3c2440 and arm920t support for the mini2440 dev board