hw/s3c24xx_lcd.c

   1 /*
   2  * Samsung S3C24xx series LCD controller.
   3  *
   4  * Copyright (c) 2007 OpenMoko, Inc.
   5  * Author: Andrzej Zaborowski <andrew@openedhand.com>
   6  * With:        Michel Pollet <buserror@gmail.com>
   7  *
   8  * This code is licenced under the GNU GPL v2.
   9  */
  10
  11 #include "s3c.h"
  12 #include "hw.h"
  13 #include "console.h"
  14
  15 typedef void (*s3c_drawfn_t)(uint32_t *, uint8_t *, const uint8_t *, int, int);
  16
  17 struct s3c_lcd_state_s {
  18     target_phys_addr_t base;
  19     void *irq;
  20     DisplayState *ds;
  21     s3c_drawfn_t *line_fn;
  22
  23     uint32_t con[5];
  24     uint32_t saddr[3];
  25     uint32_t r;
  26     uint32_t g;
  27     uint16_t b;
  28     uint32_t dithmode;
  29     uint32_t tpal;
  30     uint8_t intpnd;
  31     uint8_t srcpnd;
  32     uint8_t intmsk;
  33     uint8_t lpcsel;
  34
  35     uint16_t raw_pal[0x100];
  36
  37     int width;
  38     int height;
  39     int bpp;
  40     int enable;
  41     int msb;
  42     int frm565;
  43     void *fb;
  44     uint32_t palette[0x100];
  45     int invalidate;
  46     int invalidatep;
  47     int src_width;
  48     int dest_width;
  49     s3c_drawfn_t fn;
  50 };
  51
  52 static void s3c_lcd_update(struct s3c_lcd_state_s *s)
  53 {
  54     s->intpnd |= s->srcpnd & ~s->intmsk;
  55     qemu_set_irq(s->irq, !!s->intpnd);
  56 }
  57
  58 void s3c_lcd_reset(struct s3c_lcd_state_s *s)
  59 {
  60     s->enable = 0;
  61     s->invalidate = 1;
  62     s->invalidatep = 1;
  63     s->width = -1;
  64     s->height = -1;
  65
  66     s->con[0] = 0x00000000;
  67     s->con[1] = 0x00000000;
  68     s->con[2] = 0x00000000;
  69     s->con[3] = 0x00000000;
  70     s->con[4] = 0x00000000;
  71     s->saddr[0] = 0x00000000;
  72     s->saddr[1] = 0x00000000;
  73     s->saddr[2] = 0x00000000;
  74     s->r = 0x00000000;
  75     s->g = 0x00000000;
  76     s->b = 0x0000;
  77     s->dithmode = 0x00000;
  78     s->tpal = 0x00000000;
  79     s->intpnd = 0;
  80     s->srcpnd = 0;
  81     s->intmsk = 3;
  82     s->lpcsel = 4;
  83     s3c_lcd_update(s);
  84 }
  85
  86 #define S3C_LCDCON1     0x00    /* LCD Control register 1 */
  87 #define S3C_LCDCON2     0x04    /* LCD Control register 2 */
  88 #define S3C_LCDCON3     0x08    /* LCD Control register 3 */
  89 #define S3C_LCDCON4     0x0c    /* LCD Control register 4 */
  90 #define S3C_LCDCON5     0x10    /* LCD Control register 5 */
  91 #define S3C_LCDSADDR1   0x14    /* Framebuffer Start Address 1 register */
  92 #define S3C_LCDSADDR2   0x18    /* Framebuffer Start Address 2 register */
  93 #define S3C_LCDSADDR3   0x1c    /* Framebuffer Start Address 3 register */
  94 #define S3C_REDLUT      0x20    /* Red Lookup Table register */
  95 #define S3C_GREENLUT    0x24    /* Green Lookup Table register */
  96 #define S3C_BLUELUT     0x28    /* Blue Lookup Table register */
  97 #define S3C_DITHMODE    0x4c    /* Dithering Mode register */
  98 #define S3C_TPAL        0x50    /* Temporary Palette register */
  99 #define S3C_LCDINTPND   0x54    /* LCD Interrupt Pending register */
 100 #define S3C_LCDSRCPND   0x58    /* LCD Interrupt Source Pending register */
 101 #define S3C_LCDINTMSK   0x5c    /* LCD Interrupt Mask register */
 102 #define S3C_LPCSEL      0x60    /* LPC3600 Control register */
 103
 104 #define S3C_PALETTE     0x400   /* Palette IO start offset */
 105 #define S3C_PALETTEEND  0x5ff   /* Palette IO end offset */
 106
 107 static uint32_t s3c_lcd_read(void *opaque, target_phys_addr_t addr)
 108 {
 109     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 110
 111     switch (addr) {
 112     case S3C_LCDCON1:
 113         return s->con[0];               /* XXX Return random LINECNT? */
 114     case S3C_LCDCON2:
 115         return s->con[1];
 116     case S3C_LCDCON3:
 117         return s->con[2];
 118     case S3C_LCDCON4:
 119         return s->con[3];
 120     case S3C_LCDCON5:
 121         return s->con[4];               /* XXX Return random STATUS? */
 122     case S3C_LCDSADDR1:
 123         return s->saddr[0];
 124     case S3C_LCDSADDR2:
 125         return s->saddr[1];
 126     case S3C_LCDSADDR3:
 127         return s->saddr[2];
 128     case S3C_REDLUT:
 129         return s->r;
 130     case S3C_GREENLUT:
 131         return s->g;
 132     case S3C_BLUELUT:
 133         return s->b;
 134     case S3C_DITHMODE:
 135         return s->dithmode;
 136     case S3C_TPAL:
 137         return s->tpal;
 138     case S3C_LCDINTPND:
 139         return s->intpnd;
 140     case S3C_LCDSRCPND:
 141         return s->srcpnd;
 142     case S3C_LCDINTMSK:
 143         return s->intmsk;
 144     case S3C_LPCSEL:
 145         return s->lpcsel;
 146     case S3C_PALETTE ... S3C_PALETTEEND:
 147         /* XXX assuming 16bit access */
 148         return s->raw_pal[(addr - S3C_PALETTE) >> 1];
 149     default:
 150         printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
 151         break;
 152     }
 153     return 0;
 154 }
 155
 156 static void s3c_lcd_write(void *opaque, target_phys_addr_t addr,
 157                 uint32_t value)
 158 {
 159     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 160
 161     switch (addr) {
 162     case S3C_LCDCON1:
 163         s->con[0] = value & 0x0003ffff;
 164         s->enable = value & 1;
 165         s->bpp = (value >> 1) & 0xf;
 166         s->invalidate = 1;
 167         s->invalidatep = 1;
 168         break;
 169     case S3C_LCDCON2:
 170         s->con[1] = value;
 171         s->invalidate = 1;
 172         break;
 173     case S3C_LCDCON3:
 174         s->con[2] = value;
 175         s->invalidate = 1;
 176         break;
 177     case S3C_LCDCON4:
 178         s->con[3] = value & 0xffff;
 179         break;
 180     case S3C_LCDCON5:
 181         s->con[4] = value & 0x1fff;
 182         s->frm565 = (value >> 11) & 1;
 183         s->msb = (value >> 12) & 1;
 184         s->invalidatep = 1;
 185         s->invalidate = 1;
 186         break;
 187     case S3C_LCDSADDR1:
 188         s->saddr[0] = value;
 189 /*        s->fb = phys_ram_base +
 190                 (((s->saddr[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE); */
 191         s->fb = qemu_get_ram_ptr(
 192                 (((s->saddr[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE));
 193         s->invalidate = 1;
 194         break;
 195     case S3C_LCDSADDR2:
 196         s->saddr[1] = value;
 197         s->invalidate = 1;
 198         break;
 199     case S3C_LCDSADDR3:
 200         s->saddr[2] = value;
 201         s->invalidate = 1;
 202         break;
 203     case S3C_REDLUT:
 204         s->r = value;
 205         s->invalidatep = 1;
 206         s->invalidate = 1;
 207         break;
 208     case S3C_GREENLUT:
 209         s->g = value;
 210         s->invalidatep = 1;
 211         s->invalidate = 1;
 212         break;
 213     case S3C_BLUELUT:
 214         s->b = value;
 215         s->invalidatep = 1;
 216         s->invalidate = 1;
 217         break;
 218     case S3C_DITHMODE:
 219         s->dithmode = value;
 220         break;
 221     case S3C_TPAL:
 222         s->tpal = value;
 223         s->invalidatep = 1;
 224         s->invalidate = 1;
 225         break;
 226     case S3C_LCDINTPND:
 227         s->intpnd = value & 3;
 228         break;
 229     case S3C_LCDSRCPND:
 230         s->srcpnd = value & 3;
 231         break;
 232     case S3C_LCDINTMSK:
 233         s->intmsk = value & 7;
 234         s3c_lcd_update(s);
 235         break;
 236     case S3C_LPCSEL:
 237         s->lpcsel = (value & 3) | 4;
 238         if (value & 1)
 239             printf("%s: attempt to enable LPC3600\n", __FUNCTION__);
 240         break;
 241     case S3C_PALETTE ... S3C_PALETTEEND:
 242         /* XXX assuming 16bit access */
 243         s->raw_pal[(addr - S3C_PALETTE) >> 1] = value;
 244         break;
 245     default:
 246         printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
 247     }
 248 }
 249
 250 static CPUReadMemoryFunc *s3c_lcd_readfn[] = {
 251     s3c_lcd_read,
 252     s3c_lcd_read,
 253     s3c_lcd_read,
 254 };
 255
 256 static CPUWriteMemoryFunc *s3c_lcd_writefn[] = {
 257     s3c_lcd_write,
 258     s3c_lcd_write,
 259     s3c_lcd_write,
 260 };
 261
 262 static inline void s3c_lcd_resize(struct s3c_lcd_state_s *s)
 263 {
 264     int new_width, new_height;
 265     new_height = ((s->con[1] >> 14) & 0x3ff) + 1;
 266     new_width = ((s->con[2] >> 8) & 0x7ff) + 1;
 267     if (s->width != new_width || s->height != new_height) {
 268         s->width = new_width;
 269         s->height = new_height;
 270        // dpy_resize(s->ds, s->width, s->height);
 271         qemu_console_resize(s->ds, s->width, s->height);
 272         s->invalidate = 1;
 273     }
 274 }
 275
 276 static inline
 277 uint32_t s3c_rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
 278 {
 279     return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
 280 }
 281
 282 static inline
 283 uint32_t s3c_rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
 284 {
 285     return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
 286 }
 287
 288 static inline
 289 uint32_t s3c_rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
 290 {
 291     return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
 292 }
 293
 294 static inline
 295 uint32_t s3c_rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
 296 {
 297     return (r << 16) | (g << 8) | b;
 298 }
 299
 300 static inline
 301 uint32_t s3c_rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
 302 {
 303     return (r << 16) | (g << 8) | b;
 304 }
 305
 306 static inline uint32_t s3c_rgb(struct s3c_lcd_state_s *s,
 307                 unsigned int r, unsigned int g, unsigned b)
 308 {
 309     switch (ds_get_bits_per_pixel(s->ds)) {
 310     case 8:
 311         return s3c_rgb_to_pixel32(r << 2, g << 2, b << 2);
 312     case 15:
 313         return s3c_rgb_to_pixel15(r << 2, g << 2, b << 2);
 314     case 16:
 315         return s3c_rgb_to_pixel16(r << 2, g << 2, b << 2);
 316     case 24:
 317         return s3c_rgb_to_pixel24(r << 2, g << 2, b << 2);
 318     case 32:
 319         return s3c_rgb_to_pixel32(r << 2, g << 2, b << 2);
 320     default:
 321         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 322         exit(1);
 323     }
 324 }
 325
 326 static void s3c_lcd_palette_load(struct s3c_lcd_state_s *s)
 327 {
 328     int i, n;
 329     switch (s->bpp) {
 330     case 0:
 331     case 8:
 332         n = 2;
 333         s->src_width = s->width >> 3;
 334         s->fn = s->line_fn[0];
 335         break;
 336     case 1:
 337     case 9:
 338         n = 4;
 339         s->src_width = s->width >> 2;
 340         s->fn = s->line_fn[1];
 341         break;
 342     case 2:
 343     case 10:
 344         n = 16;
 345         s->src_width = s->width >> 1;
 346         s->fn = s->line_fn[2];
 347         break;
 348     case 3:
 349     case 11:
 350         n = 256;
 351         s->src_width = s->width >> 0;
 352         s->fn = s->line_fn[3];
 353         break;
 354     case 6:
 355         s->src_width = (s->width * 3) >> 1;
 356         s->fn = s->line_fn[4];
 357         return;
 358     case 12:
 359         s->src_width = s->width << 1;
 360         if (s->frm565)
 361             s->fn = s->line_fn[5];
 362         else
 363             s->fn = s->line_fn[6];
 364         return;
 365     case 13:
 366         s->src_width = s->width << 2;
 367         s->fn = s->line_fn[7];
 368         return;
 369     default:
 370         return;
 371     }
 372     if (s->bpp & 8) {
 373         for (i = 0; i < n; i ++)
 374             if (s->frm565)
 375                 s->palette[i] = s3c_rgb(s,
 376                         (s->raw_pal[i] >> 10) & 0x3e,
 377                         (s->raw_pal[i] >> 5) & 0x3f,
 378                         (s->raw_pal[i] << 1) & 0x3e);
 379             else
 380                 s->palette[i] = s3c_rgb(s,
 381                         ((s->raw_pal[i] >> 10) & 0x3e) | (s->raw_pal[i] & 1),
 382                         ((s->raw_pal[i] >> 6) & 0x3e) | (s->raw_pal[i] & 1),
 383                         s->raw_pal[i] & 0x3f);
 384     } else {
 385         for (i = 0; i < n; i ++)
 386             if (n < 256)
 387                 s->palette[i] = s3c_rgb(s,
 388                         ((s->r >> (i * 4)) & 0xf) << 2,
 389                         ((s->g >> (i * 4)) & 0xf) << 2,
 390                         ((s->b >> (i * 4)) & 0xf) << 2);
 391             else
 392                 s->palette[i] = s3c_rgb(s,
 393                         ((s->r >> (((i >> 5) & 7) * 4)) & 0xf) << 2,
 394                         ((s->g >> (((i >> 2) & 7) * 4)) & 0xf) << 2,
 395                         ((s->b >> ((i & 3) * 4)) & 0xf) << 2);
 396     }
 397 }
 398
 399 static void s3c_update_display(void *opaque)
 400 {
 401     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 402     int y, src_width, dest_width, dirty[2], miny, maxy;
 403     ram_addr_t x, addr, new_addr, start, end;
 404     uint8_t *src, *dest;
 405     if (!s->enable || !s->dest_width)
 406         return;
 407
 408     s3c_lcd_resize(s);
 409
 410     if (s->invalidatep) {
 411         s3c_lcd_palette_load(s);
 412         s->invalidatep = 0;
 413     }
 414
 415     src = s->fb;
 416     src_width = s->src_width;
 417
 418     dest = ds_get_data(s->ds);
 419     dest_width = s->width * s->dest_width;
 420
 421 /*    addr = (ram_addr_t) (s->fb - (void *) phys_ram_base); */
 422     addr = qemu_ram_addr_from_host(s->fb);
 423     start = addr + s->height * src_width;
 424     end = addr;
 425     dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
 426     miny = s->height;
 427     maxy = 0;
 428     for (y = 0; y < s->height; y ++) {
 429         new_addr = addr + src_width;
 430         for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
 431                         x += TARGET_PAGE_SIZE) {
 432             dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
 433             dirty[0] |= dirty[1];
 434         }
 435         if (dirty[0] || s->invalidate) {
 436             s->fn(s->palette, dest, src, s->width, s->dest_width);
 437             maxy = y;
 438             end = new_addr;
 439             if (y < miny) {
 440                 miny = y;
 441                 start = addr;
 442             }
 443         }
 444         addr = new_addr;
 445         dirty[0] = dirty[1];
 446         src += src_width;
 447         dest += dest_width;
 448     }
 449
 450     s->invalidate = 0;
 451     if (end > start)
 452         cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
 453     s->srcpnd |= (1 << 1);                      /* INT_FrSyn */
 454     s3c_lcd_update(s);
 455     dpy_update(s->ds, 0, miny, s->width, maxy);
 456 }
 457
 458 static void s3c_invalidate_display(void *opaque)
 459 {
 460     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 461     s->invalidate = 1;
 462 }
 463
 464 static void s3c_screen_dump(void *opaque, const char *filename)
 465 {
 466     /* TODO */
 467 }
 468
 469 #define BITS 8
 470 #include "s3c24xx_template.h"
 471 #define BITS 15
 472 #include "s3c24xx_template.h"
 473 #define BITS 16
 474 #include "s3c24xx_template.h"
 475 #define BITS 24
 476 #include "s3c24xx_template.h"
 477 #define BITS 32
 478 #include "s3c24xx_template.h"
 479
 480 static void s3c_lcd_save(QEMUFile *f, void *opaque)
 481 {
 482     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 483     int i;
 484     for (i = 0; i < 5; i ++)
 485         qemu_put_be32s(f, &s->con[i]);
 486     for (i = 0; i < 3; i ++)
 487         qemu_put_be32s(f, &s->saddr[i]);
 488     qemu_put_be32s(f, &s->r);
 489     qemu_put_be32s(f, &s->g);
 490     qemu_put_be16s(f, &s->b);
 491     qemu_put_be32s(f, &s->dithmode);
 492     qemu_put_be32s(f, &s->tpal);
 493     qemu_put_8s(f, &s->intpnd);
 494     qemu_put_8s(f, &s->srcpnd);
 495     qemu_put_8s(f, &s->intmsk);
 496     qemu_put_8s(f, &s->lpcsel);
 497     for (i = 0; i < 0x100; i ++)
 498         qemu_put_be16s(f, &s->raw_pal[i]);
 499 }
 500
 501 static int s3c_lcd_load(QEMUFile *f, void *opaque, int version_id)
 502 {
 503     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 504     int i;
 505     for (i = 0; i < 5; i ++)
 506         qemu_get_be32s(f, &s->con[i]);
 507     for (i = 0; i < 3; i ++)
 508         qemu_get_be32s(f, &s->saddr[i]);
 509     qemu_get_be32s(f, &s->r);
 510     qemu_get_be32s(f, &s->g);
 511     qemu_get_be16s(f, &s->b);
 512     qemu_get_be32s(f, &s->dithmode);
 513     qemu_get_be32s(f, &s->tpal);
 514     qemu_get_8s(f, &s->intpnd);
 515     qemu_get_8s(f, &s->srcpnd);
 516     qemu_get_8s(f, &s->intmsk);
 517     qemu_get_8s(f, &s->lpcsel);
 518
 519     s->invalidate = 1;
 520     s->invalidatep = 1;
 521     s->width = -1;
 522     s->height = -1;
 523     s->bpp = (s->con[0] >> 1) & 0xf;
 524     s->enable = s->con[0] & 1;
 525     s->msb = (s->con[4] >> 12) & 1;
 526     s->frm565 = (s->con[4] >> 11) & 1;
 527 /*    s->fb = phys_ram_base + (((s->saddr[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE); */
 528     s->fb = qemu_get_ram_ptr((((s->saddr[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE));
 529
 530     for (i = 0; i < 0x100; i ++)
 531         qemu_get_be16s(f, &s->raw_pal[i]);
 532
 533     return 0;
 534 }
 535
 536 struct s3c_lcd_state_s *s3c_lcd_init(target_phys_addr_t base,
 537                 qemu_irq irq)
 538 {
 539     int iomemtype;
 540     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *)
 541             qemu_mallocz(sizeof(struct s3c_lcd_state_s));
 542
 543     s->base = base;
 544     s->irq = irq;
 545
 546     s3c_lcd_reset(s);
 547
 548     s->ds = graphic_console_init(
 549                                 s3c_update_display,
 550                     s3c_invalidate_display,
 551                     s3c_screen_dump, NULL, s);
 552
 553     iomemtype = cpu_register_io_memory(0, s3c_lcd_readfn,
 554                     s3c_lcd_writefn, s);
 555     cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
 556
 557     register_savevm("s3c24xx_lcd", 0, 0, s3c_lcd_save, s3c_lcd_load, s);
 558
 559     switch (ds_get_bits_per_pixel(s->ds)) {
 560     case 0:
 561         s->dest_width = 0;
 562         break;
 563     case 8:
 564         s->line_fn = s3c_draw_fn_8;
 565         s->dest_width = 1;
 566         break;
 567     case 15:
 568         s->line_fn = s3c_draw_fn_15;
 569         s->dest_width = 2;
 570         break;
 571     case 16:
 572         s->line_fn = s3c_draw_fn_16;
 573         s->dest_width = 2;
 574         break;
 575     case 24:
 576         s->line_fn = s3c_draw_fn_24;
 577         s->dest_width = 3;
 578         break;
 579     case 32:
 580         s->line_fn = s3c_draw_fn_32;
 581         s->dest_width = 4;
 582         break;
 583     default:
 584         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 585         exit(1);
 586     }
 587     return s;
 588 }