hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "ppc.h"
  33 #include "boards.h"
  34 #include "qemu-log.h"
  35
  36 //#define HARD_DEBUG_PPC_IO
  37 //#define DEBUG_PPC_IO
  38
  39 /* SMP is not enabled, for now */
  40 #define MAX_CPUS 1
  41
  42 #define MAX_IDE_BUS 2
  43
  44 #define BIOS_SIZE (1024 * 1024)
  45 #define BIOS_FILENAME "ppc_rom.bin"
  46 #define KERNEL_LOAD_ADDR 0x01000000
  47 #define INITRD_LOAD_ADDR 0x01800000
  48
  49 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  50 #define DEBUG_PPC_IO
  51 #endif
  52
  53 #if defined (HARD_DEBUG_PPC_IO)
  54 #define PPC_IO_DPRINTF(fmt, ...)                         \
  55 do {                                                     \
  56     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  57         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  58     } else {                                             \
  59         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  60     }                                                    \
  61 } while (0)
  62 #elif defined (DEBUG_PPC_IO)
  63 #define PPC_IO_DPRINTF(fmt, ...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
  64 #else
  65 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  66 #endif
  67
  68 /* Constants for devices init */
  69 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  70 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  71 static const int ide_irq[2] = { 13, 13 };
  72
  73 #define NE2000_NB_MAX 6
  74
  75 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  76 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  77
  78 //static PITState *pit;
  79
  80 /* ISA IO ports bridge */
  81 #define PPC_IO_BASE 0x80000000
  82
  83 #if 0
  84 /* Speaker port 0x61 */
  85 static int speaker_data_on;
  86 static int dummy_refresh_clock;
  87 #endif
  88
  89 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  90 {
  91 #if 0
  92     speaker_data_on = (val >> 1) & 1;
  93     pit_set_gate(pit, 2, val & 1);
  94 #endif
  95 }
  96
  97 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
  98 {
  99 #if 0
 100     int out;
 101     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
 102     dummy_refresh_clock ^= 1;
 103     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 104         (dummy_refresh_clock << 4);
 105 #endif
 106     return 0;
 107 }
 108
 109 /* PCI intack register */
 110 /* Read-only register (?) */
 111 static void _PPC_intack_write (void *opaque,
 112                                target_phys_addr_t addr, uint32_t value)
 113 {
 114 //    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 115 }
 116
 117 static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
 118 {
 119     uint32_t retval = 0;
 120
 121     if ((addr & 0xf) == 0)
 122         retval = pic_intack_read(isa_pic);
 123 //   printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 124
 125     return retval;
 126 }
 127
 128 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 129 {
 130     return _PPC_intack_read(addr);
 131 }
 132
 133 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 134 {
 135 #ifdef TARGET_WORDS_BIGENDIAN
 136     return bswap16(_PPC_intack_read(addr));
 137 #else
 138     return _PPC_intack_read(addr);
 139 #endif
 140 }
 141
 142 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 143 {
 144 #ifdef TARGET_WORDS_BIGENDIAN
 145     return bswap32(_PPC_intack_read(addr));
 146 #else
 147     return _PPC_intack_read(addr);
 148 #endif
 149 }
 150
 151 static CPUWriteMemoryFunc *PPC_intack_write[] = {
 152     &_PPC_intack_write,
 153     &_PPC_intack_write,
 154     &_PPC_intack_write,
 155 };
 156
 157 static CPUReadMemoryFunc *PPC_intack_read[] = {
 158     &PPC_intack_readb,
 159     &PPC_intack_readw,
 160     &PPC_intack_readl,
 161 };
 162
 163 /* PowerPC control and status registers */
 164 #if 0 // Not used
 165 static struct {
 166     /* IDs */
 167     uint32_t veni_devi;
 168     uint32_t revi;
 169     /* Control and status */
 170     uint32_t gcsr;
 171     uint32_t xcfr;
 172     uint32_t ct32;
 173     uint32_t mcsr;
 174     /* General purpose registers */
 175     uint32_t gprg[6];
 176     /* Exceptions */
 177     uint32_t feen;
 178     uint32_t fest;
 179     uint32_t fema;
 180     uint32_t fecl;
 181     uint32_t eeen;
 182     uint32_t eest;
 183     uint32_t eecl;
 184     uint32_t eeint;
 185     uint32_t eemck0;
 186     uint32_t eemck1;
 187     /* Error diagnostic */
 188 } XCSR;
 189
 190 static void PPC_XCSR_writeb (void *opaque,
 191                              target_phys_addr_t addr, uint32_t value)
 192 {
 193     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 194 }
 195
 196 static void PPC_XCSR_writew (void *opaque,
 197                              target_phys_addr_t addr, uint32_t value)
 198 {
 199 #ifdef TARGET_WORDS_BIGENDIAN
 200     value = bswap16(value);
 201 #endif
 202     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 203 }
 204
 205 static void PPC_XCSR_writel (void *opaque,
 206                              target_phys_addr_t addr, uint32_t value)
 207 {
 208 #ifdef TARGET_WORDS_BIGENDIAN
 209     value = bswap32(value);
 210 #endif
 211     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 212 }
 213
 214 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 215 {
 216     uint32_t retval = 0;
 217
 218     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 219
 220     return retval;
 221 }
 222
 223 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 224 {
 225     uint32_t retval = 0;
 226
 227     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 228 #ifdef TARGET_WORDS_BIGENDIAN
 229     retval = bswap16(retval);
 230 #endif
 231
 232     return retval;
 233 }
 234
 235 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 236 {
 237     uint32_t retval = 0;
 238
 239     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 240 #ifdef TARGET_WORDS_BIGENDIAN
 241     retval = bswap32(retval);
 242 #endif
 243
 244     return retval;
 245 }
 246
 247 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
 248     &PPC_XCSR_writeb,
 249     &PPC_XCSR_writew,
 250     &PPC_XCSR_writel,
 251 };
 252
 253 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
 254     &PPC_XCSR_readb,
 255     &PPC_XCSR_readw,
 256     &PPC_XCSR_readl,
 257 };
 258 #endif
 259
 260 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 261 typedef struct sysctrl_t {
 262     qemu_irq reset_irq;
 263     m48t59_t *nvram;
 264     uint8_t state;
 265     uint8_t syscontrol;
 266     uint8_t fake_io[2];
 267     int contiguous_map;
 268     int endian;
 269 } sysctrl_t;
 270
 271 enum {
 272     STATE_HARDFILE = 0x01,
 273 };
 274
 275 static sysctrl_t *sysctrl;
 276
 277 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 278 {
 279     sysctrl_t *sysctrl = opaque;
 280
 281     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 282                    val);
 283     sysctrl->fake_io[addr - 0x0398] = val;
 284 }
 285
 286 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 287 {
 288     sysctrl_t *sysctrl = opaque;
 289
 290     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 291                    sysctrl->fake_io[addr - 0x0398]);
 292     return sysctrl->fake_io[addr - 0x0398];
 293 }
 294
 295 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 296 {
 297     sysctrl_t *sysctrl = opaque;
 298
 299     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 300                    addr - PPC_IO_BASE, val);
 301     switch (addr) {
 302     case 0x0092:
 303         /* Special port 92 */
 304         /* Check soft reset asked */
 305         if (val & 0x01) {
 306             qemu_irq_raise(sysctrl->reset_irq);
 307         } else {
 308             qemu_irq_lower(sysctrl->reset_irq);
 309         }
 310         /* Check LE mode */
 311         if (val & 0x02) {
 312             sysctrl->endian = 1;
 313         } else {
 314             sysctrl->endian = 0;
 315         }
 316         break;
 317     case 0x0800:
 318         /* Motorola CPU configuration register : read-only */
 319         break;
 320     case 0x0802:
 321         /* Motorola base module feature register : read-only */
 322         break;
 323     case 0x0803:
 324         /* Motorola base module status register : read-only */
 325         break;
 326     case 0x0808:
 327         /* Hardfile light register */
 328         if (val & 1)
 329             sysctrl->state |= STATE_HARDFILE;
 330         else
 331             sysctrl->state &= ~STATE_HARDFILE;
 332         break;
 333     case 0x0810:
 334         /* Password protect 1 register */
 335         if (sysctrl->nvram != NULL)
 336             m48t59_toggle_lock(sysctrl->nvram, 1);
 337         break;
 338     case 0x0812:
 339         /* Password protect 2 register */
 340         if (sysctrl->nvram != NULL)
 341             m48t59_toggle_lock(sysctrl->nvram, 2);
 342         break;
 343     case 0x0814:
 344         /* L2 invalidate register */
 345         //        tlb_flush(first_cpu, 1);
 346         break;
 347     case 0x081C:
 348         /* system control register */
 349         sysctrl->syscontrol = val & 0x0F;
 350         break;
 351     case 0x0850:
 352         /* I/O map type register */
 353         sysctrl->contiguous_map = val & 0x01;
 354         break;
 355     default:
 356         printf("ERROR: unaffected IO port write: %04" PRIx32
 357                " => %02" PRIx32"\n", addr, val);
 358         break;
 359     }
 360 }
 361
 362 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 363 {
 364     sysctrl_t *sysctrl = opaque;
 365     uint32_t retval = 0xFF;
 366
 367     switch (addr) {
 368     case 0x0092:
 369         /* Special port 92 */
 370         retval = 0x00;
 371         break;
 372     case 0x0800:
 373         /* Motorola CPU configuration register */
 374         retval = 0xEF; /* MPC750 */
 375         break;
 376     case 0x0802:
 377         /* Motorola Base module feature register */
 378         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 379         break;
 380     case 0x0803:
 381         /* Motorola base module status register */
 382         retval = 0xE0; /* Standard MPC750 */
 383         break;
 384     case 0x080C:
 385         /* Equipment present register:
 386          *  no L2 cache
 387          *  no upgrade processor
 388          *  no cards in PCI slots
 389          *  SCSI fuse is bad
 390          */
 391         retval = 0x3C;
 392         break;
 393     case 0x0810:
 394         /* Motorola base module extended feature register */
 395         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 396         break;
 397     case 0x0814:
 398         /* L2 invalidate: don't care */
 399         break;
 400     case 0x0818:
 401         /* Keylock */
 402         retval = 0x00;
 403         break;
 404     case 0x081C:
 405         /* system control register
 406          * 7 - 6 / 1 - 0: L2 cache enable
 407          */
 408         retval = sysctrl->syscontrol;
 409         break;
 410     case 0x0823:
 411         /* */
 412         retval = 0x03; /* no L2 cache */
 413         break;
 414     case 0x0850:
 415         /* I/O map type register */
 416         retval = sysctrl->contiguous_map;
 417         break;
 418     default:
 419         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 420         break;
 421     }
 422     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 423                    addr - PPC_IO_BASE, retval);
 424
 425     return retval;
 426 }
 427
 428 static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
 429                                                          target_phys_addr_t
 430                                                          addr)
 431 {
 432     if (sysctrl->contiguous_map == 0) {
 433         /* 64 KB contiguous space for IOs */
 434         addr &= 0xFFFF;
 435     } else {
 436         /* 8 MB non-contiguous space for IOs */
 437         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 438     }
 439
 440     return addr;
 441 }
 442
 443 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 444                                 uint32_t value)
 445 {
 446     sysctrl_t *sysctrl = opaque;
 447
 448     addr = prep_IO_address(sysctrl, addr);
 449     cpu_outb(NULL, addr, value);
 450 }
 451
 452 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 453 {
 454     sysctrl_t *sysctrl = opaque;
 455     uint32_t ret;
 456
 457     addr = prep_IO_address(sysctrl, addr);
 458     ret = cpu_inb(NULL, addr);
 459
 460     return ret;
 461 }
 462
 463 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 464                                 uint32_t value)
 465 {
 466     sysctrl_t *sysctrl = opaque;
 467
 468     addr = prep_IO_address(sysctrl, addr);
 469 #ifdef TARGET_WORDS_BIGENDIAN
 470     value = bswap16(value);
 471 #endif
 472     PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
 473     cpu_outw(NULL, addr, value);
 474 }
 475
 476 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 477 {
 478     sysctrl_t *sysctrl = opaque;
 479     uint32_t ret;
 480
 481     addr = prep_IO_address(sysctrl, addr);
 482     ret = cpu_inw(NULL, addr);
 483 #ifdef TARGET_WORDS_BIGENDIAN
 484     ret = bswap16(ret);
 485 #endif
 486     PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
 487
 488     return ret;
 489 }
 490
 491 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 492                                 uint32_t value)
 493 {
 494     sysctrl_t *sysctrl = opaque;
 495
 496     addr = prep_IO_address(sysctrl, addr);
 497 #ifdef TARGET_WORDS_BIGENDIAN
 498     value = bswap32(value);
 499 #endif
 500     PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
 501     cpu_outl(NULL, addr, value);
 502 }
 503
 504 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 505 {
 506     sysctrl_t *sysctrl = opaque;
 507     uint32_t ret;
 508
 509     addr = prep_IO_address(sysctrl, addr);
 510     ret = cpu_inl(NULL, addr);
 511 #ifdef TARGET_WORDS_BIGENDIAN
 512     ret = bswap32(ret);
 513 #endif
 514     PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
 515
 516     return ret;
 517 }
 518
 519 static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
 520     &PPC_prep_io_writeb,
 521     &PPC_prep_io_writew,
 522     &PPC_prep_io_writel,
 523 };
 524
 525 static CPUReadMemoryFunc *PPC_prep_io_read[] = {
 526     &PPC_prep_io_readb,
 527     &PPC_prep_io_readw,
 528     &PPC_prep_io_readl,
 529 };
 530
 531 #define NVRAM_SIZE        0x2000
 532
 533 /* PowerPC PREP hardware initialisation */
 534 static void ppc_prep_init (ram_addr_t ram_size,
 535                            const char *boot_device,
 536                            const char *kernel_filename,
 537                            const char *kernel_cmdline,
 538                            const char *initrd_filename,
 539                            const char *cpu_model)
 540 {
 541     CPUState *env = NULL, *envs[MAX_CPUS];
 542     char buf[1024];
 543     nvram_t nvram;
 544     m48t59_t *m48t59;
 545     int PPC_io_memory;
 546     int linux_boot, i, nb_nics1, bios_size;
 547     ram_addr_t ram_offset, bios_offset;
 548     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 549     PCIBus *pci_bus;
 550     qemu_irq *i8259;
 551     int ppc_boot_device;
 552     int index;
 553     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 554     BlockDriverState *fd[MAX_FD];
 555
 556     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 557
 558     linux_boot = (kernel_filename != NULL);
 559
 560     /* init CPUs */
 561     if (cpu_model == NULL)
 562         cpu_model = "default";
 563     for (i = 0; i < smp_cpus; i++) {
 564         env = cpu_init(cpu_model);
 565         if (!env) {
 566             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 567             exit(1);
 568         }
 569         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 570             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 571             cpu_ppc_tb_init(env, 7812500UL);
 572         } else {
 573             /* Set time-base frequency to 100 Mhz */
 574             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 575         }
 576         qemu_register_reset(&cpu_ppc_reset, env);
 577         envs[i] = env;
 578     }
 579
 580     /* allocate RAM */
 581     ram_offset = qemu_ram_alloc(ram_size);
 582     cpu_register_physical_memory(0, ram_size, ram_offset);
 583
 584     /* allocate and load BIOS */
 585     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 586     if (bios_name == NULL)
 587         bios_name = BIOS_FILENAME;
 588     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 589     bios_size = get_image_size(buf);
 590     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 591         target_phys_addr_t bios_addr;
 592         bios_size = (bios_size + 0xfff) & ~0xfff;
 593         bios_addr = (uint32_t)(-bios_size);
 594         cpu_register_physical_memory(bios_addr, bios_size,
 595                                      bios_offset | IO_MEM_ROM);
 596         bios_size = load_image_targphys(buf, bios_addr, bios_size);
 597     }
 598     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 599         hw_error("qemu: could not load PPC PREP bios '%s'\n", buf);
 600     }
 601     if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
 602         hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
 603     }
 604
 605     if (linux_boot) {
 606         kernel_base = KERNEL_LOAD_ADDR;
 607         /* now we can load the kernel */
 608         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 609                                           ram_size - kernel_base);
 610         if (kernel_size < 0) {
 611             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 612             exit(1);
 613         }
 614         /* load initrd */
 615         if (initrd_filename) {
 616             initrd_base = INITRD_LOAD_ADDR;
 617             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 618                                               ram_size - initrd_base);
 619             if (initrd_size < 0) {
 620                 hw_error("qemu: could not load initial ram disk '%s'\n",
 621                           initrd_filename);
 622             }
 623         } else {
 624             initrd_base = 0;
 625             initrd_size = 0;
 626         }
 627         ppc_boot_device = 'm';
 628     } else {
 629         kernel_base = 0;
 630         kernel_size = 0;
 631         initrd_base = 0;
 632         initrd_size = 0;
 633         ppc_boot_device = '\0';
 634         /* For now, OHW cannot boot from the network. */
 635         for (i = 0; boot_device[i] != '\0'; i++) {
 636             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 637                 ppc_boot_device = boot_device[i];
 638                 break;
 639             }
 640         }
 641         if (ppc_boot_device == '\0') {
 642             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 643             exit(1);
 644         }
 645     }
 646
 647     isa_mem_base = 0xc0000000;
 648     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 649         hw_error("Only 6xx bus is supported on PREP machine\n");
 650     }
 651     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 652     pci_bus = pci_prep_init(i8259);
 653     //    pci_bus = i440fx_init();
 654     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 655     PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
 656                                            PPC_prep_io_write, sysctrl);
 657     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 658
 659     /* init basic PC hardware */
 660     pci_vga_init(pci_bus, 0, 0);
 661     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 662     //    pit = pit_init(0x40, i8259[0]);
 663     rtc_init(0x70, i8259[8], 2000);
 664
 665     serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
 666     nb_nics1 = nb_nics;
 667     if (nb_nics1 > NE2000_NB_MAX)
 668         nb_nics1 = NE2000_NB_MAX;
 669     for(i = 0; i < nb_nics1; i++) {
 670         if (nd_table[i].model == NULL) {
 671             nd_table[i].model = "ne2k_isa";
 672         }
 673         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 674             isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
 675         } else {
 676             pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
 677         }
 678     }
 679
 680     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 681         fprintf(stderr, "qemu: too many IDE bus\n");
 682         exit(1);
 683     }
 684
 685     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 686         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 687         if (index != -1)
 688             hd[i] = drives_table[index].bdrv;
 689         else
 690             hd[i] = NULL;
 691     }
 692
 693     for(i = 0; i < MAX_IDE_BUS; i++) {
 694         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 695                      hd[2 * i],
 696                      hd[2 * i + 1]);
 697     }
 698     i8042_init(i8259[1], i8259[12], 0x60);
 699     DMA_init(1);
 700     //    SB16_init();
 701
 702     for(i = 0; i < MAX_FD; i++) {
 703         index = drive_get_index(IF_FLOPPY, 0, i);
 704         if (index != -1)
 705             fd[i] = drives_table[index].bdrv;
 706         else
 707             fd[i] = NULL;
 708     }
 709     fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
 710
 711     /* Register speaker port */
 712     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 713     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 714     /* Register fake IO ports for PREP */
 715     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 716     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 717     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 718     /* System control ports */
 719     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 720     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 721     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 722     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 723     /* PCI intack location */
 724     PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
 725                                            PPC_intack_write, NULL);
 726     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 727     /* PowerPC control and status register group */
 728 #if 0
 729     PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
 730                                            NULL);
 731     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 732 #endif
 733
 734     if (usb_enabled) {
 735         usb_ohci_init_pci(pci_bus, 3, -1);
 736     }
 737
 738     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 739     if (m48t59 == NULL)
 740         return;
 741     sysctrl->nvram = m48t59;
 742
 743     /* Initialise NVRAM */
 744     nvram.opaque = m48t59;
 745     nvram.read_fn = &m48t59_read;
 746     nvram.write_fn = &m48t59_write;
 747     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 748                          kernel_base, kernel_size,
 749                          kernel_cmdline,
 750                          initrd_base, initrd_size,
 751                          /* XXX: need an option to load a NVRAM image */
 752                          0,
 753                          graphic_width, graphic_height, graphic_depth);
 754
 755     /* Special port to get debug messages from Open-Firmware */
 756     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 757 }
 758
 759 QEMUMachine prep_machine = {
 760     .name = "prep",
 761     .desc = "PowerPC PREP platform",
 762     .init = ppc_prep_init,
 763     .max_cpus = MAX_CPUS,
 764 };