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Remove reserved registers from tcg_target_reg_alloc_order
[qemu/mini2440.git] / tcg / ppc / tcg-target.c
blobf93c1dc60a5a1932f895b5c237b5347709697588
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #ifdef __APPLE__
28 #define LINKAGE_AREA_SIZE 24
29 #define LR_OFFSET 8
30 #elif defined _AIX
31 #define LINKAGE_AREA_SIZE 52
32 #define LR_OFFSET 8
33 #else
34 #define LINKAGE_AREA_SIZE 8
35 #define LR_OFFSET 4
36 #endif
37
38 #define FAST_PATH
39 #if TARGET_PHYS_ADDR_BITS <= 32
40 #define ADDEND_OFFSET 0
41 #else
42 #define ADDEND_OFFSET 4
43 #endif
44
45 #ifndef NDEBUG
46 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
47 "r0",
48 "r1",
49 "rp",
50 "r3",
51 "r4",
52 "r5",
53 "r6",
54 "r7",
55 "r8",
56 "r9",
57 "r10",
58 "r11",
59 "r12",
60 "r13",
61 "r14",
62 "r15",
63 "r16",
64 "r17",
65 "r18",
66 "r19",
67 "r20",
68 "r21",
69 "r22",
70 "r23",
71 "r24",
72 "r25",
73 "r26",
74 "r27",
75 "r28",
76 "r29",
77 "r30",
78 "r31"
79 };
80 #endif
81
82 static const int tcg_target_reg_alloc_order[] = {
83 TCG_REG_R14,
84 TCG_REG_R15,
85 TCG_REG_R16,
86 TCG_REG_R17,
87 TCG_REG_R18,
88 TCG_REG_R19,
89 TCG_REG_R20,
90 TCG_REG_R21,
91 TCG_REG_R22,
92 TCG_REG_R23,
93 TCG_REG_R28,
94 TCG_REG_R29,
95 TCG_REG_R30,
96 TCG_REG_R31,
97 #ifdef __APPLE__
98 TCG_REG_R2,
99 #endif
100 TCG_REG_R3,
101 TCG_REG_R4,
102 TCG_REG_R5,
103 TCG_REG_R6,
104 TCG_REG_R7,
105 TCG_REG_R8,
106 TCG_REG_R9,
107 TCG_REG_R10,
108 #ifndef __APPLE__
109 TCG_REG_R11,
110 #endif
111 TCG_REG_R12,
112 #ifndef __linux__
113 TCG_REG_R13,
114 #endif
115 TCG_REG_R24,
116 TCG_REG_R25,
117 TCG_REG_R26,
118 TCG_REG_R27
119 };
120
121 static const int tcg_target_call_iarg_regs[] = {
122 TCG_REG_R3,
123 TCG_REG_R4,
124 TCG_REG_R5,
125 TCG_REG_R6,
126 TCG_REG_R7,
127 TCG_REG_R8,
128 TCG_REG_R9,
129 TCG_REG_R10
130 };
131
132 static const int tcg_target_call_oarg_regs[2] = {
133 TCG_REG_R3,
134 TCG_REG_R4
135 };
136
137 static const int tcg_target_callee_save_regs[] = {
138 #ifdef __APPLE__
139 TCG_REG_R11,
140 TCG_REG_R13,
141 #endif
142 #ifdef _AIX
143 TCG_REG_R13,
144 #endif
145 TCG_REG_R14,
146 TCG_REG_R15,
147 TCG_REG_R16,
148 TCG_REG_R17,
149 TCG_REG_R18,
150 TCG_REG_R19,
151 TCG_REG_R20,
152 TCG_REG_R21,
153 TCG_REG_R22,
154 TCG_REG_R23,
155 TCG_REG_R24,
156 TCG_REG_R25,
157 TCG_REG_R26,
158 /* TCG_REG_R27, */ /* currently used for the global env, so no
159 need to save */
160 TCG_REG_R28,
161 TCG_REG_R29,
162 TCG_REG_R30,
163 TCG_REG_R31
164 };
165
166 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
167 {
168 tcg_target_long disp;
169
170 disp = target - (tcg_target_long) pc;
171 if ((disp << 6) >> 6 != disp)
172 tcg_abort ();
173
174 return disp & 0x3fffffc;
175 }
176
177 static void reloc_pc24 (void *pc, tcg_target_long target)
178 {
179 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
180 | reloc_pc24_val (pc, target);
181 }
182
183 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
184 {
185 tcg_target_long disp;
186
187 disp = target - (tcg_target_long) pc;
188 if (disp != (int16_t) disp)
189 tcg_abort ();
190
191 return disp & 0xfffc;
192 }
193
194 static void reloc_pc14 (void *pc, tcg_target_long target)
195 {
196 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
197 | reloc_pc14_val (pc, target);
198 }
199
200 static void patch_reloc(uint8_t *code_ptr, int type,
201 tcg_target_long value, tcg_target_long addend)
202 {
203 value += addend;
204 switch (type) {
205 case R_PPC_REL14:
206 reloc_pc14 (code_ptr, value);
207 break;
208 case R_PPC_REL24:
209 reloc_pc24 (code_ptr, value);
210 break;
211 default:
212 tcg_abort();
213 }
214 }
215
216 /* maximum number of register used for input function arguments */
217 static int tcg_target_get_call_iarg_regs_count(int flags)
218 {
219 return ARRAY_SIZE (tcg_target_call_iarg_regs);
220 }
221
222 /* parse target specific constraints */
223 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
224 {
225 const char *ct_str;
226
227 ct_str = *pct_str;
228 switch (ct_str[0]) {
229 case 'A': case 'B': case 'C': case 'D':
230 ct->ct |= TCG_CT_REG;
231 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
232 break;
233 case 'r':
234 ct->ct |= TCG_CT_REG;
235 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
236 break;
237 #ifdef CONFIG_SOFTMMU
238 case 'L': /* qemu_ld constraint */
239 ct->ct |= TCG_CT_REG;
240 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
242 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
243 break;
244 case 'K': /* qemu_st[8..32] constraint */
245 ct->ct |= TCG_CT_REG;
246 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
247 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
248 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
249 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
250 #if TARGET_LONG_BITS == 64
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
252 #endif
253 break;
254 case 'M': /* qemu_st64 constraint */
255 ct->ct |= TCG_CT_REG;
256 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
258 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
259 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
260 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
262 break;
263 #else
264 case 'L':
265 case 'K':
266 ct->ct |= TCG_CT_REG;
267 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
268 break;
269 case 'M':
270 ct->ct |= TCG_CT_REG;
271 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
272 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
273 break;
274 #endif
275 default:
276 return -1;
277 }
278 ct_str++;
279 *pct_str = ct_str;
280 return 0;
281 }
282
283 /* test if a constant matches the constraint */
284 static int tcg_target_const_match(tcg_target_long val,
285 const TCGArgConstraint *arg_ct)
286 {
287 int ct;
288
289 ct = arg_ct->ct;
290 if (ct & TCG_CT_CONST)
291 return 1;
292 return 0;
293 }
294
295 #define OPCD(opc) ((opc)<<26)
296 #define XO31(opc) (OPCD(31)|((opc)<<1))
297 #define XO19(opc) (OPCD(19)|((opc)<<1))
298
299 #define B OPCD(18)
300 #define BC OPCD(16)
301 #define LBZ OPCD(34)
302 #define LHZ OPCD(40)
303 #define LHA OPCD(42)
304 #define LWZ OPCD(32)
305 #define STB OPCD(38)
306 #define STH OPCD(44)
307 #define STW OPCD(36)
308
309 #define ADDI OPCD(14)
310 #define ADDIS OPCD(15)
311 #define ORI OPCD(24)
312 #define ORIS OPCD(25)
313 #define XORI OPCD(26)
314 #define XORIS OPCD(27)
315 #define ANDI OPCD(28)
316 #define ANDIS OPCD(29)
317 #define MULLI OPCD( 7)
318 #define CMPLI OPCD(10)
319 #define CMPI OPCD(11)
320
321 #define LWZU OPCD(33)
322 #define STWU OPCD(37)
323
324 #define RLWINM OPCD(21)
325
326 #define BCLR XO19( 16)
327 #define BCCTR XO19(528)
328 #define CRAND XO19(257)
329 #define CRANDC XO19(129)
330 #define CRNAND XO19(225)
331 #define CROR XO19(449)
332
333 #define EXTSB XO31(954)
334 #define EXTSH XO31(922)
335 #define ADD XO31(266)
336 #define ADDE XO31(138)
337 #define ADDC XO31( 10)
338 #define AND XO31( 28)
339 #define SUBF XO31( 40)
340 #define SUBFC XO31( 8)
341 #define SUBFE XO31(136)
342 #define OR XO31(444)
343 #define XOR XO31(316)
344 #define MULLW XO31(235)
345 #define MULHWU XO31( 11)
346 #define DIVW XO31(491)
347 #define DIVWU XO31(459)
348 #define CMP XO31( 0)
349 #define CMPL XO31( 32)
350 #define LHBRX XO31(790)
351 #define LWBRX XO31(534)
352 #define STHBRX XO31(918)
353 #define STWBRX XO31(662)
354 #define MFSPR XO31(339)
355 #define MTSPR XO31(467)
356 #define SRAWI XO31(824)
357 #define NEG XO31(104)
358
359 #define LBZX XO31( 87)
360 #define LHZX XO31(276)
361 #define LHAX XO31(343)
362 #define LWZX XO31( 23)
363 #define STBX XO31(215)
364 #define STHX XO31(407)
365 #define STWX XO31(151)
366
367 #define SPR(a,b) ((((a)<<5)|(b))<<11)
368 #define LR SPR(8, 0)
369 #define CTR SPR(9, 0)
370
371 #define SLW XO31( 24)
372 #define SRW XO31(536)
373 #define SRAW XO31(792)
374
375 #define LMW OPCD(46)
376 #define STMW OPCD(47)
377
378 #define TW XO31(4)
379 #define TRAP (TW | TO (31))
380
381 #define RT(r) ((r)<<21)
382 #define RS(r) ((r)<<21)
383 #define RA(r) ((r)<<16)
384 #define RB(r) ((r)<<11)
385 #define TO(t) ((t)<<21)
386 #define SH(s) ((s)<<11)
387 #define MB(b) ((b)<<6)
388 #define ME(e) ((e)<<1)
389 #define BO(o) ((o)<<21)
390
391 #define LK 1
392
393 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
394 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
395
396 #define BF(n) ((n)<<23)
397 #define BI(n, c) (((c)+((n)*4))<<16)
398 #define BT(n, c) (((c)+((n)*4))<<21)
399 #define BA(n, c) (((c)+((n)*4))<<16)
400 #define BB(n, c) (((c)+((n)*4))<<11)
401
402 #define BO_COND_TRUE BO (12)
403 #define BO_COND_FALSE BO (4)
404 #define BO_ALWAYS BO (20)
405
406 enum {
407 CR_LT,
408 CR_GT,
409 CR_EQ,
410 CR_SO
411 };
412
413 static const uint32_t tcg_to_bc[10] = {
414 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
415 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
416 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
417 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
418 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
419 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
420 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
421 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
422 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
423 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
424 };
425
426 static void tcg_out_mov(TCGContext *s, int ret, int arg)
427 {
428 tcg_out32 (s, OR | SAB (arg, ret, arg));
429 }
430
431 static void tcg_out_movi(TCGContext *s, TCGType type,
432 int ret, tcg_target_long arg)
433 {
434 if (arg == (int16_t) arg)
435 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
436 else {
437 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
438 if (arg & 0xffff)
439 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
440 }
441 }
442
443 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
444 int offset, int op1, int op2)
445 {
446 if (offset == (int16_t) offset)
447 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
448 else {
449 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
450 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
451 }
452 }
453
454 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
455 {
456 tcg_target_long disp;
457
458 disp = target - (tcg_target_long) s->code_ptr;
459 if ((disp << 6) >> 6 == disp)
460 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
461 else {
462 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
463 tcg_out32 (s, MTSPR | RS (0) | CTR);
464 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
465 }
466 }
467
468 #ifdef _AIX
469 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
470 {
471 int reg;
472
473 if (const_arg) {
474 reg = 2;
475 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
476 }
477 else reg = arg;
478
479 tcg_out32 (s, LWZ | RT (0) | RA (reg));
480 tcg_out32 (s, MTSPR | RA (0) | CTR);
481 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
482 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
483 }
484 #endif
485
486 #if defined(CONFIG_SOFTMMU)
487
488 #include "../../softmmu_defs.h"
489
490 static void *qemu_ld_helpers[4] = {
491 __ldb_mmu,
492 __ldw_mmu,
493 __ldl_mmu,
494 __ldq_mmu,
495 };
496
497 static void *qemu_st_helpers[4] = {
498 __stb_mmu,
499 __stw_mmu,
500 __stl_mmu,
501 __stq_mmu,
502 };
503 #endif
504
505 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
506 {
507 int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
508 #ifdef CONFIG_SOFTMMU
509 int r2;
510 void *label1_ptr, *label2_ptr;
511 #endif
512 #if TARGET_LONG_BITS == 64
513 int addr_reg2;
514 #endif
515
516 data_reg = *args++;
517 if (opc == 3)
518 data_reg2 = *args++;
519 else
520 data_reg2 = 0;
521 addr_reg = *args++;
522 #if TARGET_LONG_BITS == 64
523 addr_reg2 = *args++;
524 #endif
525 mem_index = *args;
526 s_bits = opc & 3;
527
528 #ifdef CONFIG_SOFTMMU
529 r0 = 3;
530 r1 = 4;
531 r2 = 0;
532
533 tcg_out32 (s, (RLWINM
534 | RA (r0)
535 | RS (addr_reg)
536 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
537 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
538 | ME (31 - CPU_TLB_ENTRY_BITS)
539 )
540 );
541 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
542 tcg_out32 (s, (LWZU
543 | RT (r1)
544 | RA (r0)
545 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
546 )
547 );
548 tcg_out32 (s, (RLWINM
549 | RA (r2)
550 | RS (addr_reg)
551 | SH (0)
552 | MB ((32 - s_bits) & 31)
553 | ME (31 - TARGET_PAGE_BITS)
554 )
555 );
556
557 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
558 #if TARGET_LONG_BITS == 64
559 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
560 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
561 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
562 #endif
563
564 label1_ptr = s->code_ptr;
565 #ifdef FAST_PATH
566 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
567 #endif
568
569 /* slow path */
570 #if TARGET_LONG_BITS == 32
571 tcg_out_mov (s, 3, addr_reg);
572 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
573 #else
574 tcg_out_mov (s, 3, addr_reg2);
575 tcg_out_mov (s, 4, addr_reg);
576 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
577 #endif
578
579 #ifdef _AIX
580 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
581 #else
582 tcg_out_b (s, LK, (tcg_target_long) qemu_ld_helpers[s_bits]);
583 #endif
584 switch (opc) {
585 case 0|4:
586 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
587 break;
588 case 1|4:
589 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
590 break;
591 case 0:
592 case 1:
593 case 2:
594 if (data_reg != 3)
595 tcg_out_mov (s, data_reg, 3);
596 break;
597 case 3:
598 if (data_reg == 3) {
599 if (data_reg2 == 4) {
600 tcg_out_mov (s, 0, 4);
601 tcg_out_mov (s, 4, 3);
602 tcg_out_mov (s, 3, 0);
603 }
604 else {
605 tcg_out_mov (s, data_reg2, 3);
606 tcg_out_mov (s, 3, 4);
607 }
608 }
609 else {
610 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
611 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
612 }
613 break;
614 }
615 label2_ptr = s->code_ptr;
616 tcg_out32 (s, B);
617
618 /* label1: fast path */
619 #ifdef FAST_PATH
620 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
621 #endif
622
623 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
624 tcg_out32 (s, (LWZ
625 | RT (r0)
626 | RA (r0)
627 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
628 - offsetof (CPUTLBEntry, addr_read))
629 ));
630 /* r0 = env->tlb_table[mem_index][index].addend */
631 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
632 /* r0 = env->tlb_table[mem_index][index].addend + addr */
633
634 #else /* !CONFIG_SOFTMMU */
635 r0 = addr_reg;
636 r1 = 3;
637 #endif
638
639 #ifdef TARGET_WORDS_BIGENDIAN
640 bswap = 0;
641 #else
642 bswap = 1;
643 #endif
644 switch (opc) {
645 default:
646 case 0:
647 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
648 break;
649 case 0|4:
650 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
651 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
652 break;
653 case 1:
654 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
655 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
656 break;
657 case 1|4:
658 if (bswap) {
659 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
660 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
661 }
662 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
663 break;
664 case 2:
665 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
666 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
667 break;
668 case 3:
669 if (bswap) {
670 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
671 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
672 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r1));
673 }
674 else {
675 if (r0 == data_reg2) {
676 tcg_out32 (s, LWZ | RT (0) | RA (r0));
677 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
678 tcg_out_mov (s, data_reg2, 0);
679 }
680 else {
681 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
682 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
683 }
684 }
685 break;
686 }
687
688 #ifdef CONFIG_SOFTMMU
689 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
690 #endif
691 }
692
693 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
694 {
695 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap;
696 #ifdef CONFIG_SOFTMMU
697 int r2, ir;
698 void *label1_ptr, *label2_ptr;
699 #endif
700 #if TARGET_LONG_BITS == 64
701 int addr_reg2;
702 #endif
703
704 data_reg = *args++;
705 if (opc == 3)
706 data_reg2 = *args++;
707 else
708 data_reg2 = 0;
709 addr_reg = *args++;
710 #if TARGET_LONG_BITS == 64
711 addr_reg2 = *args++;
712 #endif
713 mem_index = *args;
714
715 #ifdef CONFIG_SOFTMMU
716 r0 = 3;
717 r1 = 4;
718 r2 = 0;
719
720 tcg_out32 (s, (RLWINM
721 | RA (r0)
722 | RS (addr_reg)
723 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
724 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
725 | ME (31 - CPU_TLB_ENTRY_BITS)
726 )
727 );
728 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
729 tcg_out32 (s, (LWZU
730 | RT (r1)
731 | RA (r0)
732 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
733 )
734 );
735 tcg_out32 (s, (RLWINM
736 | RA (r2)
737 | RS (addr_reg)
738 | SH (0)
739 | MB ((32 - opc) & 31)
740 | ME (31 - TARGET_PAGE_BITS)
741 )
742 );
743
744 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
745 #if TARGET_LONG_BITS == 64
746 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
747 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
748 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
749 #endif
750
751 label1_ptr = s->code_ptr;
752 #ifdef FAST_PATH
753 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
754 #endif
755
756 /* slow path */
757 #if TARGET_LONG_BITS == 32
758 tcg_out_mov (s, 3, addr_reg);
759 ir = 4;
760 #else
761 tcg_out_mov (s, 3, addr_reg2);
762 tcg_out_mov (s, 4, addr_reg);
763 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
764 ir = 5;
765 #else
766 ir = 4;
767 #endif
768 #endif
769
770 switch (opc) {
771 case 0:
772 tcg_out32 (s, (RLWINM
773 | RA (ir)
774 | RS (data_reg)
775 | SH (0)
776 | MB (24)
777 | ME (31)));
778 break;
779 case 1:
780 tcg_out32 (s, (RLWINM
781 | RA (ir)
782 | RS (data_reg)
783 | SH (0)
784 | MB (16)
785 | ME (31)));
786 break;
787 case 2:
788 tcg_out_mov (s, ir, data_reg);
789 break;
790 case 3:
791 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
792 ir = 5;
793 #endif
794 tcg_out_mov (s, ir++, data_reg2);
795 tcg_out_mov (s, ir, data_reg);
796 break;
797 }
798 ir++;
799
800 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
801 #ifdef _AIX
802 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
803 #else
804 tcg_out_b (s, LK, (tcg_target_long) qemu_st_helpers[opc]);
805 #endif
806 label2_ptr = s->code_ptr;
807 tcg_out32 (s, B);
808
809 /* label1: fast path */
810 #ifdef FAST_PATH
811 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
812 #endif
813
814 tcg_out32 (s, (LWZ
815 | RT (r0)
816 | RA (r0)
817 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
818 - offsetof (CPUTLBEntry, addr_write))
819 ));
820 /* r0 = env->tlb_table[mem_index][index].addend */
821 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
822 /* r0 = env->tlb_table[mem_index][index].addend + addr */
823
824 #else /* !CONFIG_SOFTMMU */
825 r1 = 3;
826 r0 = addr_reg;
827 #endif
828
829 #ifdef TARGET_WORDS_BIGENDIAN
830 bswap = 0;
831 #else
832 bswap = 1;
833 #endif
834 switch (opc) {
835 case 0:
836 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
837 break;
838 case 1:
839 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
840 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
841 break;
842 case 2:
843 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
844 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
845 break;
846 case 3:
847 if (bswap) {
848 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
849 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
850 tcg_out32 (s, STWBRX | RS (data_reg2) | RA (0) | RB (r1));
851 }
852 else {
853 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
854 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
855 }
856 break;
857 }
858
859 #ifdef CONFIG_SOFTMMU
860 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
861 #endif
862 }
863
864 void tcg_target_qemu_prologue (TCGContext *s)
865 {
866 int i, frame_size;
867
868 frame_size = 0
869 + LINKAGE_AREA_SIZE
870 + TCG_STATIC_CALL_ARGS_SIZE
871 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
872 ;
873 frame_size = (frame_size + 15) & ~15;
874
875 #ifdef _AIX
876 {
877 uint32_t addr;
878
879 /* First emit adhoc function descriptor */
880 addr = (uint32_t) s->code_ptr + 12;
881 tcg_out32 (s, addr); /* entry point */
882 s->code_ptr += 8; /* skip TOC and environment pointer */
883 }
884 #endif
885 tcg_out32 (s, MFSPR | RT (0) | LR);
886 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
887 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
888 tcg_out32 (s, (STW
889 | RS (tcg_target_callee_save_regs[i])
890 | RA (1)
891 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
892 )
893 );
894 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
895
896 tcg_out32 (s, MTSPR | RS (3) | CTR);
897 tcg_out32 (s, BCCTR | BO_ALWAYS);
898 tb_ret_addr = s->code_ptr;
899
900 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
901 tcg_out32 (s, (LWZ
902 | RT (tcg_target_callee_save_regs[i])
903 | RA (1)
904 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
905 )
906 );
907 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
908 tcg_out32 (s, MTSPR | RS (0) | LR);
909 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
910 tcg_out32 (s, BCLR | BO_ALWAYS);
911 }
912
913 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
914 tcg_target_long arg2)
915 {
916 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
917 }
918
919 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
920 tcg_target_long arg2)
921 {
922 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
923 }
924
925 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
926 {
927 if (!si && rt == ra)
928 return;
929
930 if (si == (int16_t) si)
931 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
932 else {
933 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
934 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
935 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
936 }
937 }
938
939 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
940 {
941 ppc_addi (s, reg, reg, val);
942 }
943
944 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
945 int const_arg2, int cr)
946 {
947 int imm;
948 uint32_t op;
949
950 switch (cond) {
951 case TCG_COND_EQ:
952 case TCG_COND_NE:
953 if (const_arg2) {
954 if ((int16_t) arg2 == arg2) {
955 op = CMPI;
956 imm = 1;
957 break;
958 }
959 else if ((uint16_t) arg2 == arg2) {
960 op = CMPLI;
961 imm = 1;
962 break;
963 }
964 }
965 op = CMPL;
966 imm = 0;
967 break;
968
969 case TCG_COND_LT:
970 case TCG_COND_GE:
971 case TCG_COND_LE:
972 case TCG_COND_GT:
973 if (const_arg2) {
974 if ((int16_t) arg2 == arg2) {
975 op = CMPI;
976 imm = 1;
977 break;
978 }
979 }
980 op = CMP;
981 imm = 0;
982 break;
983
984 case TCG_COND_LTU:
985 case TCG_COND_GEU:
986 case TCG_COND_LEU:
987 case TCG_COND_GTU:
988 if (const_arg2) {
989 if ((uint16_t) arg2 == arg2) {
990 op = CMPLI;
991 imm = 1;
992 break;
993 }
994 }
995 op = CMPL;
996 imm = 0;
997 break;
998
999 default:
1000 tcg_abort ();
1001 }
1002 op |= BF (cr);
1003
1004 if (imm)
1005 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1006 else {
1007 if (const_arg2) {
1008 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1009 tcg_out32 (s, op | RA (arg1) | RB (0));
1010 }
1011 else
1012 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1013 }
1014
1015 }
1016
1017 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1018 {
1019 TCGLabel *l = &s->labels[label_index];
1020
1021 if (l->has_value)
1022 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1023 else {
1024 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1025
1026 /* Thanks to Andrzej Zaborowski */
1027 tcg_out32 (s, bc | (val & 0xfffc));
1028 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1029 }
1030 }
1031
1032 static void tcg_out_brcond (TCGContext *s, int cond,
1033 TCGArg arg1, TCGArg arg2, int const_arg2,
1034 int label_index)
1035 {
1036 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1037 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1038 }
1039
1040 /* XXX: we implement it at the target level to avoid having to
1041 handle cross basic blocks temporaries */
1042 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1043 const int *const_args)
1044 {
1045 int cond = args[4], label_index = args[5], op;
1046 struct { int bit1; int bit2; int cond2; } bits[] = {
1047 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1048 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1049 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1050 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1051 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1052 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1053 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1054 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1055 }, *b = &bits[cond];
1056
1057 switch (cond) {
1058 case TCG_COND_EQ:
1059 case TCG_COND_NE:
1060 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1061 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1062 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1063 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1064 break;
1065 case TCG_COND_LT:
1066 case TCG_COND_LE:
1067 case TCG_COND_GT:
1068 case TCG_COND_GE:
1069 case TCG_COND_LTU:
1070 case TCG_COND_LEU:
1071 case TCG_COND_GTU:
1072 case TCG_COND_GEU:
1073 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1074 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1075 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1076 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1077 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1078 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1079 break;
1080 default:
1081 tcg_abort();
1082 }
1083
1084 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), label_index);
1085 }
1086
1087 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1088 {
1089 uint32_t *ptr;
1090 long disp = addr - jmp_addr;
1091 unsigned long patch_size;
1092
1093 ptr = (uint32_t *)jmp_addr;
1094
1095 if ((disp << 6) >> 6 != disp) {
1096 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1097 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1098 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1099 ptr[3] = 0x4e800420; /* brctr */
1100 patch_size = 16;
1101 } else {
1102 /* patch the branch destination */
1103 if (disp != 16) {
1104 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1105 patch_size = 4;
1106 } else {
1107 ptr[0] = 0x60000000; /* nop */
1108 ptr[1] = 0x60000000;
1109 ptr[2] = 0x60000000;
1110 ptr[3] = 0x60000000;
1111 patch_size = 16;
1112 }
1113 }
1114 /* flush icache */
1115 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1116 }
1117
1118 static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1119 const int *const_args)
1120 {
1121 switch (opc) {
1122 case INDEX_op_exit_tb:
1123 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1124 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1125 break;
1126 case INDEX_op_goto_tb:
1127 if (s->tb_jmp_offset) {
1128 /* direct jump method */
1129
1130 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1131 s->code_ptr += 16;
1132 }
1133 else {
1134 tcg_abort ();
1135 }
1136 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1137 break;
1138 case INDEX_op_br:
1139 {
1140 TCGLabel *l = &s->labels[args[0]];
1141
1142 if (l->has_value) {
1143 tcg_out_b (s, 0, l->u.value);
1144 }
1145 else {
1146 uint32_t val = *(uint32_t *) s->code_ptr;
1147
1148 /* Thanks to Andrzej Zaborowski */
1149 tcg_out32 (s, B | (val & 0x3fffffc));
1150 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1151 }
1152 }
1153 break;
1154 case INDEX_op_call:
1155 #ifdef _AIX
1156 tcg_out_call (s, args[0], const_args[0]);
1157 #else
1158 if (const_args[0]) {
1159 tcg_out_b (s, LK, args[0]);
1160 }
1161 else {
1162 tcg_out32 (s, MTSPR | RS (args[0]) | LR);
1163 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
1164 }
1165 #endif
1166 break;
1167 case INDEX_op_jmp:
1168 if (const_args[0]) {
1169 tcg_out_b (s, 0, args[0]);
1170 }
1171 else {
1172 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1173 tcg_out32 (s, BCCTR | BO_ALWAYS);
1174 }
1175 break;
1176 case INDEX_op_movi_i32:
1177 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1178 break;
1179 case INDEX_op_ld8u_i32:
1180 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1181 break;
1182 case INDEX_op_ld8s_i32:
1183 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1184 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1185 break;
1186 case INDEX_op_ld16u_i32:
1187 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1188 break;
1189 case INDEX_op_ld16s_i32:
1190 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1191 break;
1192 case INDEX_op_ld_i32:
1193 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1194 break;
1195 case INDEX_op_st8_i32:
1196 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1197 break;
1198 case INDEX_op_st16_i32:
1199 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1200 break;
1201 case INDEX_op_st_i32:
1202 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1203 break;
1204
1205 case INDEX_op_add_i32:
1206 if (const_args[2])
1207 ppc_addi (s, args[0], args[1], args[2]);
1208 else
1209 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1210 break;
1211 case INDEX_op_sub_i32:
1212 if (const_args[2])
1213 ppc_addi (s, args[0], args[1], -args[2]);
1214 else
1215 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1216 break;
1217
1218 case INDEX_op_and_i32:
1219 if (const_args[2]) {
1220 if ((args[2] & 0xffff) == args[2])
1221 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1222 else if ((args[2] & 0xffff0000) == args[2])
1223 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1224 | ((args[2] >> 16) & 0xffff));
1225 else {
1226 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1227 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1228 }
1229 }
1230 else
1231 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1232 break;
1233 case INDEX_op_or_i32:
1234 if (const_args[2]) {
1235 if (args[2] & 0xffff) {
1236 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1237 | (args[2] & 0xffff));
1238 if (args[2] >> 16)
1239 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1240 | ((args[2] >> 16) & 0xffff));
1241 }
1242 else {
1243 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1244 | ((args[2] >> 16) & 0xffff));
1245 }
1246 }
1247 else
1248 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1249 break;
1250 case INDEX_op_xor_i32:
1251 if (const_args[2]) {
1252 if ((args[2] & 0xffff) == args[2])
1253 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1254 | (args[2] & 0xffff));
1255 else if ((args[2] & 0xffff0000) == args[2])
1256 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1257 | ((args[2] >> 16) & 0xffff));
1258 else {
1259 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1260 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1261 }
1262 }
1263 else
1264 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1265 break;
1266
1267 case INDEX_op_mul_i32:
1268 if (const_args[2]) {
1269 if (args[2] == (int16_t) args[2])
1270 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1271 | (args[2] & 0xffff));
1272 else {
1273 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1274 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1275 }
1276 }
1277 else
1278 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1279 break;
1280
1281 case INDEX_op_div_i32:
1282 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1283 break;
1284
1285 case INDEX_op_divu_i32:
1286 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1287 break;
1288
1289 case INDEX_op_rem_i32:
1290 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1291 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1292 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1293 break;
1294
1295 case INDEX_op_remu_i32:
1296 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1297 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1298 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1299 break;
1300
1301 case INDEX_op_mulu2_i32:
1302 if (args[0] == args[2] || args[0] == args[3]) {
1303 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1304 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1305 tcg_out_mov (s, args[0], 0);
1306 }
1307 else {
1308 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1309 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1310 }
1311 break;
1312
1313 case INDEX_op_shl_i32:
1314 if (const_args[2]) {
1315 tcg_out32 (s, (RLWINM
1316 | RA (args[0])
1317 | RS (args[1])
1318 | SH (args[2])
1319 | MB (0)
1320 | ME (31 - args[2])
1321 )
1322 );
1323 }
1324 else
1325 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1326 break;
1327 case INDEX_op_shr_i32:
1328 if (const_args[2]) {
1329 tcg_out32 (s, (RLWINM
1330 | RA (args[0])
1331 | RS (args[1])
1332 | SH (32 - args[2])
1333 | MB (args[2])
1334 | ME (31)
1335 )
1336 );
1337 }
1338 else
1339 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1340 break;
1341 case INDEX_op_sar_i32:
1342 if (const_args[2])
1343 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1344 else
1345 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1346 break;
1347
1348 case INDEX_op_add2_i32:
1349 if (args[0] == args[3] || args[0] == args[5]) {
1350 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1351 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1352 tcg_out_mov (s, args[0], 0);
1353 }
1354 else {
1355 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1356 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1357 }
1358 break;
1359 case INDEX_op_sub2_i32:
1360 if (args[0] == args[3] || args[0] == args[5]) {
1361 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1362 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1363 tcg_out_mov (s, args[0], 0);
1364 }
1365 else {
1366 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1367 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1368 }
1369 break;
1370
1371 case INDEX_op_brcond_i32:
1372 /*
1373 args[0] = r0
1374 args[1] = r1
1375 args[2] = cond
1376 args[3] = r1 is const
1377 args[4] = label_index
1378 */
1379 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1380 break;
1381 case INDEX_op_brcond2_i32:
1382 tcg_out_brcond2(s, args, const_args);
1383 break;
1384
1385 case INDEX_op_neg_i32:
1386 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1387 break;
1388
1389 case INDEX_op_qemu_ld8u:
1390 tcg_out_qemu_ld(s, args, 0);
1391 break;
1392 case INDEX_op_qemu_ld8s:
1393 tcg_out_qemu_ld(s, args, 0 | 4);
1394 break;
1395 case INDEX_op_qemu_ld16u:
1396 tcg_out_qemu_ld(s, args, 1);
1397 break;
1398 case INDEX_op_qemu_ld16s:
1399 tcg_out_qemu_ld(s, args, 1 | 4);
1400 break;
1401 case INDEX_op_qemu_ld32u:
1402 tcg_out_qemu_ld(s, args, 2);
1403 break;
1404 case INDEX_op_qemu_ld64:
1405 tcg_out_qemu_ld(s, args, 3);
1406 break;
1407 case INDEX_op_qemu_st8:
1408 tcg_out_qemu_st(s, args, 0);
1409 break;
1410 case INDEX_op_qemu_st16:
1411 tcg_out_qemu_st(s, args, 1);
1412 break;
1413 case INDEX_op_qemu_st32:
1414 tcg_out_qemu_st(s, args, 2);
1415 break;
1416 case INDEX_op_qemu_st64:
1417 tcg_out_qemu_st(s, args, 3);
1418 break;
1419
1420 case INDEX_op_ext8s_i32:
1421 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1422 break;
1423 case INDEX_op_ext16s_i32:
1424 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1425 break;
1426
1427 default:
1428 tcg_dump_ops (s, stderr);
1429 tcg_abort ();
1430 }
1431 }
1432
1433 static const TCGTargetOpDef ppc_op_defs[] = {
1434 { INDEX_op_exit_tb, { } },
1435 { INDEX_op_goto_tb, { } },
1436 { INDEX_op_call, { "ri" } },
1437 { INDEX_op_jmp, { "ri" } },
1438 { INDEX_op_br, { } },
1439
1440 { INDEX_op_mov_i32, { "r", "r" } },
1441 { INDEX_op_movi_i32, { "r" } },
1442 { INDEX_op_ld8u_i32, { "r", "r" } },
1443 { INDEX_op_ld8s_i32, { "r", "r" } },
1444 { INDEX_op_ld16u_i32, { "r", "r" } },
1445 { INDEX_op_ld16s_i32, { "r", "r" } },
1446 { INDEX_op_ld_i32, { "r", "r" } },
1447 { INDEX_op_st8_i32, { "r", "r" } },
1448 { INDEX_op_st16_i32, { "r", "r" } },
1449 { INDEX_op_st_i32, { "r", "r" } },
1450
1451 { INDEX_op_add_i32, { "r", "r", "ri" } },
1452 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1453 { INDEX_op_div_i32, { "r", "r", "r" } },
1454 { INDEX_op_divu_i32, { "r", "r", "r" } },
1455 { INDEX_op_rem_i32, { "r", "r", "r" } },
1456 { INDEX_op_remu_i32, { "r", "r", "r" } },
1457 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1458 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1459 { INDEX_op_and_i32, { "r", "r", "ri" } },
1460 { INDEX_op_or_i32, { "r", "r", "ri" } },
1461 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1462
1463 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1464 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1465 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1466
1467 { INDEX_op_brcond_i32, { "r", "ri" } },
1468
1469 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1470 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1471 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1472
1473 { INDEX_op_neg_i32, { "r", "r" } },
1474
1475 #if TARGET_LONG_BITS == 32
1476 { INDEX_op_qemu_ld8u, { "r", "L" } },
1477 { INDEX_op_qemu_ld8s, { "r", "L" } },
1478 { INDEX_op_qemu_ld16u, { "r", "L" } },
1479 { INDEX_op_qemu_ld16s, { "r", "L" } },
1480 { INDEX_op_qemu_ld32u, { "r", "L" } },
1481 { INDEX_op_qemu_ld32s, { "r", "L" } },
1482 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1483
1484 { INDEX_op_qemu_st8, { "K", "K" } },
1485 { INDEX_op_qemu_st16, { "K", "K" } },
1486 { INDEX_op_qemu_st32, { "K", "K" } },
1487 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1488 #else
1489 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1490 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1491 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1492 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1493 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1494 { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1495 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1496
1497 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1498 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1499 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1500 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1501 #endif
1502
1503 { INDEX_op_ext8s_i32, { "r", "r" } },
1504 { INDEX_op_ext16s_i32, { "r", "r" } },
1505
1506 { -1 },
1507 };
1508
1509 void tcg_target_init(TCGContext *s)
1510 {
1511 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1512 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1513 (1 << TCG_REG_R0) |
1514 #ifdef __APPLE__
1515 (1 << TCG_REG_R2) |
1516 #endif
1517 (1 << TCG_REG_R3) |
1518 (1 << TCG_REG_R4) |
1519 (1 << TCG_REG_R5) |
1520 (1 << TCG_REG_R6) |
1521 (1 << TCG_REG_R7) |
1522 (1 << TCG_REG_R8) |
1523 (1 << TCG_REG_R9) |
1524 (1 << TCG_REG_R10) |
1525 (1 << TCG_REG_R11) |
1526 (1 << TCG_REG_R12)
1527 );
1528
1529 tcg_regset_clear(s->reserved_regs);
1530 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1531 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1532 #ifndef __APPLE__
1533 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1534 #endif
1535 #ifdef __linux__
1536 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1537 #endif
1538
1539 tcg_add_target_add_op_defs(ppc_op_defs);
1540 }
Samsung s3c2440 and arm920t support for the mini2440 dev board