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Remove reserved registers from tcg_target_reg_alloc_order
[qemu/mini2440.git] / hw / sun4m.c
bloba459055704045ffd5957d2aeca4cd48a164c9379
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, args...) \
72 do { printf("CPUIRQ: " fmt , ##args); } while (0)
73 #else
74 #define DPRINTF(fmt, args...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 // Control plane, 8-bit and 24-bit planes
87 #define TCX_SIZE (9 * 1024 * 1024)
88
89 #define MAX_CPUS 16
90 #define MAX_PILS 16
91
92 #define ESCC_CLOCK 4915200
93
94 struct sun4m_hwdef {
95 target_phys_addr_t iommu_base, slavio_base;
96 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
97 target_phys_addr_t serial_base, fd_base;
98 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
99 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
100 target_phys_addr_t ecc_base;
101 uint32_t ecc_version;
102 long vram_size, nvram_size;
103 // IRQ numbers are not PIL ones, but master interrupt controller
104 // register bit numbers
105 int esp_irq, le_irq, clock_irq, clock1_irq;
106 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
107 uint8_t nvram_machine_id;
108 uint16_t machine_id;
109 uint32_t iommu_version;
110 uint32_t intbit_to_level[32];
111 uint64_t max_mem;
112 const char * const default_cpu_model;
113 };
114
115 #define MAX_IOUNITS 5
116
117 struct sun4d_hwdef {
118 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
119 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
120 target_phys_addr_t serial_base;
121 target_phys_addr_t espdma_base, esp_base;
122 target_phys_addr_t ledma_base, le_base;
123 target_phys_addr_t tcx_base;
124 target_phys_addr_t sbi_base;
125 unsigned long vram_size, nvram_size;
126 // IRQ numbers are not PIL ones, but SBI register bit numbers
127 int esp_irq, le_irq, clock_irq, clock1_irq;
128 int ser_irq, ms_kb_irq, me_irq;
129 uint8_t nvram_machine_id;
130 uint16_t machine_id;
131 uint32_t iounit_version;
132 uint64_t max_mem;
133 const char * const default_cpu_model;
134 };
135
136 struct sun4c_hwdef {
137 target_phys_addr_t iommu_base, slavio_base;
138 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
139 target_phys_addr_t serial_base, fd_base;
140 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
141 target_phys_addr_t tcx_base, aux1_base;
142 long vram_size, nvram_size;
143 // IRQ numbers are not PIL ones, but master interrupt controller
144 // register bit numbers
145 int esp_irq, le_irq, clock_irq, clock1_irq;
146 int ser_irq, ms_kb_irq, fd_irq, me_irq;
147 uint8_t nvram_machine_id;
148 uint16_t machine_id;
149 uint32_t iommu_version;
150 uint32_t intbit_to_level[32];
151 uint64_t max_mem;
152 const char * const default_cpu_model;
153 };
154
155 int DMA_get_channel_mode (int nchan)
156 {
157 return 0;
158 }
159 int DMA_read_memory (int nchan, void *buf, int pos, int size)
160 {
161 return 0;
162 }
163 int DMA_write_memory (int nchan, void *buf, int pos, int size)
164 {
165 return 0;
166 }
167 void DMA_hold_DREQ (int nchan) {}
168 void DMA_release_DREQ (int nchan) {}
169 void DMA_schedule(int nchan) {}
170 void DMA_init (int high_page_enable) {}
171 void DMA_register_channel (int nchan,
172 DMA_transfer_handler transfer_handler,
173 void *opaque)
174 {
175 }
176
177 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
178 {
179 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
180 return 0;
181 }
182
183 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
184 const char *boot_devices, ram_addr_t RAM_size,
185 uint32_t kernel_size,
186 int width, int height, int depth,
187 int nvram_machine_id, const char *arch)
188 {
189 unsigned int i;
190 uint32_t start, end;
191 uint8_t image[0x1ff0];
192 struct OpenBIOS_nvpart_v1 *part_header;
193
194 memset(image, '\0', sizeof(image));
195
196 start = 0;
197
198 // OpenBIOS nvram variables
199 // Variable partition
200 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
201 part_header->signature = OPENBIOS_PART_SYSTEM;
202 pstrcpy(part_header->name, sizeof(part_header->name), "system");
203
204 end = start + sizeof(struct OpenBIOS_nvpart_v1);
205 for (i = 0; i < nb_prom_envs; i++)
206 end = OpenBIOS_set_var(image, end, prom_envs[i]);
207
208 // End marker
209 image[end++] = '\0';
210
211 end = start + ((end - start + 15) & ~15);
212 OpenBIOS_finish_partition(part_header, end - start);
213
214 // free partition
215 start = end;
216 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
217 part_header->signature = OPENBIOS_PART_FREE;
218 pstrcpy(part_header->name, sizeof(part_header->name), "free");
219
220 end = 0x1fd0;
221 OpenBIOS_finish_partition(part_header, end - start);
222
223 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
224 nvram_machine_id);
225
226 for (i = 0; i < sizeof(image); i++)
227 m48t59_write(nvram, i, image[i]);
228 }
229
230 static void *slavio_intctl;
231
232 void pic_info(Monitor *mon)
233 {
234 if (slavio_intctl)
235 slavio_pic_info(mon, slavio_intctl);
236 }
237
238 void irq_info(Monitor *mon)
239 {
240 if (slavio_intctl)
241 slavio_irq_info(mon, slavio_intctl);
242 }
243
244 void cpu_check_irqs(CPUState *env)
245 {
246 if (env->pil_in && (env->interrupt_index == 0 ||
247 (env->interrupt_index & ~15) == TT_EXTINT)) {
248 unsigned int i;
249
250 for (i = 15; i > 0; i--) {
251 if (env->pil_in & (1 << i)) {
252 int old_interrupt = env->interrupt_index;
253
254 env->interrupt_index = TT_EXTINT | i;
255 if (old_interrupt != env->interrupt_index) {
256 DPRINTF("Set CPU IRQ %d\n", i);
257 cpu_interrupt(env, CPU_INTERRUPT_HARD);
258 }
259 break;
260 }
261 }
262 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
263 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
264 env->interrupt_index = 0;
265 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
266 }
267 }
268
269 static void cpu_set_irq(void *opaque, int irq, int level)
270 {
271 CPUState *env = opaque;
272
273 if (level) {
274 DPRINTF("Raise CPU IRQ %d\n", irq);
275 env->halted = 0;
276 env->pil_in |= 1 << irq;
277 cpu_check_irqs(env);
278 } else {
279 DPRINTF("Lower CPU IRQ %d\n", irq);
280 env->pil_in &= ~(1 << irq);
281 cpu_check_irqs(env);
282 }
283 }
284
285 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
286 {
287 }
288
289 static void *slavio_misc;
290
291 void qemu_system_powerdown(void)
292 {
293 slavio_set_power_fail(slavio_misc, 1);
294 }
295
296 static void main_cpu_reset(void *opaque)
297 {
298 CPUState *env = opaque;
299
300 cpu_reset(env);
301 env->halted = 0;
302 }
303
304 static void secondary_cpu_reset(void *opaque)
305 {
306 CPUState *env = opaque;
307
308 cpu_reset(env);
309 env->halted = 1;
310 }
311
312 static void cpu_halt_signal(void *opaque, int irq, int level)
313 {
314 if (level && cpu_single_env)
315 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
316 }
317
318 static unsigned long sun4m_load_kernel(const char *kernel_filename,
319 const char *initrd_filename,
320 ram_addr_t RAM_size)
321 {
322 int linux_boot;
323 unsigned int i;
324 long initrd_size, kernel_size;
325
326 linux_boot = (kernel_filename != NULL);
327
328 kernel_size = 0;
329 if (linux_boot) {
330 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
331 NULL);
332 if (kernel_size < 0)
333 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
334 RAM_size - KERNEL_LOAD_ADDR);
335 if (kernel_size < 0)
336 kernel_size = load_image_targphys(kernel_filename,
337 KERNEL_LOAD_ADDR,
338 RAM_size - KERNEL_LOAD_ADDR);
339 if (kernel_size < 0) {
340 fprintf(stderr, "qemu: could not load kernel '%s'\n",
341 kernel_filename);
342 exit(1);
343 }
344
345 /* load initrd */
346 initrd_size = 0;
347 if (initrd_filename) {
348 initrd_size = load_image_targphys(initrd_filename,
349 INITRD_LOAD_ADDR,
350 RAM_size - INITRD_LOAD_ADDR);
351 if (initrd_size < 0) {
352 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353 initrd_filename);
354 exit(1);
355 }
356 }
357 if (initrd_size > 0) {
358 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
359 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
360 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
361 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
362 break;
363 }
364 }
365 }
366 }
367 return kernel_size;
368 }
369
370 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
371 const char *boot_device,
372 const char *kernel_filename,
373 const char *kernel_cmdline,
374 const char *initrd_filename, const char *cpu_model)
375
376 {
377 CPUState *env, *envs[MAX_CPUS];
378 unsigned int i;
379 void *iommu, *espdma, *ledma, *main_esp, *nvram;
380 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
381 *espdma_irq, *ledma_irq;
382 qemu_irq *esp_reset, *le_reset;
383 qemu_irq *fdc_tc;
384 qemu_irq *cpu_halt;
385 ram_addr_t ram_offset, prom_offset, idreg_offset;
386 unsigned long kernel_size;
387 int ret;
388 char buf[1024];
389 BlockDriverState *fd[MAX_FD];
390 int drive_index;
391 void *fw_cfg;
392
393 /* init CPUs */
394 if (!cpu_model)
395 cpu_model = hwdef->default_cpu_model;
396
397 for(i = 0; i < smp_cpus; i++) {
398 env = cpu_init(cpu_model);
399 if (!env) {
400 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
401 exit(1);
402 }
403 cpu_sparc_set_id(env, i);
404 envs[i] = env;
405 if (i == 0) {
406 qemu_register_reset(main_cpu_reset, env);
407 } else {
408 qemu_register_reset(secondary_cpu_reset, env);
409 env->halted = 1;
410 }
411 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
412 env->prom_addr = hwdef->slavio_base;
413 }
414
415 for (i = smp_cpus; i < MAX_CPUS; i++)
416 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
417
418
419 /* allocate RAM */
420 if ((uint64_t)RAM_size > hwdef->max_mem) {
421 fprintf(stderr,
422 "qemu: Too much memory for this machine: %d, maximum %d\n",
423 (unsigned int)(RAM_size / (1024 * 1024)),
424 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
425 exit(1);
426 }
427 ram_offset = qemu_ram_alloc(RAM_size);
428 cpu_register_physical_memory(0, RAM_size, ram_offset);
429
430 /* load boot prom */
431 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
432 cpu_register_physical_memory(hwdef->slavio_base,
433 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
434 TARGET_PAGE_MASK,
435 prom_offset | IO_MEM_ROM);
436
437 if (bios_name == NULL)
438 bios_name = PROM_FILENAME;
439 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
440 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
441 if (ret < 0 || ret > PROM_SIZE_MAX)
442 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
443 if (ret < 0 || ret > PROM_SIZE_MAX) {
444 fprintf(stderr, "qemu: could not load prom '%s'\n",
445 buf);
446 exit(1);
447 }
448
449 /* set up devices */
450 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
451 hwdef->intctl_base + 0x10000ULL,
452 &hwdef->intbit_to_level[0],
453 &slavio_irq, &slavio_cpu_irq,
454 cpu_irqs,
455 hwdef->clock_irq);
456
457 if (hwdef->idreg_base) {
458 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
459
460 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
461 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
462 idreg_offset | IO_MEM_ROM);
463 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
464 sizeof(idreg_data));
465 }
466
467 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
468 slavio_irq[hwdef->me_irq]);
469
470 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
471 iommu, &espdma_irq, &esp_reset);
472
473 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
474 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
475 &le_reset);
476
477 if (graphic_depth != 8 && graphic_depth != 24) {
478 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
479 exit (1);
480 }
481 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
482 graphic_depth);
483
484 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
485
486 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
487 hwdef->nvram_size, 8);
488
489 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
490 slavio_cpu_irq, smp_cpus);
491
492 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
493 nographic, ESCC_CLOCK, 1);
494 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
495 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
496 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
497 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
498
499 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
500 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
501 hwdef->aux1_base, hwdef->aux2_base,
502 slavio_irq[hwdef->me_irq], cpu_halt[0],
503 &fdc_tc);
504
505 if (hwdef->fd_base) {
506 /* there is zero or one floppy drive */
507 memset(fd, 0, sizeof(fd));
508 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
509 if (drive_index != -1)
510 fd[0] = drives_table[drive_index].bdrv;
511
512 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
513 fdc_tc);
514 }
515
516 if (drive_get_max_bus(IF_SCSI) > 0) {
517 fprintf(stderr, "qemu: too many SCSI bus\n");
518 exit(1);
519 }
520
521 main_esp = esp_init(hwdef->esp_base, 2,
522 espdma_memory_read, espdma_memory_write,
523 espdma, *espdma_irq, esp_reset);
524
525 for (i = 0; i < ESP_MAX_DEVS; i++) {
526 drive_index = drive_get_index(IF_SCSI, 0, i);
527 if (drive_index == -1)
528 continue;
529 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
530 }
531
532 if (hwdef->cs_base)
533 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
534
535 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
536 RAM_size);
537
538 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
539 boot_device, RAM_size, kernel_size, graphic_width,
540 graphic_height, graphic_depth, hwdef->nvram_machine_id,
541 "Sun4m");
542
543 if (hwdef->ecc_base)
544 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
545 hwdef->ecc_version);
546
547 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
548 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
549 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
550 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
551 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
552 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
553 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
554 if (kernel_cmdline) {
555 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
556 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
557 } else {
558 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
559 }
560 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
561 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
562 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
563 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
564 }
565
566 enum {
567 ss2_id = 0,
568 ss5_id = 32,
569 vger_id,
570 lx_id,
571 ss4_id,
572 scls_id,
573 sbook_id,
574 ss10_id = 64,
575 ss20_id,
576 ss600mp_id,
577 ss1000_id = 96,
578 ss2000_id,
579 };
580
581 static const struct sun4m_hwdef sun4m_hwdefs[] = {
582 /* SS-5 */
583 {
584 .iommu_base = 0x10000000,
585 .tcx_base = 0x50000000,
586 .cs_base = 0x6c000000,
587 .slavio_base = 0x70000000,
588 .ms_kb_base = 0x71000000,
589 .serial_base = 0x71100000,
590 .nvram_base = 0x71200000,
591 .fd_base = 0x71400000,
592 .counter_base = 0x71d00000,
593 .intctl_base = 0x71e00000,
594 .idreg_base = 0x78000000,
595 .dma_base = 0x78400000,
596 .esp_base = 0x78800000,
597 .le_base = 0x78c00000,
598 .apc_base = 0x6a000000,
599 .aux1_base = 0x71900000,
600 .aux2_base = 0x71910000,
601 .vram_size = 0x00100000,
602 .nvram_size = 0x2000,
603 .esp_irq = 18,
604 .le_irq = 16,
605 .clock_irq = 7,
606 .clock1_irq = 19,
607 .ms_kb_irq = 14,
608 .ser_irq = 15,
609 .fd_irq = 22,
610 .me_irq = 30,
611 .cs_irq = 5,
612 .nvram_machine_id = 0x80,
613 .machine_id = ss5_id,
614 .iommu_version = 0x05000000,
615 .intbit_to_level = {
616 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
617 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
618 },
619 .max_mem = 0x10000000,
620 .default_cpu_model = "Fujitsu MB86904",
621 },
622 /* SS-10 */
623 {
624 .iommu_base = 0xfe0000000ULL,
625 .tcx_base = 0xe20000000ULL,
626 .slavio_base = 0xff0000000ULL,
627 .ms_kb_base = 0xff1000000ULL,
628 .serial_base = 0xff1100000ULL,
629 .nvram_base = 0xff1200000ULL,
630 .fd_base = 0xff1700000ULL,
631 .counter_base = 0xff1300000ULL,
632 .intctl_base = 0xff1400000ULL,
633 .idreg_base = 0xef0000000ULL,
634 .dma_base = 0xef0400000ULL,
635 .esp_base = 0xef0800000ULL,
636 .le_base = 0xef0c00000ULL,
637 .apc_base = 0xefa000000ULL, // XXX should not exist
638 .aux1_base = 0xff1800000ULL,
639 .aux2_base = 0xff1a01000ULL,
640 .ecc_base = 0xf00000000ULL,
641 .ecc_version = 0x10000000, // version 0, implementation 1
642 .vram_size = 0x00100000,
643 .nvram_size = 0x2000,
644 .esp_irq = 18,
645 .le_irq = 16,
646 .clock_irq = 7,
647 .clock1_irq = 19,
648 .ms_kb_irq = 14,
649 .ser_irq = 15,
650 .fd_irq = 22,
651 .me_irq = 30,
652 .ecc_irq = 28,
653 .nvram_machine_id = 0x72,
654 .machine_id = ss10_id,
655 .iommu_version = 0x03000000,
656 .intbit_to_level = {
657 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
658 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
659 },
660 .max_mem = 0xf00000000ULL,
661 .default_cpu_model = "TI SuperSparc II",
662 },
663 /* SS-600MP */
664 {
665 .iommu_base = 0xfe0000000ULL,
666 .tcx_base = 0xe20000000ULL,
667 .slavio_base = 0xff0000000ULL,
668 .ms_kb_base = 0xff1000000ULL,
669 .serial_base = 0xff1100000ULL,
670 .nvram_base = 0xff1200000ULL,
671 .counter_base = 0xff1300000ULL,
672 .intctl_base = 0xff1400000ULL,
673 .dma_base = 0xef0081000ULL,
674 .esp_base = 0xef0080000ULL,
675 .le_base = 0xef0060000ULL,
676 .apc_base = 0xefa000000ULL, // XXX should not exist
677 .aux1_base = 0xff1800000ULL,
678 .aux2_base = 0xff1a01000ULL, // XXX should not exist
679 .ecc_base = 0xf00000000ULL,
680 .ecc_version = 0x00000000, // version 0, implementation 0
681 .vram_size = 0x00100000,
682 .nvram_size = 0x2000,
683 .esp_irq = 18,
684 .le_irq = 16,
685 .clock_irq = 7,
686 .clock1_irq = 19,
687 .ms_kb_irq = 14,
688 .ser_irq = 15,
689 .fd_irq = 22,
690 .me_irq = 30,
691 .ecc_irq = 28,
692 .nvram_machine_id = 0x71,
693 .machine_id = ss600mp_id,
694 .iommu_version = 0x01000000,
695 .intbit_to_level = {
696 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
697 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
698 },
699 .max_mem = 0xf00000000ULL,
700 .default_cpu_model = "TI SuperSparc II",
701 },
702 /* SS-20 */
703 {
704 .iommu_base = 0xfe0000000ULL,
705 .tcx_base = 0xe20000000ULL,
706 .slavio_base = 0xff0000000ULL,
707 .ms_kb_base = 0xff1000000ULL,
708 .serial_base = 0xff1100000ULL,
709 .nvram_base = 0xff1200000ULL,
710 .fd_base = 0xff1700000ULL,
711 .counter_base = 0xff1300000ULL,
712 .intctl_base = 0xff1400000ULL,
713 .idreg_base = 0xef0000000ULL,
714 .dma_base = 0xef0400000ULL,
715 .esp_base = 0xef0800000ULL,
716 .le_base = 0xef0c00000ULL,
717 .apc_base = 0xefa000000ULL, // XXX should not exist
718 .aux1_base = 0xff1800000ULL,
719 .aux2_base = 0xff1a01000ULL,
720 .ecc_base = 0xf00000000ULL,
721 .ecc_version = 0x20000000, // version 0, implementation 2
722 .vram_size = 0x00100000,
723 .nvram_size = 0x2000,
724 .esp_irq = 18,
725 .le_irq = 16,
726 .clock_irq = 7,
727 .clock1_irq = 19,
728 .ms_kb_irq = 14,
729 .ser_irq = 15,
730 .fd_irq = 22,
731 .me_irq = 30,
732 .ecc_irq = 28,
733 .nvram_machine_id = 0x72,
734 .machine_id = ss20_id,
735 .iommu_version = 0x13000000,
736 .intbit_to_level = {
737 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
738 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
739 },
740 .max_mem = 0xf00000000ULL,
741 .default_cpu_model = "TI SuperSparc II",
742 },
743 /* Voyager */
744 {
745 .iommu_base = 0x10000000,
746 .tcx_base = 0x50000000,
747 .slavio_base = 0x70000000,
748 .ms_kb_base = 0x71000000,
749 .serial_base = 0x71100000,
750 .nvram_base = 0x71200000,
751 .fd_base = 0x71400000,
752 .counter_base = 0x71d00000,
753 .intctl_base = 0x71e00000,
754 .idreg_base = 0x78000000,
755 .dma_base = 0x78400000,
756 .esp_base = 0x78800000,
757 .le_base = 0x78c00000,
758 .apc_base = 0x71300000, // pmc
759 .aux1_base = 0x71900000,
760 .aux2_base = 0x71910000,
761 .vram_size = 0x00100000,
762 .nvram_size = 0x2000,
763 .esp_irq = 18,
764 .le_irq = 16,
765 .clock_irq = 7,
766 .clock1_irq = 19,
767 .ms_kb_irq = 14,
768 .ser_irq = 15,
769 .fd_irq = 22,
770 .me_irq = 30,
771 .nvram_machine_id = 0x80,
772 .machine_id = vger_id,
773 .iommu_version = 0x05000000,
774 .intbit_to_level = {
775 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
776 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
777 },
778 .max_mem = 0x10000000,
779 .default_cpu_model = "Fujitsu MB86904",
780 },
781 /* LX */
782 {
783 .iommu_base = 0x10000000,
784 .tcx_base = 0x50000000,
785 .slavio_base = 0x70000000,
786 .ms_kb_base = 0x71000000,
787 .serial_base = 0x71100000,
788 .nvram_base = 0x71200000,
789 .fd_base = 0x71400000,
790 .counter_base = 0x71d00000,
791 .intctl_base = 0x71e00000,
792 .idreg_base = 0x78000000,
793 .dma_base = 0x78400000,
794 .esp_base = 0x78800000,
795 .le_base = 0x78c00000,
796 .aux1_base = 0x71900000,
797 .aux2_base = 0x71910000,
798 .vram_size = 0x00100000,
799 .nvram_size = 0x2000,
800 .esp_irq = 18,
801 .le_irq = 16,
802 .clock_irq = 7,
803 .clock1_irq = 19,
804 .ms_kb_irq = 14,
805 .ser_irq = 15,
806 .fd_irq = 22,
807 .me_irq = 30,
808 .nvram_machine_id = 0x80,
809 .machine_id = lx_id,
810 .iommu_version = 0x04000000,
811 .intbit_to_level = {
812 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
813 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
814 },
815 .max_mem = 0x10000000,
816 .default_cpu_model = "TI MicroSparc I",
817 },
818 /* SS-4 */
819 {
820 .iommu_base = 0x10000000,
821 .tcx_base = 0x50000000,
822 .cs_base = 0x6c000000,
823 .slavio_base = 0x70000000,
824 .ms_kb_base = 0x71000000,
825 .serial_base = 0x71100000,
826 .nvram_base = 0x71200000,
827 .fd_base = 0x71400000,
828 .counter_base = 0x71d00000,
829 .intctl_base = 0x71e00000,
830 .idreg_base = 0x78000000,
831 .dma_base = 0x78400000,
832 .esp_base = 0x78800000,
833 .le_base = 0x78c00000,
834 .apc_base = 0x6a000000,
835 .aux1_base = 0x71900000,
836 .aux2_base = 0x71910000,
837 .vram_size = 0x00100000,
838 .nvram_size = 0x2000,
839 .esp_irq = 18,
840 .le_irq = 16,
841 .clock_irq = 7,
842 .clock1_irq = 19,
843 .ms_kb_irq = 14,
844 .ser_irq = 15,
845 .fd_irq = 22,
846 .me_irq = 30,
847 .cs_irq = 5,
848 .nvram_machine_id = 0x80,
849 .machine_id = ss4_id,
850 .iommu_version = 0x05000000,
851 .intbit_to_level = {
852 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
853 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
854 },
855 .max_mem = 0x10000000,
856 .default_cpu_model = "Fujitsu MB86904",
857 },
858 /* SPARCClassic */
859 {
860 .iommu_base = 0x10000000,
861 .tcx_base = 0x50000000,
862 .slavio_base = 0x70000000,
863 .ms_kb_base = 0x71000000,
864 .serial_base = 0x71100000,
865 .nvram_base = 0x71200000,
866 .fd_base = 0x71400000,
867 .counter_base = 0x71d00000,
868 .intctl_base = 0x71e00000,
869 .idreg_base = 0x78000000,
870 .dma_base = 0x78400000,
871 .esp_base = 0x78800000,
872 .le_base = 0x78c00000,
873 .apc_base = 0x6a000000,
874 .aux1_base = 0x71900000,
875 .aux2_base = 0x71910000,
876 .vram_size = 0x00100000,
877 .nvram_size = 0x2000,
878 .esp_irq = 18,
879 .le_irq = 16,
880 .clock_irq = 7,
881 .clock1_irq = 19,
882 .ms_kb_irq = 14,
883 .ser_irq = 15,
884 .fd_irq = 22,
885 .me_irq = 30,
886 .nvram_machine_id = 0x80,
887 .machine_id = scls_id,
888 .iommu_version = 0x05000000,
889 .intbit_to_level = {
890 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
891 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
892 },
893 .max_mem = 0x10000000,
894 .default_cpu_model = "TI MicroSparc I",
895 },
896 /* SPARCbook */
897 {
898 .iommu_base = 0x10000000,
899 .tcx_base = 0x50000000, // XXX
900 .slavio_base = 0x70000000,
901 .ms_kb_base = 0x71000000,
902 .serial_base = 0x71100000,
903 .nvram_base = 0x71200000,
904 .fd_base = 0x71400000,
905 .counter_base = 0x71d00000,
906 .intctl_base = 0x71e00000,
907 .idreg_base = 0x78000000,
908 .dma_base = 0x78400000,
909 .esp_base = 0x78800000,
910 .le_base = 0x78c00000,
911 .apc_base = 0x6a000000,
912 .aux1_base = 0x71900000,
913 .aux2_base = 0x71910000,
914 .vram_size = 0x00100000,
915 .nvram_size = 0x2000,
916 .esp_irq = 18,
917 .le_irq = 16,
918 .clock_irq = 7,
919 .clock1_irq = 19,
920 .ms_kb_irq = 14,
921 .ser_irq = 15,
922 .fd_irq = 22,
923 .me_irq = 30,
924 .nvram_machine_id = 0x80,
925 .machine_id = sbook_id,
926 .iommu_version = 0x05000000,
927 .intbit_to_level = {
928 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
929 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
930 },
931 .max_mem = 0x10000000,
932 .default_cpu_model = "TI MicroSparc I",
933 },
934 };
935
936 /* SPARCstation 5 hardware initialisation */
937 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
938 const char *boot_device,
939 const char *kernel_filename, const char *kernel_cmdline,
940 const char *initrd_filename, const char *cpu_model)
941 {
942 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
943 kernel_cmdline, initrd_filename, cpu_model);
944 }
945
946 /* SPARCstation 10 hardware initialisation */
947 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
948 const char *boot_device,
949 const char *kernel_filename, const char *kernel_cmdline,
950 const char *initrd_filename, const char *cpu_model)
951 {
952 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
953 kernel_cmdline, initrd_filename, cpu_model);
954 }
955
956 /* SPARCserver 600MP hardware initialisation */
957 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
958 const char *boot_device,
959 const char *kernel_filename,
960 const char *kernel_cmdline,
961 const char *initrd_filename, const char *cpu_model)
962 {
963 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
964 kernel_cmdline, initrd_filename, cpu_model);
965 }
966
967 /* SPARCstation 20 hardware initialisation */
968 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
969 const char *boot_device,
970 const char *kernel_filename, const char *kernel_cmdline,
971 const char *initrd_filename, const char *cpu_model)
972 {
973 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
974 kernel_cmdline, initrd_filename, cpu_model);
975 }
976
977 /* SPARCstation Voyager hardware initialisation */
978 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
979 const char *boot_device,
980 const char *kernel_filename, const char *kernel_cmdline,
981 const char *initrd_filename, const char *cpu_model)
982 {
983 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
984 kernel_cmdline, initrd_filename, cpu_model);
985 }
986
987 /* SPARCstation LX hardware initialisation */
988 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
989 const char *boot_device,
990 const char *kernel_filename, const char *kernel_cmdline,
991 const char *initrd_filename, const char *cpu_model)
992 {
993 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
994 kernel_cmdline, initrd_filename, cpu_model);
995 }
996
997 /* SPARCstation 4 hardware initialisation */
998 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
999 const char *boot_device,
1000 const char *kernel_filename, const char *kernel_cmdline,
1001 const char *initrd_filename, const char *cpu_model)
1002 {
1003 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1004 kernel_cmdline, initrd_filename, cpu_model);
1005 }
1006
1007 /* SPARCClassic hardware initialisation */
1008 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1009 const char *boot_device,
1010 const char *kernel_filename, const char *kernel_cmdline,
1011 const char *initrd_filename, const char *cpu_model)
1012 {
1013 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1014 kernel_cmdline, initrd_filename, cpu_model);
1015 }
1016
1017 /* SPARCbook hardware initialisation */
1018 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1019 const char *boot_device,
1020 const char *kernel_filename, const char *kernel_cmdline,
1021 const char *initrd_filename, const char *cpu_model)
1022 {
1023 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1024 kernel_cmdline, initrd_filename, cpu_model);
1025 }
1026
1027 QEMUMachine ss5_machine = {
1028 .name = "SS-5",
1029 .desc = "Sun4m platform, SPARCstation 5",
1030 .init = ss5_init,
1031 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1032 .use_scsi = 1,
1033 };
1034
1035 QEMUMachine ss10_machine = {
1036 .name = "SS-10",
1037 .desc = "Sun4m platform, SPARCstation 10",
1038 .init = ss10_init,
1039 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1040 .use_scsi = 1,
1041 .max_cpus = 4,
1042 };
1043
1044 QEMUMachine ss600mp_machine = {
1045 .name = "SS-600MP",
1046 .desc = "Sun4m platform, SPARCserver 600MP",
1047 .init = ss600mp_init,
1048 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1049 .use_scsi = 1,
1050 .max_cpus = 4,
1051 };
1052
1053 QEMUMachine ss20_machine = {
1054 .name = "SS-20",
1055 .desc = "Sun4m platform, SPARCstation 20",
1056 .init = ss20_init,
1057 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1058 .use_scsi = 1,
1059 .max_cpus = 4,
1060 };
1061
1062 QEMUMachine voyager_machine = {
1063 .name = "Voyager",
1064 .desc = "Sun4m platform, SPARCstation Voyager",
1065 .init = vger_init,
1066 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1067 .use_scsi = 1,
1068 };
1069
1070 QEMUMachine ss_lx_machine = {
1071 .name = "LX",
1072 .desc = "Sun4m platform, SPARCstation LX",
1073 .init = ss_lx_init,
1074 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1075 .use_scsi = 1,
1076 };
1077
1078 QEMUMachine ss4_machine = {
1079 .name = "SS-4",
1080 .desc = "Sun4m platform, SPARCstation 4",
1081 .init = ss4_init,
1082 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1083 .use_scsi = 1,
1084 };
1085
1086 QEMUMachine scls_machine = {
1087 .name = "SPARCClassic",
1088 .desc = "Sun4m platform, SPARCClassic",
1089 .init = scls_init,
1090 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1091 .use_scsi = 1,
1092 };
1093
1094 QEMUMachine sbook_machine = {
1095 .name = "SPARCbook",
1096 .desc = "Sun4m platform, SPARCbook",
1097 .init = sbook_init,
1098 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1099 .use_scsi = 1,
1100 };
1101
1102 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1103 /* SS-1000 */
1104 {
1105 .iounit_bases = {
1106 0xfe0200000ULL,
1107 0xfe1200000ULL,
1108 0xfe2200000ULL,
1109 0xfe3200000ULL,
1110 -1,
1111 },
1112 .tcx_base = 0x820000000ULL,
1113 .slavio_base = 0xf00000000ULL,
1114 .ms_kb_base = 0xf00240000ULL,
1115 .serial_base = 0xf00200000ULL,
1116 .nvram_base = 0xf00280000ULL,
1117 .counter_base = 0xf00300000ULL,
1118 .espdma_base = 0x800081000ULL,
1119 .esp_base = 0x800080000ULL,
1120 .ledma_base = 0x800040000ULL,
1121 .le_base = 0x800060000ULL,
1122 .sbi_base = 0xf02800000ULL,
1123 .vram_size = 0x00100000,
1124 .nvram_size = 0x2000,
1125 .esp_irq = 3,
1126 .le_irq = 4,
1127 .clock_irq = 14,
1128 .clock1_irq = 10,
1129 .ms_kb_irq = 12,
1130 .ser_irq = 12,
1131 .nvram_machine_id = 0x80,
1132 .machine_id = ss1000_id,
1133 .iounit_version = 0x03000000,
1134 .max_mem = 0xf00000000ULL,
1135 .default_cpu_model = "TI SuperSparc II",
1136 },
1137 /* SS-2000 */
1138 {
1139 .iounit_bases = {
1140 0xfe0200000ULL,
1141 0xfe1200000ULL,
1142 0xfe2200000ULL,
1143 0xfe3200000ULL,
1144 0xfe4200000ULL,
1145 },
1146 .tcx_base = 0x820000000ULL,
1147 .slavio_base = 0xf00000000ULL,
1148 .ms_kb_base = 0xf00240000ULL,
1149 .serial_base = 0xf00200000ULL,
1150 .nvram_base = 0xf00280000ULL,
1151 .counter_base = 0xf00300000ULL,
1152 .espdma_base = 0x800081000ULL,
1153 .esp_base = 0x800080000ULL,
1154 .ledma_base = 0x800040000ULL,
1155 .le_base = 0x800060000ULL,
1156 .sbi_base = 0xf02800000ULL,
1157 .vram_size = 0x00100000,
1158 .nvram_size = 0x2000,
1159 .esp_irq = 3,
1160 .le_irq = 4,
1161 .clock_irq = 14,
1162 .clock1_irq = 10,
1163 .ms_kb_irq = 12,
1164 .ser_irq = 12,
1165 .nvram_machine_id = 0x80,
1166 .machine_id = ss2000_id,
1167 .iounit_version = 0x03000000,
1168 .max_mem = 0xf00000000ULL,
1169 .default_cpu_model = "TI SuperSparc II",
1170 },
1171 };
1172
1173 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1174 const char *boot_device,
1175 const char *kernel_filename,
1176 const char *kernel_cmdline,
1177 const char *initrd_filename, const char *cpu_model)
1178 {
1179 CPUState *env, *envs[MAX_CPUS];
1180 unsigned int i;
1181 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1182 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1183 *espdma_irq, *ledma_irq;
1184 qemu_irq *esp_reset, *le_reset;
1185 ram_addr_t ram_offset, prom_offset;
1186 unsigned long kernel_size;
1187 int ret;
1188 char buf[1024];
1189 int drive_index;
1190 void *fw_cfg;
1191
1192 /* init CPUs */
1193 if (!cpu_model)
1194 cpu_model = hwdef->default_cpu_model;
1195
1196 for (i = 0; i < smp_cpus; i++) {
1197 env = cpu_init(cpu_model);
1198 if (!env) {
1199 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1200 exit(1);
1201 }
1202 cpu_sparc_set_id(env, i);
1203 envs[i] = env;
1204 if (i == 0) {
1205 qemu_register_reset(main_cpu_reset, env);
1206 } else {
1207 qemu_register_reset(secondary_cpu_reset, env);
1208 env->halted = 1;
1209 }
1210 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1211 env->prom_addr = hwdef->slavio_base;
1212 }
1213
1214 for (i = smp_cpus; i < MAX_CPUS; i++)
1215 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1216
1217 /* allocate RAM */
1218 if ((uint64_t)RAM_size > hwdef->max_mem) {
1219 fprintf(stderr,
1220 "qemu: Too much memory for this machine: %d, maximum %d\n",
1221 (unsigned int)(RAM_size / (1024 * 1024)),
1222 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1223 exit(1);
1224 }
1225 ram_offset = qemu_ram_alloc(RAM_size);
1226 cpu_register_physical_memory(0, RAM_size, ram_offset);
1227
1228 /* load boot prom */
1229 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1230 cpu_register_physical_memory(hwdef->slavio_base,
1231 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1232 TARGET_PAGE_MASK,
1233 prom_offset | IO_MEM_ROM);
1234
1235 if (bios_name == NULL)
1236 bios_name = PROM_FILENAME;
1237 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1238 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1239 if (ret < 0 || ret > PROM_SIZE_MAX)
1240 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1241 if (ret < 0 || ret > PROM_SIZE_MAX) {
1242 fprintf(stderr, "qemu: could not load prom '%s'\n",
1243 buf);
1244 exit(1);
1245 }
1246
1247 /* set up devices */
1248 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1249
1250 for (i = 0; i < MAX_IOUNITS; i++)
1251 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1252 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1253 hwdef->iounit_version,
1254 sbi_irq[hwdef->me_irq]);
1255
1256 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1257 iounits[0], &espdma_irq, &esp_reset);
1258
1259 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1260 iounits[0], &ledma_irq, &le_reset);
1261
1262 if (graphic_depth != 8 && graphic_depth != 24) {
1263 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1264 exit (1);
1265 }
1266 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1267 graphic_depth);
1268
1269 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1270
1271 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1272 hwdef->nvram_size, 8);
1273
1274 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1275 sbi_cpu_irq, smp_cpus);
1276
1277 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1278 nographic, ESCC_CLOCK, 1);
1279 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1280 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1281 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1282 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1283
1284 if (drive_get_max_bus(IF_SCSI) > 0) {
1285 fprintf(stderr, "qemu: too many SCSI bus\n");
1286 exit(1);
1287 }
1288
1289 main_esp = esp_init(hwdef->esp_base, 2,
1290 espdma_memory_read, espdma_memory_write,
1291 espdma, *espdma_irq, esp_reset);
1292
1293 for (i = 0; i < ESP_MAX_DEVS; i++) {
1294 drive_index = drive_get_index(IF_SCSI, 0, i);
1295 if (drive_index == -1)
1296 continue;
1297 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1298 }
1299
1300 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1301 RAM_size);
1302
1303 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1304 boot_device, RAM_size, kernel_size, graphic_width,
1305 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1306 "Sun4d");
1307
1308 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1309 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1310 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1311 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1312 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1313 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1314 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1315 if (kernel_cmdline) {
1316 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1317 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1318 } else {
1319 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1320 }
1321 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1322 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1323 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1324 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1325 }
1326
1327 /* SPARCserver 1000 hardware initialisation */
1328 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1329 const char *boot_device,
1330 const char *kernel_filename, const char *kernel_cmdline,
1331 const char *initrd_filename, const char *cpu_model)
1332 {
1333 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1334 kernel_cmdline, initrd_filename, cpu_model);
1335 }
1336
1337 /* SPARCcenter 2000 hardware initialisation */
1338 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1339 const char *boot_device,
1340 const char *kernel_filename, const char *kernel_cmdline,
1341 const char *initrd_filename, const char *cpu_model)
1342 {
1343 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1344 kernel_cmdline, initrd_filename, cpu_model);
1345 }
1346
1347 QEMUMachine ss1000_machine = {
1348 .name = "SS-1000",
1349 .desc = "Sun4d platform, SPARCserver 1000",
1350 .init = ss1000_init,
1351 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1352 .use_scsi = 1,
1353 .max_cpus = 8,
1354 };
1355
1356 QEMUMachine ss2000_machine = {
1357 .name = "SS-2000",
1358 .desc = "Sun4d platform, SPARCcenter 2000",
1359 .init = ss2000_init,
1360 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1361 .use_scsi = 1,
1362 .max_cpus = 20,
1363 };
1364
1365 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1366 /* SS-2 */
1367 {
1368 .iommu_base = 0xf8000000,
1369 .tcx_base = 0xfe000000,
1370 .slavio_base = 0xf6000000,
1371 .intctl_base = 0xf5000000,
1372 .counter_base = 0xf3000000,
1373 .ms_kb_base = 0xf0000000,
1374 .serial_base = 0xf1000000,
1375 .nvram_base = 0xf2000000,
1376 .fd_base = 0xf7200000,
1377 .dma_base = 0xf8400000,
1378 .esp_base = 0xf8800000,
1379 .le_base = 0xf8c00000,
1380 .aux1_base = 0xf7400003,
1381 .vram_size = 0x00100000,
1382 .nvram_size = 0x800,
1383 .esp_irq = 2,
1384 .le_irq = 3,
1385 .clock_irq = 5,
1386 .clock1_irq = 7,
1387 .ms_kb_irq = 1,
1388 .ser_irq = 1,
1389 .fd_irq = 1,
1390 .me_irq = 1,
1391 .nvram_machine_id = 0x55,
1392 .machine_id = ss2_id,
1393 .max_mem = 0x10000000,
1394 .default_cpu_model = "Cypress CY7C601",
1395 },
1396 };
1397
1398 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1399 const char *boot_device,
1400 const char *kernel_filename,
1401 const char *kernel_cmdline,
1402 const char *initrd_filename, const char *cpu_model)
1403 {
1404 CPUState *env;
1405 unsigned int i;
1406 void *iommu, *espdma, *ledma, *main_esp, *nvram;
1407 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1408 qemu_irq *esp_reset, *le_reset;
1409 qemu_irq *fdc_tc;
1410 ram_addr_t ram_offset, prom_offset;
1411 unsigned long kernel_size;
1412 int ret;
1413 char buf[1024];
1414 BlockDriverState *fd[MAX_FD];
1415 int drive_index;
1416 void *fw_cfg;
1417
1418 /* init CPU */
1419 if (!cpu_model)
1420 cpu_model = hwdef->default_cpu_model;
1421
1422 env = cpu_init(cpu_model);
1423 if (!env) {
1424 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1425 exit(1);
1426 }
1427
1428 cpu_sparc_set_id(env, 0);
1429
1430 qemu_register_reset(main_cpu_reset, env);
1431 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1432 env->prom_addr = hwdef->slavio_base;
1433
1434 /* allocate RAM */
1435 if ((uint64_t)RAM_size > hwdef->max_mem) {
1436 fprintf(stderr,
1437 "qemu: Too much memory for this machine: %d, maximum %d\n",
1438 (unsigned int)(RAM_size / (1024 * 1024)),
1439 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1440 exit(1);
1441 }
1442 ram_offset = qemu_ram_alloc(RAM_size);
1443 cpu_register_physical_memory(0, RAM_size, ram_offset);
1444
1445 /* load boot prom */
1446 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1447 cpu_register_physical_memory(hwdef->slavio_base,
1448 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1449 TARGET_PAGE_MASK,
1450 prom_offset | IO_MEM_ROM);
1451
1452 if (bios_name == NULL)
1453 bios_name = PROM_FILENAME;
1454 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1455 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1456 if (ret < 0 || ret > PROM_SIZE_MAX)
1457 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1458 if (ret < 0 || ret > PROM_SIZE_MAX) {
1459 fprintf(stderr, "qemu: could not load prom '%s'\n",
1460 buf);
1461 exit(1);
1462 }
1463
1464 /* set up devices */
1465 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1466 &slavio_irq, cpu_irqs);
1467
1468 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1469 slavio_irq[hwdef->me_irq]);
1470
1471 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1472 iommu, &espdma_irq, &esp_reset);
1473
1474 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1475 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1476 &le_reset);
1477
1478 if (graphic_depth != 8 && graphic_depth != 24) {
1479 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1480 exit (1);
1481 }
1482 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1483 graphic_depth);
1484
1485 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1486
1487 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1488 hwdef->nvram_size, 2);
1489
1490 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1491 nographic, ESCC_CLOCK, 1);
1492 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1493 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1494 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1495 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1496 ESCC_CLOCK, 1);
1497
1498 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1499 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1500
1501 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1502 /* there is zero or one floppy drive */
1503 memset(fd, 0, sizeof(fd));
1504 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1505 if (drive_index != -1)
1506 fd[0] = drives_table[drive_index].bdrv;
1507
1508 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1509 fdc_tc);
1510 }
1511
1512 if (drive_get_max_bus(IF_SCSI) > 0) {
1513 fprintf(stderr, "qemu: too many SCSI bus\n");
1514 exit(1);
1515 }
1516
1517 main_esp = esp_init(hwdef->esp_base, 2,
1518 espdma_memory_read, espdma_memory_write,
1519 espdma, *espdma_irq, esp_reset);
1520
1521 for (i = 0; i < ESP_MAX_DEVS; i++) {
1522 drive_index = drive_get_index(IF_SCSI, 0, i);
1523 if (drive_index == -1)
1524 continue;
1525 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1526 }
1527
1528 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1529 RAM_size);
1530
1531 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1532 boot_device, RAM_size, kernel_size, graphic_width,
1533 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1534 "Sun4c");
1535
1536 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1537 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1538 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1539 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1540 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1541 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1542 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1543 if (kernel_cmdline) {
1544 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1545 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1546 } else {
1547 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1548 }
1549 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1550 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1551 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1552 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1553 }
1554
1555 /* SPARCstation 2 hardware initialisation */
1556 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1557 const char *boot_device,
1558 const char *kernel_filename, const char *kernel_cmdline,
1559 const char *initrd_filename, const char *cpu_model)
1560 {
1561 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1562 kernel_cmdline, initrd_filename, cpu_model);
1563 }
1564
1565 QEMUMachine ss2_machine = {
1566 .name = "SS-2",
1567 .desc = "Sun4c platform, SPARCstation 2",
1568 .init = ss2_init,
1569 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1570 .use_scsi = 1,
1571 };
Samsung s3c2440 and arm920t support for the mini2440 dev board