?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Fix interrupt exclusion via SSTEP_NOIRQ
[qemu/mini2440.git] / target-sparc / translate.c
blob63c338b206ca8ec7f3593fc04421e441a23a7c80
1 /*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include <stdarg.h>
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <string.h>
26 #include <inttypes.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "disas.h"
31 #include "helper.h"
32 #include "tcg-op.h"
33
34 #define DEBUG_DISAS
35
36 #define DYNAMIC_PC 1 /* dynamic pc value */
37 #define JUMP_PC 2 /* dynamic pc value which takes only two values
38 according to jump_pc[T2] */
39
40 /* global register indexes */
41 static TCGv cpu_env, cpu_regwptr;
42 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
43 static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
44 static TCGv cpu_y;
45 #ifndef CONFIG_USER_ONLY
46 static TCGv cpu_tbr;
47 #endif
48 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
49 #ifdef TARGET_SPARC64
50 static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr;
51 static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
52 static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, cpu_softint;
53 #else
54 static TCGv cpu_wim;
55 #endif
56 /* local register indexes (only used inside old micro ops) */
57 static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
58 /* Floating point registers */
59 static TCGv cpu_fpr[TARGET_FPREGS];
60
61 #include "gen-icount.h"
62
63 typedef struct DisasContext {
64 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
65 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
66 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
67 int is_br;
68 int mem_idx;
69 int fpu_enabled;
70 int address_mask_32bit;
71 struct TranslationBlock *tb;
72 sparc_def_t *def;
73 } DisasContext;
74
75 // This function uses non-native bit order
76 #define GET_FIELD(X, FROM, TO) \
77 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
78
79 // This function uses the order in the manuals, i.e. bit 0 is 2^0
80 #define GET_FIELD_SP(X, FROM, TO) \
81 GET_FIELD(X, 31 - (TO), 31 - (FROM))
82
83 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
84 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
85
86 #ifdef TARGET_SPARC64
87 #define FFPREG(r) (r)
88 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
89 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
90 #else
91 #define FFPREG(r) (r)
92 #define DFPREG(r) (r & 0x1e)
93 #define QFPREG(r) (r & 0x1c)
94 #endif
95
96 #define UA2005_HTRAP_MASK 0xff
97 #define V8_TRAP_MASK 0x7f
98
99 static int sign_extend(int x, int len)
100 {
101 len = 32 - len;
102 return (x << len) >> len;
103 }
104
105 #define IS_IMM (insn & (1<<13))
106
107 /* floating point registers moves */
108 static void gen_op_load_fpr_DT0(unsigned int src)
109 {
110 tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +
111 offsetof(CPU_DoubleU, l.upper));
112 tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
113 offsetof(CPU_DoubleU, l.lower));
114 }
115
116 static void gen_op_load_fpr_DT1(unsigned int src)
117 {
118 tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) +
119 offsetof(CPU_DoubleU, l.upper));
120 tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
121 offsetof(CPU_DoubleU, l.lower));
122 }
123
124 static void gen_op_store_DT0_fpr(unsigned int dst)
125 {
126 tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) +
127 offsetof(CPU_DoubleU, l.upper));
128 tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
129 offsetof(CPU_DoubleU, l.lower));
130 }
131
132 static void gen_op_load_fpr_QT0(unsigned int src)
133 {
134 tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
135 offsetof(CPU_QuadU, l.upmost));
136 tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
137 offsetof(CPU_QuadU, l.upper));
138 tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
139 offsetof(CPU_QuadU, l.lower));
140 tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
141 offsetof(CPU_QuadU, l.lowest));
142 }
143
144 static void gen_op_load_fpr_QT1(unsigned int src)
145 {
146 tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
147 offsetof(CPU_QuadU, l.upmost));
148 tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
149 offsetof(CPU_QuadU, l.upper));
150 tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
151 offsetof(CPU_QuadU, l.lower));
152 tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
153 offsetof(CPU_QuadU, l.lowest));
154 }
155
156 static void gen_op_store_QT0_fpr(unsigned int dst)
157 {
158 tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
159 offsetof(CPU_QuadU, l.upmost));
160 tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
161 offsetof(CPU_QuadU, l.upper));
162 tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
163 offsetof(CPU_QuadU, l.lower));
164 tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
165 offsetof(CPU_QuadU, l.lowest));
166 }
167
168 /* moves */
169 #ifdef CONFIG_USER_ONLY
170 #define supervisor(dc) 0
171 #ifdef TARGET_SPARC64
172 #define hypervisor(dc) 0
173 #endif
174 #else
175 #define supervisor(dc) (dc->mem_idx >= 1)
176 #ifdef TARGET_SPARC64
177 #define hypervisor(dc) (dc->mem_idx == 2)
178 #else
179 #endif
180 #endif
181
182 #ifdef TARGET_SPARC64
183 #ifndef TARGET_ABI32
184 #define AM_CHECK(dc) ((dc)->address_mask_32bit)
185 #else
186 #define AM_CHECK(dc) (1)
187 #endif
188 #endif
189
190 static inline void gen_address_mask(DisasContext *dc, TCGv addr)
191 {
192 #ifdef TARGET_SPARC64
193 if (AM_CHECK(dc))
194 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
195 #endif
196 }
197
198 static inline void gen_movl_reg_TN(int reg, TCGv tn)
199 {
200 if (reg == 0)
201 tcg_gen_movi_tl(tn, 0);
202 else if (reg < 8)
203 tcg_gen_mov_tl(tn, cpu_gregs[reg]);
204 else {
205 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
206 }
207 }
208
209 static inline void gen_movl_TN_reg(int reg, TCGv tn)
210 {
211 if (reg == 0)
212 return;
213 else if (reg < 8)
214 tcg_gen_mov_tl(cpu_gregs[reg], tn);
215 else {
216 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
217 }
218 }
219
220 static inline void gen_goto_tb(DisasContext *s, int tb_num,
221 target_ulong pc, target_ulong npc)
222 {
223 TranslationBlock *tb;
224
225 tb = s->tb;
226 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
227 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
228 /* jump to same page: we can use a direct jump */
229 tcg_gen_goto_tb(tb_num);
230 tcg_gen_movi_tl(cpu_pc, pc);
231 tcg_gen_movi_tl(cpu_npc, npc);
232 tcg_gen_exit_tb((long)tb + tb_num);
233 } else {
234 /* jump to another page: currently not optimized */
235 tcg_gen_movi_tl(cpu_pc, pc);
236 tcg_gen_movi_tl(cpu_npc, npc);
237 tcg_gen_exit_tb(0);
238 }
239 }
240
241 // XXX suboptimal
242 static inline void gen_mov_reg_N(TCGv reg, TCGv src)
243 {
244 tcg_gen_extu_i32_tl(reg, src);
245 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
246 tcg_gen_andi_tl(reg, reg, 0x1);
247 }
248
249 static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
250 {
251 tcg_gen_extu_i32_tl(reg, src);
252 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
253 tcg_gen_andi_tl(reg, reg, 0x1);
254 }
255
256 static inline void gen_mov_reg_V(TCGv reg, TCGv src)
257 {
258 tcg_gen_extu_i32_tl(reg, src);
259 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
260 tcg_gen_andi_tl(reg, reg, 0x1);
261 }
262
263 static inline void gen_mov_reg_C(TCGv reg, TCGv src)
264 {
265 tcg_gen_extu_i32_tl(reg, src);
266 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
267 tcg_gen_andi_tl(reg, reg, 0x1);
268 }
269
270 static inline void gen_cc_clear_icc(void)
271 {
272 tcg_gen_movi_i32(cpu_psr, 0);
273 }
274
275 #ifdef TARGET_SPARC64
276 static inline void gen_cc_clear_xcc(void)
277 {
278 tcg_gen_movi_i32(cpu_xcc, 0);
279 }
280 #endif
281
282 /* old op:
283 if (!T0)
284 env->psr |= PSR_ZERO;
285 if ((int32_t) T0 < 0)
286 env->psr |= PSR_NEG;
287 */
288 static inline void gen_cc_NZ_icc(TCGv dst)
289 {
290 TCGv r_temp;
291 int l1, l2;
292
293 l1 = gen_new_label();
294 l2 = gen_new_label();
295 r_temp = tcg_temp_new(TCG_TYPE_TL);
296 tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
297 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
298 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
299 gen_set_label(l1);
300 tcg_gen_ext32s_tl(r_temp, dst);
301 tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
302 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
303 gen_set_label(l2);
304 tcg_temp_free(r_temp);
305 }
306
307 #ifdef TARGET_SPARC64
308 static inline void gen_cc_NZ_xcc(TCGv dst)
309 {
310 int l1, l2;
311
312 l1 = gen_new_label();
313 l2 = gen_new_label();
314 tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
315 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
316 gen_set_label(l1);
317 tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
318 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
319 gen_set_label(l2);
320 }
321 #endif
322
323 /* old op:
324 if (T0 < src1)
325 env->psr |= PSR_CARRY;
326 */
327 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
328 {
329 TCGv r_temp1, r_temp2;
330 int l1;
331
332 l1 = gen_new_label();
333 r_temp1 = tcg_temp_new(TCG_TYPE_TL);
334 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
335 tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
336 tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
337 tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
338 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
339 gen_set_label(l1);
340 tcg_temp_free(r_temp1);
341 tcg_temp_free(r_temp2);
342 }
343
344 #ifdef TARGET_SPARC64
345 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
346 {
347 int l1;
348
349 l1 = gen_new_label();
350 tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
351 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
352 gen_set_label(l1);
353 }
354 #endif
355
356 /* old op:
357 if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
358 env->psr |= PSR_OVF;
359 */
360 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
361 {
362 TCGv r_temp;
363
364 r_temp = tcg_temp_new(TCG_TYPE_TL);
365 tcg_gen_xor_tl(r_temp, src1, src2);
366 tcg_gen_xori_tl(r_temp, r_temp, -1);
367 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
368 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
369 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
370 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
371 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
372 tcg_temp_free(r_temp);
373 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
374 }
375
376 #ifdef TARGET_SPARC64
377 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
378 {
379 TCGv r_temp;
380
381 r_temp = tcg_temp_new(TCG_TYPE_TL);
382 tcg_gen_xor_tl(r_temp, src1, src2);
383 tcg_gen_xori_tl(r_temp, r_temp, -1);
384 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
385 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
386 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
387 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
388 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
389 tcg_temp_free(r_temp);
390 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
391 }
392 #endif
393
394 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
395 {
396 TCGv r_temp, r_const;
397 int l1;
398
399 l1 = gen_new_label();
400
401 r_temp = tcg_temp_new(TCG_TYPE_TL);
402 tcg_gen_xor_tl(r_temp, src1, src2);
403 tcg_gen_xori_tl(r_temp, r_temp, -1);
404 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
405 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
406 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
407 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
408 r_const = tcg_const_i32(TT_TOVF);
409 tcg_gen_helper_0_1(raise_exception, r_const);
410 tcg_temp_free(r_const);
411 gen_set_label(l1);
412 tcg_temp_free(r_temp);
413 }
414
415 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
416 {
417 int l1;
418
419 l1 = gen_new_label();
420 tcg_gen_or_tl(cpu_tmp0, src1, src2);
421 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
422 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
423 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
424 gen_set_label(l1);
425 }
426
427 static inline void gen_tag_tv(TCGv src1, TCGv src2)
428 {
429 int l1;
430 TCGv r_const;
431
432 l1 = gen_new_label();
433 tcg_gen_or_tl(cpu_tmp0, src1, src2);
434 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
435 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
436 r_const = tcg_const_i32(TT_TOVF);
437 tcg_gen_helper_0_1(raise_exception, r_const);
438 tcg_temp_free(r_const);
439 gen_set_label(l1);
440 }
441
442 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
443 {
444 tcg_gen_mov_tl(cpu_cc_src, src1);
445 tcg_gen_mov_tl(cpu_cc_src2, src2);
446 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
447 gen_cc_clear_icc();
448 gen_cc_NZ_icc(cpu_cc_dst);
449 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
450 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
451 #ifdef TARGET_SPARC64
452 gen_cc_clear_xcc();
453 gen_cc_NZ_xcc(cpu_cc_dst);
454 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
455 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
456 #endif
457 tcg_gen_mov_tl(dst, cpu_cc_dst);
458 }
459
460 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
461 {
462 tcg_gen_mov_tl(cpu_cc_src, src1);
463 tcg_gen_mov_tl(cpu_cc_src2, src2);
464 gen_mov_reg_C(cpu_tmp0, cpu_psr);
465 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
466 gen_cc_clear_icc();
467 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
468 #ifdef TARGET_SPARC64
469 gen_cc_clear_xcc();
470 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
471 #endif
472 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
473 gen_cc_NZ_icc(cpu_cc_dst);
474 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
475 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
476 #ifdef TARGET_SPARC64
477 gen_cc_NZ_xcc(cpu_cc_dst);
478 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
479 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
480 #endif
481 tcg_gen_mov_tl(dst, cpu_cc_dst);
482 }
483
484 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
485 {
486 tcg_gen_mov_tl(cpu_cc_src, src1);
487 tcg_gen_mov_tl(cpu_cc_src2, src2);
488 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
489 gen_cc_clear_icc();
490 gen_cc_NZ_icc(cpu_cc_dst);
491 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
492 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
493 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
494 #ifdef TARGET_SPARC64
495 gen_cc_clear_xcc();
496 gen_cc_NZ_xcc(cpu_cc_dst);
497 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
498 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
499 #endif
500 tcg_gen_mov_tl(dst, cpu_cc_dst);
501 }
502
503 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
504 {
505 tcg_gen_mov_tl(cpu_cc_src, src1);
506 tcg_gen_mov_tl(cpu_cc_src2, src2);
507 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
508 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
509 gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
510 gen_cc_clear_icc();
511 gen_cc_NZ_icc(cpu_cc_dst);
512 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
513 #ifdef TARGET_SPARC64
514 gen_cc_clear_xcc();
515 gen_cc_NZ_xcc(cpu_cc_dst);
516 gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
517 gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
518 #endif
519 tcg_gen_mov_tl(dst, cpu_cc_dst);
520 }
521
522 /* old op:
523 if (src1 < T1)
524 env->psr |= PSR_CARRY;
525 */
526 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
527 {
528 TCGv r_temp1, r_temp2;
529 int l1;
530
531 l1 = gen_new_label();
532 r_temp1 = tcg_temp_new(TCG_TYPE_TL);
533 r_temp2 = tcg_temp_new(TCG_TYPE_TL);
534 tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
535 tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
536 tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
537 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
538 gen_set_label(l1);
539 tcg_temp_free(r_temp1);
540 tcg_temp_free(r_temp2);
541 }
542
543 #ifdef TARGET_SPARC64
544 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
545 {
546 int l1;
547
548 l1 = gen_new_label();
549 tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
550 tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
551 gen_set_label(l1);
552 }
553 #endif
554
555 /* old op:
556 if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
557 env->psr |= PSR_OVF;
558 */
559 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
560 {
561 TCGv r_temp;
562
563 r_temp = tcg_temp_new(TCG_TYPE_TL);
564 tcg_gen_xor_tl(r_temp, src1, src2);
565 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
566 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
567 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
568 tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
569 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
570 tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
571 tcg_temp_free(r_temp);
572 }
573
574 #ifdef TARGET_SPARC64
575 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
576 {
577 TCGv r_temp;
578
579 r_temp = tcg_temp_new(TCG_TYPE_TL);
580 tcg_gen_xor_tl(r_temp, src1, src2);
581 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
582 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
583 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
584 tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
585 tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
586 tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
587 tcg_temp_free(r_temp);
588 }
589 #endif
590
591 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
592 {
593 TCGv r_temp, r_const;
594 int l1;
595
596 l1 = gen_new_label();
597
598 r_temp = tcg_temp_new(TCG_TYPE_TL);
599 tcg_gen_xor_tl(r_temp, src1, src2);
600 tcg_gen_xor_tl(cpu_tmp0, src1, dst);
601 tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
602 tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
603 tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
604 r_const = tcg_const_i32(TT_TOVF);
605 tcg_gen_helper_0_1(raise_exception, r_const);
606 tcg_temp_free(r_const);
607 gen_set_label(l1);
608 tcg_temp_free(r_temp);
609 }
610
611 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
612 {
613 tcg_gen_mov_tl(cpu_cc_src, src1);
614 tcg_gen_mov_tl(cpu_cc_src2, src2);
615 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
616 gen_cc_clear_icc();
617 gen_cc_NZ_icc(cpu_cc_dst);
618 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
619 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
620 #ifdef TARGET_SPARC64
621 gen_cc_clear_xcc();
622 gen_cc_NZ_xcc(cpu_cc_dst);
623 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
624 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
625 #endif
626 tcg_gen_mov_tl(dst, cpu_cc_dst);
627 }
628
629 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
630 {
631 tcg_gen_mov_tl(cpu_cc_src, src1);
632 tcg_gen_mov_tl(cpu_cc_src2, src2);
633 gen_mov_reg_C(cpu_tmp0, cpu_psr);
634 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
635 gen_cc_clear_icc();
636 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
637 #ifdef TARGET_SPARC64
638 gen_cc_clear_xcc();
639 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
640 #endif
641 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
642 gen_cc_NZ_icc(cpu_cc_dst);
643 gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
644 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
645 #ifdef TARGET_SPARC64
646 gen_cc_NZ_xcc(cpu_cc_dst);
647 gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
648 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
649 #endif
650 tcg_gen_mov_tl(dst, cpu_cc_dst);
651 }
652
653 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
654 {
655 tcg_gen_mov_tl(cpu_cc_src, src1);
656 tcg_gen_mov_tl(cpu_cc_src2, src2);
657 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
658 gen_cc_clear_icc();
659 gen_cc_NZ_icc(cpu_cc_dst);
660 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
661 gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
662 gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
663 #ifdef TARGET_SPARC64
664 gen_cc_clear_xcc();
665 gen_cc_NZ_xcc(cpu_cc_dst);
666 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
667 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
668 #endif
669 tcg_gen_mov_tl(dst, cpu_cc_dst);
670 }
671
672 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
673 {
674 tcg_gen_mov_tl(cpu_cc_src, src1);
675 tcg_gen_mov_tl(cpu_cc_src2, src2);
676 gen_tag_tv(cpu_cc_src, cpu_cc_src2);
677 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
678 gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
679 gen_cc_clear_icc();
680 gen_cc_NZ_icc(cpu_cc_dst);
681 gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
682 #ifdef TARGET_SPARC64
683 gen_cc_clear_xcc();
684 gen_cc_NZ_xcc(cpu_cc_dst);
685 gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
686 gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
687 #endif
688 tcg_gen_mov_tl(dst, cpu_cc_dst);
689 }
690
691 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
692 {
693 TCGv r_temp;
694 int l1;
695
696 l1 = gen_new_label();
697 r_temp = tcg_temp_new(TCG_TYPE_TL);
698
699 /* old op:
700 if (!(env->y & 1))
701 T1 = 0;
702 */
703 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
704 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
705 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
706 tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
707 tcg_gen_movi_tl(cpu_cc_src2, 0);
708 gen_set_label(l1);
709
710 // b2 = T0 & 1;
711 // env->y = (b2 << 31) | (env->y >> 1);
712 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
713 tcg_gen_shli_tl(r_temp, r_temp, 31);
714 tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
715 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
716 tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
717 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
718
719 // b1 = N ^ V;
720 gen_mov_reg_N(cpu_tmp0, cpu_psr);
721 gen_mov_reg_V(r_temp, cpu_psr);
722 tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
723 tcg_temp_free(r_temp);
724
725 // T0 = (b1 << 31) | (T0 >> 1);
726 // src1 = T0;
727 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
728 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
729 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
730
731 /* do addition and update flags */
732 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
733
734 gen_cc_clear_icc();
735 gen_cc_NZ_icc(cpu_cc_dst);
736 gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
737 gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
738 tcg_gen_mov_tl(dst, cpu_cc_dst);
739 }
740
741 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
742 {
743 TCGv r_temp, r_temp2;
744
745 r_temp = tcg_temp_new(TCG_TYPE_I64);
746 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
747
748 tcg_gen_extu_tl_i64(r_temp, src2);
749 tcg_gen_extu_tl_i64(r_temp2, src1);
750 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
751
752 tcg_gen_shri_i64(r_temp, r_temp2, 32);
753 tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
754 tcg_temp_free(r_temp);
755 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
756 #ifdef TARGET_SPARC64
757 tcg_gen_mov_i64(dst, r_temp2);
758 #else
759 tcg_gen_trunc_i64_tl(dst, r_temp2);
760 #endif
761 tcg_temp_free(r_temp2);
762 }
763
764 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
765 {
766 TCGv r_temp, r_temp2;
767
768 r_temp = tcg_temp_new(TCG_TYPE_I64);
769 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
770
771 tcg_gen_ext_tl_i64(r_temp, src2);
772 tcg_gen_ext_tl_i64(r_temp2, src1);
773 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
774
775 tcg_gen_shri_i64(r_temp, r_temp2, 32);
776 tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
777 tcg_temp_free(r_temp);
778 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
779 #ifdef TARGET_SPARC64
780 tcg_gen_mov_i64(dst, r_temp2);
781 #else
782 tcg_gen_trunc_i64_tl(dst, r_temp2);
783 #endif
784 tcg_temp_free(r_temp2);
785 }
786
787 #ifdef TARGET_SPARC64
788 static inline void gen_trap_ifdivzero_tl(TCGv divisor)
789 {
790 TCGv r_const;
791 int l1;
792
793 l1 = gen_new_label();
794 tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
795 r_const = tcg_const_i32(TT_DIV_ZERO);
796 tcg_gen_helper_0_1(raise_exception, r_const);
797 tcg_temp_free(r_const);
798 gen_set_label(l1);
799 }
800
801 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
802 {
803 int l1, l2;
804
805 l1 = gen_new_label();
806 l2 = gen_new_label();
807 tcg_gen_mov_tl(cpu_cc_src, src1);
808 tcg_gen_mov_tl(cpu_cc_src2, src2);
809 gen_trap_ifdivzero_tl(cpu_cc_src2);
810 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
811 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
812 tcg_gen_movi_i64(dst, INT64_MIN);
813 tcg_gen_br(l2);
814 gen_set_label(l1);
815 tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
816 gen_set_label(l2);
817 }
818 #endif
819
820 static inline void gen_op_div_cc(TCGv dst)
821 {
822 int l1;
823
824 tcg_gen_mov_tl(cpu_cc_dst, dst);
825 gen_cc_clear_icc();
826 gen_cc_NZ_icc(cpu_cc_dst);
827 l1 = gen_new_label();
828 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
829 tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
830 gen_set_label(l1);
831 }
832
833 static inline void gen_op_logic_cc(TCGv dst)
834 {
835 tcg_gen_mov_tl(cpu_cc_dst, dst);
836
837 gen_cc_clear_icc();
838 gen_cc_NZ_icc(cpu_cc_dst);
839 #ifdef TARGET_SPARC64
840 gen_cc_clear_xcc();
841 gen_cc_NZ_xcc(cpu_cc_dst);
842 #endif
843 }
844
845 // 1
846 static inline void gen_op_eval_ba(TCGv dst)
847 {
848 tcg_gen_movi_tl(dst, 1);
849 }
850
851 // Z
852 static inline void gen_op_eval_be(TCGv dst, TCGv src)
853 {
854 gen_mov_reg_Z(dst, src);
855 }
856
857 // Z | (N ^ V)
858 static inline void gen_op_eval_ble(TCGv dst, TCGv src)
859 {
860 gen_mov_reg_N(cpu_tmp0, src);
861 gen_mov_reg_V(dst, src);
862 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
863 gen_mov_reg_Z(cpu_tmp0, src);
864 tcg_gen_or_tl(dst, dst, cpu_tmp0);
865 }
866
867 // N ^ V
868 static inline void gen_op_eval_bl(TCGv dst, TCGv src)
869 {
870 gen_mov_reg_V(cpu_tmp0, src);
871 gen_mov_reg_N(dst, src);
872 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
873 }
874
875 // C | Z
876 static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
877 {
878 gen_mov_reg_Z(cpu_tmp0, src);
879 gen_mov_reg_C(dst, src);
880 tcg_gen_or_tl(dst, dst, cpu_tmp0);
881 }
882
883 // C
884 static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
885 {
886 gen_mov_reg_C(dst, src);
887 }
888
889 // V
890 static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
891 {
892 gen_mov_reg_V(dst, src);
893 }
894
895 // 0
896 static inline void gen_op_eval_bn(TCGv dst)
897 {
898 tcg_gen_movi_tl(dst, 0);
899 }
900
901 // N
902 static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
903 {
904 gen_mov_reg_N(dst, src);
905 }
906
907 // !Z
908 static inline void gen_op_eval_bne(TCGv dst, TCGv src)
909 {
910 gen_mov_reg_Z(dst, src);
911 tcg_gen_xori_tl(dst, dst, 0x1);
912 }
913
914 // !(Z | (N ^ V))
915 static inline void gen_op_eval_bg(TCGv dst, TCGv src)
916 {
917 gen_mov_reg_N(cpu_tmp0, src);
918 gen_mov_reg_V(dst, src);
919 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
920 gen_mov_reg_Z(cpu_tmp0, src);
921 tcg_gen_or_tl(dst, dst, cpu_tmp0);
922 tcg_gen_xori_tl(dst, dst, 0x1);
923 }
924
925 // !(N ^ V)
926 static inline void gen_op_eval_bge(TCGv dst, TCGv src)
927 {
928 gen_mov_reg_V(cpu_tmp0, src);
929 gen_mov_reg_N(dst, src);
930 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
931 tcg_gen_xori_tl(dst, dst, 0x1);
932 }
933
934 // !(C | Z)
935 static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
936 {
937 gen_mov_reg_Z(cpu_tmp0, src);
938 gen_mov_reg_C(dst, src);
939 tcg_gen_or_tl(dst, dst, cpu_tmp0);
940 tcg_gen_xori_tl(dst, dst, 0x1);
941 }
942
943 // !C
944 static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
945 {
946 gen_mov_reg_C(dst, src);
947 tcg_gen_xori_tl(dst, dst, 0x1);
948 }
949
950 // !N
951 static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
952 {
953 gen_mov_reg_N(dst, src);
954 tcg_gen_xori_tl(dst, dst, 0x1);
955 }
956
957 // !V
958 static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
959 {
960 gen_mov_reg_V(dst, src);
961 tcg_gen_xori_tl(dst, dst, 0x1);
962 }
963
964 /*
965 FPSR bit field FCC1 | FCC0:
966 0 =
967 1 <
968 2 >
969 3 unordered
970 */
971 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
972 unsigned int fcc_offset)
973 {
974 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
975 tcg_gen_andi_tl(reg, reg, 0x1);
976 }
977
978 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
979 unsigned int fcc_offset)
980 {
981 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
982 tcg_gen_andi_tl(reg, reg, 0x1);
983 }
984
985 // !0: FCC0 | FCC1
986 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
987 unsigned int fcc_offset)
988 {
989 gen_mov_reg_FCC0(dst, src, fcc_offset);
990 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
991 tcg_gen_or_tl(dst, dst, cpu_tmp0);
992 }
993
994 // 1 or 2: FCC0 ^ FCC1
995 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
996 unsigned int fcc_offset)
997 {
998 gen_mov_reg_FCC0(dst, src, fcc_offset);
999 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1000 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1001 }
1002
1003 // 1 or 3: FCC0
1004 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1005 unsigned int fcc_offset)
1006 {
1007 gen_mov_reg_FCC0(dst, src, fcc_offset);
1008 }
1009
1010 // 1: FCC0 & !FCC1
1011 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1012 unsigned int fcc_offset)
1013 {
1014 gen_mov_reg_FCC0(dst, src, fcc_offset);
1015 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1016 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1017 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1018 }
1019
1020 // 2 or 3: FCC1
1021 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1022 unsigned int fcc_offset)
1023 {
1024 gen_mov_reg_FCC1(dst, src, fcc_offset);
1025 }
1026
1027 // 2: !FCC0 & FCC1
1028 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1029 unsigned int fcc_offset)
1030 {
1031 gen_mov_reg_FCC0(dst, src, fcc_offset);
1032 tcg_gen_xori_tl(dst, dst, 0x1);
1033 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1034 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1035 }
1036
1037 // 3: FCC0 & FCC1
1038 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1039 unsigned int fcc_offset)
1040 {
1041 gen_mov_reg_FCC0(dst, src, fcc_offset);
1042 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1043 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1044 }
1045
1046 // 0: !(FCC0 | FCC1)
1047 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1048 unsigned int fcc_offset)
1049 {
1050 gen_mov_reg_FCC0(dst, src, fcc_offset);
1051 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1052 tcg_gen_or_tl(dst, dst, cpu_tmp0);
1053 tcg_gen_xori_tl(dst, dst, 0x1);
1054 }
1055
1056 // 0 or 3: !(FCC0 ^ FCC1)
1057 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1058 unsigned int fcc_offset)
1059 {
1060 gen_mov_reg_FCC0(dst, src, fcc_offset);
1061 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1062 tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1063 tcg_gen_xori_tl(dst, dst, 0x1);
1064 }
1065
1066 // 0 or 2: !FCC0
1067 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1068 unsigned int fcc_offset)
1069 {
1070 gen_mov_reg_FCC0(dst, src, fcc_offset);
1071 tcg_gen_xori_tl(dst, dst, 0x1);
1072 }
1073
1074 // !1: !(FCC0 & !FCC1)
1075 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1076 unsigned int fcc_offset)
1077 {
1078 gen_mov_reg_FCC0(dst, src, fcc_offset);
1079 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1080 tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1081 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1082 tcg_gen_xori_tl(dst, dst, 0x1);
1083 }
1084
1085 // 0 or 1: !FCC1
1086 static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1087 unsigned int fcc_offset)
1088 {
1089 gen_mov_reg_FCC1(dst, src, fcc_offset);
1090 tcg_gen_xori_tl(dst, dst, 0x1);
1091 }
1092
1093 // !2: !(!FCC0 & FCC1)
1094 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1095 unsigned int fcc_offset)
1096 {
1097 gen_mov_reg_FCC0(dst, src, fcc_offset);
1098 tcg_gen_xori_tl(dst, dst, 0x1);
1099 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1100 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1101 tcg_gen_xori_tl(dst, dst, 0x1);
1102 }
1103
1104 // !3: !(FCC0 & FCC1)
1105 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1106 unsigned int fcc_offset)
1107 {
1108 gen_mov_reg_FCC0(dst, src, fcc_offset);
1109 gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1110 tcg_gen_and_tl(dst, dst, cpu_tmp0);
1111 tcg_gen_xori_tl(dst, dst, 0x1);
1112 }
1113
1114 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1115 target_ulong pc2, TCGv r_cond)
1116 {
1117 int l1;
1118
1119 l1 = gen_new_label();
1120
1121 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1122
1123 gen_goto_tb(dc, 0, pc1, pc1 + 4);
1124
1125 gen_set_label(l1);
1126 gen_goto_tb(dc, 1, pc2, pc2 + 4);
1127 }
1128
1129 static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1130 target_ulong pc2, TCGv r_cond)
1131 {
1132 int l1;
1133
1134 l1 = gen_new_label();
1135
1136 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1137
1138 gen_goto_tb(dc, 0, pc2, pc1);
1139
1140 gen_set_label(l1);
1141 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1142 }
1143
1144 static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1145 TCGv r_cond)
1146 {
1147 int l1, l2;
1148
1149 l1 = gen_new_label();
1150 l2 = gen_new_label();
1151
1152 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1153
1154 tcg_gen_movi_tl(cpu_npc, npc1);
1155 tcg_gen_br(l2);
1156
1157 gen_set_label(l1);
1158 tcg_gen_movi_tl(cpu_npc, npc2);
1159 gen_set_label(l2);
1160 }
1161
1162 /* call this function before using the condition register as it may
1163 have been set for a jump */
1164 static inline void flush_cond(DisasContext *dc, TCGv cond)
1165 {
1166 if (dc->npc == JUMP_PC) {
1167 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1168 dc->npc = DYNAMIC_PC;
1169 }
1170 }
1171
1172 static inline void save_npc(DisasContext *dc, TCGv cond)
1173 {
1174 if (dc->npc == JUMP_PC) {
1175 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1176 dc->npc = DYNAMIC_PC;
1177 } else if (dc->npc != DYNAMIC_PC) {
1178 tcg_gen_movi_tl(cpu_npc, dc->npc);
1179 }
1180 }
1181
1182 static inline void save_state(DisasContext *dc, TCGv cond)
1183 {
1184 tcg_gen_movi_tl(cpu_pc, dc->pc);
1185 save_npc(dc, cond);
1186 }
1187
1188 static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1189 {
1190 if (dc->npc == JUMP_PC) {
1191 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1192 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1193 dc->pc = DYNAMIC_PC;
1194 } else if (dc->npc == DYNAMIC_PC) {
1195 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1196 dc->pc = DYNAMIC_PC;
1197 } else {
1198 dc->pc = dc->npc;
1199 }
1200 }
1201
1202 static inline void gen_op_next_insn(void)
1203 {
1204 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1205 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1206 }
1207
1208 static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1209 {
1210 TCGv r_src;
1211
1212 #ifdef TARGET_SPARC64
1213 if (cc)
1214 r_src = cpu_xcc;
1215 else
1216 r_src = cpu_psr;
1217 #else
1218 r_src = cpu_psr;
1219 #endif
1220 switch (cond) {
1221 case 0x0:
1222 gen_op_eval_bn(r_dst);
1223 break;
1224 case 0x1:
1225 gen_op_eval_be(r_dst, r_src);
1226 break;
1227 case 0x2:
1228 gen_op_eval_ble(r_dst, r_src);
1229 break;
1230 case 0x3:
1231 gen_op_eval_bl(r_dst, r_src);
1232 break;
1233 case 0x4:
1234 gen_op_eval_bleu(r_dst, r_src);
1235 break;
1236 case 0x5:
1237 gen_op_eval_bcs(r_dst, r_src);
1238 break;
1239 case 0x6:
1240 gen_op_eval_bneg(r_dst, r_src);
1241 break;
1242 case 0x7:
1243 gen_op_eval_bvs(r_dst, r_src);
1244 break;
1245 case 0x8:
1246 gen_op_eval_ba(r_dst);
1247 break;
1248 case 0x9:
1249 gen_op_eval_bne(r_dst, r_src);
1250 break;
1251 case 0xa:
1252 gen_op_eval_bg(r_dst, r_src);
1253 break;
1254 case 0xb:
1255 gen_op_eval_bge(r_dst, r_src);
1256 break;
1257 case 0xc:
1258 gen_op_eval_bgu(r_dst, r_src);
1259 break;
1260 case 0xd:
1261 gen_op_eval_bcc(r_dst, r_src);
1262 break;
1263 case 0xe:
1264 gen_op_eval_bpos(r_dst, r_src);
1265 break;
1266 case 0xf:
1267 gen_op_eval_bvc(r_dst, r_src);
1268 break;
1269 }
1270 }
1271
1272 static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1273 {
1274 unsigned int offset;
1275
1276 switch (cc) {
1277 default:
1278 case 0x0:
1279 offset = 0;
1280 break;
1281 case 0x1:
1282 offset = 32 - 10;
1283 break;
1284 case 0x2:
1285 offset = 34 - 10;
1286 break;
1287 case 0x3:
1288 offset = 36 - 10;
1289 break;
1290 }
1291
1292 switch (cond) {
1293 case 0x0:
1294 gen_op_eval_bn(r_dst);
1295 break;
1296 case 0x1:
1297 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1298 break;
1299 case 0x2:
1300 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1301 break;
1302 case 0x3:
1303 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1304 break;
1305 case 0x4:
1306 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1307 break;
1308 case 0x5:
1309 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1310 break;
1311 case 0x6:
1312 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1313 break;
1314 case 0x7:
1315 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1316 break;
1317 case 0x8:
1318 gen_op_eval_ba(r_dst);
1319 break;
1320 case 0x9:
1321 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1322 break;
1323 case 0xa:
1324 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1325 break;
1326 case 0xb:
1327 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1328 break;
1329 case 0xc:
1330 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1331 break;
1332 case 0xd:
1333 gen_op_eval_fble(r_dst, cpu_fsr, offset);
1334 break;
1335 case 0xe:
1336 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1337 break;
1338 case 0xf:
1339 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1340 break;
1341 }
1342 }
1343
1344 #ifdef TARGET_SPARC64
1345 // Inverted logic
1346 static const int gen_tcg_cond_reg[8] = {
1347 -1,
1348 TCG_COND_NE,
1349 TCG_COND_GT,
1350 TCG_COND_GE,
1351 -1,
1352 TCG_COND_EQ,
1353 TCG_COND_LE,
1354 TCG_COND_LT,
1355 };
1356
1357 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1358 {
1359 int l1;
1360
1361 l1 = gen_new_label();
1362 tcg_gen_movi_tl(r_dst, 0);
1363 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1364 tcg_gen_movi_tl(r_dst, 1);
1365 gen_set_label(l1);
1366 }
1367 #endif
1368
1369 /* XXX: potentially incorrect if dynamic npc */
1370 static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1371 TCGv r_cond)
1372 {
1373 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1374 target_ulong target = dc->pc + offset;
1375
1376 if (cond == 0x0) {
1377 /* unconditional not taken */
1378 if (a) {
1379 dc->pc = dc->npc + 4;
1380 dc->npc = dc->pc + 4;
1381 } else {
1382 dc->pc = dc->npc;
1383 dc->npc = dc->pc + 4;
1384 }
1385 } else if (cond == 0x8) {
1386 /* unconditional taken */
1387 if (a) {
1388 dc->pc = target;
1389 dc->npc = dc->pc + 4;
1390 } else {
1391 dc->pc = dc->npc;
1392 dc->npc = target;
1393 }
1394 } else {
1395 flush_cond(dc, r_cond);
1396 gen_cond(r_cond, cc, cond);
1397 if (a) {
1398 gen_branch_a(dc, target, dc->npc, r_cond);
1399 dc->is_br = 1;
1400 } else {
1401 dc->pc = dc->npc;
1402 dc->jump_pc[0] = target;
1403 dc->jump_pc[1] = dc->npc + 4;
1404 dc->npc = JUMP_PC;
1405 }
1406 }
1407 }
1408
1409 /* XXX: potentially incorrect if dynamic npc */
1410 static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1411 TCGv r_cond)
1412 {
1413 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1414 target_ulong target = dc->pc + offset;
1415
1416 if (cond == 0x0) {
1417 /* unconditional not taken */
1418 if (a) {
1419 dc->pc = dc->npc + 4;
1420 dc->npc = dc->pc + 4;
1421 } else {
1422 dc->pc = dc->npc;
1423 dc->npc = dc->pc + 4;
1424 }
1425 } else if (cond == 0x8) {
1426 /* unconditional taken */
1427 if (a) {
1428 dc->pc = target;
1429 dc->npc = dc->pc + 4;
1430 } else {
1431 dc->pc = dc->npc;
1432 dc->npc = target;
1433 }
1434 } else {
1435 flush_cond(dc, r_cond);
1436 gen_fcond(r_cond, cc, cond);
1437 if (a) {
1438 gen_branch_a(dc, target, dc->npc, r_cond);
1439 dc->is_br = 1;
1440 } else {
1441 dc->pc = dc->npc;
1442 dc->jump_pc[0] = target;
1443 dc->jump_pc[1] = dc->npc + 4;
1444 dc->npc = JUMP_PC;
1445 }
1446 }
1447 }
1448
1449 #ifdef TARGET_SPARC64
1450 /* XXX: potentially incorrect if dynamic npc */
1451 static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1452 TCGv r_cond, TCGv r_reg)
1453 {
1454 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1455 target_ulong target = dc->pc + offset;
1456
1457 flush_cond(dc, r_cond);
1458 gen_cond_reg(r_cond, cond, r_reg);
1459 if (a) {
1460 gen_branch_a(dc, target, dc->npc, r_cond);
1461 dc->is_br = 1;
1462 } else {
1463 dc->pc = dc->npc;
1464 dc->jump_pc[0] = target;
1465 dc->jump_pc[1] = dc->npc + 4;
1466 dc->npc = JUMP_PC;
1467 }
1468 }
1469
1470 static GenOpFunc * const gen_fcmpd[4] = {
1471 helper_fcmpd,
1472 helper_fcmpd_fcc1,
1473 helper_fcmpd_fcc2,
1474 helper_fcmpd_fcc3,
1475 };
1476
1477 static GenOpFunc * const gen_fcmpq[4] = {
1478 helper_fcmpq,
1479 helper_fcmpq_fcc1,
1480 helper_fcmpq_fcc2,
1481 helper_fcmpq_fcc3,
1482 };
1483
1484 static GenOpFunc * const gen_fcmped[4] = {
1485 helper_fcmped,
1486 helper_fcmped_fcc1,
1487 helper_fcmped_fcc2,
1488 helper_fcmped_fcc3,
1489 };
1490
1491 static GenOpFunc * const gen_fcmpeq[4] = {
1492 helper_fcmpeq,
1493 helper_fcmpeq_fcc1,
1494 helper_fcmpeq_fcc2,
1495 helper_fcmpeq_fcc3,
1496 };
1497
1498 static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
1499 {
1500 switch (fccno) {
1501 case 0:
1502 tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2);
1503 break;
1504 case 1:
1505 tcg_gen_helper_0_2(helper_fcmps_fcc1, r_rs1, r_rs2);
1506 break;
1507 case 2:
1508 tcg_gen_helper_0_2(helper_fcmps_fcc2, r_rs1, r_rs2);
1509 break;
1510 case 3:
1511 tcg_gen_helper_0_2(helper_fcmps_fcc3, r_rs1, r_rs2);
1512 break;
1513 }
1514 }
1515
1516 static inline void gen_op_fcmpd(int fccno)
1517 {
1518 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1519 }
1520
1521 static inline void gen_op_fcmpq(int fccno)
1522 {
1523 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1524 }
1525
1526 static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
1527 {
1528 switch (fccno) {
1529 case 0:
1530 tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2);
1531 break;
1532 case 1:
1533 tcg_gen_helper_0_2(helper_fcmpes_fcc1, r_rs1, r_rs2);
1534 break;
1535 case 2:
1536 tcg_gen_helper_0_2(helper_fcmpes_fcc2, r_rs1, r_rs2);
1537 break;
1538 case 3:
1539 tcg_gen_helper_0_2(helper_fcmpes_fcc3, r_rs1, r_rs2);
1540 break;
1541 }
1542 }
1543
1544 static inline void gen_op_fcmped(int fccno)
1545 {
1546 tcg_gen_helper_0_0(gen_fcmped[fccno]);
1547 }
1548
1549 static inline void gen_op_fcmpeq(int fccno)
1550 {
1551 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1552 }
1553
1554 #else
1555
1556 static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
1557 {
1558 tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2);
1559 }
1560
1561 static inline void gen_op_fcmpd(int fccno)
1562 {
1563 tcg_gen_helper_0_0(helper_fcmpd);
1564 }
1565
1566 static inline void gen_op_fcmpq(int fccno)
1567 {
1568 tcg_gen_helper_0_0(helper_fcmpq);
1569 }
1570
1571 static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
1572 {
1573 tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2);
1574 }
1575
1576 static inline void gen_op_fcmped(int fccno)
1577 {
1578 tcg_gen_helper_0_0(helper_fcmped);
1579 }
1580
1581 static inline void gen_op_fcmpeq(int fccno)
1582 {
1583 tcg_gen_helper_0_0(helper_fcmpeq);
1584 }
1585 #endif
1586
1587 static inline void gen_op_fpexception_im(int fsr_flags)
1588 {
1589 TCGv r_const;
1590
1591 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
1592 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1593 r_const = tcg_const_i32(TT_FP_EXCP);
1594 tcg_gen_helper_0_1(raise_exception, r_const);
1595 tcg_temp_free(r_const);
1596 }
1597
1598 static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1599 {
1600 #if !defined(CONFIG_USER_ONLY)
1601 if (!dc->fpu_enabled) {
1602 TCGv r_const;
1603
1604 save_state(dc, r_cond);
1605 r_const = tcg_const_i32(TT_NFPU_INSN);
1606 tcg_gen_helper_0_1(raise_exception, r_const);
1607 tcg_temp_free(r_const);
1608 dc->is_br = 1;
1609 return 1;
1610 }
1611 #endif
1612 return 0;
1613 }
1614
1615 static inline void gen_op_clear_ieee_excp_and_FTT(void)
1616 {
1617 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
1618 }
1619
1620 static inline void gen_clear_float_exceptions(void)
1621 {
1622 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1623 }
1624
1625 /* asi moves */
1626 #ifdef TARGET_SPARC64
1627 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1628 {
1629 int asi;
1630 TCGv r_asi;
1631
1632 if (IS_IMM) {
1633 r_asi = tcg_temp_new(TCG_TYPE_I32);
1634 tcg_gen_mov_i32(r_asi, cpu_asi);
1635 } else {
1636 asi = GET_FIELD(insn, 19, 26);
1637 r_asi = tcg_const_i32(asi);
1638 }
1639 return r_asi;
1640 }
1641
1642 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1643 int sign)
1644 {
1645 TCGv r_asi, r_size, r_sign;
1646
1647 r_asi = gen_get_asi(insn, addr);
1648 r_size = tcg_const_i32(size);
1649 r_sign = tcg_const_i32(sign);
1650 tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1651 tcg_temp_free(r_sign);
1652 tcg_temp_free(r_size);
1653 tcg_temp_free(r_asi);
1654 }
1655
1656 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1657 {
1658 TCGv r_asi, r_size;
1659
1660 r_asi = gen_get_asi(insn, addr);
1661 r_size = tcg_const_i32(size);
1662 tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1663 tcg_temp_free(r_size);
1664 tcg_temp_free(r_asi);
1665 }
1666
1667 static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1668 {
1669 TCGv r_asi, r_size, r_rd;
1670
1671 r_asi = gen_get_asi(insn, addr);
1672 r_size = tcg_const_i32(size);
1673 r_rd = tcg_const_i32(rd);
1674 tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1675 tcg_temp_free(r_rd);
1676 tcg_temp_free(r_size);
1677 tcg_temp_free(r_asi);
1678 }
1679
1680 static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1681 {
1682 TCGv r_asi, r_size, r_rd;
1683
1684 r_asi = gen_get_asi(insn, addr);
1685 r_size = tcg_const_i32(size);
1686 r_rd = tcg_const_i32(rd);
1687 tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1688 tcg_temp_free(r_rd);
1689 tcg_temp_free(r_size);
1690 tcg_temp_free(r_asi);
1691 }
1692
1693 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1694 {
1695 TCGv r_asi, r_size, r_sign;
1696
1697 r_asi = gen_get_asi(insn, addr);
1698 r_size = tcg_const_i32(4);
1699 r_sign = tcg_const_i32(0);
1700 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1701 tcg_temp_free(r_sign);
1702 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1703 tcg_temp_free(r_size);
1704 tcg_temp_free(r_asi);
1705 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1706 }
1707
1708 static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1709 {
1710 TCGv r_asi, r_rd;
1711
1712 r_asi = gen_get_asi(insn, addr);
1713 r_rd = tcg_const_i32(rd);
1714 tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
1715 tcg_temp_free(r_rd);
1716 tcg_temp_free(r_asi);
1717 }
1718
1719 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1720 {
1721 TCGv r_asi, r_size;
1722
1723 gen_movl_reg_TN(rd + 1, cpu_tmp0);
1724 tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
1725 r_asi = gen_get_asi(insn, addr);
1726 r_size = tcg_const_i32(8);
1727 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1728 tcg_temp_free(r_size);
1729 tcg_temp_free(r_asi);
1730 }
1731
1732 static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1733 int rd)
1734 {
1735 TCGv r_val1, r_asi;
1736
1737 r_val1 = tcg_temp_new(TCG_TYPE_TL);
1738 gen_movl_reg_TN(rd, r_val1);
1739 r_asi = gen_get_asi(insn, addr);
1740 tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1741 tcg_temp_free(r_asi);
1742 tcg_temp_free(r_val1);
1743 }
1744
1745 static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1746 int rd)
1747 {
1748 TCGv r_asi;
1749
1750 gen_movl_reg_TN(rd, cpu_tmp64);
1751 r_asi = gen_get_asi(insn, addr);
1752 tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1753 tcg_temp_free(r_asi);
1754 }
1755
1756 #elif !defined(CONFIG_USER_ONLY)
1757
1758 static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1759 int sign)
1760 {
1761 TCGv r_asi, r_size, r_sign;
1762
1763 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1764 r_size = tcg_const_i32(size);
1765 r_sign = tcg_const_i32(sign);
1766 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1767 tcg_temp_free(r_sign);
1768 tcg_temp_free(r_size);
1769 tcg_temp_free(r_asi);
1770 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1771 }
1772
1773 static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1774 {
1775 TCGv r_asi, r_size;
1776
1777 tcg_gen_extu_tl_i64(cpu_tmp64, src);
1778 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1779 r_size = tcg_const_i32(size);
1780 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1781 tcg_temp_free(r_size);
1782 tcg_temp_free(r_asi);
1783 }
1784
1785 static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1786 {
1787 TCGv r_asi, r_size, r_sign;
1788
1789 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1790 r_size = tcg_const_i32(4);
1791 r_sign = tcg_const_i32(0);
1792 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1793 tcg_temp_free(r_sign);
1794 tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1795 tcg_temp_free(r_size);
1796 tcg_temp_free(r_asi);
1797 tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1798 }
1799
1800 static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1801 {
1802 TCGv r_asi, r_size, r_sign;
1803
1804 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1805 r_size = tcg_const_i32(8);
1806 r_sign = tcg_const_i32(0);
1807 tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1808 tcg_temp_free(r_sign);
1809 tcg_temp_free(r_size);
1810 tcg_temp_free(r_asi);
1811 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1812 gen_movl_TN_reg(rd + 1, cpu_tmp0);
1813 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1814 tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1815 gen_movl_TN_reg(rd, hi);
1816 }
1817
1818 static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1819 {
1820 TCGv r_asi, r_size;
1821
1822 gen_movl_reg_TN(rd + 1, cpu_tmp0);
1823 tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
1824 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1825 r_size = tcg_const_i32(8);
1826 tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1827 tcg_temp_free(r_size);
1828 tcg_temp_free(r_asi);
1829 }
1830 #endif
1831
1832 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1833 static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1834 {
1835 TCGv r_val, r_asi, r_size;
1836
1837 gen_ld_asi(dst, addr, insn, 1, 0);
1838
1839 r_val = tcg_const_i64(0xffULL);
1840 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1841 r_size = tcg_const_i32(1);
1842 tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1843 tcg_temp_free(r_size);
1844 tcg_temp_free(r_asi);
1845 tcg_temp_free(r_val);
1846 }
1847 #endif
1848
1849 static inline TCGv get_src1(unsigned int insn, TCGv def)
1850 {
1851 TCGv r_rs1 = def;
1852 unsigned int rs1;
1853
1854 rs1 = GET_FIELD(insn, 13, 17);
1855 if (rs1 == 0)
1856 r_rs1 = tcg_const_tl(0); // XXX how to free?
1857 else if (rs1 < 8)
1858 r_rs1 = cpu_gregs[rs1];
1859 else
1860 tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1861 return r_rs1;
1862 }
1863
1864 static inline TCGv get_src2(unsigned int insn, TCGv def)
1865 {
1866 TCGv r_rs2 = def;
1867 unsigned int rs2;
1868
1869 if (IS_IMM) { /* immediate */
1870 rs2 = GET_FIELDs(insn, 19, 31);
1871 r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1872 } else { /* register */
1873 rs2 = GET_FIELD(insn, 27, 31);
1874 if (rs2 == 0)
1875 r_rs2 = tcg_const_tl(0); // XXX how to free?
1876 else if (rs2 < 8)
1877 r_rs2 = cpu_gregs[rs2];
1878 else
1879 tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1880 }
1881 return r_rs2;
1882 }
1883
1884 #define CHECK_IU_FEATURE(dc, FEATURE) \
1885 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1886 goto illegal_insn;
1887 #define CHECK_FPU_FEATURE(dc, FEATURE) \
1888 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1889 goto nfpu_insn;
1890
1891 /* before an instruction, dc->pc must be static */
1892 static void disas_sparc_insn(DisasContext * dc)
1893 {
1894 unsigned int insn, opc, rs1, rs2, rd;
1895
1896 if (unlikely(loglevel & CPU_LOG_TB_OP))
1897 tcg_gen_debug_insn_start(dc->pc);
1898 insn = ldl_code(dc->pc);
1899 opc = GET_FIELD(insn, 0, 1);
1900
1901 rd = GET_FIELD(insn, 2, 6);
1902
1903 cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1904 cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1905
1906 switch (opc) {
1907 case 0: /* branches/sethi */
1908 {
1909 unsigned int xop = GET_FIELD(insn, 7, 9);
1910 int32_t target;
1911 switch (xop) {
1912 #ifdef TARGET_SPARC64
1913 case 0x1: /* V9 BPcc */
1914 {
1915 int cc;
1916
1917 target = GET_FIELD_SP(insn, 0, 18);
1918 target = sign_extend(target, 18);
1919 target <<= 2;
1920 cc = GET_FIELD_SP(insn, 20, 21);
1921 if (cc == 0)
1922 do_branch(dc, target, insn, 0, cpu_cond);
1923 else if (cc == 2)
1924 do_branch(dc, target, insn, 1, cpu_cond);
1925 else
1926 goto illegal_insn;
1927 goto jmp_insn;
1928 }
1929 case 0x3: /* V9 BPr */
1930 {
1931 target = GET_FIELD_SP(insn, 0, 13) |
1932 (GET_FIELD_SP(insn, 20, 21) << 14);
1933 target = sign_extend(target, 16);
1934 target <<= 2;
1935 cpu_src1 = get_src1(insn, cpu_src1);
1936 do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1937 goto jmp_insn;
1938 }
1939 case 0x5: /* V9 FBPcc */
1940 {
1941 int cc = GET_FIELD_SP(insn, 20, 21);
1942 if (gen_trap_ifnofpu(dc, cpu_cond))
1943 goto jmp_insn;
1944 target = GET_FIELD_SP(insn, 0, 18);
1945 target = sign_extend(target, 19);
1946 target <<= 2;
1947 do_fbranch(dc, target, insn, cc, cpu_cond);
1948 goto jmp_insn;
1949 }
1950 #else
1951 case 0x7: /* CBN+x */
1952 {
1953 goto ncp_insn;
1954 }
1955 #endif
1956 case 0x2: /* BN+x */
1957 {
1958 target = GET_FIELD(insn, 10, 31);
1959 target = sign_extend(target, 22);
1960 target <<= 2;
1961 do_branch(dc, target, insn, 0, cpu_cond);
1962 goto jmp_insn;
1963 }
1964 case 0x6: /* FBN+x */
1965 {
1966 if (gen_trap_ifnofpu(dc, cpu_cond))
1967 goto jmp_insn;
1968 target = GET_FIELD(insn, 10, 31);
1969 target = sign_extend(target, 22);
1970 target <<= 2;
1971 do_fbranch(dc, target, insn, 0, cpu_cond);
1972 goto jmp_insn;
1973 }
1974 case 0x4: /* SETHI */
1975 if (rd) { // nop
1976 uint32_t value = GET_FIELD(insn, 10, 31);
1977 TCGv r_const;
1978
1979 r_const = tcg_const_tl(value << 10);
1980 gen_movl_TN_reg(rd, r_const);
1981 tcg_temp_free(r_const);
1982 }
1983 break;
1984 case 0x0: /* UNIMPL */
1985 default:
1986 goto illegal_insn;
1987 }
1988 break;
1989 }
1990 break;
1991 case 1:
1992 /*CALL*/ {
1993 target_long target = GET_FIELDs(insn, 2, 31) << 2;
1994 TCGv r_const;
1995
1996 r_const = tcg_const_tl(dc->pc);
1997 gen_movl_TN_reg(15, r_const);
1998 tcg_temp_free(r_const);
1999 target += dc->pc;
2000 gen_mov_pc_npc(dc, cpu_cond);
2001 dc->npc = target;
2002 }
2003 goto jmp_insn;
2004 case 2: /* FPU & Logical Operations */
2005 {
2006 unsigned int xop = GET_FIELD(insn, 7, 12);
2007 if (xop == 0x3a) { /* generate trap */
2008 int cond;
2009
2010 cpu_src1 = get_src1(insn, cpu_src1);
2011 if (IS_IMM) {
2012 rs2 = GET_FIELD(insn, 25, 31);
2013 tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2014 } else {
2015 rs2 = GET_FIELD(insn, 27, 31);
2016 if (rs2 != 0) {
2017 gen_movl_reg_TN(rs2, cpu_src2);
2018 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2019 } else
2020 tcg_gen_mov_tl(cpu_dst, cpu_src1);
2021 }
2022 cond = GET_FIELD(insn, 3, 6);
2023 if (cond == 0x8) {
2024 save_state(dc, cpu_cond);
2025 if ((dc->def->features & CPU_FEATURE_HYPV) &&
2026 supervisor(dc))
2027 tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
2028 else
2029 tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
2030 tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
2031 tcg_gen_helper_0_1(raise_exception, cpu_dst);
2032 } else if (cond != 0) {
2033 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2034 int l1;
2035 #ifdef TARGET_SPARC64
2036 /* V9 icc/xcc */
2037 int cc = GET_FIELD_SP(insn, 11, 12);
2038
2039 save_state(dc, cpu_cond);
2040 if (cc == 0)
2041 gen_cond(r_cond, 0, cond);
2042 else if (cc == 2)
2043 gen_cond(r_cond, 1, cond);
2044 else
2045 goto illegal_insn;
2046 #else
2047 save_state(dc, cpu_cond);
2048 gen_cond(r_cond, 0, cond);
2049 #endif
2050 l1 = gen_new_label();
2051 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
2052
2053 if ((dc->def->features & CPU_FEATURE_HYPV) &&
2054 supervisor(dc))
2055 tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
2056 else
2057 tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
2058 tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
2059 tcg_gen_helper_0_1(raise_exception, cpu_dst);
2060
2061 gen_set_label(l1);
2062 tcg_temp_free(r_cond);
2063 }
2064 gen_op_next_insn();
2065 tcg_gen_exit_tb(0);
2066 dc->is_br = 1;
2067 goto jmp_insn;
2068 } else if (xop == 0x28) {
2069 rs1 = GET_FIELD(insn, 13, 17);
2070 switch(rs1) {
2071 case 0: /* rdy */
2072 #ifndef TARGET_SPARC64
2073 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2074 manual, rdy on the microSPARC
2075 II */
2076 case 0x0f: /* stbar in the SPARCv8 manual,
2077 rdy on the microSPARC II */
2078 case 0x10 ... 0x1f: /* implementation-dependent in the
2079 SPARCv8 manual, rdy on the
2080 microSPARC II */
2081 #endif
2082 gen_movl_TN_reg(rd, cpu_y);
2083 break;
2084 #ifdef TARGET_SPARC64
2085 case 0x2: /* V9 rdccr */
2086 tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2087 gen_movl_TN_reg(rd, cpu_dst);
2088 break;
2089 case 0x3: /* V9 rdasi */
2090 tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
2091 gen_movl_TN_reg(rd, cpu_dst);
2092 break;
2093 case 0x4: /* V9 rdtick */
2094 {
2095 TCGv r_tickptr;
2096
2097 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2098 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2099 offsetof(CPUState, tick));
2100 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2101 r_tickptr);
2102 tcg_temp_free(r_tickptr);
2103 gen_movl_TN_reg(rd, cpu_dst);
2104 }
2105 break;
2106 case 0x5: /* V9 rdpc */
2107 {
2108 TCGv r_const;
2109
2110 r_const = tcg_const_tl(dc->pc);
2111 gen_movl_TN_reg(rd, r_const);
2112 tcg_temp_free(r_const);
2113 }
2114 break;
2115 case 0x6: /* V9 rdfprs */
2116 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
2117 gen_movl_TN_reg(rd, cpu_dst);
2118 break;
2119 case 0xf: /* V9 membar */
2120 break; /* no effect */
2121 case 0x13: /* Graphics Status */
2122 if (gen_trap_ifnofpu(dc, cpu_cond))
2123 goto jmp_insn;
2124 gen_movl_TN_reg(rd, cpu_gsr);
2125 break;
2126 case 0x16: /* Softint */
2127 tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
2128 gen_movl_TN_reg(rd, cpu_dst);
2129 break;
2130 case 0x17: /* Tick compare */
2131 gen_movl_TN_reg(rd, cpu_tick_cmpr);
2132 break;
2133 case 0x18: /* System tick */
2134 {
2135 TCGv r_tickptr;
2136
2137 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2138 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2139 offsetof(CPUState, stick));
2140 tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2141 r_tickptr);
2142 tcg_temp_free(r_tickptr);
2143 gen_movl_TN_reg(rd, cpu_dst);
2144 }
2145 break;
2146 case 0x19: /* System tick compare */
2147 gen_movl_TN_reg(rd, cpu_stick_cmpr);
2148 break;
2149 case 0x10: /* Performance Control */
2150 case 0x11: /* Performance Instrumentation Counter */
2151 case 0x12: /* Dispatch Control */
2152 case 0x14: /* Softint set, WO */
2153 case 0x15: /* Softint clear, WO */
2154 #endif
2155 default:
2156 goto illegal_insn;
2157 }
2158 #if !defined(CONFIG_USER_ONLY)
2159 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2160 #ifndef TARGET_SPARC64
2161 if (!supervisor(dc))
2162 goto priv_insn;
2163 tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2164 #else
2165 CHECK_IU_FEATURE(dc, HYPV);
2166 if (!hypervisor(dc))
2167 goto priv_insn;
2168 rs1 = GET_FIELD(insn, 13, 17);
2169 switch (rs1) {
2170 case 0: // hpstate
2171 // gen_op_rdhpstate();
2172 break;
2173 case 1: // htstate
2174 // gen_op_rdhtstate();
2175 break;
2176 case 3: // hintp
2177 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
2178 break;
2179 case 5: // htba
2180 tcg_gen_mov_tl(cpu_dst, cpu_htba);
2181 break;
2182 case 6: // hver
2183 tcg_gen_mov_tl(cpu_dst, cpu_hver);
2184 break;
2185 case 31: // hstick_cmpr
2186 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
2187 break;
2188 default:
2189 goto illegal_insn;
2190 }
2191 #endif
2192 gen_movl_TN_reg(rd, cpu_dst);
2193 break;
2194 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2195 if (!supervisor(dc))
2196 goto priv_insn;
2197 #ifdef TARGET_SPARC64
2198 rs1 = GET_FIELD(insn, 13, 17);
2199 switch (rs1) {
2200 case 0: // tpc
2201 {
2202 TCGv r_tsptr;
2203
2204 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2205 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2206 offsetof(CPUState, tsptr));
2207 tcg_gen_ld_tl(cpu_tmp32, r_tsptr,
2208 offsetof(trap_state, tpc));
2209 tcg_temp_free(r_tsptr);
2210 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2211 }
2212 break;
2213 case 1: // tnpc
2214 {
2215 TCGv r_tsptr;
2216
2217 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2218 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2219 offsetof(CPUState, tsptr));
2220 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2221 offsetof(trap_state, tnpc));
2222 tcg_temp_free(r_tsptr);
2223 }
2224 break;
2225 case 2: // tstate
2226 {
2227 TCGv r_tsptr;
2228
2229 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2230 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2231 offsetof(CPUState, tsptr));
2232 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2233 offsetof(trap_state, tstate));
2234 tcg_temp_free(r_tsptr);
2235 }
2236 break;
2237 case 3: // tt
2238 {
2239 TCGv r_tsptr;
2240
2241 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2242 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2243 offsetof(CPUState, tsptr));
2244 tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2245 offsetof(trap_state, tt));
2246 tcg_temp_free(r_tsptr);
2247 }
2248 break;
2249 case 4: // tick
2250 {
2251 TCGv r_tickptr;
2252
2253 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2254 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2255 offsetof(CPUState, tick));
2256 tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2257 r_tickptr);
2258 gen_movl_TN_reg(rd, cpu_tmp0);
2259 tcg_temp_free(r_tickptr);
2260 }
2261 break;
2262 case 5: // tba
2263 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
2264 break;
2265 case 6: // pstate
2266 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2267 offsetof(CPUSPARCState, pstate));
2268 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2269 break;
2270 case 7: // tl
2271 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2272 offsetof(CPUSPARCState, tl));
2273 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2274 break;
2275 case 8: // pil
2276 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2277 offsetof(CPUSPARCState, psrpil));
2278 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2279 break;
2280 case 9: // cwp
2281 tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2282 break;
2283 case 10: // cansave
2284 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2285 offsetof(CPUSPARCState, cansave));
2286 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2287 break;
2288 case 11: // canrestore
2289 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2290 offsetof(CPUSPARCState, canrestore));
2291 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2292 break;
2293 case 12: // cleanwin
2294 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2295 offsetof(CPUSPARCState, cleanwin));
2296 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2297 break;
2298 case 13: // otherwin
2299 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2300 offsetof(CPUSPARCState, otherwin));
2301 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2302 break;
2303 case 14: // wstate
2304 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2305 offsetof(CPUSPARCState, wstate));
2306 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2307 break;
2308 case 16: // UA2005 gl
2309 CHECK_IU_FEATURE(dc, GL);
2310 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2311 offsetof(CPUSPARCState, gl));
2312 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2313 break;
2314 case 26: // UA2005 strand status
2315 CHECK_IU_FEATURE(dc, HYPV);
2316 if (!hypervisor(dc))
2317 goto priv_insn;
2318 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
2319 break;
2320 case 31: // ver
2321 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
2322 break;
2323 case 15: // fq
2324 default:
2325 goto illegal_insn;
2326 }
2327 #else
2328 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
2329 #endif
2330 gen_movl_TN_reg(rd, cpu_tmp0);
2331 break;
2332 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2333 #ifdef TARGET_SPARC64
2334 save_state(dc, cpu_cond);
2335 tcg_gen_helper_0_0(helper_flushw);
2336 #else
2337 if (!supervisor(dc))
2338 goto priv_insn;
2339 gen_movl_TN_reg(rd, cpu_tbr);
2340 #endif
2341 break;
2342 #endif
2343 } else if (xop == 0x34) { /* FPU Operations */
2344 if (gen_trap_ifnofpu(dc, cpu_cond))
2345 goto jmp_insn;
2346 gen_op_clear_ieee_excp_and_FTT();
2347 rs1 = GET_FIELD(insn, 13, 17);
2348 rs2 = GET_FIELD(insn, 27, 31);
2349 xop = GET_FIELD(insn, 18, 26);
2350 switch (xop) {
2351 case 0x1: /* fmovs */
2352 tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
2353 break;
2354 case 0x5: /* fnegs */
2355 tcg_gen_helper_1_1(helper_fnegs, cpu_fpr[rd],
2356 cpu_fpr[rs2]);
2357 break;
2358 case 0x9: /* fabss */
2359 tcg_gen_helper_1_1(helper_fabss, cpu_fpr[rd],
2360 cpu_fpr[rs2]);
2361 break;
2362 case 0x29: /* fsqrts */
2363 CHECK_FPU_FEATURE(dc, FSQRT);
2364 gen_clear_float_exceptions();
2365 tcg_gen_helper_1_1(helper_fsqrts, cpu_tmp32,
2366 cpu_fpr[rs2]);
2367 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2368 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2369 break;
2370 case 0x2a: /* fsqrtd */
2371 CHECK_FPU_FEATURE(dc, FSQRT);
2372 gen_op_load_fpr_DT1(DFPREG(rs2));
2373 gen_clear_float_exceptions();
2374 tcg_gen_helper_0_0(helper_fsqrtd);
2375 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2376 gen_op_store_DT0_fpr(DFPREG(rd));
2377 break;
2378 case 0x2b: /* fsqrtq */
2379 CHECK_FPU_FEATURE(dc, FLOAT128);
2380 gen_op_load_fpr_QT1(QFPREG(rs2));
2381 gen_clear_float_exceptions();
2382 tcg_gen_helper_0_0(helper_fsqrtq);
2383 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2384 gen_op_store_QT0_fpr(QFPREG(rd));
2385 break;
2386 case 0x41: /* fadds */
2387 gen_clear_float_exceptions();
2388 tcg_gen_helper_1_2(helper_fadds, cpu_tmp32,
2389 cpu_fpr[rs1], cpu_fpr[rs2]);
2390 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2391 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2392 break;
2393 case 0x42:
2394 gen_op_load_fpr_DT0(DFPREG(rs1));
2395 gen_op_load_fpr_DT1(DFPREG(rs2));
2396 gen_clear_float_exceptions();
2397 tcg_gen_helper_0_0(helper_faddd);
2398 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2399 gen_op_store_DT0_fpr(DFPREG(rd));
2400 break;
2401 case 0x43: /* faddq */
2402 CHECK_FPU_FEATURE(dc, FLOAT128);
2403 gen_op_load_fpr_QT0(QFPREG(rs1));
2404 gen_op_load_fpr_QT1(QFPREG(rs2));
2405 gen_clear_float_exceptions();
2406 tcg_gen_helper_0_0(helper_faddq);
2407 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2408 gen_op_store_QT0_fpr(QFPREG(rd));
2409 break;
2410 case 0x45: /* fsubs */
2411 gen_clear_float_exceptions();
2412 tcg_gen_helper_1_2(helper_fsubs, cpu_tmp32,
2413 cpu_fpr[rs1], cpu_fpr[rs2]);
2414 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2415 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2416 break;
2417 case 0x46:
2418 gen_op_load_fpr_DT0(DFPREG(rs1));
2419 gen_op_load_fpr_DT1(DFPREG(rs2));
2420 gen_clear_float_exceptions();
2421 tcg_gen_helper_0_0(helper_fsubd);
2422 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2423 gen_op_store_DT0_fpr(DFPREG(rd));
2424 break;
2425 case 0x47: /* fsubq */
2426 CHECK_FPU_FEATURE(dc, FLOAT128);
2427 gen_op_load_fpr_QT0(QFPREG(rs1));
2428 gen_op_load_fpr_QT1(QFPREG(rs2));
2429 gen_clear_float_exceptions();
2430 tcg_gen_helper_0_0(helper_fsubq);
2431 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2432 gen_op_store_QT0_fpr(QFPREG(rd));
2433 break;
2434 case 0x49: /* fmuls */
2435 CHECK_FPU_FEATURE(dc, FMUL);
2436 gen_clear_float_exceptions();
2437 tcg_gen_helper_1_2(helper_fmuls, cpu_tmp32,
2438 cpu_fpr[rs1], cpu_fpr[rs2]);
2439 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2440 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2441 break;
2442 case 0x4a: /* fmuld */
2443 CHECK_FPU_FEATURE(dc, FMUL);
2444 gen_op_load_fpr_DT0(DFPREG(rs1));
2445 gen_op_load_fpr_DT1(DFPREG(rs2));
2446 gen_clear_float_exceptions();
2447 tcg_gen_helper_0_0(helper_fmuld);
2448 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2449 gen_op_store_DT0_fpr(DFPREG(rd));
2450 break;
2451 case 0x4b: /* fmulq */
2452 CHECK_FPU_FEATURE(dc, FLOAT128);
2453 CHECK_FPU_FEATURE(dc, FMUL);
2454 gen_op_load_fpr_QT0(QFPREG(rs1));
2455 gen_op_load_fpr_QT1(QFPREG(rs2));
2456 gen_clear_float_exceptions();
2457 tcg_gen_helper_0_0(helper_fmulq);
2458 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2459 gen_op_store_QT0_fpr(QFPREG(rd));
2460 break;
2461 case 0x4d: /* fdivs */
2462 gen_clear_float_exceptions();
2463 tcg_gen_helper_1_2(helper_fdivs, cpu_tmp32,
2464 cpu_fpr[rs1], cpu_fpr[rs2]);
2465 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2466 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2467 break;
2468 case 0x4e:
2469 gen_op_load_fpr_DT0(DFPREG(rs1));
2470 gen_op_load_fpr_DT1(DFPREG(rs2));
2471 gen_clear_float_exceptions();
2472 tcg_gen_helper_0_0(helper_fdivd);
2473 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2474 gen_op_store_DT0_fpr(DFPREG(rd));
2475 break;
2476 case 0x4f: /* fdivq */
2477 CHECK_FPU_FEATURE(dc, FLOAT128);
2478 gen_op_load_fpr_QT0(QFPREG(rs1));
2479 gen_op_load_fpr_QT1(QFPREG(rs2));
2480 gen_clear_float_exceptions();
2481 tcg_gen_helper_0_0(helper_fdivq);
2482 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2483 gen_op_store_QT0_fpr(QFPREG(rd));
2484 break;
2485 case 0x69: /* fsmuld */
2486 CHECK_FPU_FEATURE(dc, FSMULD);
2487 gen_clear_float_exceptions();
2488 tcg_gen_helper_0_2(helper_fsmuld, cpu_fpr[rs1],
2489 cpu_fpr[rs2]);
2490 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2491 gen_op_store_DT0_fpr(DFPREG(rd));
2492 break;
2493 case 0x6e: /* fdmulq */
2494 CHECK_FPU_FEATURE(dc, FLOAT128);
2495 gen_op_load_fpr_DT0(DFPREG(rs1));
2496 gen_op_load_fpr_DT1(DFPREG(rs2));
2497 gen_clear_float_exceptions();
2498 tcg_gen_helper_0_0(helper_fdmulq);
2499 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2500 gen_op_store_QT0_fpr(QFPREG(rd));
2501 break;
2502 case 0xc4: /* fitos */
2503 gen_clear_float_exceptions();
2504 tcg_gen_helper_1_1(helper_fitos, cpu_tmp32,
2505 cpu_fpr[rs2]);
2506 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2507 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2508 break;
2509 case 0xc6: /* fdtos */
2510 gen_op_load_fpr_DT1(DFPREG(rs2));
2511 gen_clear_float_exceptions();
2512 tcg_gen_helper_1_0(helper_fdtos, cpu_tmp32);
2513 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2514 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2515 break;
2516 case 0xc7: /* fqtos */
2517 CHECK_FPU_FEATURE(dc, FLOAT128);
2518 gen_op_load_fpr_QT1(QFPREG(rs2));
2519 gen_clear_float_exceptions();
2520 tcg_gen_helper_1_0(helper_fqtos, cpu_tmp32);
2521 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2522 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2523 break;
2524 case 0xc8: /* fitod */
2525 tcg_gen_helper_0_1(helper_fitod, cpu_fpr[rs2]);
2526 gen_op_store_DT0_fpr(DFPREG(rd));
2527 break;
2528 case 0xc9: /* fstod */
2529 tcg_gen_helper_0_1(helper_fstod, cpu_fpr[rs2]);
2530 gen_op_store_DT0_fpr(DFPREG(rd));
2531 break;
2532 case 0xcb: /* fqtod */
2533 CHECK_FPU_FEATURE(dc, FLOAT128);
2534 gen_op_load_fpr_QT1(QFPREG(rs2));
2535 gen_clear_float_exceptions();
2536 tcg_gen_helper_0_0(helper_fqtod);
2537 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2538 gen_op_store_DT0_fpr(DFPREG(rd));
2539 break;
2540 case 0xcc: /* fitoq */
2541 CHECK_FPU_FEATURE(dc, FLOAT128);
2542 tcg_gen_helper_0_1(helper_fitoq, cpu_fpr[rs2]);
2543 gen_op_store_QT0_fpr(QFPREG(rd));
2544 break;
2545 case 0xcd: /* fstoq */
2546 CHECK_FPU_FEATURE(dc, FLOAT128);
2547 tcg_gen_helper_0_1(helper_fstoq, cpu_fpr[rs2]);
2548 gen_op_store_QT0_fpr(QFPREG(rd));
2549 break;
2550 case 0xce: /* fdtoq */
2551 CHECK_FPU_FEATURE(dc, FLOAT128);
2552 gen_op_load_fpr_DT1(DFPREG(rs2));
2553 tcg_gen_helper_0_0(helper_fdtoq);
2554 gen_op_store_QT0_fpr(QFPREG(rd));
2555 break;
2556 case 0xd1: /* fstoi */
2557 gen_clear_float_exceptions();
2558 tcg_gen_helper_1_1(helper_fstoi, cpu_tmp32,
2559 cpu_fpr[rs2]);
2560 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2561 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2562 break;
2563 case 0xd2: /* fdtoi */
2564 gen_op_load_fpr_DT1(DFPREG(rs2));
2565 gen_clear_float_exceptions();
2566 tcg_gen_helper_1_0(helper_fdtoi, cpu_tmp32);
2567 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2568 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2569 break;
2570 case 0xd3: /* fqtoi */
2571 CHECK_FPU_FEATURE(dc, FLOAT128);
2572 gen_op_load_fpr_QT1(QFPREG(rs2));
2573 gen_clear_float_exceptions();
2574 tcg_gen_helper_1_0(helper_fqtoi, cpu_tmp32);
2575 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2576 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2577 break;
2578 #ifdef TARGET_SPARC64
2579 case 0x2: /* V9 fmovd */
2580 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)],
2581 cpu_fpr[DFPREG(rs2)]);
2582 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
2583 cpu_fpr[DFPREG(rs2) + 1]);
2584 break;
2585 case 0x3: /* V9 fmovq */
2586 CHECK_FPU_FEATURE(dc, FLOAT128);
2587 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)],
2588 cpu_fpr[QFPREG(rs2)]);
2589 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
2590 cpu_fpr[QFPREG(rs2) + 1]);
2591 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
2592 cpu_fpr[QFPREG(rs2) + 2]);
2593 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
2594 cpu_fpr[QFPREG(rs2) + 3]);
2595 break;
2596 case 0x6: /* V9 fnegd */
2597 gen_op_load_fpr_DT1(DFPREG(rs2));
2598 tcg_gen_helper_0_0(helper_fnegd);
2599 gen_op_store_DT0_fpr(DFPREG(rd));
2600 break;
2601 case 0x7: /* V9 fnegq */
2602 CHECK_FPU_FEATURE(dc, FLOAT128);
2603 gen_op_load_fpr_QT1(QFPREG(rs2));
2604 tcg_gen_helper_0_0(helper_fnegq);
2605 gen_op_store_QT0_fpr(QFPREG(rd));
2606 break;
2607 case 0xa: /* V9 fabsd */
2608 gen_op_load_fpr_DT1(DFPREG(rs2));
2609 tcg_gen_helper_0_0(helper_fabsd);
2610 gen_op_store_DT0_fpr(DFPREG(rd));
2611 break;
2612 case 0xb: /* V9 fabsq */
2613 CHECK_FPU_FEATURE(dc, FLOAT128);
2614 gen_op_load_fpr_QT1(QFPREG(rs2));
2615 tcg_gen_helper_0_0(helper_fabsq);
2616 gen_op_store_QT0_fpr(QFPREG(rd));
2617 break;
2618 case 0x81: /* V9 fstox */
2619 gen_clear_float_exceptions();
2620 tcg_gen_helper_0_1(helper_fstox, cpu_fpr[rs2]);
2621 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2622 gen_op_store_DT0_fpr(DFPREG(rd));
2623 break;
2624 case 0x82: /* V9 fdtox */
2625 gen_op_load_fpr_DT1(DFPREG(rs2));
2626 gen_clear_float_exceptions();
2627 tcg_gen_helper_0_0(helper_fdtox);
2628 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2629 gen_op_store_DT0_fpr(DFPREG(rd));
2630 break;
2631 case 0x83: /* V9 fqtox */
2632 CHECK_FPU_FEATURE(dc, FLOAT128);
2633 gen_op_load_fpr_QT1(QFPREG(rs2));
2634 gen_clear_float_exceptions();
2635 tcg_gen_helper_0_0(helper_fqtox);
2636 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2637 gen_op_store_DT0_fpr(DFPREG(rd));
2638 break;
2639 case 0x84: /* V9 fxtos */
2640 gen_op_load_fpr_DT1(DFPREG(rs2));
2641 gen_clear_float_exceptions();
2642 tcg_gen_helper_1_0(helper_fxtos, cpu_tmp32);
2643 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2644 tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
2645 break;
2646 case 0x88: /* V9 fxtod */
2647 gen_op_load_fpr_DT1(DFPREG(rs2));
2648 gen_clear_float_exceptions();
2649 tcg_gen_helper_0_0(helper_fxtod);
2650 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2651 gen_op_store_DT0_fpr(DFPREG(rd));
2652 break;
2653 case 0x8c: /* V9 fxtoq */
2654 CHECK_FPU_FEATURE(dc, FLOAT128);
2655 gen_op_load_fpr_DT1(DFPREG(rs2));
2656 gen_clear_float_exceptions();
2657 tcg_gen_helper_0_0(helper_fxtoq);
2658 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2659 gen_op_store_QT0_fpr(QFPREG(rd));
2660 break;
2661 #endif
2662 default:
2663 goto illegal_insn;
2664 }
2665 } else if (xop == 0x35) { /* FPU Operations */
2666 #ifdef TARGET_SPARC64
2667 int cond;
2668 #endif
2669 if (gen_trap_ifnofpu(dc, cpu_cond))
2670 goto jmp_insn;
2671 gen_op_clear_ieee_excp_and_FTT();
2672 rs1 = GET_FIELD(insn, 13, 17);
2673 rs2 = GET_FIELD(insn, 27, 31);
2674 xop = GET_FIELD(insn, 18, 26);
2675 #ifdef TARGET_SPARC64
2676 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2677 int l1;
2678
2679 l1 = gen_new_label();
2680 cond = GET_FIELD_SP(insn, 14, 17);
2681 cpu_src1 = get_src1(insn, cpu_src1);
2682 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2683 0, l1);
2684 tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
2685 gen_set_label(l1);
2686 break;
2687 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2688 int l1;
2689
2690 l1 = gen_new_label();
2691 cond = GET_FIELD_SP(insn, 14, 17);
2692 cpu_src1 = get_src1(insn, cpu_src1);
2693 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2694 0, l1);
2695 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
2696 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]);
2697 gen_set_label(l1);
2698 break;
2699 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2700 int l1;
2701
2702 CHECK_FPU_FEATURE(dc, FLOAT128);
2703 l1 = gen_new_label();
2704 cond = GET_FIELD_SP(insn, 14, 17);
2705 cpu_src1 = get_src1(insn, cpu_src1);
2706 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2707 0, l1);
2708 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]);
2709 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]);
2710 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]);
2711 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]);
2712 gen_set_label(l1);
2713 break;
2714 }
2715 #endif
2716 switch (xop) {
2717 #ifdef TARGET_SPARC64
2718 #define FMOVSCC(fcc) \
2719 { \
2720 TCGv r_cond; \
2721 int l1; \
2722 \
2723 l1 = gen_new_label(); \
2724 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2725 cond = GET_FIELD_SP(insn, 14, 17); \
2726 gen_fcond(r_cond, fcc, cond); \
2727 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2728 0, l1); \
2729 tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \
2730 gen_set_label(l1); \
2731 tcg_temp_free(r_cond); \
2732 }
2733 #define FMOVDCC(fcc) \
2734 { \
2735 TCGv r_cond; \
2736 int l1; \
2737 \
2738 l1 = gen_new_label(); \
2739 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2740 cond = GET_FIELD_SP(insn, 14, 17); \
2741 gen_fcond(r_cond, fcc, cond); \
2742 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2743 0, l1); \
2744 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \
2745 cpu_fpr[DFPREG(rs2)]); \
2746 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
2747 cpu_fpr[DFPREG(rs2) + 1]); \
2748 gen_set_label(l1); \
2749 tcg_temp_free(r_cond); \
2750 }
2751 #define FMOVQCC(fcc) \
2752 { \
2753 TCGv r_cond; \
2754 int l1; \
2755 \
2756 l1 = gen_new_label(); \
2757 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2758 cond = GET_FIELD_SP(insn, 14, 17); \
2759 gen_fcond(r_cond, fcc, cond); \
2760 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2761 0, l1); \
2762 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \
2763 cpu_fpr[QFPREG(rs2)]); \
2764 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
2765 cpu_fpr[QFPREG(rs2) + 1]); \
2766 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
2767 cpu_fpr[QFPREG(rs2) + 2]); \
2768 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
2769 cpu_fpr[QFPREG(rs2) + 3]); \
2770 gen_set_label(l1); \
2771 tcg_temp_free(r_cond); \
2772 }
2773 case 0x001: /* V9 fmovscc %fcc0 */
2774 FMOVSCC(0);
2775 break;
2776 case 0x002: /* V9 fmovdcc %fcc0 */
2777 FMOVDCC(0);
2778 break;
2779 case 0x003: /* V9 fmovqcc %fcc0 */
2780 CHECK_FPU_FEATURE(dc, FLOAT128);
2781 FMOVQCC(0);
2782 break;
2783 case 0x041: /* V9 fmovscc %fcc1 */
2784 FMOVSCC(1);
2785 break;
2786 case 0x042: /* V9 fmovdcc %fcc1 */
2787 FMOVDCC(1);
2788 break;
2789 case 0x043: /* V9 fmovqcc %fcc1 */
2790 CHECK_FPU_FEATURE(dc, FLOAT128);
2791 FMOVQCC(1);
2792 break;
2793 case 0x081: /* V9 fmovscc %fcc2 */
2794 FMOVSCC(2);
2795 break;
2796 case 0x082: /* V9 fmovdcc %fcc2 */
2797 FMOVDCC(2);
2798 break;
2799 case 0x083: /* V9 fmovqcc %fcc2 */
2800 CHECK_FPU_FEATURE(dc, FLOAT128);
2801 FMOVQCC(2);
2802 break;
2803 case 0x0c1: /* V9 fmovscc %fcc3 */
2804 FMOVSCC(3);
2805 break;
2806 case 0x0c2: /* V9 fmovdcc %fcc3 */
2807 FMOVDCC(3);
2808 break;
2809 case 0x0c3: /* V9 fmovqcc %fcc3 */
2810 CHECK_FPU_FEATURE(dc, FLOAT128);
2811 FMOVQCC(3);
2812 break;
2813 #undef FMOVSCC
2814 #undef FMOVDCC
2815 #undef FMOVQCC
2816 #define FMOVCC(size_FDQ, icc) \
2817 { \
2818 TCGv r_cond; \
2819 int l1; \
2820 \
2821 l1 = gen_new_label(); \
2822 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2823 cond = GET_FIELD_SP(insn, 14, 17); \
2824 gen_cond(r_cond, icc, cond); \
2825 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2826 0, l1); \
2827 glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2828 (glue(size_FDQ, FPREG(rs2))); \
2829 glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2830 (glue(size_FDQ, FPREG(rd))); \
2831 gen_set_label(l1); \
2832 tcg_temp_free(r_cond); \
2833 }
2834 #define FMOVSCC(icc) \
2835 { \
2836 TCGv r_cond; \
2837 int l1; \
2838 \
2839 l1 = gen_new_label(); \
2840 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2841 cond = GET_FIELD_SP(insn, 14, 17); \
2842 gen_cond(r_cond, icc, cond); \
2843 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2844 0, l1); \
2845 tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \
2846 gen_set_label(l1); \
2847 tcg_temp_free(r_cond); \
2848 }
2849 #define FMOVDCC(icc) \
2850 { \
2851 TCGv r_cond; \
2852 int l1; \
2853 \
2854 l1 = gen_new_label(); \
2855 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2856 cond = GET_FIELD_SP(insn, 14, 17); \
2857 gen_cond(r_cond, icc, cond); \
2858 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2859 0, l1); \
2860 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \
2861 cpu_fpr[DFPREG(rs2)]); \
2862 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
2863 cpu_fpr[DFPREG(rs2) + 1]); \
2864 gen_set_label(l1); \
2865 tcg_temp_free(r_cond); \
2866 }
2867 #define FMOVQCC(icc) \
2868 { \
2869 TCGv r_cond; \
2870 int l1; \
2871 \
2872 l1 = gen_new_label(); \
2873 r_cond = tcg_temp_new(TCG_TYPE_TL); \
2874 cond = GET_FIELD_SP(insn, 14, 17); \
2875 gen_cond(r_cond, icc, cond); \
2876 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2877 0, l1); \
2878 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \
2879 cpu_fpr[QFPREG(rs2)]); \
2880 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
2881 cpu_fpr[QFPREG(rs2) + 1]); \
2882 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
2883 cpu_fpr[QFPREG(rs2) + 2]); \
2884 tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
2885 cpu_fpr[QFPREG(rs2) + 3]); \
2886 gen_set_label(l1); \
2887 tcg_temp_free(r_cond); \
2888 }
2889
2890 case 0x101: /* V9 fmovscc %icc */
2891 FMOVSCC(0);
2892 break;
2893 case 0x102: /* V9 fmovdcc %icc */
2894 FMOVDCC(0);
2895 case 0x103: /* V9 fmovqcc %icc */
2896 CHECK_FPU_FEATURE(dc, FLOAT128);
2897 FMOVQCC(0);
2898 break;
2899 case 0x181: /* V9 fmovscc %xcc */
2900 FMOVSCC(1);
2901 break;
2902 case 0x182: /* V9 fmovdcc %xcc */
2903 FMOVDCC(1);
2904 break;
2905 case 0x183: /* V9 fmovqcc %xcc */
2906 CHECK_FPU_FEATURE(dc, FLOAT128);
2907 FMOVQCC(1);
2908 break;
2909 #undef FMOVSCC
2910 #undef FMOVDCC
2911 #undef FMOVQCC
2912 #endif
2913 case 0x51: /* fcmps, V9 %fcc */
2914 gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
2915 break;
2916 case 0x52: /* fcmpd, V9 %fcc */
2917 gen_op_load_fpr_DT0(DFPREG(rs1));
2918 gen_op_load_fpr_DT1(DFPREG(rs2));
2919 gen_op_fcmpd(rd & 3);
2920 break;
2921 case 0x53: /* fcmpq, V9 %fcc */
2922 CHECK_FPU_FEATURE(dc, FLOAT128);
2923 gen_op_load_fpr_QT0(QFPREG(rs1));
2924 gen_op_load_fpr_QT1(QFPREG(rs2));
2925 gen_op_fcmpq(rd & 3);
2926 break;
2927 case 0x55: /* fcmpes, V9 %fcc */
2928 gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
2929 break;
2930 case 0x56: /* fcmped, V9 %fcc */
2931 gen_op_load_fpr_DT0(DFPREG(rs1));
2932 gen_op_load_fpr_DT1(DFPREG(rs2));
2933 gen_op_fcmped(rd & 3);
2934 break;
2935 case 0x57: /* fcmpeq, V9 %fcc */
2936 CHECK_FPU_FEATURE(dc, FLOAT128);
2937 gen_op_load_fpr_QT0(QFPREG(rs1));
2938 gen_op_load_fpr_QT1(QFPREG(rs2));
2939 gen_op_fcmpeq(rd & 3);
2940 break;
2941 default:
2942 goto illegal_insn;
2943 }
2944 } else if (xop == 0x2) {
2945 // clr/mov shortcut
2946
2947 rs1 = GET_FIELD(insn, 13, 17);
2948 if (rs1 == 0) {
2949 // or %g0, x, y -> mov T0, x; mov y, T0
2950 if (IS_IMM) { /* immediate */
2951 TCGv r_const;
2952
2953 rs2 = GET_FIELDs(insn, 19, 31);
2954 r_const = tcg_const_tl((int)rs2);
2955 gen_movl_TN_reg(rd, r_const);
2956 tcg_temp_free(r_const);
2957 } else { /* register */
2958 rs2 = GET_FIELD(insn, 27, 31);
2959 gen_movl_reg_TN(rs2, cpu_dst);
2960 gen_movl_TN_reg(rd, cpu_dst);
2961 }
2962 } else {
2963 cpu_src1 = get_src1(insn, cpu_src1);
2964 if (IS_IMM) { /* immediate */
2965 rs2 = GET_FIELDs(insn, 19, 31);
2966 tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2967 gen_movl_TN_reg(rd, cpu_dst);
2968 } else { /* register */
2969 // or x, %g0, y -> mov T1, x; mov y, T1
2970 rs2 = GET_FIELD(insn, 27, 31);
2971 if (rs2 != 0) {
2972 gen_movl_reg_TN(rs2, cpu_src2);
2973 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2974 gen_movl_TN_reg(rd, cpu_dst);
2975 } else
2976 gen_movl_TN_reg(rd, cpu_src1);
2977 }
2978 }
2979 #ifdef TARGET_SPARC64
2980 } else if (xop == 0x25) { /* sll, V9 sllx */
2981 cpu_src1 = get_src1(insn, cpu_src1);
2982 if (IS_IMM) { /* immediate */
2983 rs2 = GET_FIELDs(insn, 20, 31);
2984 if (insn & (1 << 12)) {
2985 tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2986 } else {
2987 tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
2988 }
2989 } else { /* register */
2990 rs2 = GET_FIELD(insn, 27, 31);
2991 gen_movl_reg_TN(rs2, cpu_src2);
2992 if (insn & (1 << 12)) {
2993 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2994 } else {
2995 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2996 }
2997 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2998 }
2999 gen_movl_TN_reg(rd, cpu_dst);
3000 } else if (xop == 0x26) { /* srl, V9 srlx */
3001 cpu_src1 = get_src1(insn, cpu_src1);
3002 if (IS_IMM) { /* immediate */
3003 rs2 = GET_FIELDs(insn, 20, 31);
3004 if (insn & (1 << 12)) {
3005 tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
3006 } else {
3007 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3008 tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
3009 }
3010 } else { /* register */
3011 rs2 = GET_FIELD(insn, 27, 31);
3012 gen_movl_reg_TN(rs2, cpu_src2);
3013 if (insn & (1 << 12)) {
3014 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3015 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
3016 } else {
3017 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3018 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3019 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
3020 }
3021 }
3022 gen_movl_TN_reg(rd, cpu_dst);
3023 } else if (xop == 0x27) { /* sra, V9 srax */
3024 cpu_src1 = get_src1(insn, cpu_src1);
3025 if (IS_IMM) { /* immediate */
3026 rs2 = GET_FIELDs(insn, 20, 31);
3027 if (insn & (1 << 12)) {
3028 tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
3029 } else {
3030 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3031 tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
3032 tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
3033 }
3034 } else { /* register */
3035 rs2 = GET_FIELD(insn, 27, 31);
3036 gen_movl_reg_TN(rs2, cpu_src2);
3037 if (insn & (1 << 12)) {
3038 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3039 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
3040 } else {
3041 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3042 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3043 tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
3044 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
3045 }
3046 }
3047 gen_movl_TN_reg(rd, cpu_dst);
3048 #endif
3049 } else if (xop < 0x36) {
3050 cpu_src1 = get_src1(insn, cpu_src1);
3051 cpu_src2 = get_src2(insn, cpu_src2);
3052 if (xop < 0x20) {
3053 switch (xop & ~0x10) {
3054 case 0x0:
3055 if (xop & 0x10)
3056 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3057 else
3058 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3059 break;
3060 case 0x1:
3061 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
3062 if (xop & 0x10)
3063 gen_op_logic_cc(cpu_dst);
3064 break;
3065 case 0x2:
3066 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3067 if (xop & 0x10)
3068 gen_op_logic_cc(cpu_dst);
3069 break;
3070 case 0x3:
3071 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3072 if (xop & 0x10)
3073 gen_op_logic_cc(cpu_dst);
3074 break;
3075 case 0x4:
3076 if (xop & 0x10)
3077 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3078 else
3079 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3080 break;
3081 case 0x5:
3082 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3083 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3084 if (xop & 0x10)
3085 gen_op_logic_cc(cpu_dst);
3086 break;
3087 case 0x6:
3088 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3089 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3090 if (xop & 0x10)
3091 gen_op_logic_cc(cpu_dst);
3092 break;
3093 case 0x7:
3094 tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3095 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3096 if (xop & 0x10)
3097 gen_op_logic_cc(cpu_dst);
3098 break;
3099 case 0x8:
3100 if (xop & 0x10)
3101 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3102 else {
3103 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3104 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3105 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3106 }
3107 break;
3108 #ifdef TARGET_SPARC64
3109 case 0x9: /* V9 mulx */
3110 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3111 break;
3112 #endif
3113 case 0xa:
3114 CHECK_IU_FEATURE(dc, MUL);
3115 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3116 if (xop & 0x10)
3117 gen_op_logic_cc(cpu_dst);
3118 break;
3119 case 0xb:
3120 CHECK_IU_FEATURE(dc, MUL);
3121 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3122 if (xop & 0x10)
3123 gen_op_logic_cc(cpu_dst);
3124 break;
3125 case 0xc:
3126 if (xop & 0x10)
3127 gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3128 else {
3129 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3130 tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3131 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3132 }
3133 break;
3134 #ifdef TARGET_SPARC64
3135 case 0xd: /* V9 udivx */
3136 tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3137 tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3138 gen_trap_ifdivzero_tl(cpu_cc_src2);
3139 tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3140 break;
3141 #endif
3142 case 0xe:
3143 CHECK_IU_FEATURE(dc, DIV);
3144 tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3145 cpu_src2);
3146 if (xop & 0x10)
3147 gen_op_div_cc(cpu_dst);
3148 break;
3149 case 0xf:
3150 CHECK_IU_FEATURE(dc, DIV);
3151 tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3152 cpu_src2);
3153 if (xop & 0x10)
3154 gen_op_div_cc(cpu_dst);
3155 break;
3156 default:
3157 goto illegal_insn;
3158 }
3159 gen_movl_TN_reg(rd, cpu_dst);
3160 } else {
3161 switch (xop) {
3162 case 0x20: /* taddcc */
3163 gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3164 gen_movl_TN_reg(rd, cpu_dst);
3165 break;
3166 case 0x21: /* tsubcc */
3167 gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3168 gen_movl_TN_reg(rd, cpu_dst);
3169 break;
3170 case 0x22: /* taddcctv */
3171 save_state(dc, cpu_cond);
3172 gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3173 gen_movl_TN_reg(rd, cpu_dst);
3174 break;
3175 case 0x23: /* tsubcctv */
3176 save_state(dc, cpu_cond);
3177 gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3178 gen_movl_TN_reg(rd, cpu_dst);
3179 break;
3180 case 0x24: /* mulscc */
3181 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3182 gen_movl_TN_reg(rd, cpu_dst);
3183 break;
3184 #ifndef TARGET_SPARC64
3185 case 0x25: /* sll */
3186 if (IS_IMM) { /* immediate */
3187 rs2 = GET_FIELDs(insn, 20, 31);
3188 tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3189 } else { /* register */
3190 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3191 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3192 }
3193 gen_movl_TN_reg(rd, cpu_dst);
3194 break;
3195 case 0x26: /* srl */
3196 if (IS_IMM) { /* immediate */
3197 rs2 = GET_FIELDs(insn, 20, 31);
3198 tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3199 } else { /* register */
3200 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3201 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3202 }
3203 gen_movl_TN_reg(rd, cpu_dst);
3204 break;
3205 case 0x27: /* sra */
3206 if (IS_IMM) { /* immediate */
3207 rs2 = GET_FIELDs(insn, 20, 31);
3208 tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3209 } else { /* register */
3210 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3211 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3212 }
3213 gen_movl_TN_reg(rd, cpu_dst);
3214 break;
3215 #endif
3216 case 0x30:
3217 {
3218 switch(rd) {
3219 case 0: /* wry */
3220 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3221 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
3222 break;
3223 #ifndef TARGET_SPARC64
3224 case 0x01 ... 0x0f: /* undefined in the
3225 SPARCv8 manual, nop
3226 on the microSPARC
3227 II */
3228 case 0x10 ... 0x1f: /* implementation-dependent
3229 in the SPARCv8
3230 manual, nop on the
3231 microSPARC II */
3232 break;
3233 #else
3234 case 0x2: /* V9 wrccr */
3235 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3236 tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3237 break;
3238 case 0x3: /* V9 wrasi */
3239 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3240 tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst);
3241 break;
3242 case 0x6: /* V9 wrfprs */
3243 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3244 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst);
3245 save_state(dc, cpu_cond);
3246 gen_op_next_insn();
3247 tcg_gen_exit_tb(0);
3248 dc->is_br = 1;
3249 break;
3250 case 0xf: /* V9 sir, nop if user */
3251 #if !defined(CONFIG_USER_ONLY)
3252 if (supervisor(dc))
3253 ; // XXX
3254 #endif
3255 break;
3256 case 0x13: /* Graphics Status */
3257 if (gen_trap_ifnofpu(dc, cpu_cond))
3258 goto jmp_insn;
3259 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
3260 break;
3261 case 0x14: /* Softint set */
3262 if (!supervisor(dc))
3263 goto illegal_insn;
3264 tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3265 tcg_gen_helper_0_1(helper_set_softint,
3266 cpu_tmp64);
3267 break;
3268 case 0x15: /* Softint clear */
3269 if (!supervisor(dc))
3270 goto illegal_insn;
3271 tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3272 tcg_gen_helper_0_1(helper_clear_softint,
3273 cpu_tmp64);
3274 break;
3275 case 0x16: /* Softint write */
3276 if (!supervisor(dc))
3277 goto illegal_insn;
3278 tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3279 tcg_gen_helper_0_1(helper_write_softint,
3280 cpu_tmp64);
3281 break;
3282 case 0x17: /* Tick compare */
3283 #if !defined(CONFIG_USER_ONLY)
3284 if (!supervisor(dc))
3285 goto illegal_insn;
3286 #endif
3287 {
3288 TCGv r_tickptr;
3289
3290 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
3291 cpu_src2);
3292 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3293 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3294 offsetof(CPUState, tick));
3295 tcg_gen_helper_0_2(helper_tick_set_limit,
3296 r_tickptr, cpu_tick_cmpr);
3297 tcg_temp_free(r_tickptr);
3298 }
3299 break;
3300 case 0x18: /* System tick */
3301 #if !defined(CONFIG_USER_ONLY)
3302 if (!supervisor(dc))
3303 goto illegal_insn;
3304 #endif
3305 {
3306 TCGv r_tickptr;
3307
3308 tcg_gen_xor_tl(cpu_dst, cpu_src1,
3309 cpu_src2);
3310 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3311 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3312 offsetof(CPUState, stick));
3313 tcg_gen_helper_0_2(helper_tick_set_count,
3314 r_tickptr, cpu_dst);
3315 tcg_temp_free(r_tickptr);
3316 }
3317 break;
3318 case 0x19: /* System tick compare */
3319 #if !defined(CONFIG_USER_ONLY)
3320 if (!supervisor(dc))
3321 goto illegal_insn;
3322 #endif
3323 {
3324 TCGv r_tickptr;
3325
3326 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
3327 cpu_src2);
3328 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3329 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3330 offsetof(CPUState, stick));
3331 tcg_gen_helper_0_2(helper_tick_set_limit,
3332 r_tickptr, cpu_stick_cmpr);
3333 tcg_temp_free(r_tickptr);
3334 }
3335 break;
3336
3337 case 0x10: /* Performance Control */
3338 case 0x11: /* Performance Instrumentation
3339 Counter */
3340 case 0x12: /* Dispatch Control */
3341 #endif
3342 default:
3343 goto illegal_insn;
3344 }
3345 }
3346 break;
3347 #if !defined(CONFIG_USER_ONLY)
3348 case 0x31: /* wrpsr, V9 saved, restored */
3349 {
3350 if (!supervisor(dc))
3351 goto priv_insn;
3352 #ifdef TARGET_SPARC64
3353 switch (rd) {
3354 case 0:
3355 tcg_gen_helper_0_0(helper_saved);
3356 break;
3357 case 1:
3358 tcg_gen_helper_0_0(helper_restored);
3359 break;
3360 case 2: /* UA2005 allclean */
3361 case 3: /* UA2005 otherw */
3362 case 4: /* UA2005 normalw */
3363 case 5: /* UA2005 invalw */
3364 // XXX
3365 default:
3366 goto illegal_insn;
3367 }
3368 #else
3369 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3370 tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3371 save_state(dc, cpu_cond);
3372 gen_op_next_insn();
3373 tcg_gen_exit_tb(0);
3374 dc->is_br = 1;
3375 #endif
3376 }
3377 break;
3378 case 0x32: /* wrwim, V9 wrpr */
3379 {
3380 if (!supervisor(dc))
3381 goto priv_insn;
3382 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3383 #ifdef TARGET_SPARC64
3384 switch (rd) {
3385 case 0: // tpc
3386 {
3387 TCGv r_tsptr;
3388
3389 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3390 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3391 offsetof(CPUState, tsptr));
3392 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3393 offsetof(trap_state, tpc));
3394 tcg_temp_free(r_tsptr);
3395 }
3396 break;
3397 case 1: // tnpc
3398 {
3399 TCGv r_tsptr;
3400
3401 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3402 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3403 offsetof(CPUState, tsptr));
3404 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3405 offsetof(trap_state, tnpc));
3406 tcg_temp_free(r_tsptr);
3407 }
3408 break;
3409 case 2: // tstate
3410 {
3411 TCGv r_tsptr;
3412
3413 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3414 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3415 offsetof(CPUState, tsptr));
3416 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3417 offsetof(trap_state,
3418 tstate));
3419 tcg_temp_free(r_tsptr);
3420 }
3421 break;
3422 case 3: // tt
3423 {
3424 TCGv r_tsptr;
3425
3426 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3427 tcg_gen_ld_ptr(r_tsptr, cpu_env,
3428 offsetof(CPUState, tsptr));
3429 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3430 tcg_gen_st_i32(cpu_tmp32, r_tsptr,
3431 offsetof(trap_state, tt));
3432 tcg_temp_free(r_tsptr);
3433 }
3434 break;
3435 case 4: // tick
3436 {
3437 TCGv r_tickptr;
3438
3439 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3440 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3441 offsetof(CPUState, tick));
3442 tcg_gen_helper_0_2(helper_tick_set_count,
3443 r_tickptr, cpu_tmp0);
3444 tcg_temp_free(r_tickptr);
3445 }
3446 break;
3447 case 5: // tba
3448 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
3449 break;
3450 case 6: // pstate
3451 save_state(dc, cpu_cond);
3452 tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3453 gen_op_next_insn();
3454 tcg_gen_exit_tb(0);
3455 dc->is_br = 1;
3456 break;
3457 case 7: // tl
3458 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3459 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3460 offsetof(CPUSPARCState, tl));
3461 break;
3462 case 8: // pil
3463 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3464 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3465 offsetof(CPUSPARCState,
3466 psrpil));
3467 break;
3468 case 9: // cwp
3469 tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3470 break;
3471 case 10: // cansave
3472 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3473 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3474 offsetof(CPUSPARCState,
3475 cansave));
3476 break;
3477 case 11: // canrestore
3478 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3479 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3480 offsetof(CPUSPARCState,
3481 canrestore));
3482 break;
3483 case 12: // cleanwin
3484 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3485 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3486 offsetof(CPUSPARCState,
3487 cleanwin));
3488 break;
3489 case 13: // otherwin
3490 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3491 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3492 offsetof(CPUSPARCState,
3493 otherwin));
3494 break;
3495 case 14: // wstate
3496 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3497 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3498 offsetof(CPUSPARCState,
3499 wstate));
3500 break;
3501 case 16: // UA2005 gl
3502 CHECK_IU_FEATURE(dc, GL);
3503 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3504 tcg_gen_st_i32(cpu_tmp32, cpu_env,
3505 offsetof(CPUSPARCState, gl));
3506 break;
3507 case 26: // UA2005 strand status
3508 CHECK_IU_FEATURE(dc, HYPV);
3509 if (!hypervisor(dc))
3510 goto priv_insn;
3511 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
3512 break;
3513 default:
3514 goto illegal_insn;
3515 }
3516 #else
3517 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3518 if (dc->def->nwindows != 32)
3519 tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
3520 (1 << dc->def->nwindows) - 1);
3521 tcg_gen_mov_i32(cpu_wim, cpu_tmp32);
3522 #endif
3523 }
3524 break;
3525 case 0x33: /* wrtbr, UA2005 wrhpr */
3526 {
3527 #ifndef TARGET_SPARC64
3528 if (!supervisor(dc))
3529 goto priv_insn;
3530 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
3531 #else
3532 CHECK_IU_FEATURE(dc, HYPV);
3533 if (!hypervisor(dc))
3534 goto priv_insn;
3535 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3536 switch (rd) {
3537 case 0: // hpstate
3538 // XXX gen_op_wrhpstate();
3539 save_state(dc, cpu_cond);
3540 gen_op_next_insn();
3541 tcg_gen_exit_tb(0);
3542 dc->is_br = 1;
3543 break;
3544 case 1: // htstate
3545 // XXX gen_op_wrhtstate();
3546 break;
3547 case 3: // hintp
3548 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
3549 break;
3550 case 5: // htba
3551 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
3552 break;
3553 case 31: // hstick_cmpr
3554 {
3555 TCGv r_tickptr;
3556
3557 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
3558 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3559 tcg_gen_ld_ptr(r_tickptr, cpu_env,
3560 offsetof(CPUState, hstick));
3561 tcg_gen_helper_0_2(helper_tick_set_limit,
3562 r_tickptr, cpu_hstick_cmpr);
3563 tcg_temp_free(r_tickptr);
3564 }
3565 break;
3566 case 6: // hver readonly
3567 default:
3568 goto illegal_insn;
3569 }
3570 #endif
3571 }
3572 break;
3573 #endif
3574 #ifdef TARGET_SPARC64
3575 case 0x2c: /* V9 movcc */
3576 {
3577 int cc = GET_FIELD_SP(insn, 11, 12);
3578 int cond = GET_FIELD_SP(insn, 14, 17);
3579 TCGv r_cond;
3580 int l1;
3581
3582 r_cond = tcg_temp_new(TCG_TYPE_TL);
3583 if (insn & (1 << 18)) {
3584 if (cc == 0)
3585 gen_cond(r_cond, 0, cond);
3586 else if (cc == 2)
3587 gen_cond(r_cond, 1, cond);
3588 else
3589 goto illegal_insn;
3590 } else {
3591 gen_fcond(r_cond, cc, cond);
3592 }
3593
3594 l1 = gen_new_label();
3595
3596 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3597 if (IS_IMM) { /* immediate */
3598 TCGv r_const;
3599
3600 rs2 = GET_FIELD_SPs(insn, 0, 10);
3601 r_const = tcg_const_tl((int)rs2);
3602 gen_movl_TN_reg(rd, r_const);
3603 tcg_temp_free(r_const);
3604 } else {
3605 rs2 = GET_FIELD_SP(insn, 0, 4);
3606 gen_movl_reg_TN(rs2, cpu_tmp0);
3607 gen_movl_TN_reg(rd, cpu_tmp0);
3608 }
3609 gen_set_label(l1);
3610 tcg_temp_free(r_cond);
3611 break;
3612 }
3613 case 0x2d: /* V9 sdivx */
3614 gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3615 gen_movl_TN_reg(rd, cpu_dst);
3616 break;
3617 case 0x2e: /* V9 popc */
3618 {
3619 cpu_src2 = get_src2(insn, cpu_src2);
3620 tcg_gen_helper_1_1(helper_popc, cpu_dst,
3621 cpu_src2);
3622 gen_movl_TN_reg(rd, cpu_dst);
3623 }
3624 case 0x2f: /* V9 movr */
3625 {
3626 int cond = GET_FIELD_SP(insn, 10, 12);
3627 int l1;
3628
3629 cpu_src1 = get_src1(insn, cpu_src1);
3630
3631 l1 = gen_new_label();
3632
3633 tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3634 cpu_src1, 0, l1);
3635 if (IS_IMM) { /* immediate */
3636 TCGv r_const;
3637
3638 rs2 = GET_FIELD_SPs(insn, 0, 9);
3639 r_const = tcg_const_tl((int)rs2);
3640 gen_movl_TN_reg(rd, r_const);
3641 tcg_temp_free(r_const);
3642 } else {
3643 rs2 = GET_FIELD_SP(insn, 0, 4);
3644 gen_movl_reg_TN(rs2, cpu_tmp0);
3645 gen_movl_TN_reg(rd, cpu_tmp0);
3646 }
3647 gen_set_label(l1);
3648 break;
3649 }
3650 #endif
3651 default:
3652 goto illegal_insn;
3653 }
3654 }
3655 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3656 #ifdef TARGET_SPARC64
3657 int opf = GET_FIELD_SP(insn, 5, 13);
3658 rs1 = GET_FIELD(insn, 13, 17);
3659 rs2 = GET_FIELD(insn, 27, 31);
3660 if (gen_trap_ifnofpu(dc, cpu_cond))
3661 goto jmp_insn;
3662
3663 switch (opf) {
3664 case 0x000: /* VIS I edge8cc */
3665 case 0x001: /* VIS II edge8n */
3666 case 0x002: /* VIS I edge8lcc */
3667 case 0x003: /* VIS II edge8ln */
3668 case 0x004: /* VIS I edge16cc */
3669 case 0x005: /* VIS II edge16n */
3670 case 0x006: /* VIS I edge16lcc */
3671 case 0x007: /* VIS II edge16ln */
3672 case 0x008: /* VIS I edge32cc */
3673 case 0x009: /* VIS II edge32n */
3674 case 0x00a: /* VIS I edge32lcc */
3675 case 0x00b: /* VIS II edge32ln */
3676 // XXX
3677 goto illegal_insn;
3678 case 0x010: /* VIS I array8 */
3679 CHECK_FPU_FEATURE(dc, VIS1);
3680 cpu_src1 = get_src1(insn, cpu_src1);
3681 gen_movl_reg_TN(rs2, cpu_src2);
3682 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3683 cpu_src2);
3684 gen_movl_TN_reg(rd, cpu_dst);
3685 break;
3686 case 0x012: /* VIS I array16 */
3687 CHECK_FPU_FEATURE(dc, VIS1);
3688 cpu_src1 = get_src1(insn, cpu_src1);
3689 gen_movl_reg_TN(rs2, cpu_src2);
3690 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3691 cpu_src2);
3692 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3693 gen_movl_TN_reg(rd, cpu_dst);
3694 break;
3695 case 0x014: /* VIS I array32 */
3696 CHECK_FPU_FEATURE(dc, VIS1);
3697 cpu_src1 = get_src1(insn, cpu_src1);
3698 gen_movl_reg_TN(rs2, cpu_src2);
3699 tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3700 cpu_src2);
3701 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3702 gen_movl_TN_reg(rd, cpu_dst);
3703 break;
3704 case 0x018: /* VIS I alignaddr */
3705 CHECK_FPU_FEATURE(dc, VIS1);
3706 cpu_src1 = get_src1(insn, cpu_src1);
3707 gen_movl_reg_TN(rs2, cpu_src2);
3708 tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3709 cpu_src2);
3710 gen_movl_TN_reg(rd, cpu_dst);
3711 break;
3712 case 0x019: /* VIS II bmask */
3713 case 0x01a: /* VIS I alignaddrl */
3714 // XXX
3715 goto illegal_insn;
3716 case 0x020: /* VIS I fcmple16 */
3717 CHECK_FPU_FEATURE(dc, VIS1);
3718 gen_op_load_fpr_DT0(DFPREG(rs1));
3719 gen_op_load_fpr_DT1(DFPREG(rs2));
3720 tcg_gen_helper_0_0(helper_fcmple16);
3721 gen_op_store_DT0_fpr(DFPREG(rd));
3722 break;
3723 case 0x022: /* VIS I fcmpne16 */
3724 CHECK_FPU_FEATURE(dc, VIS1);
3725 gen_op_load_fpr_DT0(DFPREG(rs1));
3726 gen_op_load_fpr_DT1(DFPREG(rs2));
3727 tcg_gen_helper_0_0(helper_fcmpne16);
3728 gen_op_store_DT0_fpr(DFPREG(rd));
3729 break;
3730 case 0x024: /* VIS I fcmple32 */
3731 CHECK_FPU_FEATURE(dc, VIS1);
3732 gen_op_load_fpr_DT0(DFPREG(rs1));
3733 gen_op_load_fpr_DT1(DFPREG(rs2));
3734 tcg_gen_helper_0_0(helper_fcmple32);
3735 gen_op_store_DT0_fpr(DFPREG(rd));
3736 break;
3737 case 0x026: /* VIS I fcmpne32 */
3738 CHECK_FPU_FEATURE(dc, VIS1);
3739 gen_op_load_fpr_DT0(DFPREG(rs1));
3740 gen_op_load_fpr_DT1(DFPREG(rs2));
3741 tcg_gen_helper_0_0(helper_fcmpne32);
3742 gen_op_store_DT0_fpr(DFPREG(rd));
3743 break;
3744 case 0x028: /* VIS I fcmpgt16 */
3745 CHECK_FPU_FEATURE(dc, VIS1);
3746 gen_op_load_fpr_DT0(DFPREG(rs1));
3747 gen_op_load_fpr_DT1(DFPREG(rs2));
3748 tcg_gen_helper_0_0(helper_fcmpgt16);
3749 gen_op_store_DT0_fpr(DFPREG(rd));
3750 break;
3751 case 0x02a: /* VIS I fcmpeq16 */
3752 CHECK_FPU_FEATURE(dc, VIS1);
3753 gen_op_load_fpr_DT0(DFPREG(rs1));
3754 gen_op_load_fpr_DT1(DFPREG(rs2));
3755 tcg_gen_helper_0_0(helper_fcmpeq16);
3756 gen_op_store_DT0_fpr(DFPREG(rd));
3757 break;
3758 case 0x02c: /* VIS I fcmpgt32 */
3759 CHECK_FPU_FEATURE(dc, VIS1);
3760 gen_op_load_fpr_DT0(DFPREG(rs1));
3761 gen_op_load_fpr_DT1(DFPREG(rs2));
3762 tcg_gen_helper_0_0(helper_fcmpgt32);
3763 gen_op_store_DT0_fpr(DFPREG(rd));
3764 break;
3765 case 0x02e: /* VIS I fcmpeq32 */
3766 CHECK_FPU_FEATURE(dc, VIS1);
3767 gen_op_load_fpr_DT0(DFPREG(rs1));
3768 gen_op_load_fpr_DT1(DFPREG(rs2));
3769 tcg_gen_helper_0_0(helper_fcmpeq32);
3770 gen_op_store_DT0_fpr(DFPREG(rd));
3771 break;
3772 case 0x031: /* VIS I fmul8x16 */
3773 CHECK_FPU_FEATURE(dc, VIS1);
3774 gen_op_load_fpr_DT0(DFPREG(rs1));
3775 gen_op_load_fpr_DT1(DFPREG(rs2));
3776 tcg_gen_helper_0_0(helper_fmul8x16);
3777 gen_op_store_DT0_fpr(DFPREG(rd));
3778 break;
3779 case 0x033: /* VIS I fmul8x16au */
3780 CHECK_FPU_FEATURE(dc, VIS1);
3781 gen_op_load_fpr_DT0(DFPREG(rs1));
3782 gen_op_load_fpr_DT1(DFPREG(rs2));
3783 tcg_gen_helper_0_0(helper_fmul8x16au);
3784 gen_op_store_DT0_fpr(DFPREG(rd));
3785 break;
3786 case 0x035: /* VIS I fmul8x16al */
3787 CHECK_FPU_FEATURE(dc, VIS1);
3788 gen_op_load_fpr_DT0(DFPREG(rs1));
3789 gen_op_load_fpr_DT1(DFPREG(rs2));
3790 tcg_gen_helper_0_0(helper_fmul8x16al);
3791 gen_op_store_DT0_fpr(DFPREG(rd));
3792 break;
3793 case 0x036: /* VIS I fmul8sux16 */
3794 CHECK_FPU_FEATURE(dc, VIS1);
3795 gen_op_load_fpr_DT0(DFPREG(rs1));
3796 gen_op_load_fpr_DT1(DFPREG(rs2));
3797 tcg_gen_helper_0_0(helper_fmul8sux16);
3798 gen_op_store_DT0_fpr(DFPREG(rd));
3799 break;
3800 case 0x037: /* VIS I fmul8ulx16 */
3801 CHECK_FPU_FEATURE(dc, VIS1);
3802 gen_op_load_fpr_DT0(DFPREG(rs1));
3803 gen_op_load_fpr_DT1(DFPREG(rs2));
3804 tcg_gen_helper_0_0(helper_fmul8ulx16);
3805 gen_op_store_DT0_fpr(DFPREG(rd));
3806 break;
3807 case 0x038: /* VIS I fmuld8sux16 */
3808 CHECK_FPU_FEATURE(dc, VIS1);
3809 gen_op_load_fpr_DT0(DFPREG(rs1));
3810 gen_op_load_fpr_DT1(DFPREG(rs2));
3811 tcg_gen_helper_0_0(helper_fmuld8sux16);
3812 gen_op_store_DT0_fpr(DFPREG(rd));
3813 break;
3814 case 0x039: /* VIS I fmuld8ulx16 */
3815 CHECK_FPU_FEATURE(dc, VIS1);
3816 gen_op_load_fpr_DT0(DFPREG(rs1));
3817 gen_op_load_fpr_DT1(DFPREG(rs2));
3818 tcg_gen_helper_0_0(helper_fmuld8ulx16);
3819 gen_op_store_DT0_fpr(DFPREG(rd));
3820 break;
3821 case 0x03a: /* VIS I fpack32 */
3822 case 0x03b: /* VIS I fpack16 */
3823 case 0x03d: /* VIS I fpackfix */
3824 case 0x03e: /* VIS I pdist */
3825 // XXX
3826 goto illegal_insn;
3827 case 0x048: /* VIS I faligndata */
3828 CHECK_FPU_FEATURE(dc, VIS1);
3829 gen_op_load_fpr_DT0(DFPREG(rs1));
3830 gen_op_load_fpr_DT1(DFPREG(rs2));
3831 tcg_gen_helper_0_0(helper_faligndata);
3832 gen_op_store_DT0_fpr(DFPREG(rd));
3833 break;
3834 case 0x04b: /* VIS I fpmerge */
3835 CHECK_FPU_FEATURE(dc, VIS1);
3836 gen_op_load_fpr_DT0(DFPREG(rs1));
3837 gen_op_load_fpr_DT1(DFPREG(rs2));
3838 tcg_gen_helper_0_0(helper_fpmerge);
3839 gen_op_store_DT0_fpr(DFPREG(rd));
3840 break;
3841 case 0x04c: /* VIS II bshuffle */
3842 // XXX
3843 goto illegal_insn;
3844 case 0x04d: /* VIS I fexpand */
3845 CHECK_FPU_FEATURE(dc, VIS1);
3846 gen_op_load_fpr_DT0(DFPREG(rs1));
3847 gen_op_load_fpr_DT1(DFPREG(rs2));
3848 tcg_gen_helper_0_0(helper_fexpand);
3849 gen_op_store_DT0_fpr(DFPREG(rd));
3850 break;
3851 case 0x050: /* VIS I fpadd16 */
3852 CHECK_FPU_FEATURE(dc, VIS1);
3853 gen_op_load_fpr_DT0(DFPREG(rs1));
3854 gen_op_load_fpr_DT1(DFPREG(rs2));
3855 tcg_gen_helper_0_0(helper_fpadd16);
3856 gen_op_store_DT0_fpr(DFPREG(rd));
3857 break;
3858 case 0x051: /* VIS I fpadd16s */
3859 CHECK_FPU_FEATURE(dc, VIS1);
3860 tcg_gen_helper_1_2(helper_fpadd16s, cpu_fpr[rd],
3861 cpu_fpr[rs1], cpu_fpr[rs2]);
3862 break;
3863 case 0x052: /* VIS I fpadd32 */
3864 CHECK_FPU_FEATURE(dc, VIS1);
3865 gen_op_load_fpr_DT0(DFPREG(rs1));
3866 gen_op_load_fpr_DT1(DFPREG(rs2));
3867 tcg_gen_helper_0_0(helper_fpadd32);
3868 gen_op_store_DT0_fpr(DFPREG(rd));
3869 break;
3870 case 0x053: /* VIS I fpadd32s */
3871 CHECK_FPU_FEATURE(dc, VIS1);
3872 tcg_gen_helper_1_2(helper_fpadd32s, cpu_fpr[rd],
3873 cpu_fpr[rs1], cpu_fpr[rs2]);
3874 break;
3875 case 0x054: /* VIS I fpsub16 */
3876 CHECK_FPU_FEATURE(dc, VIS1);
3877 gen_op_load_fpr_DT0(DFPREG(rs1));
3878 gen_op_load_fpr_DT1(DFPREG(rs2));
3879 tcg_gen_helper_0_0(helper_fpsub16);
3880 gen_op_store_DT0_fpr(DFPREG(rd));
3881 break;
3882 case 0x055: /* VIS I fpsub16s */
3883 CHECK_FPU_FEATURE(dc, VIS1);
3884 tcg_gen_helper_1_2(helper_fpsub16s, cpu_fpr[rd],
3885 cpu_fpr[rs1], cpu_fpr[rs2]);
3886 break;
3887 case 0x056: /* VIS I fpsub32 */
3888 CHECK_FPU_FEATURE(dc, VIS1);
3889 gen_op_load_fpr_DT0(DFPREG(rs1));
3890 gen_op_load_fpr_DT1(DFPREG(rs2));
3891 tcg_gen_helper_0_0(helper_fpsub32);
3892 gen_op_store_DT0_fpr(DFPREG(rd));
3893 break;
3894 case 0x057: /* VIS I fpsub32s */
3895 CHECK_FPU_FEATURE(dc, VIS1);
3896 tcg_gen_helper_1_2(helper_fpsub32s, cpu_fpr[rd],
3897 cpu_fpr[rs1], cpu_fpr[rs2]);
3898 break;
3899 case 0x060: /* VIS I fzero */
3900 CHECK_FPU_FEATURE(dc, VIS1);
3901 tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
3902 tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0);
3903 break;
3904 case 0x061: /* VIS I fzeros */
3905 CHECK_FPU_FEATURE(dc, VIS1);
3906 tcg_gen_movi_i32(cpu_fpr[rd], 0);
3907 break;
3908 case 0x062: /* VIS I fnor */
3909 CHECK_FPU_FEATURE(dc, VIS1);
3910 tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
3911 cpu_fpr[DFPREG(rs2)]);
3912 tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);
3913 tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
3914 cpu_fpr[DFPREG(rs2) + 1]);
3915 tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1);
3916 break;
3917 case 0x063: /* VIS I fnors */
3918 CHECK_FPU_FEATURE(dc, VIS1);
3919 tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
3920 tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
3921 break;
3922 case 0x064: /* VIS I fandnot2 */
3923 CHECK_FPU_FEATURE(dc, VIS1);
3924 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);
3925 tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
3926 cpu_fpr[DFPREG(rs2)]);
3927 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1);
3928 tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
3929 cpu_fpr[DFPREG(rs2) + 1]);
3930 break;
3931 case 0x065: /* VIS I fandnot2s */
3932 CHECK_FPU_FEATURE(dc, VIS1);
3933 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);
3934 tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]);
3935 break;
3936 case 0x066: /* VIS I fnot2 */
3937 CHECK_FPU_FEATURE(dc, VIS1);
3938 tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
3939 -1);
3940 tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
3941 cpu_fpr[DFPREG(rs2) + 1], -1);
3942 break;
3943 case 0x067: /* VIS I fnot2s */
3944 CHECK_FPU_FEATURE(dc, VIS1);
3945 tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs2], -1);
3946 break;
3947 case 0x068: /* VIS I fandnot1 */
3948 CHECK_FPU_FEATURE(dc, VIS1);
3949 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
3950 tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
3951 cpu_fpr[DFPREG(rs1)]);
3952 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
3953 tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
3954 cpu_fpr[DFPREG(rs1) + 1]);
3955 break;
3956 case 0x069: /* VIS I fandnot1s */
3957 CHECK_FPU_FEATURE(dc, VIS1);
3958 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
3959 tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
3960 break;
3961 case 0x06a: /* VIS I fnot1 */
3962 CHECK_FPU_FEATURE(dc, VIS1);
3963 tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
3964 -1);
3965 tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1],
3966 cpu_fpr[DFPREG(rs1) + 1], -1);
3967 break;
3968 case 0x06b: /* VIS I fnot1s */
3969 CHECK_FPU_FEATURE(dc, VIS1);
3970 tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs1], -1);
3971 break;
3972 case 0x06c: /* VIS I fxor */
3973 CHECK_FPU_FEATURE(dc, VIS1);
3974 tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
3975 cpu_fpr[DFPREG(rs2)]);
3976 tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
3977 cpu_fpr[DFPREG(rs1) + 1],
3978 cpu_fpr[DFPREG(rs2) + 1]);
3979 break;
3980 case 0x06d: /* VIS I fxors */
3981 CHECK_FPU_FEATURE(dc, VIS1);
3982 tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
3983 break;
3984 case 0x06e: /* VIS I fnand */
3985 CHECK_FPU_FEATURE(dc, VIS1);
3986 tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
3987 cpu_fpr[DFPREG(rs2)]);
3988 tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1);
3989 tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
3990 cpu_fpr[DFPREG(rs2) + 1]);
3991 tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1);
3992 break;
3993 case 0x06f: /* VIS I fnands */
3994 CHECK_FPU_FEATURE(dc, VIS1);
3995 tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
3996 tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
3997 break;
3998 case 0x070: /* VIS I fand */
3999 CHECK_FPU_FEATURE(dc, VIS1);
4000 tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4001 cpu_fpr[DFPREG(rs2)]);
4002 tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
4003 cpu_fpr[DFPREG(rs1) + 1],
4004 cpu_fpr[DFPREG(rs2) + 1]);
4005 break;
4006 case 0x071: /* VIS I fands */
4007 CHECK_FPU_FEATURE(dc, VIS1);
4008 tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4009 break;
4010 case 0x072: /* VIS I fxnor */
4011 CHECK_FPU_FEATURE(dc, VIS1);
4012 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
4013 tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
4014 cpu_fpr[DFPREG(rs1)]);
4015 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);
4016 tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
4017 cpu_fpr[DFPREG(rs1) + 1]);
4018 break;
4019 case 0x073: /* VIS I fxnors */
4020 CHECK_FPU_FEATURE(dc, VIS1);
4021 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
4022 tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
4023 break;
4024 case 0x074: /* VIS I fsrc1 */
4025 CHECK_FPU_FEATURE(dc, VIS1);
4026 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
4027 tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
4028 cpu_fpr[DFPREG(rs1) + 1]);
4029 break;
4030 case 0x075: /* VIS I fsrc1s */
4031 CHECK_FPU_FEATURE(dc, VIS1);
4032 tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]);
4033 break;
4034 case 0x076: /* VIS I fornot2 */
4035 CHECK_FPU_FEATURE(dc, VIS1);
4036 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1);
4037 tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
4038 cpu_fpr[DFPREG(rs2)]);
4039 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1);
4040 tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
4041 cpu_fpr[DFPREG(rs2) + 1]);
4042 break;
4043 case 0x077: /* VIS I fornot2s */
4044 CHECK_FPU_FEATURE(dc, VIS1);
4045 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);
4046 tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]);
4047 break;
4048 case 0x078: /* VIS I fsrc2 */
4049 CHECK_FPU_FEATURE(dc, VIS1);
4050 gen_op_load_fpr_DT0(DFPREG(rs2));
4051 gen_op_store_DT0_fpr(DFPREG(rd));
4052 break;
4053 case 0x079: /* VIS I fsrc2s */
4054 CHECK_FPU_FEATURE(dc, VIS1);
4055 tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
4056 break;
4057 case 0x07a: /* VIS I fornot1 */
4058 CHECK_FPU_FEATURE(dc, VIS1);
4059 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
4060 tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
4061 cpu_fpr[DFPREG(rs1)]);
4062 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);
4063 tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
4064 cpu_fpr[DFPREG(rs1) + 1]);
4065 break;
4066 case 0x07b: /* VIS I fornot1s */
4067 CHECK_FPU_FEATURE(dc, VIS1);
4068 tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
4069 tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
4070 break;
4071 case 0x07c: /* VIS I for */
4072 CHECK_FPU_FEATURE(dc, VIS1);
4073 tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4074 cpu_fpr[DFPREG(rs2)]);
4075 tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
4076 cpu_fpr[DFPREG(rs1) + 1],
4077 cpu_fpr[DFPREG(rs2) + 1]);
4078 break;
4079 case 0x07d: /* VIS I fors */
4080 CHECK_FPU_FEATURE(dc, VIS1);
4081 tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4082 break;
4083 case 0x07e: /* VIS I fone */
4084 CHECK_FPU_FEATURE(dc, VIS1);
4085 tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
4086 tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1);
4087 break;
4088 case 0x07f: /* VIS I fones */
4089 CHECK_FPU_FEATURE(dc, VIS1);
4090 tcg_gen_movi_i32(cpu_fpr[rd], -1);
4091 break;
4092 case 0x080: /* VIS I shutdown */
4093 case 0x081: /* VIS II siam */
4094 // XXX
4095 goto illegal_insn;
4096 default:
4097 goto illegal_insn;
4098 }
4099 #else
4100 goto ncp_insn;
4101 #endif
4102 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4103 #ifdef TARGET_SPARC64
4104 goto illegal_insn;
4105 #else
4106 goto ncp_insn;
4107 #endif
4108 #ifdef TARGET_SPARC64
4109 } else if (xop == 0x39) { /* V9 return */
4110 TCGv r_const;
4111
4112 save_state(dc, cpu_cond);
4113 cpu_src1 = get_src1(insn, cpu_src1);
4114 if (IS_IMM) { /* immediate */
4115 rs2 = GET_FIELDs(insn, 19, 31);
4116 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4117 } else { /* register */
4118 rs2 = GET_FIELD(insn, 27, 31);
4119 if (rs2) {
4120 gen_movl_reg_TN(rs2, cpu_src2);
4121 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4122 } else
4123 tcg_gen_mov_tl(cpu_dst, cpu_src1);
4124 }
4125 tcg_gen_helper_0_0(helper_restore);
4126 gen_mov_pc_npc(dc, cpu_cond);
4127 r_const = tcg_const_i32(3);
4128 tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4129 tcg_temp_free(r_const);
4130 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4131 dc->npc = DYNAMIC_PC;
4132 goto jmp_insn;
4133 #endif
4134 } else {
4135 cpu_src1 = get_src1(insn, cpu_src1);
4136 if (IS_IMM) { /* immediate */
4137 rs2 = GET_FIELDs(insn, 19, 31);
4138 tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4139 } else { /* register */
4140 rs2 = GET_FIELD(insn, 27, 31);
4141 if (rs2) {
4142 gen_movl_reg_TN(rs2, cpu_src2);
4143 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4144 } else
4145 tcg_gen_mov_tl(cpu_dst, cpu_src1);
4146 }
4147 switch (xop) {
4148 case 0x38: /* jmpl */
4149 {
4150 TCGv r_const;
4151
4152 r_const = tcg_const_tl(dc->pc);
4153 gen_movl_TN_reg(rd, r_const);
4154 tcg_temp_free(r_const);
4155 gen_mov_pc_npc(dc, cpu_cond);
4156 r_const = tcg_const_i32(3);
4157 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4158 r_const);
4159 tcg_temp_free(r_const);
4160 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4161 dc->npc = DYNAMIC_PC;
4162 }
4163 goto jmp_insn;
4164 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4165 case 0x39: /* rett, V9 return */
4166 {
4167 TCGv r_const;
4168
4169 if (!supervisor(dc))
4170 goto priv_insn;
4171 gen_mov_pc_npc(dc, cpu_cond);
4172 r_const = tcg_const_i32(3);
4173 tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4174 r_const);
4175 tcg_temp_free(r_const);
4176 tcg_gen_mov_tl(cpu_npc, cpu_dst);
4177 dc->npc = DYNAMIC_PC;
4178 tcg_gen_helper_0_0(helper_rett);
4179 }
4180 goto jmp_insn;
4181 #endif
4182 case 0x3b: /* flush */
4183 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4184 goto unimp_flush;
4185 tcg_gen_helper_0_1(helper_flush, cpu_dst);
4186 break;
4187 case 0x3c: /* save */
4188 save_state(dc, cpu_cond);
4189 tcg_gen_helper_0_0(helper_save);
4190 gen_movl_TN_reg(rd, cpu_dst);
4191 break;
4192 case 0x3d: /* restore */
4193 save_state(dc, cpu_cond);
4194 tcg_gen_helper_0_0(helper_restore);
4195 gen_movl_TN_reg(rd, cpu_dst);
4196 break;
4197 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4198 case 0x3e: /* V9 done/retry */
4199 {
4200 switch (rd) {
4201 case 0:
4202 if (!supervisor(dc))
4203 goto priv_insn;
4204 dc->npc = DYNAMIC_PC;
4205 dc->pc = DYNAMIC_PC;
4206 tcg_gen_helper_0_0(helper_done);
4207 goto jmp_insn;
4208 case 1:
4209 if (!supervisor(dc))
4210 goto priv_insn;
4211 dc->npc = DYNAMIC_PC;
4212 dc->pc = DYNAMIC_PC;
4213 tcg_gen_helper_0_0(helper_retry);
4214 goto jmp_insn;
4215 default:
4216 goto illegal_insn;
4217 }
4218 }
4219 break;
4220 #endif
4221 default:
4222 goto illegal_insn;
4223 }
4224 }
4225 break;
4226 }
4227 break;
4228 case 3: /* load/store instructions */
4229 {
4230 unsigned int xop = GET_FIELD(insn, 7, 12);
4231
4232 cpu_src1 = get_src1(insn, cpu_src1);
4233 if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
4234 rs2 = GET_FIELD(insn, 27, 31);
4235 gen_movl_reg_TN(rs2, cpu_src2);
4236 tcg_gen_mov_tl(cpu_addr, cpu_src1);
4237 } else if (IS_IMM) { /* immediate */
4238 rs2 = GET_FIELDs(insn, 19, 31);
4239 tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4240 } else { /* register */
4241 rs2 = GET_FIELD(insn, 27, 31);
4242 if (rs2 != 0) {
4243 gen_movl_reg_TN(rs2, cpu_src2);
4244 tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4245 } else
4246 tcg_gen_mov_tl(cpu_addr, cpu_src1);
4247 }
4248 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4249 (xop > 0x17 && xop <= 0x1d ) ||
4250 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4251 switch (xop) {
4252 case 0x0: /* load unsigned word */
4253 gen_address_mask(dc, cpu_addr);
4254 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4255 break;
4256 case 0x1: /* load unsigned byte */
4257 gen_address_mask(dc, cpu_addr);
4258 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4259 break;
4260 case 0x2: /* load unsigned halfword */
4261 gen_address_mask(dc, cpu_addr);
4262 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4263 break;
4264 case 0x3: /* load double word */
4265 if (rd & 1)
4266 goto illegal_insn;
4267 else {
4268 TCGv r_const;
4269
4270 save_state(dc, cpu_cond);
4271 r_const = tcg_const_i32(7);
4272 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4273 r_const); // XXX remove
4274 tcg_temp_free(r_const);
4275 gen_address_mask(dc, cpu_addr);
4276 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4277 tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4278 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4279 gen_movl_TN_reg(rd + 1, cpu_tmp0);
4280 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4281 tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4282 tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4283 }
4284 break;
4285 case 0x9: /* load signed byte */
4286 gen_address_mask(dc, cpu_addr);
4287 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4288 break;
4289 case 0xa: /* load signed halfword */
4290 gen_address_mask(dc, cpu_addr);
4291 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4292 break;
4293 case 0xd: /* ldstub -- XXX: should be atomically */
4294 {
4295 TCGv r_const;
4296
4297 gen_address_mask(dc, cpu_addr);
4298 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4299 r_const = tcg_const_tl(0xff);
4300 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4301 tcg_temp_free(r_const);
4302 }
4303 break;
4304 case 0x0f: /* swap register with memory. Also
4305 atomically */
4306 CHECK_IU_FEATURE(dc, SWAP);
4307 gen_movl_reg_TN(rd, cpu_val);
4308 gen_address_mask(dc, cpu_addr);
4309 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4310 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4311 tcg_gen_mov_tl(cpu_val, cpu_tmp0);
4312 break;
4313 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4314 case 0x10: /* load word alternate */
4315 #ifndef TARGET_SPARC64
4316 if (IS_IMM)
4317 goto illegal_insn;
4318 if (!supervisor(dc))
4319 goto priv_insn;
4320 #endif
4321 save_state(dc, cpu_cond);
4322 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4323 break;
4324 case 0x11: /* load unsigned byte alternate */
4325 #ifndef TARGET_SPARC64
4326 if (IS_IMM)
4327 goto illegal_insn;
4328 if (!supervisor(dc))
4329 goto priv_insn;
4330 #endif
4331 save_state(dc, cpu_cond);
4332 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4333 break;
4334 case 0x12: /* load unsigned halfword alternate */
4335 #ifndef TARGET_SPARC64
4336 if (IS_IMM)
4337 goto illegal_insn;
4338 if (!supervisor(dc))
4339 goto priv_insn;
4340 #endif
4341 save_state(dc, cpu_cond);
4342 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4343 break;
4344 case 0x13: /* load double word alternate */
4345 #ifndef TARGET_SPARC64
4346 if (IS_IMM)
4347 goto illegal_insn;
4348 if (!supervisor(dc))
4349 goto priv_insn;
4350 #endif
4351 if (rd & 1)
4352 goto illegal_insn;
4353 save_state(dc, cpu_cond);
4354 gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4355 goto skip_move;
4356 case 0x19: /* load signed byte alternate */
4357 #ifndef TARGET_SPARC64
4358 if (IS_IMM)
4359 goto illegal_insn;
4360 if (!supervisor(dc))
4361 goto priv_insn;
4362 #endif
4363 save_state(dc, cpu_cond);
4364 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4365 break;
4366 case 0x1a: /* load signed halfword alternate */
4367 #ifndef TARGET_SPARC64
4368 if (IS_IMM)
4369 goto illegal_insn;
4370 if (!supervisor(dc))
4371 goto priv_insn;
4372 #endif
4373 save_state(dc, cpu_cond);
4374 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4375 break;
4376 case 0x1d: /* ldstuba -- XXX: should be atomically */
4377 #ifndef TARGET_SPARC64
4378 if (IS_IMM)
4379 goto illegal_insn;
4380 if (!supervisor(dc))
4381 goto priv_insn;
4382 #endif
4383 save_state(dc, cpu_cond);
4384 gen_ldstub_asi(cpu_val, cpu_addr, insn);
4385 break;
4386 case 0x1f: /* swap reg with alt. memory. Also
4387 atomically */
4388 CHECK_IU_FEATURE(dc, SWAP);
4389 #ifndef TARGET_SPARC64
4390 if (IS_IMM)
4391 goto illegal_insn;
4392 if (!supervisor(dc))
4393 goto priv_insn;
4394 #endif
4395 save_state(dc, cpu_cond);
4396 gen_movl_reg_TN(rd, cpu_val);
4397 gen_swap_asi(cpu_val, cpu_addr, insn);
4398 break;
4399
4400 #ifndef TARGET_SPARC64
4401 case 0x30: /* ldc */
4402 case 0x31: /* ldcsr */
4403 case 0x33: /* lddc */
4404 goto ncp_insn;
4405 #endif
4406 #endif
4407 #ifdef TARGET_SPARC64
4408 case 0x08: /* V9 ldsw */
4409 gen_address_mask(dc, cpu_addr);
4410 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4411 break;
4412 case 0x0b: /* V9 ldx */
4413 gen_address_mask(dc, cpu_addr);
4414 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4415 break;
4416 case 0x18: /* V9 ldswa */
4417 save_state(dc, cpu_cond);
4418 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4419 break;
4420 case 0x1b: /* V9 ldxa */
4421 save_state(dc, cpu_cond);
4422 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4423 break;
4424 case 0x2d: /* V9 prefetch, no effect */
4425 goto skip_move;
4426 case 0x30: /* V9 ldfa */
4427 save_state(dc, cpu_cond);
4428 gen_ldf_asi(cpu_addr, insn, 4, rd);
4429 goto skip_move;
4430 case 0x33: /* V9 lddfa */
4431 save_state(dc, cpu_cond);
4432 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4433 goto skip_move;
4434 case 0x3d: /* V9 prefetcha, no effect */
4435 goto skip_move;
4436 case 0x32: /* V9 ldqfa */
4437 CHECK_FPU_FEATURE(dc, FLOAT128);
4438 save_state(dc, cpu_cond);
4439 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4440 goto skip_move;
4441 #endif
4442 default:
4443 goto illegal_insn;
4444 }
4445 gen_movl_TN_reg(rd, cpu_val);
4446 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4447 skip_move: ;
4448 #endif
4449 } else if (xop >= 0x20 && xop < 0x24) {
4450 if (gen_trap_ifnofpu(dc, cpu_cond))
4451 goto jmp_insn;
4452 save_state(dc, cpu_cond);
4453 switch (xop) {
4454 case 0x20: /* load fpreg */
4455 gen_address_mask(dc, cpu_addr);
4456 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4457 tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
4458 break;
4459 case 0x21: /* ldfsr, V9 ldxfsr */
4460 #ifdef TARGET_SPARC64
4461 gen_address_mask(dc, cpu_addr);
4462 if (rd == 1) {
4463 tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4464 tcg_gen_helper_0_1(helper_ldxfsr, cpu_tmp64);
4465 } else
4466 #else
4467 {
4468 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4469 tcg_gen_helper_0_1(helper_ldfsr, cpu_tmp32);
4470 }
4471 #endif
4472 break;
4473 case 0x22: /* load quad fpreg */
4474 {
4475 TCGv r_const;
4476
4477 CHECK_FPU_FEATURE(dc, FLOAT128);
4478 r_const = tcg_const_i32(dc->mem_idx);
4479 tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4480 tcg_temp_free(r_const);
4481 gen_op_store_QT0_fpr(QFPREG(rd));
4482 }
4483 break;
4484 case 0x23: /* load double fpreg */
4485 {
4486 TCGv r_const;
4487
4488 r_const = tcg_const_i32(dc->mem_idx);
4489 tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4490 tcg_temp_free(r_const);
4491 gen_op_store_DT0_fpr(DFPREG(rd));
4492 }
4493 break;
4494 default:
4495 goto illegal_insn;
4496 }
4497 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4498 xop == 0xe || xop == 0x1e) {
4499 gen_movl_reg_TN(rd, cpu_val);
4500 switch (xop) {
4501 case 0x4: /* store word */
4502 gen_address_mask(dc, cpu_addr);
4503 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4504 break;
4505 case 0x5: /* store byte */
4506 gen_address_mask(dc, cpu_addr);
4507 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4508 break;
4509 case 0x6: /* store halfword */
4510 gen_address_mask(dc, cpu_addr);
4511 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4512 break;
4513 case 0x7: /* store double word */
4514 if (rd & 1)
4515 goto illegal_insn;
4516 else {
4517 TCGv r_const;
4518
4519 save_state(dc, cpu_cond);
4520 gen_address_mask(dc, cpu_addr);
4521 r_const = tcg_const_i32(7);
4522 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4523 r_const); // XXX remove
4524 tcg_temp_free(r_const);
4525 gen_movl_reg_TN(rd + 1, cpu_tmp0);
4526 tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val);
4527 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4528 }
4529 break;
4530 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4531 case 0x14: /* store word alternate */
4532 #ifndef TARGET_SPARC64
4533 if (IS_IMM)
4534 goto illegal_insn;
4535 if (!supervisor(dc))
4536 goto priv_insn;
4537 #endif
4538 save_state(dc, cpu_cond);
4539 gen_st_asi(cpu_val, cpu_addr, insn, 4);
4540 break;
4541 case 0x15: /* store byte alternate */
4542 #ifndef TARGET_SPARC64
4543 if (IS_IMM)
4544 goto illegal_insn;
4545 if (!supervisor(dc))
4546 goto priv_insn;
4547 #endif
4548 save_state(dc, cpu_cond);
4549 gen_st_asi(cpu_val, cpu_addr, insn, 1);
4550 break;
4551 case 0x16: /* store halfword alternate */
4552 #ifndef TARGET_SPARC64
4553 if (IS_IMM)
4554 goto illegal_insn;
4555 if (!supervisor(dc))
4556 goto priv_insn;
4557 #endif
4558 save_state(dc, cpu_cond);
4559 gen_st_asi(cpu_val, cpu_addr, insn, 2);
4560 break;
4561 case 0x17: /* store double word alternate */
4562 #ifndef TARGET_SPARC64
4563 if (IS_IMM)
4564 goto illegal_insn;
4565 if (!supervisor(dc))
4566 goto priv_insn;
4567 #endif
4568 if (rd & 1)
4569 goto illegal_insn;
4570 else {
4571 save_state(dc, cpu_cond);
4572 gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4573 }
4574 break;
4575 #endif
4576 #ifdef TARGET_SPARC64
4577 case 0x0e: /* V9 stx */
4578 gen_address_mask(dc, cpu_addr);
4579 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4580 break;
4581 case 0x1e: /* V9 stxa */
4582 save_state(dc, cpu_cond);
4583 gen_st_asi(cpu_val, cpu_addr, insn, 8);
4584 break;
4585 #endif
4586 default:
4587 goto illegal_insn;
4588 }
4589 } else if (xop > 0x23 && xop < 0x28) {
4590 if (gen_trap_ifnofpu(dc, cpu_cond))
4591 goto jmp_insn;
4592 save_state(dc, cpu_cond);
4593 switch (xop) {
4594 case 0x24: /* store fpreg */
4595 gen_address_mask(dc, cpu_addr);
4596 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
4597 tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
4598 break;
4599 case 0x25: /* stfsr, V9 stxfsr */
4600 #ifdef TARGET_SPARC64
4601 gen_address_mask(dc, cpu_addr);
4602 tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
4603 if (rd == 1)
4604 tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4605 else
4606 tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx);
4607 #else
4608 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
4609 tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4610 #endif
4611 break;
4612 case 0x26:
4613 #ifdef TARGET_SPARC64
4614 /* V9 stqf, store quad fpreg */
4615 {
4616 TCGv r_const;
4617
4618 CHECK_FPU_FEATURE(dc, FLOAT128);
4619 gen_op_load_fpr_QT0(QFPREG(rd));
4620 r_const = tcg_const_i32(dc->mem_idx);
4621 tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4622 tcg_temp_free(r_const);
4623 }
4624 break;
4625 #else /* !TARGET_SPARC64 */
4626 /* stdfq, store floating point queue */
4627 #if defined(CONFIG_USER_ONLY)
4628 goto illegal_insn;
4629 #else
4630 if (!supervisor(dc))
4631 goto priv_insn;
4632 if (gen_trap_ifnofpu(dc, cpu_cond))
4633 goto jmp_insn;
4634 goto nfq_insn;
4635 #endif
4636 #endif
4637 case 0x27: /* store double fpreg */
4638 {
4639 TCGv r_const;
4640
4641 gen_op_load_fpr_DT0(DFPREG(rd));
4642 r_const = tcg_const_i32(dc->mem_idx);
4643 tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4644 tcg_temp_free(r_const);
4645 }
4646 break;
4647 default:
4648 goto illegal_insn;
4649 }
4650 } else if (xop > 0x33 && xop < 0x3f) {
4651 save_state(dc, cpu_cond);
4652 switch (xop) {
4653 #ifdef TARGET_SPARC64
4654 case 0x34: /* V9 stfa */
4655 gen_stf_asi(cpu_addr, insn, 4, rd);
4656 break;
4657 case 0x36: /* V9 stqfa */
4658 {
4659 TCGv r_const;
4660
4661 CHECK_FPU_FEATURE(dc, FLOAT128);
4662 r_const = tcg_const_i32(7);
4663 tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4664 r_const);
4665 tcg_temp_free(r_const);
4666 gen_op_load_fpr_QT0(QFPREG(rd));
4667 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4668 }
4669 break;
4670 case 0x37: /* V9 stdfa */
4671 gen_op_load_fpr_DT0(DFPREG(rd));
4672 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4673 break;
4674 case 0x3c: /* V9 casa */
4675 gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4676 gen_movl_TN_reg(rd, cpu_val);
4677 break;
4678 case 0x3e: /* V9 casxa */
4679 gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4680 gen_movl_TN_reg(rd, cpu_val);
4681 break;
4682 #else
4683 case 0x34: /* stc */
4684 case 0x35: /* stcsr */
4685 case 0x36: /* stdcq */
4686 case 0x37: /* stdc */
4687 goto ncp_insn;
4688 #endif
4689 default:
4690 goto illegal_insn;
4691 }
4692 }
4693 else
4694 goto illegal_insn;
4695 }
4696 break;
4697 }
4698 /* default case for non jump instructions */
4699 if (dc->npc == DYNAMIC_PC) {
4700 dc->pc = DYNAMIC_PC;
4701 gen_op_next_insn();
4702 } else if (dc->npc == JUMP_PC) {
4703 /* we can do a static jump */
4704 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4705 dc->is_br = 1;
4706 } else {
4707 dc->pc = dc->npc;
4708 dc->npc = dc->npc + 4;
4709 }
4710 jmp_insn:
4711 return;
4712 illegal_insn:
4713 {
4714 TCGv r_const;
4715
4716 save_state(dc, cpu_cond);
4717 r_const = tcg_const_i32(TT_ILL_INSN);
4718 tcg_gen_helper_0_1(raise_exception, r_const);
4719 tcg_temp_free(r_const);
4720 dc->is_br = 1;
4721 }
4722 return;
4723 unimp_flush:
4724 {
4725 TCGv r_const;
4726
4727 save_state(dc, cpu_cond);
4728 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4729 tcg_gen_helper_0_1(raise_exception, r_const);
4730 tcg_temp_free(r_const);
4731 dc->is_br = 1;
4732 }
4733 return;
4734 #if !defined(CONFIG_USER_ONLY)
4735 priv_insn:
4736 {
4737 TCGv r_const;
4738
4739 save_state(dc, cpu_cond);
4740 r_const = tcg_const_i32(TT_PRIV_INSN);
4741 tcg_gen_helper_0_1(raise_exception, r_const);
4742 tcg_temp_free(r_const);
4743 dc->is_br = 1;
4744 }
4745 return;
4746 #endif
4747 nfpu_insn:
4748 save_state(dc, cpu_cond);
4749 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4750 dc->is_br = 1;
4751 return;
4752 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4753 nfq_insn:
4754 save_state(dc, cpu_cond);
4755 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4756 dc->is_br = 1;
4757 return;
4758 #endif
4759 #ifndef TARGET_SPARC64
4760 ncp_insn:
4761 {
4762 TCGv r_const;
4763
4764 save_state(dc, cpu_cond);
4765 r_const = tcg_const_i32(TT_NCP_INSN);
4766 tcg_gen_helper_0_1(raise_exception, r_const);
4767 tcg_temp_free(r_const);
4768 dc->is_br = 1;
4769 }
4770 return;
4771 #endif
4772 }
4773
4774 static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4775 int spc, CPUSPARCState *env)
4776 {
4777 target_ulong pc_start, last_pc;
4778 uint16_t *gen_opc_end;
4779 DisasContext dc1, *dc = &dc1;
4780 int j, lj = -1;
4781 int num_insns;
4782 int max_insns;
4783
4784 memset(dc, 0, sizeof(DisasContext));
4785 dc->tb = tb;
4786 pc_start = tb->pc;
4787 dc->pc = pc_start;
4788 last_pc = dc->pc;
4789 dc->npc = (target_ulong) tb->cs_base;
4790 dc->mem_idx = cpu_mmu_index(env);
4791 dc->def = env->def;
4792 if ((dc->def->features & CPU_FEATURE_FLOAT))
4793 dc->fpu_enabled = cpu_fpu_enabled(env);
4794 else
4795 dc->fpu_enabled = 0;
4796 #ifdef TARGET_SPARC64
4797 dc->address_mask_32bit = env->pstate & PS_AM;
4798 #endif
4799 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4800
4801 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4802 cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4803 cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4804
4805 cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4806
4807 // loads and stores
4808 cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4809 cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4810
4811 num_insns = 0;
4812 max_insns = tb->cflags & CF_COUNT_MASK;
4813 if (max_insns == 0)
4814 max_insns = CF_COUNT_MASK;
4815 gen_icount_start();
4816 do {
4817 if (env->nb_breakpoints > 0) {
4818 for(j = 0; j < env->nb_breakpoints; j++) {
4819 if (env->breakpoints[j] == dc->pc) {
4820 if (dc->pc != pc_start)
4821 save_state(dc, cpu_cond);
4822 tcg_gen_helper_0_0(helper_debug);
4823 tcg_gen_exit_tb(0);
4824 dc->is_br = 1;
4825 goto exit_gen_loop;
4826 }
4827 }
4828 }
4829 if (spc) {
4830 if (loglevel > 0)
4831 fprintf(logfile, "Search PC...\n");
4832 j = gen_opc_ptr - gen_opc_buf;
4833 if (lj < j) {
4834 lj++;
4835 while (lj < j)
4836 gen_opc_instr_start[lj++] = 0;
4837 gen_opc_pc[lj] = dc->pc;
4838 gen_opc_npc[lj] = dc->npc;
4839 gen_opc_instr_start[lj] = 1;
4840 gen_opc_icount[lj] = num_insns;
4841 }
4842 }
4843 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4844 gen_io_start();
4845 last_pc = dc->pc;
4846 disas_sparc_insn(dc);
4847 num_insns++;
4848
4849 if (dc->is_br)
4850 break;
4851 /* if the next PC is different, we abort now */
4852 if (dc->pc != (last_pc + 4))
4853 break;
4854 /* if we reach a page boundary, we stop generation so that the
4855 PC of a TT_TFAULT exception is always in the right page */
4856 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4857 break;
4858 /* if single step mode, we generate only one instruction and
4859 generate an exception */
4860 if (env->singlestep_enabled) {
4861 tcg_gen_movi_tl(cpu_pc, dc->pc);
4862 tcg_gen_exit_tb(0);
4863 break;
4864 }
4865 } while ((gen_opc_ptr < gen_opc_end) &&
4866 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4867 num_insns < max_insns);
4868
4869 exit_gen_loop:
4870 tcg_temp_free(cpu_addr);
4871 tcg_temp_free(cpu_val);
4872 tcg_temp_free(cpu_dst);
4873 tcg_temp_free(cpu_tmp64);
4874 tcg_temp_free(cpu_tmp32);
4875 tcg_temp_free(cpu_tmp0);
4876 if (tb->cflags & CF_LAST_IO)
4877 gen_io_end();
4878 if (!dc->is_br) {
4879 if (dc->pc != DYNAMIC_PC &&
4880 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4881 /* static PC and NPC: we can use direct chaining */
4882 gen_goto_tb(dc, 0, dc->pc, dc->npc);
4883 } else {
4884 if (dc->pc != DYNAMIC_PC)
4885 tcg_gen_movi_tl(cpu_pc, dc->pc);
4886 save_npc(dc, cpu_cond);
4887 tcg_gen_exit_tb(0);
4888 }
4889 }
4890 gen_icount_end(tb, num_insns);
4891 *gen_opc_ptr = INDEX_op_end;
4892 if (spc) {
4893 j = gen_opc_ptr - gen_opc_buf;
4894 lj++;
4895 while (lj <= j)
4896 gen_opc_instr_start[lj++] = 0;
4897 #if 0
4898 if (loglevel > 0) {
4899 page_dump(logfile);
4900 }
4901 #endif
4902 gen_opc_jump_pc[0] = dc->jump_pc[0];
4903 gen_opc_jump_pc[1] = dc->jump_pc[1];
4904 } else {
4905 tb->size = last_pc + 4 - pc_start;
4906 tb->icount = num_insns;
4907 }
4908 #ifdef DEBUG_DISAS
4909 if (loglevel & CPU_LOG_TB_IN_ASM) {
4910 fprintf(logfile, "--------------\n");
4911 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4912 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4913 fprintf(logfile, "\n");
4914 }
4915 #endif
4916 }
4917
4918 void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4919 {
4920 gen_intermediate_code_internal(tb, 0, env);
4921 }
4922
4923 void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4924 {
4925 gen_intermediate_code_internal(tb, 1, env);
4926 }
4927
4928 void gen_intermediate_code_init(CPUSPARCState *env)
4929 {
4930 unsigned int i;
4931 static int inited;
4932 static const char * const gregnames[8] = {
4933 NULL, // g0 not used
4934 "g1",
4935 "g2",
4936 "g3",
4937 "g4",
4938 "g5",
4939 "g6",
4940 "g7",
4941 };
4942 static const char * const fregnames[64] = {
4943 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
4944 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
4945 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
4946 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
4947 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
4948 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
4949 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
4950 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
4951 };
4952
4953 /* init various static tables */
4954 if (!inited) {
4955 inited = 1;
4956
4957 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4958 cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4959 offsetof(CPUState, regwptr),
4960 "regwptr");
4961 #ifdef TARGET_SPARC64
4962 cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4963 TCG_AREG0, offsetof(CPUState, xcc),
4964 "xcc");
4965 cpu_asi = tcg_global_mem_new(TCG_TYPE_I32,
4966 TCG_AREG0, offsetof(CPUState, asi),
4967 "asi");
4968 cpu_fprs = tcg_global_mem_new(TCG_TYPE_I32,
4969 TCG_AREG0, offsetof(CPUState, fprs),
4970 "fprs");
4971 cpu_gsr = tcg_global_mem_new(TCG_TYPE_TL,
4972 TCG_AREG0, offsetof(CPUState, gsr),
4973 "gsr");
4974 cpu_tick_cmpr = tcg_global_mem_new(TCG_TYPE_TL,
4975 TCG_AREG0,
4976 offsetof(CPUState, tick_cmpr),
4977 "tick_cmpr");
4978 cpu_stick_cmpr = tcg_global_mem_new(TCG_TYPE_TL,
4979 TCG_AREG0,
4980 offsetof(CPUState, stick_cmpr),
4981 "stick_cmpr");
4982 cpu_hstick_cmpr = tcg_global_mem_new(TCG_TYPE_TL,
4983 TCG_AREG0,
4984 offsetof(CPUState, hstick_cmpr),
4985 "hstick_cmpr");
4986 cpu_hintp = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4987 offsetof(CPUState, hintp),
4988 "hintp");
4989 cpu_htba = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4990 offsetof(CPUState, htba),
4991 "htba");
4992 cpu_hver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4993 offsetof(CPUState, hver),
4994 "hver");
4995 cpu_ssr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4996 offsetof(CPUState, ssr), "ssr");
4997 cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4998 offsetof(CPUState, version), "ver");
4999 cpu_softint = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
5000 offsetof(CPUState, softint),
5001 "softint");
5002 #else
5003 cpu_wim = tcg_global_mem_new(TCG_TYPE_I32,
5004 TCG_AREG0, offsetof(CPUState, wim),
5005 "wim");
5006 #endif
5007 cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
5008 TCG_AREG0, offsetof(CPUState, cond),
5009 "cond");
5010 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
5011 TCG_AREG0, offsetof(CPUState, cc_src),
5012 "cc_src");
5013 cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
5014 offsetof(CPUState, cc_src2),
5015 "cc_src2");
5016 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
5017 TCG_AREG0, offsetof(CPUState, cc_dst),
5018 "cc_dst");
5019 cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
5020 TCG_AREG0, offsetof(CPUState, psr),
5021 "psr");
5022 cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
5023 TCG_AREG0, offsetof(CPUState, fsr),
5024 "fsr");
5025 cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
5026 TCG_AREG0, offsetof(CPUState, pc),
5027 "pc");
5028 cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
5029 TCG_AREG0, offsetof(CPUState, npc),
5030 "npc");
5031 cpu_y = tcg_global_mem_new(TCG_TYPE_TL,
5032 TCG_AREG0, offsetof(CPUState, y), "y");
5033 #ifndef CONFIG_USER_ONLY
5034 cpu_tbr = tcg_global_mem_new(TCG_TYPE_TL,
5035 TCG_AREG0, offsetof(CPUState, tbr),
5036 "tbr");
5037 #endif
5038 for (i = 1; i < 8; i++)
5039 cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
5040 offsetof(CPUState, gregs[i]),
5041 gregnames[i]);
5042 for (i = 0; i < TARGET_FPREGS; i++)
5043 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
5044 offsetof(CPUState, fpr[i]),
5045 fregnames[i]);
5046
5047 /* register helpers */
5048
5049 #undef DEF_HELPER
5050 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
5051 #include "helper.h"
5052 }
5053 }
5054
5055 void gen_pc_load(CPUState *env, TranslationBlock *tb,
5056 unsigned long searched_pc, int pc_pos, void *puc)
5057 {
5058 target_ulong npc;
5059 env->pc = gen_opc_pc[pc_pos];
5060 npc = gen_opc_npc[pc_pos];
5061 if (npc == 1) {
5062 /* dynamic NPC: already stored */
5063 } else if (npc == 2) {
5064 target_ulong t2 = (target_ulong)(unsigned long)puc;
5065 /* jump PC: use T2 and the jump targets of the translation */
5066 if (t2)
5067 env->npc = gen_opc_jump_pc[0];
5068 else
5069 env->npc = gen_opc_jump_pc[1];
5070 } else {
5071 env->npc = npc;
5072 }
5073 }
Samsung s3c2440 and arm920t support for the mini2440 dev board