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Fix interrupt exclusion via SSTEP_NOIRQ
[qemu/mini2440.git] / target-ppc / translate.c
blob03e553a34843f88e2c1e530e8c96429471619be7
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "disas.h"
29 #include "helper.h"
30 #include "tcg-op.h"
31 #include "qemu-common.h"
32
33 #define CPU_SINGLE_STEP 0x1
34 #define CPU_BRANCH_STEP 0x2
35 #define GDBSTUB_SINGLE_STEP 0x4
36
37 /* Include definitions for instructions classes and implementations flags */
38 //#define DO_SINGLE_STEP
39 //#define PPC_DEBUG_DISAS
40 //#define DO_PPC_STATISTICS
41 //#define OPTIMIZE_FPRF_UPDATE
42
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv cpu_fpr[32];
60 static TCGv cpu_avrh[32], cpu_avrl[32];
61 static TCGv cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_ctr;
64 static TCGv cpu_lr;
65 static TCGv cpu_xer;
66 static TCGv cpu_fpscr;
67
68 /* dyngen register indexes */
69 static TCGv cpu_T[3];
70 #if defined(TARGET_PPC64)
71 #define cpu_T64 cpu_T
72 #else
73 static TCGv cpu_T64[3];
74 #endif
75 static TCGv cpu_FT[3];
76 static TCGv cpu_AVRh[3], cpu_AVRl[3];
77
78 #include "gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 static int done_init = 0;
85
86 if (done_init)
87 return;
88
89 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
90 #if TARGET_LONG_BITS > HOST_LONG_BITS
91 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t0), "T0");
93 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t1), "T1");
95 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
96 TCG_AREG0, offsetof(CPUState, t2), "T2");
97 #else
98 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
100 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
101 #endif
102 #if !defined(TARGET_PPC64)
103 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
104 TCG_AREG0, offsetof(CPUState, t0_64),
105 "T0_64");
106 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
107 TCG_AREG0, offsetof(CPUState, t1_64),
108 "T1_64");
109 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
110 TCG_AREG0, offsetof(CPUState, t2_64),
111 "T2_64");
112 #endif
113
114 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft0), "FT0");
116 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft1), "FT1");
118 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
119 offsetof(CPUState, ft2), "FT2");
120
121 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[0]), "AVR0H");
123 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr0.u64[1]), "AVR0L");
125 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[0]), "AVR1H");
127 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr1.u64[1]), "AVR1L");
129 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[0]), "AVR2H");
131 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
132 offsetof(CPUState, avr2.u64[1]), "AVR2L");
133
134 p = cpu_reg_names;
135
136 for (i = 0; i < 8; i++) {
137 sprintf(p, "crf%d", i);
138 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
139 offsetof(CPUState, crf[i]), p);
140 p += 5;
141 }
142
143 for (i = 0; i < 32; i++) {
144 sprintf(p, "r%d", i);
145 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
146 offsetof(CPUState, gpr[i]), p);
147 p += (i < 10) ? 3 : 4;
148 #if !defined(TARGET_PPC64)
149 sprintf(p, "r%dH", i);
150 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
151 offsetof(CPUState, gprh[i]), p);
152 p += (i < 10) ? 4 : 5;
153 #endif
154
155 sprintf(p, "fp%d", i);
156 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
157 offsetof(CPUState, fpr[i]), p);
158 p += (i < 10) ? 4 : 5;
159
160 sprintf(p, "avr%dH", i);
161 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
162 offsetof(CPUState, avr[i].u64[0]), p);
163 p += (i < 10) ? 6 : 7;
164
165 sprintf(p, "avr%dL", i);
166 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
167 offsetof(CPUState, avr[i].u64[1]), p);
168 p += (i < 10) ? 6 : 7;
169 }
170
171 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
172 offsetof(CPUState, nip), "nip");
173
174 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
175 offsetof(CPUState, ctr), "ctr");
176
177 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
178 offsetof(CPUState, lr), "lr");
179
180 cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
181 offsetof(CPUState, xer), "xer");
182
183 cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
184 offsetof(CPUState, fpscr), "fpscr");
185
186 /* register helpers */
187 #undef DEF_HELPER
188 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
189 #include "helper.h"
190
191 done_init = 1;
192 }
193
194 #if defined(OPTIMIZE_FPRF_UPDATE)
195 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
196 static uint16_t **gen_fprf_ptr;
197 #endif
198
199 /* internal defines */
200 typedef struct DisasContext {
201 struct TranslationBlock *tb;
202 target_ulong nip;
203 uint32_t opcode;
204 uint32_t exception;
205 /* Routine used to access memory */
206 int mem_idx;
207 /* Translation flags */
208 #if !defined(CONFIG_USER_ONLY)
209 int supervisor;
210 #endif
211 #if defined(TARGET_PPC64)
212 int sf_mode;
213 #endif
214 int fpu_enabled;
215 int altivec_enabled;
216 int spe_enabled;
217 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
218 int singlestep_enabled;
219 int dcache_line_size;
220 } DisasContext;
221
222 struct opc_handler_t {
223 /* invalid bits */
224 uint32_t inval;
225 /* instruction type */
226 uint64_t type;
227 /* handler */
228 void (*handler)(DisasContext *ctx);
229 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
230 const char *oname;
231 #endif
232 #if defined(DO_PPC_STATISTICS)
233 uint64_t count;
234 #endif
235 };
236
237 static always_inline void gen_reset_fpstatus (void)
238 {
239 #ifdef CONFIG_SOFTFLOAT
240 gen_op_reset_fpstatus();
241 #endif
242 }
243
244 static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
245 {
246 if (set_fprf != 0) {
247 /* This case might be optimized later */
248 #if defined(OPTIMIZE_FPRF_UPDATE)
249 *gen_fprf_ptr++ = gen_opc_ptr;
250 #endif
251 gen_op_compute_fprf(1);
252 if (unlikely(set_rc))
253 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
254 gen_op_float_check_status();
255 } else if (unlikely(set_rc)) {
256 /* We always need to compute fpcc */
257 gen_op_compute_fprf(0);
258 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
259 if (set_fprf)
260 gen_op_float_check_status();
261 }
262 }
263
264 static always_inline void gen_optimize_fprf (void)
265 {
266 #if defined(OPTIMIZE_FPRF_UPDATE)
267 uint16_t **ptr;
268
269 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
270 *ptr = INDEX_op_nop1;
271 gen_fprf_ptr = gen_fprf_buf;
272 #endif
273 }
274
275 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
276 {
277 #if defined(TARGET_PPC64)
278 if (ctx->sf_mode)
279 tcg_gen_movi_tl(cpu_nip, nip);
280 else
281 #endif
282 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
283 }
284
285 #define GEN_EXCP(ctx, excp, error) \
286 do { \
287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
288 gen_update_nip(ctx, (ctx)->nip); \
289 } \
290 gen_op_raise_exception_err((excp), (error)); \
291 ctx->exception = (excp); \
292 } while (0)
293
294 #define GEN_EXCP_INVAL(ctx) \
295 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
296 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
297
298 #define GEN_EXCP_PRIVOPC(ctx) \
299 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
300 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
301
302 #define GEN_EXCP_PRIVREG(ctx) \
303 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
304 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
305
306 #define GEN_EXCP_NO_FP(ctx) \
307 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
308
309 #define GEN_EXCP_NO_AP(ctx) \
310 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
311
312 #define GEN_EXCP_NO_VR(ctx) \
313 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
314
315 /* Stop translation */
316 static always_inline void GEN_STOP (DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static always_inline void GEN_SYNC (DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 static void gen_##name (DisasContext *ctx); \
330 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
331 static void gen_##name (DisasContext *ctx)
332
333 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
334 static void gen_##name (DisasContext *ctx); \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
336 static void gen_##name (DisasContext *ctx)
337
338 typedef struct opcode_t {
339 unsigned char opc1, opc2, opc3;
340 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
341 unsigned char pad[5];
342 #else
343 unsigned char pad[1];
344 #endif
345 opc_handler_t handler;
346 const char *oname;
347 } opcode_t;
348
349 /*****************************************************************************/
350 /*** Instruction decoding ***/
351 #define EXTRACT_HELPER(name, shift, nb) \
352 static always_inline uint32_t name (uint32_t opcode) \
353 { \
354 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
355 }
356
357 #define EXTRACT_SHELPER(name, shift, nb) \
358 static always_inline int32_t name (uint32_t opcode) \
359 { \
360 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
361 }
362
363 /* Opcode part 1 */
364 EXTRACT_HELPER(opc1, 26, 6);
365 /* Opcode part 2 */
366 EXTRACT_HELPER(opc2, 1, 5);
367 /* Opcode part 3 */
368 EXTRACT_HELPER(opc3, 6, 5);
369 /* Update Cr0 flags */
370 EXTRACT_HELPER(Rc, 0, 1);
371 /* Destination */
372 EXTRACT_HELPER(rD, 21, 5);
373 /* Source */
374 EXTRACT_HELPER(rS, 21, 5);
375 /* First operand */
376 EXTRACT_HELPER(rA, 16, 5);
377 /* Second operand */
378 EXTRACT_HELPER(rB, 11, 5);
379 /* Third operand */
380 EXTRACT_HELPER(rC, 6, 5);
381 /*** Get CRn ***/
382 EXTRACT_HELPER(crfD, 23, 3);
383 EXTRACT_HELPER(crfS, 18, 3);
384 EXTRACT_HELPER(crbD, 21, 5);
385 EXTRACT_HELPER(crbA, 16, 5);
386 EXTRACT_HELPER(crbB, 11, 5);
387 /* SPR / TBL */
388 EXTRACT_HELPER(_SPR, 11, 10);
389 static always_inline uint32_t SPR (uint32_t opcode)
390 {
391 uint32_t sprn = _SPR(opcode);
392
393 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
394 }
395 /*** Get constants ***/
396 EXTRACT_HELPER(IMM, 12, 8);
397 /* 16 bits signed immediate value */
398 EXTRACT_SHELPER(SIMM, 0, 16);
399 /* 16 bits unsigned immediate value */
400 EXTRACT_HELPER(UIMM, 0, 16);
401 /* Bit count */
402 EXTRACT_HELPER(NB, 11, 5);
403 /* Shift count */
404 EXTRACT_HELPER(SH, 11, 5);
405 /* Mask start */
406 EXTRACT_HELPER(MB, 6, 5);
407 /* Mask end */
408 EXTRACT_HELPER(ME, 1, 5);
409 /* Trap operand */
410 EXTRACT_HELPER(TO, 21, 5);
411
412 EXTRACT_HELPER(CRM, 12, 8);
413 EXTRACT_HELPER(FM, 17, 8);
414 EXTRACT_HELPER(SR, 16, 4);
415 EXTRACT_HELPER(FPIMM, 12, 4);
416
417 /*** Jump target decoding ***/
418 /* Displacement */
419 EXTRACT_SHELPER(d, 0, 16);
420 /* Immediate address */
421 static always_inline target_ulong LI (uint32_t opcode)
422 {
423 return (opcode >> 0) & 0x03FFFFFC;
424 }
425
426 static always_inline uint32_t BD (uint32_t opcode)
427 {
428 return (opcode >> 0) & 0xFFFC;
429 }
430
431 EXTRACT_HELPER(BO, 21, 5);
432 EXTRACT_HELPER(BI, 16, 5);
433 /* Absolute/relative address */
434 EXTRACT_HELPER(AA, 1, 1);
435 /* Link */
436 EXTRACT_HELPER(LK, 0, 1);
437
438 /* Create a mask between <start> and <end> bits */
439 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
440 {
441 target_ulong ret;
442
443 #if defined(TARGET_PPC64)
444 if (likely(start == 0)) {
445 ret = UINT64_MAX << (63 - end);
446 } else if (likely(end == 63)) {
447 ret = UINT64_MAX >> start;
448 }
449 #else
450 if (likely(start == 0)) {
451 ret = UINT32_MAX << (31 - end);
452 } else if (likely(end == 31)) {
453 ret = UINT32_MAX >> start;
454 }
455 #endif
456 else {
457 ret = (((target_ulong)(-1ULL)) >> (start)) ^
458 (((target_ulong)(-1ULL) >> (end)) >> 1);
459 if (unlikely(start > end))
460 return ~ret;
461 }
462
463 return ret;
464 }
465
466 /*****************************************************************************/
467 /* PowerPC Instructions types definitions */
468 enum {
469 PPC_NONE = 0x0000000000000000ULL,
470 /* PowerPC base instructions set */
471 PPC_INSNS_BASE = 0x0000000000000001ULL,
472 /* integer operations instructions */
473 #define PPC_INTEGER PPC_INSNS_BASE
474 /* flow control instructions */
475 #define PPC_FLOW PPC_INSNS_BASE
476 /* virtual memory instructions */
477 #define PPC_MEM PPC_INSNS_BASE
478 /* ld/st with reservation instructions */
479 #define PPC_RES PPC_INSNS_BASE
480 /* spr/msr access instructions */
481 #define PPC_MISC PPC_INSNS_BASE
482 /* Deprecated instruction sets */
483 /* Original POWER instruction set */
484 PPC_POWER = 0x0000000000000002ULL,
485 /* POWER2 instruction set extension */
486 PPC_POWER2 = 0x0000000000000004ULL,
487 /* Power RTC support */
488 PPC_POWER_RTC = 0x0000000000000008ULL,
489 /* Power-to-PowerPC bridge (601) */
490 PPC_POWER_BR = 0x0000000000000010ULL,
491 /* 64 bits PowerPC instruction set */
492 PPC_64B = 0x0000000000000020ULL,
493 /* New 64 bits extensions (PowerPC 2.0x) */
494 PPC_64BX = 0x0000000000000040ULL,
495 /* 64 bits hypervisor extensions */
496 PPC_64H = 0x0000000000000080ULL,
497 /* New wait instruction (PowerPC 2.0x) */
498 PPC_WAIT = 0x0000000000000100ULL,
499 /* Time base mftb instruction */
500 PPC_MFTB = 0x0000000000000200ULL,
501
502 /* Fixed-point unit extensions */
503 /* PowerPC 602 specific */
504 PPC_602_SPEC = 0x0000000000000400ULL,
505 /* isel instruction */
506 PPC_ISEL = 0x0000000000000800ULL,
507 /* popcntb instruction */
508 PPC_POPCNTB = 0x0000000000001000ULL,
509 /* string load / store */
510 PPC_STRING = 0x0000000000002000ULL,
511
512 /* Floating-point unit extensions */
513 /* Optional floating point instructions */
514 PPC_FLOAT = 0x0000000000010000ULL,
515 /* New floating-point extensions (PowerPC 2.0x) */
516 PPC_FLOAT_EXT = 0x0000000000020000ULL,
517 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
518 PPC_FLOAT_FRES = 0x0000000000080000ULL,
519 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
520 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
521 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
522 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
523
524 /* Vector/SIMD extensions */
525 /* Altivec support */
526 PPC_ALTIVEC = 0x0000000001000000ULL,
527 /* PowerPC 2.03 SPE extension */
528 PPC_SPE = 0x0000000002000000ULL,
529 /* PowerPC 2.03 SPE floating-point extension */
530 PPC_SPEFPU = 0x0000000004000000ULL,
531
532 /* Optional memory control instructions */
533 PPC_MEM_TLBIA = 0x0000000010000000ULL,
534 PPC_MEM_TLBIE = 0x0000000020000000ULL,
535 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
536 /* sync instruction */
537 PPC_MEM_SYNC = 0x0000000080000000ULL,
538 /* eieio instruction */
539 PPC_MEM_EIEIO = 0x0000000100000000ULL,
540
541 /* Cache control instructions */
542 PPC_CACHE = 0x0000000200000000ULL,
543 /* icbi instruction */
544 PPC_CACHE_ICBI = 0x0000000400000000ULL,
545 /* dcbz instruction with fixed cache line size */
546 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
547 /* dcbz instruction with tunable cache line size */
548 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
549 /* dcba instruction */
550 PPC_CACHE_DCBA = 0x0000002000000000ULL,
551 /* Freescale cache locking instructions */
552 PPC_CACHE_LOCK = 0x0000004000000000ULL,
553
554 /* MMU related extensions */
555 /* external control instructions */
556 PPC_EXTERN = 0x0000010000000000ULL,
557 /* segment register access instructions */
558 PPC_SEGMENT = 0x0000020000000000ULL,
559 /* PowerPC 6xx TLB management instructions */
560 PPC_6xx_TLB = 0x0000040000000000ULL,
561 /* PowerPC 74xx TLB management instructions */
562 PPC_74xx_TLB = 0x0000080000000000ULL,
563 /* PowerPC 40x TLB management instructions */
564 PPC_40x_TLB = 0x0000100000000000ULL,
565 /* segment register access instructions for PowerPC 64 "bridge" */
566 PPC_SEGMENT_64B = 0x0000200000000000ULL,
567 /* SLB management */
568 PPC_SLBI = 0x0000400000000000ULL,
569
570 /* Embedded PowerPC dedicated instructions */
571 PPC_WRTEE = 0x0001000000000000ULL,
572 /* PowerPC 40x exception model */
573 PPC_40x_EXCP = 0x0002000000000000ULL,
574 /* PowerPC 405 Mac instructions */
575 PPC_405_MAC = 0x0004000000000000ULL,
576 /* PowerPC 440 specific instructions */
577 PPC_440_SPEC = 0x0008000000000000ULL,
578 /* BookE (embedded) PowerPC specification */
579 PPC_BOOKE = 0x0010000000000000ULL,
580 /* mfapidi instruction */
581 PPC_MFAPIDI = 0x0020000000000000ULL,
582 /* tlbiva instruction */
583 PPC_TLBIVA = 0x0040000000000000ULL,
584 /* tlbivax instruction */
585 PPC_TLBIVAX = 0x0080000000000000ULL,
586 /* PowerPC 4xx dedicated instructions */
587 PPC_4xx_COMMON = 0x0100000000000000ULL,
588 /* PowerPC 40x ibct instructions */
589 PPC_40x_ICBT = 0x0200000000000000ULL,
590 /* rfmci is not implemented in all BookE PowerPC */
591 PPC_RFMCI = 0x0400000000000000ULL,
592 /* rfdi instruction */
593 PPC_RFDI = 0x0800000000000000ULL,
594 /* DCR accesses */
595 PPC_DCR = 0x1000000000000000ULL,
596 /* DCR extended accesse */
597 PPC_DCRX = 0x2000000000000000ULL,
598 /* user-mode DCR access, implemented in PowerPC 460 */
599 PPC_DCRUX = 0x4000000000000000ULL,
600 };
601
602 /*****************************************************************************/
603 /* PowerPC instructions table */
604 #if HOST_LONG_BITS == 64
605 #define OPC_ALIGN 8
606 #else
607 #define OPC_ALIGN 4
608 #endif
609 #if defined(__APPLE__)
610 #define OPCODES_SECTION \
611 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
612 #else
613 #define OPCODES_SECTION \
614 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
615 #endif
616
617 #if defined(DO_PPC_STATISTICS)
618 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
619 OPCODES_SECTION opcode_t opc_##name = { \
620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
623 .pad = { 0, }, \
624 .handler = { \
625 .inval = invl, \
626 .type = _typ, \
627 .handler = &gen_##name, \
628 .oname = stringify(name), \
629 }, \
630 .oname = stringify(name), \
631 }
632 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
633 OPCODES_SECTION opcode_t opc_##name = { \
634 .opc1 = op1, \
635 .opc2 = op2, \
636 .opc3 = op3, \
637 .pad = { 0, }, \
638 .handler = { \
639 .inval = invl, \
640 .type = _typ, \
641 .handler = &gen_##name, \
642 .oname = onam, \
643 }, \
644 .oname = onam, \
645 }
646 #else
647 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
648 OPCODES_SECTION opcode_t opc_##name = { \
649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
652 .pad = { 0, }, \
653 .handler = { \
654 .inval = invl, \
655 .type = _typ, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = stringify(name), \
659 }
660 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
661 OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = onam, \
672 }
673 #endif
674
675 #define GEN_OPCODE_MARK(name) \
676 OPCODES_SECTION opcode_t opc_##name = { \
677 .opc1 = 0xFF, \
678 .opc2 = 0xFF, \
679 .opc3 = 0xFF, \
680 .pad = { 0, }, \
681 .handler = { \
682 .inval = 0x00000000, \
683 .type = 0x00, \
684 .handler = NULL, \
685 }, \
686 .oname = stringify(name), \
687 }
688
689 /* Start opcode list */
690 GEN_OPCODE_MARK(start);
691
692 /* Invalid instruction */
693 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
694 {
695 GEN_EXCP_INVAL(ctx);
696 }
697
698 static opc_handler_t invalid_handler = {
699 .inval = 0xFFFFFFFF,
700 .type = PPC_NONE,
701 .handler = gen_invalid,
702 };
703
704 /*** Integer comparison ***/
705
706 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
707 {
708 int l1, l2, l3;
709
710 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
711 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
712 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
713
714 l1 = gen_new_label();
715 l2 = gen_new_label();
716 l3 = gen_new_label();
717 if (s) {
718 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
719 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
720 } else {
721 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
723 }
724 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
725 tcg_gen_br(l3);
726 gen_set_label(l1);
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
728 tcg_gen_br(l3);
729 gen_set_label(l2);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
731 gen_set_label(l3);
732 }
733
734 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
735 {
736 TCGv t0 = tcg_const_local_tl(arg1);
737 gen_op_cmp(arg0, t0, s, crf);
738 tcg_temp_free(t0);
739 }
740
741 #if defined(TARGET_PPC64)
742 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
743 {
744 TCGv t0, t1;
745 t0 = tcg_temp_local_new(TCG_TYPE_TL);
746 t1 = tcg_temp_local_new(TCG_TYPE_TL);
747 if (s) {
748 tcg_gen_ext32s_tl(t0, arg0);
749 tcg_gen_ext32s_tl(t1, arg1);
750 } else {
751 tcg_gen_ext32u_tl(t0, arg0);
752 tcg_gen_ext32u_tl(t1, arg1);
753 }
754 gen_op_cmp(t0, t1, s, crf);
755 tcg_temp_free(t1);
756 tcg_temp_free(t0);
757 }
758
759 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
760 {
761 TCGv t0 = tcg_const_local_tl(arg1);
762 gen_op_cmp32(arg0, t0, s, crf);
763 tcg_temp_free(t0);
764 }
765 #endif
766
767 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
768 {
769 #if defined(TARGET_PPC64)
770 if (!(ctx->sf_mode))
771 gen_op_cmpi32(reg, 0, 1, 0);
772 else
773 #endif
774 gen_op_cmpi(reg, 0, 1, 0);
775 }
776
777 /* cmp */
778 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
779 {
780 #if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
782 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
783 1, crfD(ctx->opcode));
784 else
785 #endif
786 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
787 1, crfD(ctx->opcode));
788 }
789
790 /* cmpi */
791 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
792 {
793 #if defined(TARGET_PPC64)
794 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
795 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
796 1, crfD(ctx->opcode));
797 else
798 #endif
799 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
800 1, crfD(ctx->opcode));
801 }
802
803 /* cmpl */
804 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
805 {
806 #if defined(TARGET_PPC64)
807 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
808 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
809 0, crfD(ctx->opcode));
810 else
811 #endif
812 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
813 0, crfD(ctx->opcode));
814 }
815
816 /* cmpli */
817 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
818 {
819 #if defined(TARGET_PPC64)
820 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
821 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
822 0, crfD(ctx->opcode));
823 else
824 #endif
825 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
826 0, crfD(ctx->opcode));
827 }
828
829 /* isel (PowerPC 2.03 specification) */
830 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
831 {
832 int l1, l2;
833 uint32_t bi = rC(ctx->opcode);
834 uint32_t mask;
835 TCGv t0;
836
837 l1 = gen_new_label();
838 l2 = gen_new_label();
839
840 mask = 1 << (3 - (bi & 0x03));
841 t0 = tcg_temp_new(TCG_TYPE_I32);
842 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
843 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
844 if (rA(ctx->opcode) == 0)
845 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
846 else
847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
848 tcg_gen_br(l2);
849 gen_set_label(l1);
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
851 gen_set_label(l2);
852 }
853
854 /*** Integer arithmetic ***/
855
856 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
857 {
858 int l1;
859 TCGv t0;
860
861 l1 = gen_new_label();
862 /* Start with XER OV disabled, the most likely case */
863 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
864 t0 = tcg_temp_local_new(TCG_TYPE_TL);
865 tcg_gen_xor_tl(t0, arg0, arg1);
866 #if defined(TARGET_PPC64)
867 if (!ctx->sf_mode)
868 tcg_gen_ext32s_tl(t0, t0);
869 #endif
870 if (sub)
871 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
872 else
873 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
874 tcg_gen_xor_tl(t0, arg1, arg2);
875 #if defined(TARGET_PPC64)
876 if (!ctx->sf_mode)
877 tcg_gen_ext32s_tl(t0, t0);
878 #endif
879 if (sub)
880 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
881 else
882 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
883 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
884 gen_set_label(l1);
885 tcg_temp_free(t0);
886 }
887
888 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
889 {
890 int l1 = gen_new_label();
891
892 #if defined(TARGET_PPC64)
893 if (!(ctx->sf_mode)) {
894 TCGv t0, t1;
895 t0 = tcg_temp_new(TCG_TYPE_TL);
896 t1 = tcg_temp_new(TCG_TYPE_TL);
897
898 tcg_gen_ext32u_tl(t0, arg1);
899 tcg_gen_ext32u_tl(t1, arg2);
900 if (sub) {
901 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
902 } else {
903 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
904 }
905 } else
906 #endif
907 if (sub) {
908 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
909 } else {
910 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
911 }
912 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
913 gen_set_label(l1);
914 }
915
916 /* Common add function */
917 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
918 int add_ca, int compute_ca, int compute_ov)
919 {
920 TCGv t0, t1;
921
922 if ((!compute_ca && !compute_ov) ||
923 (GET_TCGV(ret) != GET_TCGV(arg1) && GET_TCGV(ret) != GET_TCGV(arg2))) {
924 t0 = ret;
925 } else {
926 t0 = tcg_temp_local_new(TCG_TYPE_TL);
927 }
928
929 if (add_ca) {
930 t1 = tcg_temp_local_new(TCG_TYPE_TL);
931 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
932 tcg_gen_shri_tl(t1, t1, XER_CA);
933 }
934
935 if (compute_ca && compute_ov) {
936 /* Start with XER CA and OV disabled, the most likely case */
937 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
938 } else if (compute_ca) {
939 /* Start with XER CA disabled, the most likely case */
940 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
941 } else if (compute_ov) {
942 /* Start with XER OV disabled, the most likely case */
943 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
944 }
945
946 tcg_gen_add_tl(t0, arg1, arg2);
947
948 if (compute_ca) {
949 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
950 }
951 if (add_ca) {
952 tcg_gen_add_tl(t0, t0, t1);
953 gen_op_arith_compute_ca(ctx, t0, t1, 0);
954 tcg_temp_free(t1);
955 }
956 if (compute_ov) {
957 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
958 }
959
960 if (unlikely(Rc(ctx->opcode) != 0))
961 gen_set_Rc0(ctx, t0);
962
963 if (GET_TCGV(t0) != GET_TCGV(ret)) {
964 tcg_gen_mov_tl(ret, t0);
965 tcg_temp_free(t0);
966 }
967 }
968 /* Add functions with two operands */
969 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
970 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
971 { \
972 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
973 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
974 add_ca, compute_ca, compute_ov); \
975 }
976 /* Add functions with one operand and one immediate */
977 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
978 add_ca, compute_ca, compute_ov) \
979 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
980 { \
981 TCGv t0 = tcg_const_local_tl(const_val); \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], t0, \
984 add_ca, compute_ca, compute_ov); \
985 tcg_temp_free(t0); \
986 }
987
988 /* add add. addo addo. */
989 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
990 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
991 /* addc addc. addco addco. */
992 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
993 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
994 /* adde adde. addeo addeo. */
995 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
996 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
997 /* addme addme. addmeo addmeo. */
998 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
999 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1000 /* addze addze. addzeo addzeo.*/
1001 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1002 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1003 /* addi */
1004 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1005 {
1006 target_long simm = SIMM(ctx->opcode);
1007
1008 if (rA(ctx->opcode) == 0) {
1009 /* li case */
1010 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1011 } else {
1012 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1013 }
1014 }
1015 /* addic addic.*/
1016 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1017 int compute_Rc0)
1018 {
1019 target_long simm = SIMM(ctx->opcode);
1020
1021 /* Start with XER CA and OV disabled, the most likely case */
1022 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1023
1024 if (likely(simm != 0)) {
1025 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1026 tcg_gen_addi_tl(t0, arg1, simm);
1027 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1028 tcg_gen_mov_tl(ret, t0);
1029 tcg_temp_free(t0);
1030 } else {
1031 tcg_gen_mov_tl(ret, arg1);
1032 }
1033 if (compute_Rc0) {
1034 gen_set_Rc0(ctx, ret);
1035 }
1036 }
1037 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1038 {
1039 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1040 }
1041 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1042 {
1043 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1044 }
1045 /* addis */
1046 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1047 {
1048 target_long simm = SIMM(ctx->opcode);
1049
1050 if (rA(ctx->opcode) == 0) {
1051 /* lis case */
1052 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1053 } else {
1054 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1055 }
1056 }
1057
1058 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1059 int sign, int compute_ov)
1060 {
1061 int l1, l2, l3;
1062 TCGv t0, t1, t2;
1063
1064 #if defined(TARGET_PPC64)
1065 t0 = tcg_temp_local_new(TCG_TYPE_I32);
1066 t1 = t0;
1067 t2 = tcg_temp_local_new(TCG_TYPE_I32);
1068 tcg_gen_trunc_i64_i32(t1, arg1);
1069 tcg_gen_trunc_i64_i32(t2, arg2);
1070 #else
1071 t0 = ret;
1072 t1 = arg1;
1073 t2 = arg2;
1074 #endif
1075 l1 = gen_new_label();
1076 l2 = gen_new_label();
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l1);
1078 if (sign) {
1079 l3 = gen_new_label();
1080 tcg_gen_brcondi_i32(TCG_COND_NE, t2, -1, l3);
1081 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, INT32_MIN, l1);
1082 gen_set_label(l3);
1083 }
1084 if (sign) {
1085 tcg_gen_div_i32(t0, t1, t2);
1086 } else {
1087 tcg_gen_divu_i32(t0, t1, t2);
1088 }
1089 if (compute_ov) {
1090 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1091 }
1092 tcg_gen_br(l2);
1093 gen_set_label(l1);
1094 if (sign) {
1095 tcg_gen_sari_i32(t0, t1, 31);
1096 } else {
1097 tcg_gen_movi_i32(t0, 0);
1098 }
1099 if (compute_ov) {
1100 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1101 }
1102 gen_set_label(l2);
1103 #if defined(TARGET_PPC64)
1104 tcg_gen_extu_i32_i64(ret, t0);
1105 tcg_temp_free(t0);
1106 #endif
1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, ret);
1109 }
1110 /* Div functions */
1111 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1112 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1113 { \
1114 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1115 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1116 sign, compute_ov); \
1117 }
1118 /* divwu divwu. divwuo divwuo. */
1119 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1120 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1121 /* divw divw. divwo divwo. */
1122 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1123 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1124 #if defined(TARGET_PPC64)
1125 static always_inline void gen_op_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1126 int sign, int compute_ov)
1127 {
1128 int l1, l2, l3;
1129
1130 l1 = gen_new_label();
1131 l2 = gen_new_label();
1132
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1134 if (sign) {
1135 l3 = gen_new_label();
1136 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1137 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1138 gen_set_label(l3);
1139 }
1140 if (sign) {
1141 tcg_gen_div_i64(ret, arg1, arg2);
1142 } else {
1143 tcg_gen_divu_i64(ret, arg1, arg2);
1144 }
1145 if (compute_ov) {
1146 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1147 }
1148 tcg_gen_br(l2);
1149 gen_set_label(l1);
1150 if (sign) {
1151 tcg_gen_sari_i64(ret, arg1, 63);
1152 } else {
1153 tcg_gen_movi_i64(ret, 0);
1154 }
1155 if (compute_ov) {
1156 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1157 }
1158 gen_set_label(l2);
1159 if (unlikely(Rc(ctx->opcode) != 0))
1160 gen_set_Rc0(ctx, ret);
1161 }
1162 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1163 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1164 { \
1165 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1167 sign, compute_ov); \
1168 }
1169 /* divwu divwu. divwuo divwuo. */
1170 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1171 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1172 /* divw divw. divwo divwo. */
1173 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1174 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1175 #endif
1176
1177 /* mulhw mulhw. */
1178 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1179 {
1180 TCGv t0, t1;
1181
1182 t0 = tcg_temp_new(TCG_TYPE_I64);
1183 t1 = tcg_temp_new(TCG_TYPE_I64);
1184 #if defined(TARGET_PPC64)
1185 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1186 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1187 tcg_gen_mul_i64(t0, t0, t1);
1188 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1189 #else
1190 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1191 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1192 tcg_gen_mul_i64(t0, t0, t1);
1193 tcg_gen_shri_i64(t0, t0, 32);
1194 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1195 #endif
1196 tcg_temp_free(t0);
1197 tcg_temp_free(t1);
1198 if (unlikely(Rc(ctx->opcode) != 0))
1199 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1200 }
1201 /* mulhwu mulhwu. */
1202 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1203 {
1204 TCGv t0, t1;
1205
1206 t0 = tcg_temp_new(TCG_TYPE_I64);
1207 t1 = tcg_temp_new(TCG_TYPE_I64);
1208 #if defined(TARGET_PPC64)
1209 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1210 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1211 tcg_gen_mul_i64(t0, t0, t1);
1212 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1213 #else
1214 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1215 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1216 tcg_gen_mul_i64(t0, t0, t1);
1217 tcg_gen_shri_i64(t0, t0, 32);
1218 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1219 #endif
1220 tcg_temp_free(t0);
1221 tcg_temp_free(t1);
1222 if (unlikely(Rc(ctx->opcode) != 0))
1223 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1224 }
1225 /* mullw mullw. */
1226 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1227 {
1228 #if defined(TARGET_PPC64)
1229 TCGv t0, t1;
1230 t0 = tcg_temp_new(TCG_TYPE_TL);
1231 t1 = tcg_temp_new(TCG_TYPE_TL);
1232 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1233 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1234 tcg_gen_mul_tl(t0, t0, t1);
1235 tcg_temp_free(t0);
1236 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], t0);
1237 tcg_temp_free(t1);
1238 #else
1239 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1240 cpu_gpr[rB(ctx->opcode)]);
1241 #endif
1242 if (unlikely(Rc(ctx->opcode) != 0))
1243 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1244 }
1245 /* mullwo mullwo. */
1246 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1247 {
1248 int l1;
1249 TCGv t0, t1;
1250
1251 t0 = tcg_temp_local_new(TCG_TYPE_I64);
1252 t1 = tcg_temp_local_new(TCG_TYPE_I64);
1253 l1 = gen_new_label();
1254 /* Start with XER OV disabled, the most likely case */
1255 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1256 #if defined(TARGET_PPC64)
1257 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1258 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1259 #else
1260 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1261 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1262 #endif
1263 tcg_gen_mul_i64(t0, t0, t1);
1264 #if defined(TARGET_PPC64)
1265 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1266 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1267 #else
1268 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1269 tcg_gen_ext32s_i64(t1, t0);
1270 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1271 #endif
1272 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1273 gen_set_label(l1);
1274 if (unlikely(Rc(ctx->opcode) != 0))
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1276 }
1277 /* mulli */
1278 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1279 {
1280 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1281 SIMM(ctx->opcode));
1282 }
1283 #if defined(TARGET_PPC64)
1284 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1285 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1286 { \
1287 tcg_gen_helper_1_2(helper_##name, cpu_gpr[rD(ctx->opcode)], \
1288 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1289 if (unlikely(Rc(ctx->opcode) != 0)) \
1290 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1291 }
1292 /* mulhd mulhd. */
1293 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1294 /* mulhdu mulhdu. */
1295 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1296 /* mulld mulld. */
1297 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1298 {
1299 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1300 cpu_gpr[rB(ctx->opcode)]);
1301 if (unlikely(Rc(ctx->opcode) != 0))
1302 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1303 }
1304 /* mulldo mulldo. */
1305 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1306 #endif
1307
1308 /* neg neg. nego nego. */
1309 static always_inline void gen_op_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1310 {
1311 int l1, l2;
1312
1313 l1 = gen_new_label();
1314 l2 = gen_new_label();
1315 #if defined(TARGET_PPC64)
1316 if (ctx->sf_mode) {
1317 tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT64_MIN, l1);
1318 } else {
1319 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1320 tcg_gen_ext32s_tl(t0, arg1);
1321 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1322 }
1323 #else
1324 tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT32_MIN, l1);
1325 #endif
1326 tcg_gen_neg_tl(ret, arg1);
1327 if (ov_check) {
1328 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1329 }
1330 tcg_gen_br(l2);
1331 gen_set_label(l1);
1332 tcg_gen_mov_tl(ret, arg1);
1333 if (ov_check) {
1334 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1335 }
1336 gen_set_label(l2);
1337 if (unlikely(Rc(ctx->opcode) != 0))
1338 gen_set_Rc0(ctx, ret);
1339 }
1340 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1341 {
1342 gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1343 }
1344 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1345 {
1346 gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1347 }
1348
1349 /* Common subf function */
1350 static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1351 int add_ca, int compute_ca, int compute_ov)
1352 {
1353 TCGv t0, t1;
1354
1355 if ((!compute_ca && !compute_ov) ||
1356 (GET_TCGV(ret) != GET_TCGV(arg1) && GET_TCGV(ret) != GET_TCGV(arg2))) {
1357 t0 = ret;
1358 } else {
1359 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1360 }
1361
1362 if (add_ca) {
1363 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1364 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1365 tcg_gen_shri_tl(t1, t1, XER_CA);
1366 }
1367
1368 if (compute_ca && compute_ov) {
1369 /* Start with XER CA and OV disabled, the most likely case */
1370 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1371 } else if (compute_ca) {
1372 /* Start with XER CA disabled, the most likely case */
1373 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1374 } else if (compute_ov) {
1375 /* Start with XER OV disabled, the most likely case */
1376 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1377 }
1378
1379 if (add_ca) {
1380 tcg_gen_not_tl(t0, arg1);
1381 tcg_gen_add_tl(t0, t0, arg2);
1382 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1383 tcg_gen_add_tl(t0, t0, t1);
1384 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1385 tcg_temp_free(t1);
1386 } else {
1387 tcg_gen_sub_tl(t0, arg2, arg1);
1388 if (compute_ca) {
1389 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1390 }
1391 }
1392 if (compute_ov) {
1393 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1394 }
1395
1396 if (unlikely(Rc(ctx->opcode) != 0))
1397 gen_set_Rc0(ctx, t0);
1398
1399 if (GET_TCGV(t0) != GET_TCGV(ret)) {
1400 tcg_gen_mov_tl(ret, t0);
1401 tcg_temp_free(t0);
1402 }
1403 }
1404 /* Sub functions with Two operands functions */
1405 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1406 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1407 { \
1408 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1409 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1410 add_ca, compute_ca, compute_ov); \
1411 }
1412 /* Sub functions with one operand and one immediate */
1413 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1414 add_ca, compute_ca, compute_ov) \
1415 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1416 { \
1417 TCGv t0 = tcg_const_local_tl(const_val); \
1418 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1419 cpu_gpr[rA(ctx->opcode)], t0, \
1420 add_ca, compute_ca, compute_ov); \
1421 tcg_temp_free(t0); \
1422 }
1423 /* subf subf. subfo subfo. */
1424 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1425 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1426 /* subfc subfc. subfco subfco. */
1427 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1428 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1429 /* subfe subfe. subfeo subfo. */
1430 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1431 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1432 /* subfme subfme. subfmeo subfmeo. */
1433 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1434 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1435 /* subfze subfze. subfzeo subfzeo.*/
1436 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1437 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1438 /* subfic */
1439 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1440 {
1441 /* Start with XER CA and OV disabled, the most likely case */
1442 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1443 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1444 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1445 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1446 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1447 tcg_temp_free(t1);
1448 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1449 tcg_temp_free(t0);
1450 }
1451
1452 /*** Integer logical ***/
1453 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1454 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1455 { \
1456 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1457 cpu_gpr[rB(ctx->opcode)]); \
1458 if (unlikely(Rc(ctx->opcode) != 0)) \
1459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1460 }
1461
1462 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1463 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1464 { \
1465 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1466 if (unlikely(Rc(ctx->opcode) != 0)) \
1467 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1468 }
1469
1470 /* and & and. */
1471 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1472 /* andc & andc. */
1473 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1474 /* andi. */
1475 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1476 {
1477 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1479 }
1480 /* andis. */
1481 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1482 {
1483 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1485 }
1486 /* cntlzw */
1487 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1488 {
1489 tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1490 if (unlikely(Rc(ctx->opcode) != 0))
1491 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1492 }
1493 /* eqv & eqv. */
1494 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1495 /* extsb & extsb. */
1496 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1497 /* extsh & extsh. */
1498 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1499 /* nand & nand. */
1500 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1501 /* nor & nor. */
1502 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1503 /* or & or. */
1504 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1505 {
1506 int rs, ra, rb;
1507
1508 rs = rS(ctx->opcode);
1509 ra = rA(ctx->opcode);
1510 rb = rB(ctx->opcode);
1511 /* Optimisation for mr. ri case */
1512 if (rs != ra || rs != rb) {
1513 if (rs != rb)
1514 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1515 else
1516 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1517 if (unlikely(Rc(ctx->opcode) != 0))
1518 gen_set_Rc0(ctx, cpu_gpr[ra]);
1519 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1520 gen_set_Rc0(ctx, cpu_gpr[rs]);
1521 #if defined(TARGET_PPC64)
1522 } else {
1523 int prio = 0;
1524
1525 switch (rs) {
1526 case 1:
1527 /* Set process priority to low */
1528 prio = 2;
1529 break;
1530 case 6:
1531 /* Set process priority to medium-low */
1532 prio = 3;
1533 break;
1534 case 2:
1535 /* Set process priority to normal */
1536 prio = 4;
1537 break;
1538 #if !defined(CONFIG_USER_ONLY)
1539 case 31:
1540 if (ctx->supervisor > 0) {
1541 /* Set process priority to very low */
1542 prio = 1;
1543 }
1544 break;
1545 case 5:
1546 if (ctx->supervisor > 0) {
1547 /* Set process priority to medium-hight */
1548 prio = 5;
1549 }
1550 break;
1551 case 3:
1552 if (ctx->supervisor > 0) {
1553 /* Set process priority to high */
1554 prio = 6;
1555 }
1556 break;
1557 case 7:
1558 if (ctx->supervisor > 1) {
1559 /* Set process priority to very high */
1560 prio = 7;
1561 }
1562 break;
1563 #endif
1564 default:
1565 /* nop */
1566 break;
1567 }
1568 if (prio) {
1569 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1570 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1571 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1572 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1573 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1574 tcg_temp_free(t0);
1575 }
1576 #endif
1577 }
1578 }
1579 /* orc & orc. */
1580 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1581 /* xor & xor. */
1582 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1583 {
1584 /* Optimisation for "set to zero" case */
1585 if (rS(ctx->opcode) != rB(ctx->opcode))
1586 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1587 else
1588 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1589 if (unlikely(Rc(ctx->opcode) != 0))
1590 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1591 }
1592 /* ori */
1593 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1594 {
1595 target_ulong uimm = UIMM(ctx->opcode);
1596
1597 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1598 /* NOP */
1599 /* XXX: should handle special NOPs for POWER series */
1600 return;
1601 }
1602 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1603 }
1604 /* oris */
1605 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1606 {
1607 target_ulong uimm = UIMM(ctx->opcode);
1608
1609 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1610 /* NOP */
1611 return;
1612 }
1613 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1614 }
1615 /* xori */
1616 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1617 {
1618 target_ulong uimm = UIMM(ctx->opcode);
1619
1620 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1621 /* NOP */
1622 return;
1623 }
1624 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1625 }
1626 /* xoris */
1627 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1628 {
1629 target_ulong uimm = UIMM(ctx->opcode);
1630
1631 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1632 /* NOP */
1633 return;
1634 }
1635 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1636 }
1637 /* popcntb : PowerPC 2.03 specification */
1638 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1639 {
1640 #if defined(TARGET_PPC64)
1641 if (ctx->sf_mode)
1642 tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1643 else
1644 #endif
1645 tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1646 }
1647
1648 #if defined(TARGET_PPC64)
1649 /* extsw & extsw. */
1650 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1651 /* cntlzd */
1652 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1653 {
1654 tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 if (unlikely(Rc(ctx->opcode) != 0))
1656 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1657 }
1658 #endif
1659
1660 /*** Integer rotate ***/
1661 /* rlwimi & rlwimi. */
1662 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1663 {
1664 uint32_t mb, me, sh;
1665
1666 mb = MB(ctx->opcode);
1667 me = ME(ctx->opcode);
1668 sh = SH(ctx->opcode);
1669 if (likely(sh == 0 && mb == 0 && me == 31)) {
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1671 } else {
1672 TCGv t0, t1;
1673 target_ulong mask;
1674
1675 t0 = tcg_temp_new(TCG_TYPE_TL);
1676 #if defined(TARGET_PPC64)
1677 t1 = tcg_temp_new(TCG_TYPE_I32);
1678 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1679 tcg_gen_rotli_i32(t1, t1, sh);
1680 tcg_gen_extu_i32_i64(t0, t1);
1681 tcg_temp_free(t1);
1682 #else
1683 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1684 #endif
1685 #if defined(TARGET_PPC64)
1686 mb += 32;
1687 me += 32;
1688 #endif
1689 mask = MASK(mb, me);
1690 t1 = tcg_temp_new(TCG_TYPE_TL);
1691 tcg_gen_andi_tl(t0, t0, mask);
1692 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1693 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1694 tcg_temp_free(t0);
1695 tcg_temp_free(t1);
1696 }
1697 if (unlikely(Rc(ctx->opcode) != 0))
1698 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1699 }
1700 /* rlwinm & rlwinm. */
1701 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1702 {
1703 uint32_t mb, me, sh;
1704
1705 sh = SH(ctx->opcode);
1706 mb = MB(ctx->opcode);
1707 me = ME(ctx->opcode);
1708
1709 if (likely(mb == 0 && me == (31 - sh))) {
1710 if (likely(sh == 0)) {
1711 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1712 } else {
1713 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1714 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1715 tcg_gen_shli_tl(t0, t0, sh);
1716 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1717 tcg_temp_free(t0);
1718 }
1719 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1720 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1721 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1722 tcg_gen_shri_tl(t0, t0, mb);
1723 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1724 tcg_temp_free(t0);
1725 } else {
1726 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1727 #if defined(TARGET_PPC64)
1728 TCGv t1 = tcg_temp_new(TCG_TYPE_I32);
1729 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1730 tcg_gen_rotli_i32(t1, t1, sh);
1731 tcg_gen_extu_i32_i64(t0, t1);
1732 tcg_temp_free(t1);
1733 #else
1734 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1735 #endif
1736 #if defined(TARGET_PPC64)
1737 mb += 32;
1738 me += 32;
1739 #endif
1740 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1741 tcg_temp_free(t0);
1742 }
1743 if (unlikely(Rc(ctx->opcode) != 0))
1744 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1745 }
1746 /* rlwnm & rlwnm. */
1747 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1748 {
1749 uint32_t mb, me;
1750 TCGv t0;
1751 #if defined(TARGET_PPC64)
1752 TCGv t1, t2;
1753 #endif
1754
1755 mb = MB(ctx->opcode);
1756 me = ME(ctx->opcode);
1757 t0 = tcg_temp_new(TCG_TYPE_TL);
1758 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1759 #if defined(TARGET_PPC64)
1760 t1 = tcg_temp_new(TCG_TYPE_I32);
1761 t2 = tcg_temp_new(TCG_TYPE_I32);
1762 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1763 tcg_gen_trunc_i64_i32(t2, t0);
1764 tcg_gen_rotl_i32(t1, t1, t2);
1765 tcg_gen_extu_i32_i64(t0, t1);
1766 tcg_temp_free(t1);
1767 tcg_temp_free(t2);
1768 #else
1769 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1770 #endif
1771 if (unlikely(mb != 0 || me != 31)) {
1772 #if defined(TARGET_PPC64)
1773 mb += 32;
1774 me += 32;
1775 #endif
1776 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1777 } else {
1778 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1779 }
1780 tcg_temp_free(t0);
1781 if (unlikely(Rc(ctx->opcode) != 0))
1782 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1783 }
1784
1785 #if defined(TARGET_PPC64)
1786 #define GEN_PPC64_R2(name, opc1, opc2) \
1787 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1788 { \
1789 gen_##name(ctx, 0); \
1790 } \
1791 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1792 PPC_64B) \
1793 { \
1794 gen_##name(ctx, 1); \
1795 }
1796 #define GEN_PPC64_R4(name, opc1, opc2) \
1797 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1798 { \
1799 gen_##name(ctx, 0, 0); \
1800 } \
1801 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1802 PPC_64B) \
1803 { \
1804 gen_##name(ctx, 0, 1); \
1805 } \
1806 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1807 PPC_64B) \
1808 { \
1809 gen_##name(ctx, 1, 0); \
1810 } \
1811 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1812 PPC_64B) \
1813 { \
1814 gen_##name(ctx, 1, 1); \
1815 }
1816
1817 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1818 uint32_t me, uint32_t sh)
1819 {
1820 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1821 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1822 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1823 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1824 } else {
1825 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1826 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1827 if (likely(mb == 0 && me == 63)) {
1828 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1829 } else {
1830 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1831 }
1832 tcg_temp_free(t0);
1833 }
1834 if (unlikely(Rc(ctx->opcode) != 0))
1835 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1836 }
1837 /* rldicl - rldicl. */
1838 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1839 {
1840 uint32_t sh, mb;
1841
1842 sh = SH(ctx->opcode) | (shn << 5);
1843 mb = MB(ctx->opcode) | (mbn << 5);
1844 gen_rldinm(ctx, mb, 63, sh);
1845 }
1846 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1847 /* rldicr - rldicr. */
1848 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1849 {
1850 uint32_t sh, me;
1851
1852 sh = SH(ctx->opcode) | (shn << 5);
1853 me = MB(ctx->opcode) | (men << 5);
1854 gen_rldinm(ctx, 0, me, sh);
1855 }
1856 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1857 /* rldic - rldic. */
1858 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1859 {
1860 uint32_t sh, mb;
1861
1862 sh = SH(ctx->opcode) | (shn << 5);
1863 mb = MB(ctx->opcode) | (mbn << 5);
1864 gen_rldinm(ctx, mb, 63 - sh, sh);
1865 }
1866 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1867
1868 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1869 uint32_t me)
1870 {
1871 TCGv t0;
1872
1873 mb = MB(ctx->opcode);
1874 me = ME(ctx->opcode);
1875 t0 = tcg_temp_new(TCG_TYPE_TL);
1876 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1877 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1878 if (unlikely(mb != 0 || me != 63)) {
1879 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1880 } else {
1881 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1882 }
1883 tcg_temp_free(t0);
1884 if (unlikely(Rc(ctx->opcode) != 0))
1885 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1886 }
1887
1888 /* rldcl - rldcl. */
1889 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1890 {
1891 uint32_t mb;
1892
1893 mb = MB(ctx->opcode) | (mbn << 5);
1894 gen_rldnm(ctx, mb, 63);
1895 }
1896 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1897 /* rldcr - rldcr. */
1898 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1899 {
1900 uint32_t me;
1901
1902 me = MB(ctx->opcode) | (men << 5);
1903 gen_rldnm(ctx, 0, me);
1904 }
1905 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1906 /* rldimi - rldimi. */
1907 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1908 {
1909 uint32_t sh, mb, me;
1910
1911 sh = SH(ctx->opcode) | (shn << 5);
1912 mb = MB(ctx->opcode) | (mbn << 5);
1913 me = 63 - sh;
1914 if (unlikely(sh == 0 && mb == 0)) {
1915 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1916 } else {
1917 TCGv t0, t1;
1918 target_ulong mask;
1919
1920 t0 = tcg_temp_new(TCG_TYPE_TL);
1921 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1922 t1 = tcg_temp_new(TCG_TYPE_TL);
1923 mask = MASK(mb, me);
1924 tcg_gen_andi_tl(t0, t0, mask);
1925 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1926 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1927 tcg_temp_free(t0);
1928 tcg_temp_free(t1);
1929 }
1930 if (unlikely(Rc(ctx->opcode) != 0))
1931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1932 }
1933 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1934 #endif
1935
1936 /*** Integer shift ***/
1937 /* slw & slw. */
1938 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1939 {
1940 TCGv t0;
1941 int l1, l2;
1942 l1 = gen_new_label();
1943 l2 = gen_new_label();
1944
1945 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1946 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1947 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1948 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1949 tcg_gen_br(l2);
1950 gen_set_label(l1);
1951 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1952 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1953 gen_set_label(l2);
1954 tcg_temp_free(t0);
1955 if (unlikely(Rc(ctx->opcode) != 0))
1956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1957 }
1958 /* sraw & sraw. */
1959 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1960 {
1961 tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)],
1962 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1963 if (unlikely(Rc(ctx->opcode) != 0))
1964 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1965 }
1966 /* srawi & srawi. */
1967 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1968 {
1969 int sh = SH(ctx->opcode);
1970 if (sh != 0) {
1971 int l1, l2;
1972 TCGv t0;
1973 l1 = gen_new_label();
1974 l2 = gen_new_label();
1975 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1976 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1977 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1978 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1979 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1980 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1981 tcg_gen_br(l2);
1982 gen_set_label(l1);
1983 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1984 gen_set_label(l2);
1985 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1986 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1987 tcg_temp_free(t0);
1988 } else {
1989 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1990 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1991 }
1992 if (unlikely(Rc(ctx->opcode) != 0))
1993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1994 }
1995 /* srw & srw. */
1996 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1997 {
1998 TCGv t0, t1;
1999 int l1, l2;
2000 l1 = gen_new_label();
2001 l2 = gen_new_label();
2002
2003 t0 = tcg_temp_local_new(TCG_TYPE_TL);
2004 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
2005 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
2006 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2007 tcg_gen_br(l2);
2008 gen_set_label(l1);
2009 t1 = tcg_temp_new(TCG_TYPE_TL);
2010 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
2011 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
2012 tcg_temp_free(t1);
2013 gen_set_label(l2);
2014 tcg_temp_free(t0);
2015 if (unlikely(Rc(ctx->opcode) != 0))
2016 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2017 }
2018 #if defined(TARGET_PPC64)
2019 /* sld & sld. */
2020 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2021 {
2022 TCGv t0;
2023 int l1, l2;
2024 l1 = gen_new_label();
2025 l2 = gen_new_label();
2026
2027 t0 = tcg_temp_local_new(TCG_TYPE_TL);
2028 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2029 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2030 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2031 tcg_gen_br(l2);
2032 gen_set_label(l1);
2033 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2034 gen_set_label(l2);
2035 tcg_temp_free(t0);
2036 if (unlikely(Rc(ctx->opcode) != 0))
2037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2038 }
2039 /* srad & srad. */
2040 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2041 {
2042 tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)],
2043 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2044 if (unlikely(Rc(ctx->opcode) != 0))
2045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2046 }
2047 /* sradi & sradi. */
2048 static always_inline void gen_sradi (DisasContext *ctx, int n)
2049 {
2050 int sh = SH(ctx->opcode) + (n << 5);
2051 if (sh != 0) {
2052 int l1, l2;
2053 TCGv t0;
2054 l1 = gen_new_label();
2055 l2 = gen_new_label();
2056 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2057 t0 = tcg_temp_new(TCG_TYPE_TL);
2058 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2059 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2060 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2061 tcg_gen_br(l2);
2062 gen_set_label(l1);
2063 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2064 gen_set_label(l2);
2065 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2066 } else {
2067 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2068 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2069 }
2070 if (unlikely(Rc(ctx->opcode) != 0))
2071 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2072 }
2073 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2074 {
2075 gen_sradi(ctx, 0);
2076 }
2077 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2078 {
2079 gen_sradi(ctx, 1);
2080 }
2081 /* srd & srd. */
2082 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2083 {
2084 TCGv t0;
2085 int l1, l2;
2086 l1 = gen_new_label();
2087 l2 = gen_new_label();
2088
2089 t0 = tcg_temp_local_new(TCG_TYPE_TL);
2090 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2091 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2092 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2093 tcg_gen_br(l2);
2094 gen_set_label(l1);
2095 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2096 gen_set_label(l2);
2097 tcg_temp_free(t0);
2098 if (unlikely(Rc(ctx->opcode) != 0))
2099 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2100 }
2101 #endif
2102
2103 /*** Floating-Point arithmetic ***/
2104 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2105 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2106 { \
2107 if (unlikely(!ctx->fpu_enabled)) { \
2108 GEN_EXCP_NO_FP(ctx); \
2109 return; \
2110 } \
2111 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2112 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
2113 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
2114 gen_reset_fpstatus(); \
2115 gen_op_f##op(); \
2116 if (isfloat) { \
2117 gen_op_frsp(); \
2118 } \
2119 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2120 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
2121 }
2122
2123 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2124 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2125 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2126
2127 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2128 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2129 { \
2130 if (unlikely(!ctx->fpu_enabled)) { \
2131 GEN_EXCP_NO_FP(ctx); \
2132 return; \
2133 } \
2134 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2135 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
2136 gen_reset_fpstatus(); \
2137 gen_op_f##op(); \
2138 if (isfloat) { \
2139 gen_op_frsp(); \
2140 } \
2141 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2142 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
2143 }
2144 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2145 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2146 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2147
2148 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2149 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2150 { \
2151 if (unlikely(!ctx->fpu_enabled)) { \
2152 GEN_EXCP_NO_FP(ctx); \
2153 return; \
2154 } \
2155 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2156 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
2157 gen_reset_fpstatus(); \
2158 gen_op_f##op(); \
2159 if (isfloat) { \
2160 gen_op_frsp(); \
2161 } \
2162 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2163 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
2164 }
2165 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2166 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2167 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2168
2169 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2170 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2171 { \
2172 if (unlikely(!ctx->fpu_enabled)) { \
2173 GEN_EXCP_NO_FP(ctx); \
2174 return; \
2175 } \
2176 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
2177 gen_reset_fpstatus(); \
2178 gen_op_f##name(); \
2179 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2180 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
2181 }
2182
2183 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2184 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2185 { \
2186 if (unlikely(!ctx->fpu_enabled)) { \
2187 GEN_EXCP_NO_FP(ctx); \
2188 return; \
2189 } \
2190 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
2191 gen_reset_fpstatus(); \
2192 gen_op_f##name(); \
2193 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2194 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
2195 }
2196
2197 /* fadd - fadds */
2198 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2199 /* fdiv - fdivs */
2200 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2201 /* fmul - fmuls */
2202 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2203
2204 /* fre */
2205 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2206
2207 /* fres */
2208 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2209
2210 /* frsqrte */
2211 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2212
2213 /* frsqrtes */
2214 static always_inline void gen_op_frsqrtes (void)
2215 {
2216 gen_op_frsqrte();
2217 gen_op_frsp();
2218 }
2219 GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
2220
2221 /* fsel */
2222 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2223 /* fsub - fsubs */
2224 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2225 /* Optional: */
2226 /* fsqrt */
2227 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2228 {
2229 if (unlikely(!ctx->fpu_enabled)) {
2230 GEN_EXCP_NO_FP(ctx);
2231 return;
2232 }
2233 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2234 gen_reset_fpstatus();
2235 gen_op_fsqrt();
2236 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2237 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
2238 }
2239
2240 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2241 {
2242 if (unlikely(!ctx->fpu_enabled)) {
2243 GEN_EXCP_NO_FP(ctx);
2244 return;
2245 }
2246 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2247 gen_reset_fpstatus();
2248 gen_op_fsqrt();
2249 gen_op_frsp();
2250 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2251 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
2252 }
2253
2254 /*** Floating-Point multiply-and-add ***/
2255 /* fmadd - fmadds */
2256 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2257 /* fmsub - fmsubs */
2258 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2259 /* fnmadd - fnmadds */
2260 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2261 /* fnmsub - fnmsubs */
2262 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2263
2264 /*** Floating-Point round & convert ***/
2265 /* fctiw */
2266 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2267 /* fctiwz */
2268 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2269 /* frsp */
2270 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2271 #if defined(TARGET_PPC64)
2272 /* fcfid */
2273 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2274 /* fctid */
2275 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2276 /* fctidz */
2277 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2278 #endif
2279
2280 /* frin */
2281 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2282 /* friz */
2283 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2284 /* frip */
2285 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2286 /* frim */
2287 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2288
2289 /*** Floating-Point compare ***/
2290 /* fcmpo */
2291 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
2292 {
2293 if (unlikely(!ctx->fpu_enabled)) {
2294 GEN_EXCP_NO_FP(ctx);
2295 return;
2296 }
2297 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2298 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
2299 gen_reset_fpstatus();
2300 tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
2301 gen_op_float_check_status();
2302 }
2303
2304 /* fcmpu */
2305 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
2306 {
2307 if (unlikely(!ctx->fpu_enabled)) {
2308 GEN_EXCP_NO_FP(ctx);
2309 return;
2310 }
2311 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2312 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
2313 gen_reset_fpstatus();
2314 tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
2315 gen_op_float_check_status();
2316 }
2317
2318 /*** Floating-point move ***/
2319 /* fabs */
2320 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2321 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2322
2323 /* fmr - fmr. */
2324 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2325 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2326 {
2327 if (unlikely(!ctx->fpu_enabled)) {
2328 GEN_EXCP_NO_FP(ctx);
2329 return;
2330 }
2331 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2332 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2333 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
2334 }
2335
2336 /* fnabs */
2337 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2338 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2339 /* fneg */
2340 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2341 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2342
2343 /*** Floating-Point status & ctrl register ***/
2344 /* mcrfs */
2345 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2346 {
2347 int bfa;
2348
2349 if (unlikely(!ctx->fpu_enabled)) {
2350 GEN_EXCP_NO_FP(ctx);
2351 return;
2352 }
2353 gen_optimize_fprf();
2354 bfa = 4 * (7 - crfS(ctx->opcode));
2355 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2356 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2357 gen_op_fpscr_resetbit(~(0xF << bfa));
2358 }
2359
2360 /* mffs */
2361 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2362 {
2363 if (unlikely(!ctx->fpu_enabled)) {
2364 GEN_EXCP_NO_FP(ctx);
2365 return;
2366 }
2367 gen_optimize_fprf();
2368 gen_reset_fpstatus();
2369 gen_op_load_fpscr_FT0();
2370 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2371 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
2372 }
2373
2374 /* mtfsb0 */
2375 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2376 {
2377 uint8_t crb;
2378
2379 if (unlikely(!ctx->fpu_enabled)) {
2380 GEN_EXCP_NO_FP(ctx);
2381 return;
2382 }
2383 crb = 32 - (crbD(ctx->opcode) >> 2);
2384 gen_optimize_fprf();
2385 gen_reset_fpstatus();
2386 if (likely(crb != 30 && crb != 29))
2387 gen_op_fpscr_resetbit(~(1 << crb));
2388 if (unlikely(Rc(ctx->opcode) != 0)) {
2389 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2390 }
2391 }
2392
2393 /* mtfsb1 */
2394 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2395 {
2396 uint8_t crb;
2397
2398 if (unlikely(!ctx->fpu_enabled)) {
2399 GEN_EXCP_NO_FP(ctx);
2400 return;
2401 }
2402 crb = 32 - (crbD(ctx->opcode) >> 2);
2403 gen_optimize_fprf();
2404 gen_reset_fpstatus();
2405 /* XXX: we pretend we can only do IEEE floating-point computations */
2406 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2407 gen_op_fpscr_setbit(crb);
2408 if (unlikely(Rc(ctx->opcode) != 0)) {
2409 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2410 }
2411 /* We can raise a differed exception */
2412 gen_op_float_check_status();
2413 }
2414
2415 /* mtfsf */
2416 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2417 {
2418 if (unlikely(!ctx->fpu_enabled)) {
2419 GEN_EXCP_NO_FP(ctx);
2420 return;
2421 }
2422 gen_optimize_fprf();
2423 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2424 gen_reset_fpstatus();
2425 gen_op_store_fpscr(FM(ctx->opcode));
2426 if (unlikely(Rc(ctx->opcode) != 0)) {
2427 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2428 }
2429 /* We can raise a differed exception */
2430 gen_op_float_check_status();
2431 }
2432
2433 /* mtfsfi */
2434 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2435 {
2436 int bf, sh;
2437
2438 if (unlikely(!ctx->fpu_enabled)) {
2439 GEN_EXCP_NO_FP(ctx);
2440 return;
2441 }
2442 bf = crbD(ctx->opcode) >> 2;
2443 sh = 7 - bf;
2444 gen_optimize_fprf();
2445 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
2446 gen_reset_fpstatus();
2447 gen_op_store_fpscr(1 << sh);
2448 if (unlikely(Rc(ctx->opcode) != 0)) {
2449 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2450 }
2451 /* We can raise a differed exception */
2452 gen_op_float_check_status();
2453 }
2454
2455 /*** Addressing modes ***/
2456 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2457 static always_inline void gen_addr_imm_index (TCGv EA,
2458 DisasContext *ctx,
2459 target_long maskl)
2460 {
2461 target_long simm = SIMM(ctx->opcode);
2462
2463 simm &= ~maskl;
2464 if (rA(ctx->opcode) == 0)
2465 tcg_gen_movi_tl(EA, simm);
2466 else if (likely(simm != 0))
2467 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2468 else
2469 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2470 }
2471
2472 static always_inline void gen_addr_reg_index (TCGv EA,
2473 DisasContext *ctx)
2474 {
2475 if (rA(ctx->opcode) == 0)
2476 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2477 else
2478 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2479 }
2480
2481 static always_inline void gen_addr_register (TCGv EA,
2482 DisasContext *ctx)
2483 {
2484 if (rA(ctx->opcode) == 0)
2485 tcg_gen_movi_tl(EA, 0);
2486 else
2487 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2488 }
2489
2490 #if defined(TARGET_PPC64)
2491 #define _GEN_MEM_FUNCS(name, mode) \
2492 &gen_op_##name##_##mode, \
2493 &gen_op_##name##_le_##mode, \
2494 &gen_op_##name##_64_##mode, \
2495 &gen_op_##name##_le_64_##mode
2496 #else
2497 #define _GEN_MEM_FUNCS(name, mode) \
2498 &gen_op_##name##_##mode, \
2499 &gen_op_##name##_le_##mode
2500 #endif
2501 #if defined(CONFIG_USER_ONLY)
2502 #if defined(TARGET_PPC64)
2503 #define NB_MEM_FUNCS 4
2504 #else
2505 #define NB_MEM_FUNCS 2
2506 #endif
2507 #define GEN_MEM_FUNCS(name) \
2508 _GEN_MEM_FUNCS(name, raw)
2509 #else
2510 #if defined(TARGET_PPC64)
2511 #define NB_MEM_FUNCS 12
2512 #else
2513 #define NB_MEM_FUNCS 6
2514 #endif
2515 #define GEN_MEM_FUNCS(name) \
2516 _GEN_MEM_FUNCS(name, user), \
2517 _GEN_MEM_FUNCS(name, kernel), \
2518 _GEN_MEM_FUNCS(name, hypv)
2519 #endif
2520
2521 /*** Integer load ***/
2522 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2523 #define OP_LD_TABLE(width) \
2524 static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2525 GEN_MEM_FUNCS(l##width), \
2526 };
2527 #define OP_ST_TABLE(width) \
2528 static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2529 GEN_MEM_FUNCS(st##width), \
2530 };
2531
2532
2533 #if defined(TARGET_PPC64)
2534 #define GEN_QEMU_LD_PPC64(width) \
2535 static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2536 { \
2537 if (likely(flags & 2)) \
2538 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2539 else { \
2540 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2541 tcg_gen_ext32u_tl(addr, t1); \
2542 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2543 tcg_temp_free(addr); \
2544 } \
2545 }
2546 GEN_QEMU_LD_PPC64(8u)
2547 GEN_QEMU_LD_PPC64(8s)
2548 GEN_QEMU_LD_PPC64(16u)
2549 GEN_QEMU_LD_PPC64(16s)
2550 GEN_QEMU_LD_PPC64(32u)
2551 GEN_QEMU_LD_PPC64(32s)
2552 GEN_QEMU_LD_PPC64(64)
2553
2554 #define GEN_QEMU_ST_PPC64(width) \
2555 static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2556 { \
2557 if (likely(flags & 2)) \
2558 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2559 else { \
2560 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2561 tcg_gen_ext32u_tl(addr, t1); \
2562 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2563 tcg_temp_free(addr); \
2564 } \
2565 }
2566 GEN_QEMU_ST_PPC64(8)
2567 GEN_QEMU_ST_PPC64(16)
2568 GEN_QEMU_ST_PPC64(32)
2569 GEN_QEMU_ST_PPC64(64)
2570
2571 static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2572 {
2573 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
2574 }
2575
2576 static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2577 {
2578 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
2579 }
2580
2581 static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2582 {
2583 if (unlikely(flags & 1)) {
2584 TCGv t0;
2585 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2586 t0 = tcg_temp_new(TCG_TYPE_I32);
2587 tcg_gen_trunc_tl_i32(t0, arg0);
2588 tcg_gen_bswap16_i32(t0, t0);
2589 tcg_gen_extu_i32_tl(arg0, t0);
2590 tcg_temp_free(t0);
2591 } else
2592 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2593 }
2594
2595 static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2596 {
2597 if (unlikely(flags & 1)) {
2598 TCGv t0;
2599 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2600 t0 = tcg_temp_new(TCG_TYPE_I32);
2601 tcg_gen_trunc_tl_i32(t0, arg0);
2602 tcg_gen_bswap16_i32(t0, t0);
2603 tcg_gen_extu_i32_tl(arg0, t0);
2604 tcg_gen_ext16s_tl(arg0, arg0);
2605 tcg_temp_free(t0);
2606 } else
2607 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
2608 }
2609
2610 static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2611 {
2612 if (unlikely(flags & 1)) {
2613 TCGv t0;
2614 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2615 t0 = tcg_temp_new(TCG_TYPE_I32);
2616 tcg_gen_trunc_tl_i32(t0, arg0);
2617 tcg_gen_bswap_i32(t0, t0);
2618 tcg_gen_extu_i32_tl(arg0, t0);
2619 tcg_temp_free(t0);
2620 } else
2621 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2622 }
2623
2624 static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
2625 {
2626 if (unlikely(flags & 1)) {
2627 TCGv t0;
2628 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2629 t0 = tcg_temp_new(TCG_TYPE_I32);
2630 tcg_gen_trunc_tl_i32(t0, arg0);
2631 tcg_gen_bswap_i32(t0, t0);
2632 tcg_gen_ext_i32_tl(arg0, t0);
2633 tcg_temp_free(t0);
2634 } else
2635 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
2636 }
2637
2638 static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2639 {
2640 gen_qemu_ld64_ppc64(arg0, arg1, flags);
2641 if (unlikely(flags & 1))
2642 tcg_gen_bswap_i64(arg0, arg0);
2643 }
2644
2645 static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2646 {
2647 gen_qemu_st8_ppc64(arg0, arg1, flags);
2648 }
2649
2650 static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2651 {
2652 if (unlikely(flags & 1)) {
2653 TCGv t0, t1;
2654 t0 = tcg_temp_new(TCG_TYPE_I32);
2655 tcg_gen_trunc_tl_i32(t0, arg0);
2656 tcg_gen_ext16u_i32(t0, t0);
2657 tcg_gen_bswap16_i32(t0, t0);
2658 t1 = tcg_temp_new(TCG_TYPE_I64);
2659 tcg_gen_extu_i32_tl(t1, t0);
2660 tcg_temp_free(t0);
2661 gen_qemu_st16_ppc64(t1, arg1, flags);
2662 tcg_temp_free(t1);
2663 } else
2664 gen_qemu_st16_ppc64(arg0, arg1, flags);
2665 }
2666
2667 static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2668 {
2669 if (unlikely(flags & 1)) {
2670 TCGv t0, t1;
2671 t0 = tcg_temp_new(TCG_TYPE_I32);
2672 tcg_gen_trunc_tl_i32(t0, arg0);
2673 tcg_gen_bswap_i32(t0, t0);
2674 t1 = tcg_temp_new(TCG_TYPE_I64);
2675 tcg_gen_extu_i32_tl(t1, t0);
2676 tcg_temp_free(t0);
2677 gen_qemu_st32_ppc64(t1, arg1, flags);
2678 tcg_temp_free(t1);
2679 } else
2680 gen_qemu_st32_ppc64(arg0, arg1, flags);
2681 }
2682
2683 static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2684 {
2685 if (unlikely(flags & 1)) {
2686 TCGv t0 = tcg_temp_new(TCG_TYPE_I64);
2687 tcg_gen_bswap_i64(t0, arg0);
2688 gen_qemu_st64_ppc64(t0, arg1, flags);
2689 tcg_temp_free(t0);
2690 } else
2691 gen_qemu_st64_ppc64(arg0, arg1, flags);
2692 }
2693
2694
2695 #else /* defined(TARGET_PPC64) */
2696 #define GEN_QEMU_LD_PPC32(width) \
2697 static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
2698 { \
2699 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
2700 }
2701 GEN_QEMU_LD_PPC32(8u)
2702 GEN_QEMU_LD_PPC32(8s)
2703 GEN_QEMU_LD_PPC32(16u)
2704 GEN_QEMU_LD_PPC32(16s)
2705 GEN_QEMU_LD_PPC32(32u)
2706 GEN_QEMU_LD_PPC32(32s)
2707 GEN_QEMU_LD_PPC32(64)
2708
2709 #define GEN_QEMU_ST_PPC32(width) \
2710 static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
2711 { \
2712 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
2713 }
2714 GEN_QEMU_ST_PPC32(8)
2715 GEN_QEMU_ST_PPC32(16)
2716 GEN_QEMU_ST_PPC32(32)
2717 GEN_QEMU_ST_PPC32(64)
2718
2719 static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2720 {
2721 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
2722 }
2723
2724 static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2725 {
2726 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
2727 }
2728
2729 static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2730 {
2731 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
2732 if (unlikely(flags & 1))
2733 tcg_gen_bswap16_i32(arg0, arg0);
2734 }
2735
2736 static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2737 {
2738 if (unlikely(flags & 1)) {
2739 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2740 tcg_gen_bswap16_i32(arg0, arg0);
2741 tcg_gen_ext16s_i32(arg0, arg0);
2742 } else
2743 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
2744 }
2745
2746 static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2747 {
2748 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
2749 if (unlikely(flags & 1))
2750 tcg_gen_bswap_i32(arg0, arg0);
2751 }
2752
2753 static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2754 {
2755 gen_qemu_ld64_ppc32(arg0, arg1, flags);
2756 if (unlikely(flags & 1))
2757 tcg_gen_bswap_i64(arg0, arg0);
2758 }
2759
2760 static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2761 {
2762 gen_qemu_st8_ppc32(arg0, arg1, flags >> 1);
2763 }
2764
2765 static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2766 {
2767 if (unlikely(flags & 1)) {
2768 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2769 tcg_gen_ext16u_i32(temp, arg0);
2770 tcg_gen_bswap16_i32(temp, temp);
2771 gen_qemu_st16_ppc32(temp, arg1, flags >> 1);
2772 tcg_temp_free(temp);
2773 } else
2774 gen_qemu_st16_ppc32(arg0, arg1, flags >> 1);
2775 }
2776
2777 static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2778 {
2779 if (unlikely(flags & 1)) {
2780 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2781 tcg_gen_bswap_i32(temp, arg0);
2782 gen_qemu_st32_ppc32(temp, arg1, flags >> 1);
2783 tcg_temp_free(temp);
2784 } else
2785 gen_qemu_st32_ppc32(arg0, arg1, flags >> 1);
2786 }
2787
2788 static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2789 {
2790 if (unlikely(flags & 1)) {
2791 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2792 tcg_gen_bswap_i64(temp, arg0);
2793 gen_qemu_st64_ppc32(temp, arg1, flags >> 1);
2794 tcg_temp_free(temp);
2795 } else
2796 gen_qemu_st64_ppc32(arg0, arg1, flags >> 1);
2797 }
2798
2799 #endif
2800
2801 #define GEN_LD(width, opc, type) \
2802 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2803 { \
2804 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2805 gen_addr_imm_index(EA, ctx, 0); \
2806 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2807 tcg_temp_free(EA); \
2808 }
2809
2810 #define GEN_LDU(width, opc, type) \
2811 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2812 { \
2813 TCGv EA; \
2814 if (unlikely(rA(ctx->opcode) == 0 || \
2815 rA(ctx->opcode) == rD(ctx->opcode))) { \
2816 GEN_EXCP_INVAL(ctx); \
2817 return; \
2818 } \
2819 EA = tcg_temp_new(TCG_TYPE_TL); \
2820 if (type == PPC_64B) \
2821 gen_addr_imm_index(EA, ctx, 0x03); \
2822 else \
2823 gen_addr_imm_index(EA, ctx, 0); \
2824 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2825 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2826 tcg_temp_free(EA); \
2827 }
2828
2829 #define GEN_LDUX(width, opc2, opc3, type) \
2830 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2831 { \
2832 TCGv EA; \
2833 if (unlikely(rA(ctx->opcode) == 0 || \
2834 rA(ctx->opcode) == rD(ctx->opcode))) { \
2835 GEN_EXCP_INVAL(ctx); \
2836 return; \
2837 } \
2838 EA = tcg_temp_new(TCG_TYPE_TL); \
2839 gen_addr_reg_index(EA, ctx); \
2840 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2841 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2842 tcg_temp_free(EA); \
2843 }
2844
2845 #define GEN_LDX(width, opc2, opc3, type) \
2846 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2847 { \
2848 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2849 gen_addr_reg_index(EA, ctx); \
2850 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2851 tcg_temp_free(EA); \
2852 }
2853
2854 #define GEN_LDS(width, op, type) \
2855 GEN_LD(width, op | 0x20, type); \
2856 GEN_LDU(width, op | 0x21, type); \
2857 GEN_LDUX(width, 0x17, op | 0x01, type); \
2858 GEN_LDX(width, 0x17, op | 0x00, type)
2859
2860 /* lbz lbzu lbzux lbzx */
2861 GEN_LDS(8u, 0x02, PPC_INTEGER);
2862 /* lha lhau lhaux lhax */
2863 GEN_LDS(16s, 0x0A, PPC_INTEGER);
2864 /* lhz lhzu lhzux lhzx */
2865 GEN_LDS(16u, 0x08, PPC_INTEGER);
2866 /* lwz lwzu lwzux lwzx */
2867 GEN_LDS(32u, 0x00, PPC_INTEGER);
2868 #if defined(TARGET_PPC64)
2869 /* lwaux */
2870 GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
2871 /* lwax */
2872 GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
2873 /* ldux */
2874 GEN_LDUX(64, 0x15, 0x01, PPC_64B);
2875 /* ldx */
2876 GEN_LDX(64, 0x15, 0x00, PPC_64B);
2877 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2878 {
2879 TCGv EA;
2880 if (Rc(ctx->opcode)) {
2881 if (unlikely(rA(ctx->opcode) == 0 ||
2882 rA(ctx->opcode) == rD(ctx->opcode))) {
2883 GEN_EXCP_INVAL(ctx);
2884 return;
2885 }
2886 }
2887 EA = tcg_temp_new(TCG_TYPE_TL);
2888 gen_addr_imm_index(EA, ctx, 0x03);
2889 if (ctx->opcode & 0x02) {
2890 /* lwa (lwau is undefined) */
2891 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2892 } else {
2893 /* ld - ldu */
2894 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2895 }
2896 if (Rc(ctx->opcode))
2897 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2898 tcg_temp_free(EA);
2899 }
2900 /* lq */
2901 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2902 {
2903 #if defined(CONFIG_USER_ONLY)
2904 GEN_EXCP_PRIVOPC(ctx);
2905 #else
2906 int ra, rd;
2907 TCGv EA;
2908
2909 /* Restore CPU state */
2910 if (unlikely(ctx->supervisor == 0)) {
2911 GEN_EXCP_PRIVOPC(ctx);
2912 return;
2913 }
2914 ra = rA(ctx->opcode);
2915 rd = rD(ctx->opcode);
2916 if (unlikely((rd & 1) || rd == ra)) {
2917 GEN_EXCP_INVAL(ctx);
2918 return;
2919 }
2920 if (unlikely(ctx->mem_idx & 1)) {
2921 /* Little-endian mode is not handled */
2922 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2923 return;
2924 }
2925 EA = tcg_temp_new(TCG_TYPE_TL);
2926 gen_addr_imm_index(EA, ctx, 0x0F);
2927 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2928 tcg_gen_addi_tl(EA, EA, 8);
2929 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2930 tcg_temp_free(EA);
2931 #endif
2932 }
2933 #endif
2934
2935 /*** Integer store ***/
2936 #define GEN_ST(width, opc, type) \
2937 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2938 { \
2939 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2940 gen_addr_imm_index(EA, ctx, 0); \
2941 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2942 tcg_temp_free(EA); \
2943 }
2944
2945 #define GEN_STU(width, opc, type) \
2946 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2947 { \
2948 TCGv EA; \
2949 if (unlikely(rA(ctx->opcode) == 0)) { \
2950 GEN_EXCP_INVAL(ctx); \
2951 return; \
2952 } \
2953 EA = tcg_temp_new(TCG_TYPE_TL); \
2954 if (type == PPC_64B) \
2955 gen_addr_imm_index(EA, ctx, 0x03); \
2956 else \
2957 gen_addr_imm_index(EA, ctx, 0); \
2958 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2959 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2960 tcg_temp_free(EA); \
2961 }
2962
2963 #define GEN_STUX(width, opc2, opc3, type) \
2964 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2965 { \
2966 TCGv EA; \
2967 if (unlikely(rA(ctx->opcode) == 0)) { \
2968 GEN_EXCP_INVAL(ctx); \
2969 return; \
2970 } \
2971 EA = tcg_temp_new(TCG_TYPE_TL); \
2972 gen_addr_reg_index(EA, ctx); \
2973 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2974 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2975 tcg_temp_free(EA); \
2976 }
2977
2978 #define GEN_STX(width, opc2, opc3, type) \
2979 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2980 { \
2981 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2982 gen_addr_reg_index(EA, ctx); \
2983 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2984 tcg_temp_free(EA); \
2985 }
2986
2987 #define GEN_STS(width, op, type) \
2988 GEN_ST(width, op | 0x20, type); \
2989 GEN_STU(width, op | 0x21, type); \
2990 GEN_STUX(width, 0x17, op | 0x01, type); \
2991 GEN_STX(width, 0x17, op | 0x00, type)
2992
2993 /* stb stbu stbux stbx */
2994 GEN_STS(8, 0x06, PPC_INTEGER);
2995 /* sth sthu sthux sthx */
2996 GEN_STS(16, 0x0C, PPC_INTEGER);
2997 /* stw stwu stwux stwx */
2998 GEN_STS(32, 0x04, PPC_INTEGER);
2999 #if defined(TARGET_PPC64)
3000 GEN_STUX(64, 0x15, 0x05, PPC_64B);
3001 GEN_STX(64, 0x15, 0x04, PPC_64B);
3002 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
3003 {
3004 int rs;
3005 TCGv EA;
3006
3007 rs = rS(ctx->opcode);
3008 if ((ctx->opcode & 0x3) == 0x2) {
3009 #if defined(CONFIG_USER_ONLY)
3010 GEN_EXCP_PRIVOPC(ctx);
3011 #else
3012 /* stq */
3013 if (unlikely(ctx->supervisor == 0)) {
3014 GEN_EXCP_PRIVOPC(ctx);
3015 return;
3016 }
3017 if (unlikely(rs & 1)) {
3018 GEN_EXCP_INVAL(ctx);
3019 return;
3020 }
3021 if (unlikely(ctx->mem_idx & 1)) {
3022 /* Little-endian mode is not handled */
3023 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3024 return;
3025 }
3026 EA = tcg_temp_new(TCG_TYPE_TL);
3027 gen_addr_imm_index(EA, ctx, 0x03);
3028 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3029 tcg_gen_addi_tl(EA, EA, 8);
3030 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3031 tcg_temp_free(EA);
3032 #endif
3033 } else {
3034 /* std / stdu */
3035 if (Rc(ctx->opcode)) {
3036 if (unlikely(rA(ctx->opcode) == 0)) {
3037 GEN_EXCP_INVAL(ctx);
3038 return;
3039 }
3040 }
3041 EA = tcg_temp_new(TCG_TYPE_TL);
3042 gen_addr_imm_index(EA, ctx, 0x03);
3043 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3044 if (Rc(ctx->opcode))
3045 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3046 tcg_temp_free(EA);
3047 }
3048 }
3049 #endif
3050 /*** Integer load and store with byte reverse ***/
3051 /* lhbrx */
3052 void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3053 {
3054 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3055 gen_qemu_ld16u(temp, t1, flags);
3056 tcg_gen_bswap16_i32(temp, temp);
3057 tcg_gen_extu_i32_tl(t0, temp);
3058 tcg_temp_free(temp);
3059 }
3060 GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
3061
3062 /* lwbrx */
3063 void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3064 {
3065 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3066 gen_qemu_ld32u(temp, t1, flags);
3067 tcg_gen_bswap_i32(temp, temp);
3068 tcg_gen_extu_i32_tl(t0, temp);
3069 tcg_temp_free(temp);
3070 }
3071 GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
3072
3073 /* sthbrx */
3074 void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3075 {
3076 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3077 tcg_gen_trunc_tl_i32(temp, t0);
3078 tcg_gen_ext16u_i32(temp, temp);
3079 tcg_gen_bswap16_i32(temp, temp);
3080 gen_qemu_st16(temp, t1, flags);
3081 tcg_temp_free(temp);
3082 }
3083 GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
3084
3085 /* stwbrx */
3086 void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3087 {
3088 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3089 tcg_gen_trunc_tl_i32(temp, t0);
3090 tcg_gen_bswap_i32(temp, temp);
3091 gen_qemu_st32(temp, t1, flags);
3092 tcg_temp_free(temp);
3093 }
3094 GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
3095
3096 /*** Integer load and store multiple ***/
3097 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
3098 static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
3099 GEN_MEM_FUNCS(lmw),
3100 };
3101 static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
3102 GEN_MEM_FUNCS(stmw),
3103 };
3104
3105 /* lmw */
3106 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3107 {
3108 /* NIP cannot be restored if the memory exception comes from an helper */
3109 gen_update_nip(ctx, ctx->nip - 4);
3110 gen_addr_imm_index(cpu_T[0], ctx, 0);
3111 op_ldstm(lmw, rD(ctx->opcode));
3112 }
3113
3114 /* stmw */
3115 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3116 {
3117 /* NIP cannot be restored if the memory exception comes from an helper */
3118 gen_update_nip(ctx, ctx->nip - 4);
3119 gen_addr_imm_index(cpu_T[0], ctx, 0);
3120 op_ldstm(stmw, rS(ctx->opcode));
3121 }
3122
3123 /*** Integer load and store strings ***/
3124 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
3125 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
3126 /* string load & stores are by definition endian-safe */
3127 #define gen_op_lswi_le_raw gen_op_lswi_raw
3128 #define gen_op_lswi_le_user gen_op_lswi_user
3129 #define gen_op_lswi_le_kernel gen_op_lswi_kernel
3130 #define gen_op_lswi_le_hypv gen_op_lswi_hypv
3131 #define gen_op_lswi_le_64_raw gen_op_lswi_raw
3132 #define gen_op_lswi_le_64_user gen_op_lswi_user
3133 #define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
3134 #define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
3135 static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
3136 GEN_MEM_FUNCS(lswi),
3137 };
3138 #define gen_op_lswx_le_raw gen_op_lswx_raw
3139 #define gen_op_lswx_le_user gen_op_lswx_user
3140 #define gen_op_lswx_le_kernel gen_op_lswx_kernel
3141 #define gen_op_lswx_le_hypv gen_op_lswx_hypv
3142 #define gen_op_lswx_le_64_raw gen_op_lswx_raw
3143 #define gen_op_lswx_le_64_user gen_op_lswx_user
3144 #define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
3145 #define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
3146 static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
3147 GEN_MEM_FUNCS(lswx),
3148 };
3149 #define gen_op_stsw_le_raw gen_op_stsw_raw
3150 #define gen_op_stsw_le_user gen_op_stsw_user
3151 #define gen_op_stsw_le_kernel gen_op_stsw_kernel
3152 #define gen_op_stsw_le_hypv gen_op_stsw_hypv
3153 #define gen_op_stsw_le_64_raw gen_op_stsw_raw
3154 #define gen_op_stsw_le_64_user gen_op_stsw_user
3155 #define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3156 #define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
3157 static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3158 GEN_MEM_FUNCS(stsw),
3159 };
3160
3161 /* lswi */
3162 /* PowerPC32 specification says we must generate an exception if
3163 * rA is in the range of registers to be loaded.
3164 * In an other hand, IBM says this is valid, but rA won't be loaded.
3165 * For now, I'll follow the spec...
3166 */
3167 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
3168 {
3169 int nb = NB(ctx->opcode);
3170 int start = rD(ctx->opcode);
3171 int ra = rA(ctx->opcode);
3172 int nr;
3173
3174 if (nb == 0)
3175 nb = 32;
3176 nr = nb / 4;
3177 if (unlikely(((start + nr) > 32 &&
3178 start <= ra && (start + nr - 32) > ra) ||
3179 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3180 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3181 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
3182 return;
3183 }
3184 /* NIP cannot be restored if the memory exception comes from an helper */
3185 gen_update_nip(ctx, ctx->nip - 4);
3186 gen_addr_register(cpu_T[0], ctx);
3187 tcg_gen_movi_tl(cpu_T[1], nb);
3188 op_ldsts(lswi, start);
3189 }
3190
3191 /* lswx */
3192 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
3193 {
3194 int ra = rA(ctx->opcode);
3195 int rb = rB(ctx->opcode);
3196
3197 /* NIP cannot be restored if the memory exception comes from an helper */
3198 gen_update_nip(ctx, ctx->nip - 4);
3199 gen_addr_reg_index(cpu_T[0], ctx);
3200 if (ra == 0) {
3201 ra = rb;
3202 }
3203 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
3204 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
3205 }
3206
3207 /* stswi */
3208 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
3209 {
3210 int nb = NB(ctx->opcode);
3211
3212 /* NIP cannot be restored if the memory exception comes from an helper */
3213 gen_update_nip(ctx, ctx->nip - 4);
3214 gen_addr_register(cpu_T[0], ctx);
3215 if (nb == 0)
3216 nb = 32;
3217 tcg_gen_movi_tl(cpu_T[1], nb);
3218 op_ldsts(stsw, rS(ctx->opcode));
3219 }
3220
3221 /* stswx */
3222 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
3223 {
3224 /* NIP cannot be restored if the memory exception comes from an helper */
3225 gen_update_nip(ctx, ctx->nip - 4);
3226 gen_addr_reg_index(cpu_T[0], ctx);
3227 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
3228 op_ldsts(stsw, rS(ctx->opcode));
3229 }
3230
3231 /*** Memory synchronisation ***/
3232 /* eieio */
3233 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
3234 {
3235 }
3236
3237 /* isync */
3238 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
3239 {
3240 GEN_STOP(ctx);
3241 }
3242
3243 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3244 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
3245 static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3246 GEN_MEM_FUNCS(lwarx),
3247 };
3248 static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3249 GEN_MEM_FUNCS(stwcx),
3250 };
3251
3252 /* lwarx */
3253 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3254 {
3255 /* NIP cannot be restored if the memory exception comes from an helper */
3256 gen_update_nip(ctx, ctx->nip - 4);
3257 gen_addr_reg_index(cpu_T[0], ctx);
3258 op_lwarx();
3259 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
3260 }
3261
3262 /* stwcx. */
3263 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3264 {
3265 /* NIP cannot be restored if the memory exception comes from an helper */
3266 gen_update_nip(ctx, ctx->nip - 4);
3267 gen_addr_reg_index(cpu_T[0], ctx);
3268 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3269 op_stwcx();
3270 }
3271
3272 #if defined(TARGET_PPC64)
3273 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3274 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
3275 static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3276 GEN_MEM_FUNCS(ldarx),
3277 };
3278 static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3279 GEN_MEM_FUNCS(stdcx),
3280 };
3281
3282 /* ldarx */
3283 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3284 {
3285 /* NIP cannot be restored if the memory exception comes from an helper */
3286 gen_update_nip(ctx, ctx->nip - 4);
3287 gen_addr_reg_index(cpu_T[0], ctx);
3288 op_ldarx();
3289 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
3290 }
3291
3292 /* stdcx. */
3293 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3294 {
3295 /* NIP cannot be restored if the memory exception comes from an helper */
3296 gen_update_nip(ctx, ctx->nip - 4);
3297 gen_addr_reg_index(cpu_T[0], ctx);
3298 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
3299 op_stdcx();
3300 }
3301 #endif /* defined(TARGET_PPC64) */
3302
3303 /* sync */
3304 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
3305 {
3306 }
3307
3308 /* wait */
3309 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3310 {
3311 /* Stop translation, as the CPU is supposed to sleep from now */
3312 gen_op_wait();
3313 GEN_EXCP(ctx, EXCP_HLT, 1);
3314 }
3315
3316 /*** Floating-point load ***/
3317 #define GEN_LDF(width, opc, type) \
3318 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3319 { \
3320 if (unlikely(!ctx->fpu_enabled)) { \
3321 GEN_EXCP_NO_FP(ctx); \
3322 return; \
3323 } \
3324 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3325 op_ldst(l##width); \
3326 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3327 }
3328
3329 #define GEN_LDUF(width, opc, type) \
3330 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3331 { \
3332 if (unlikely(!ctx->fpu_enabled)) { \
3333 GEN_EXCP_NO_FP(ctx); \
3334 return; \
3335 } \
3336 if (unlikely(rA(ctx->opcode) == 0)) { \
3337 GEN_EXCP_INVAL(ctx); \
3338 return; \
3339 } \
3340 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3341 op_ldst(l##width); \
3342 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3343 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
3344 }
3345
3346 #define GEN_LDUXF(width, opc, type) \
3347 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3348 { \
3349 if (unlikely(!ctx->fpu_enabled)) { \
3350 GEN_EXCP_NO_FP(ctx); \
3351 return; \
3352 } \
3353 if (unlikely(rA(ctx->opcode) == 0)) { \
3354 GEN_EXCP_INVAL(ctx); \
3355 return; \
3356 } \
3357 gen_addr_reg_index(cpu_T[0], ctx); \
3358 op_ldst(l##width); \
3359 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3360 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
3361 }
3362
3363 #define GEN_LDXF(width, opc2, opc3, type) \
3364 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3365 { \
3366 if (unlikely(!ctx->fpu_enabled)) { \
3367 GEN_EXCP_NO_FP(ctx); \
3368 return; \
3369 } \
3370 gen_addr_reg_index(cpu_T[0], ctx); \
3371 op_ldst(l##width); \
3372 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3373 }
3374
3375 #define GEN_LDFS(width, op, type) \
3376 OP_LD_TABLE(width); \
3377 GEN_LDF(width, op | 0x20, type); \
3378 GEN_LDUF(width, op | 0x21, type); \
3379 GEN_LDUXF(width, op | 0x01, type); \
3380 GEN_LDXF(width, 0x17, op | 0x00, type)
3381
3382 /* lfd lfdu lfdux lfdx */
3383 GEN_LDFS(fd, 0x12, PPC_FLOAT);
3384 /* lfs lfsu lfsux lfsx */
3385 GEN_LDFS(fs, 0x10, PPC_FLOAT);
3386
3387 /*** Floating-point store ***/
3388 #define GEN_STF(width, opc, type) \
3389 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3390 { \
3391 if (unlikely(!ctx->fpu_enabled)) { \
3392 GEN_EXCP_NO_FP(ctx); \
3393 return; \
3394 } \
3395 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3396 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3397 op_ldst(st##width); \
3398 }
3399
3400 #define GEN_STUF(width, opc, type) \
3401 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3402 { \
3403 if (unlikely(!ctx->fpu_enabled)) { \
3404 GEN_EXCP_NO_FP(ctx); \
3405 return; \
3406 } \
3407 if (unlikely(rA(ctx->opcode) == 0)) { \
3408 GEN_EXCP_INVAL(ctx); \
3409 return; \
3410 } \
3411 gen_addr_imm_index(cpu_T[0], ctx, 0); \
3412 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3413 op_ldst(st##width); \
3414 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
3415 }
3416
3417 #define GEN_STUXF(width, opc, type) \
3418 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3419 { \
3420 if (unlikely(!ctx->fpu_enabled)) { \
3421 GEN_EXCP_NO_FP(ctx); \
3422 return; \
3423 } \
3424 if (unlikely(rA(ctx->opcode) == 0)) { \
3425 GEN_EXCP_INVAL(ctx); \
3426 return; \
3427 } \
3428 gen_addr_reg_index(cpu_T[0], ctx); \
3429 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3430 op_ldst(st##width); \
3431 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
3432 }
3433
3434 #define GEN_STXF(width, opc2, opc3, type) \
3435 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3436 { \
3437 if (unlikely(!ctx->fpu_enabled)) { \
3438 GEN_EXCP_NO_FP(ctx); \
3439 return; \
3440 } \
3441 gen_addr_reg_index(cpu_T[0], ctx); \
3442 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
3443 op_ldst(st##width); \
3444 }
3445
3446 #define GEN_STFS(width, op, type) \
3447 OP_ST_TABLE(width); \
3448 GEN_STF(width, op | 0x20, type); \
3449 GEN_STUF(width, op | 0x21, type); \
3450 GEN_STUXF(width, op | 0x01, type); \
3451 GEN_STXF(width, 0x17, op | 0x00, type)
3452
3453 /* stfd stfdu stfdux stfdx */
3454 GEN_STFS(fd, 0x16, PPC_FLOAT);
3455 /* stfs stfsu stfsux stfsx */
3456 GEN_STFS(fs, 0x14, PPC_FLOAT);
3457
3458 /* Optional: */
3459 /* stfiwx */
3460 OP_ST_TABLE(fiw);
3461 GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3462
3463 /*** Branch ***/
3464 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3465 target_ulong dest)
3466 {
3467 TranslationBlock *tb;
3468 tb = ctx->tb;
3469 #if defined(TARGET_PPC64)
3470 if (!ctx->sf_mode)
3471 dest = (uint32_t) dest;
3472 #endif
3473 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3474 likely(!ctx->singlestep_enabled)) {
3475 tcg_gen_goto_tb(n);
3476 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3477 tcg_gen_exit_tb((long)tb + n);
3478 } else {
3479 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3480 if (unlikely(ctx->singlestep_enabled)) {
3481 if ((ctx->singlestep_enabled &
3482 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3483 ctx->exception == POWERPC_EXCP_BRANCH) {
3484 target_ulong tmp = ctx->nip;
3485 ctx->nip = dest;
3486 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3487 ctx->nip = tmp;
3488 }
3489 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3490 gen_update_nip(ctx, dest);
3491 gen_op_debug();
3492 }
3493 }
3494 tcg_gen_exit_tb(0);
3495 }
3496 }
3497
3498 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3499 {
3500 #if defined(TARGET_PPC64)
3501 if (ctx->sf_mode == 0)
3502 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3503 else
3504 #endif
3505 tcg_gen_movi_tl(cpu_lr, nip);
3506 }
3507
3508 /* b ba bl bla */
3509 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3510 {
3511 target_ulong li, target;
3512
3513 ctx->exception = POWERPC_EXCP_BRANCH;
3514 /* sign extend LI */
3515 #if defined(TARGET_PPC64)
3516 if (ctx->sf_mode)
3517 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3518 else
3519 #endif
3520 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3521 if (likely(AA(ctx->opcode) == 0))
3522 target = ctx->nip + li - 4;
3523 else
3524 target = li;
3525 if (LK(ctx->opcode))
3526 gen_setlr(ctx, ctx->nip);
3527 gen_goto_tb(ctx, 0, target);
3528 }
3529
3530 #define BCOND_IM 0
3531 #define BCOND_LR 1
3532 #define BCOND_CTR 2
3533
3534 static always_inline void gen_bcond (DisasContext *ctx, int type)
3535 {
3536 uint32_t bo = BO(ctx->opcode);
3537 int l1 = gen_new_label();
3538 TCGv target;
3539
3540 ctx->exception = POWERPC_EXCP_BRANCH;
3541 if (type == BCOND_LR || type == BCOND_CTR) {
3542 target = tcg_temp_local_new(TCG_TYPE_TL);
3543 if (type == BCOND_CTR)
3544 tcg_gen_mov_tl(target, cpu_ctr);
3545 else
3546 tcg_gen_mov_tl(target, cpu_lr);
3547 }
3548 if (LK(ctx->opcode))
3549 gen_setlr(ctx, ctx->nip);
3550 l1 = gen_new_label();
3551 if ((bo & 0x4) == 0) {
3552 /* Decrement and test CTR */
3553 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3554 if (unlikely(type == BCOND_CTR)) {
3555 GEN_EXCP_INVAL(ctx);
3556 return;
3557 }
3558 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3559 #if defined(TARGET_PPC64)
3560 if (!ctx->sf_mode)
3561 tcg_gen_ext32u_tl(temp, cpu_ctr);
3562 else
3563 #endif
3564 tcg_gen_mov_tl(temp, cpu_ctr);
3565 if (bo & 0x2) {
3566 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3567 } else {
3568 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3569 }
3570 }
3571 if ((bo & 0x10) == 0) {
3572 /* Test CR */
3573 uint32_t bi = BI(ctx->opcode);
3574 uint32_t mask = 1 << (3 - (bi & 0x03));
3575 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3576
3577 if (bo & 0x8) {
3578 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3579 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3580 } else {
3581 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3582 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3583 }
3584 }
3585 if (type == BCOND_IM) {
3586
3587 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3588 if (likely(AA(ctx->opcode) == 0)) {
3589 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3590 } else {
3591 gen_goto_tb(ctx, 0, li);
3592 }
3593 gen_set_label(l1);
3594 gen_goto_tb(ctx, 1, ctx->nip);
3595 } else {
3596 #if defined(TARGET_PPC64)
3597 if (!(ctx->sf_mode))
3598 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3599 else
3600 #endif
3601 tcg_gen_andi_tl(cpu_nip, target, ~3);
3602 tcg_gen_exit_tb(0);
3603 gen_set_label(l1);
3604 #if defined(TARGET_PPC64)
3605 if (!(ctx->sf_mode))
3606 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3607 else
3608 #endif
3609 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3610 tcg_gen_exit_tb(0);
3611 }
3612 }
3613
3614 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3615 {
3616 gen_bcond(ctx, BCOND_IM);
3617 }
3618
3619 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3620 {
3621 gen_bcond(ctx, BCOND_CTR);
3622 }
3623
3624 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3625 {
3626 gen_bcond(ctx, BCOND_LR);
3627 }
3628
3629 /*** Condition register logical ***/
3630 #define GEN_CRLOGIC(name, tcg_op, opc) \
3631 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3632 { \
3633 uint8_t bitmask; \
3634 int sh; \
3635 TCGv t0, t1; \
3636 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3637 t0 = tcg_temp_new(TCG_TYPE_I32); \
3638 if (sh > 0) \
3639 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3640 else if (sh < 0) \
3641 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3642 else \
3643 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3644 t1 = tcg_temp_new(TCG_TYPE_I32); \
3645 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3646 if (sh > 0) \
3647 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3648 else if (sh < 0) \
3649 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3650 else \
3651 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3652 tcg_op(t0, t0, t1); \
3653 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3654 tcg_gen_andi_i32(t0, t0, bitmask); \
3655 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3656 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3657 tcg_temp_free(t0); \
3658 tcg_temp_free(t1); \
3659 }
3660
3661 /* crand */
3662 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3663 /* crandc */
3664 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3665 /* creqv */
3666 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3667 /* crnand */
3668 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3669 /* crnor */
3670 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3671 /* cror */
3672 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3673 /* crorc */
3674 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3675 /* crxor */
3676 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3677 /* mcrf */
3678 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3679 {
3680 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3681 }
3682
3683 /*** System linkage ***/
3684 /* rfi (supervisor only) */
3685 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3686 {
3687 #if defined(CONFIG_USER_ONLY)
3688 GEN_EXCP_PRIVOPC(ctx);
3689 #else
3690 /* Restore CPU state */
3691 if (unlikely(!ctx->supervisor)) {
3692 GEN_EXCP_PRIVOPC(ctx);
3693 return;
3694 }
3695 gen_op_rfi();
3696 GEN_SYNC(ctx);
3697 #endif
3698 }
3699
3700 #if defined(TARGET_PPC64)
3701 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3702 {
3703 #if defined(CONFIG_USER_ONLY)
3704 GEN_EXCP_PRIVOPC(ctx);
3705 #else
3706 /* Restore CPU state */
3707 if (unlikely(!ctx->supervisor)) {
3708 GEN_EXCP_PRIVOPC(ctx);
3709 return;
3710 }
3711 gen_op_rfid();
3712 GEN_SYNC(ctx);
3713 #endif
3714 }
3715
3716 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3717 {
3718 #if defined(CONFIG_USER_ONLY)
3719 GEN_EXCP_PRIVOPC(ctx);
3720 #else
3721 /* Restore CPU state */
3722 if (unlikely(ctx->supervisor <= 1)) {
3723 GEN_EXCP_PRIVOPC(ctx);
3724 return;
3725 }
3726 gen_op_hrfid();
3727 GEN_SYNC(ctx);
3728 #endif
3729 }
3730 #endif
3731
3732 /* sc */
3733 #if defined(CONFIG_USER_ONLY)
3734 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3735 #else
3736 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3737 #endif
3738 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3739 {
3740 uint32_t lev;
3741
3742 lev = (ctx->opcode >> 5) & 0x7F;
3743 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3744 }
3745
3746 /*** Trap ***/
3747 /* tw */
3748 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3749 {
3750 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3751 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3752 /* Update the nip since this might generate a trap exception */
3753 gen_update_nip(ctx, ctx->nip);
3754 gen_op_tw(TO(ctx->opcode));
3755 }
3756
3757 /* twi */
3758 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3759 {
3760 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3761 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3762 /* Update the nip since this might generate a trap exception */
3763 gen_update_nip(ctx, ctx->nip);
3764 gen_op_tw(TO(ctx->opcode));
3765 }
3766
3767 #if defined(TARGET_PPC64)
3768 /* td */
3769 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3770 {
3771 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3772 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3773 /* Update the nip since this might generate a trap exception */
3774 gen_update_nip(ctx, ctx->nip);
3775 gen_op_td(TO(ctx->opcode));
3776 }
3777
3778 /* tdi */
3779 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3780 {
3781 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3782 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3783 /* Update the nip since this might generate a trap exception */
3784 gen_update_nip(ctx, ctx->nip);
3785 gen_op_td(TO(ctx->opcode));
3786 }
3787 #endif
3788
3789 /*** Processor control ***/
3790 /* mcrxr */
3791 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3792 {
3793 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3794 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3795 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3796 }
3797
3798 /* mfcr */
3799 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3800 {
3801 uint32_t crm, crn;
3802
3803 if (likely(ctx->opcode & 0x00100000)) {
3804 crm = CRM(ctx->opcode);
3805 if (likely((crm ^ (crm - 1)) == 0)) {
3806 crn = ffs(crm);
3807 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3808 }
3809 } else {
3810 tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
3811 }
3812 }
3813
3814 /* mfmsr */
3815 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3816 {
3817 #if defined(CONFIG_USER_ONLY)
3818 GEN_EXCP_PRIVREG(ctx);
3819 #else
3820 if (unlikely(!ctx->supervisor)) {
3821 GEN_EXCP_PRIVREG(ctx);
3822 return;
3823 }
3824 gen_op_load_msr();
3825 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3826 #endif
3827 }
3828
3829 #if 1
3830 #define SPR_NOACCESS ((void *)(-1UL))
3831 #else
3832 static void spr_noaccess (void *opaque, int sprn)
3833 {
3834 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3835 printf("ERROR: try to access SPR %d !\n", sprn);
3836 }
3837 #define SPR_NOACCESS (&spr_noaccess)
3838 #endif
3839
3840 /* mfspr */
3841 static always_inline void gen_op_mfspr (DisasContext *ctx)
3842 {
3843 void (*read_cb)(void *opaque, int sprn);
3844 uint32_t sprn = SPR(ctx->opcode);
3845
3846 #if !defined(CONFIG_USER_ONLY)
3847 if (ctx->supervisor == 2)
3848 read_cb = ctx->spr_cb[sprn].hea_read;
3849 else if (ctx->supervisor)
3850 read_cb = ctx->spr_cb[sprn].oea_read;
3851 else
3852 #endif
3853 read_cb = ctx->spr_cb[sprn].uea_read;
3854 if (likely(read_cb != NULL)) {
3855 if (likely(read_cb != SPR_NOACCESS)) {
3856 (*read_cb)(ctx, sprn);
3857 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3858 } else {
3859 /* Privilege exception */
3860 /* This is a hack to avoid warnings when running Linux:
3861 * this OS breaks the PowerPC virtualisation model,
3862 * allowing userland application to read the PVR
3863 */
3864 if (sprn != SPR_PVR) {
3865 if (loglevel != 0) {
3866 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3867 ADDRX "\n", sprn, sprn, ctx->nip);
3868 }
3869 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3870 sprn, sprn, ctx->nip);
3871 }
3872 GEN_EXCP_PRIVREG(ctx);
3873 }
3874 } else {
3875 /* Not defined */
3876 if (loglevel != 0) {
3877 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3878 ADDRX "\n", sprn, sprn, ctx->nip);
3879 }
3880 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3881 sprn, sprn, ctx->nip);
3882 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3883 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3884 }
3885 }
3886
3887 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3888 {
3889 gen_op_mfspr(ctx);
3890 }
3891
3892 /* mftb */
3893 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3894 {
3895 gen_op_mfspr(ctx);
3896 }
3897
3898 /* mtcrf */
3899 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3900 {
3901 uint32_t crm, crn;
3902
3903 crm = CRM(ctx->opcode);
3904 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3905 crn = ffs(crm);
3906 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3907 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3908 } else {
3909 TCGv t0 = tcg_const_tl(crm);
3910 tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], t0);
3911 tcg_temp_free(t0);
3912 }
3913 }
3914
3915 /* mtmsr */
3916 #if defined(TARGET_PPC64)
3917 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3918 {
3919 #if defined(CONFIG_USER_ONLY)
3920 GEN_EXCP_PRIVREG(ctx);
3921 #else
3922 if (unlikely(!ctx->supervisor)) {
3923 GEN_EXCP_PRIVREG(ctx);
3924 return;
3925 }
3926 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3927 if (ctx->opcode & 0x00010000) {
3928 /* Special form that does not need any synchronisation */
3929 gen_op_update_riee();
3930 } else {
3931 /* XXX: we need to update nip before the store
3932 * if we enter power saving mode, we will exit the loop
3933 * directly from ppc_store_msr
3934 */
3935 gen_update_nip(ctx, ctx->nip);
3936 gen_op_store_msr();
3937 /* Must stop the translation as machine state (may have) changed */
3938 /* Note that mtmsr is not always defined as context-synchronizing */
3939 ctx->exception = POWERPC_EXCP_STOP;
3940 }
3941 #endif
3942 }
3943 #endif
3944
3945 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3946 {
3947 #if defined(CONFIG_USER_ONLY)
3948 GEN_EXCP_PRIVREG(ctx);
3949 #else
3950 if (unlikely(!ctx->supervisor)) {
3951 GEN_EXCP_PRIVREG(ctx);
3952 return;
3953 }
3954 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3955 if (ctx->opcode & 0x00010000) {
3956 /* Special form that does not need any synchronisation */
3957 gen_op_update_riee();
3958 } else {
3959 /* XXX: we need to update nip before the store
3960 * if we enter power saving mode, we will exit the loop
3961 * directly from ppc_store_msr
3962 */
3963 gen_update_nip(ctx, ctx->nip);
3964 #if defined(TARGET_PPC64)
3965 if (!ctx->sf_mode)
3966 gen_op_store_msr_32();
3967 else
3968 #endif
3969 gen_op_store_msr();
3970 /* Must stop the translation as machine state (may have) changed */
3971 /* Note that mtmsrd is not always defined as context-synchronizing */
3972 ctx->exception = POWERPC_EXCP_STOP;
3973 }
3974 #endif
3975 }
3976
3977 /* mtspr */
3978 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3979 {
3980 void (*write_cb)(void *opaque, int sprn);
3981 uint32_t sprn = SPR(ctx->opcode);
3982
3983 #if !defined(CONFIG_USER_ONLY)
3984 if (ctx->supervisor == 2)
3985 write_cb = ctx->spr_cb[sprn].hea_write;
3986 else if (ctx->supervisor)
3987 write_cb = ctx->spr_cb[sprn].oea_write;
3988 else
3989 #endif
3990 write_cb = ctx->spr_cb[sprn].uea_write;
3991 if (likely(write_cb != NULL)) {
3992 if (likely(write_cb != SPR_NOACCESS)) {
3993 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3994 (*write_cb)(ctx, sprn);
3995 } else {
3996 /* Privilege exception */
3997 if (loglevel != 0) {
3998 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3999 ADDRX "\n", sprn, sprn, ctx->nip);
4000 }
4001 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4002 sprn, sprn, ctx->nip);
4003 GEN_EXCP_PRIVREG(ctx);
4004 }
4005 } else {
4006 /* Not defined */
4007 if (loglevel != 0) {
4008 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4009 ADDRX "\n", sprn, sprn, ctx->nip);
4010 }
4011 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4012 sprn, sprn, ctx->nip);
4013 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4014 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
4015 }
4016 }
4017
4018 /*** Cache management ***/
4019 /* dcbf */
4020 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4021 {
4022 /* XXX: specification says this is treated as a load by the MMU */
4023 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
4024 gen_addr_reg_index(t0, ctx);
4025 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4026 tcg_temp_free(t0);
4027 }
4028
4029 /* dcbi (Supervisor only) */
4030 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
4031 {
4032 #if defined(CONFIG_USER_ONLY)
4033 GEN_EXCP_PRIVOPC(ctx);
4034 #else
4035 TCGv EA, val;
4036 if (unlikely(!ctx->supervisor)) {
4037 GEN_EXCP_PRIVOPC(ctx);
4038 return;
4039 }
4040 EA = tcg_temp_new(TCG_TYPE_TL);
4041 gen_addr_reg_index(EA, ctx);
4042 val = tcg_temp_new(TCG_TYPE_TL);
4043 /* XXX: specification says this should be treated as a store by the MMU */
4044 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4045 gen_qemu_st8(val, EA, ctx->mem_idx);
4046 tcg_temp_free(val);
4047 tcg_temp_free(EA);
4048 #endif
4049 }
4050
4051 /* dcdst */
4052 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4053 {
4054 /* XXX: specification say this is treated as a load by the MMU */
4055 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
4056 gen_addr_reg_index(t0, ctx);
4057 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4058 tcg_temp_free(t0);
4059 }
4060
4061 /* dcbt */
4062 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
4063 {
4064 /* interpreted as no-op */
4065 /* XXX: specification say this is treated as a load by the MMU
4066 * but does not generate any exception
4067 */
4068 }
4069
4070 /* dcbtst */
4071 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
4072 {
4073 /* interpreted as no-op */
4074 /* XXX: specification say this is treated as a load by the MMU
4075 * but does not generate any exception
4076 */
4077 }
4078
4079 /* dcbz */
4080 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
4081 static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
4082 /* 32 bytes cache line size */
4083 {
4084 #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
4085 #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
4086 #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
4087 #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
4088 #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
4089 #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
4090 #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
4091 #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
4092 GEN_MEM_FUNCS(dcbz_l32),
4093 },
4094 /* 64 bytes cache line size */
4095 {
4096 #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
4097 #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
4098 #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
4099 #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
4100 #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
4101 #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
4102 #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
4103 #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
4104 GEN_MEM_FUNCS(dcbz_l64),
4105 },
4106 /* 128 bytes cache line size */
4107 {
4108 #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
4109 #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
4110 #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
4111 #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
4112 #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
4113 #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
4114 #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
4115 #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
4116 GEN_MEM_FUNCS(dcbz_l128),
4117 },
4118 /* tunable cache line size */
4119 {
4120 #define gen_op_dcbz_le_raw gen_op_dcbz_raw
4121 #define gen_op_dcbz_le_user gen_op_dcbz_user
4122 #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
4123 #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
4124 #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
4125 #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
4126 #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
4127 #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
4128 GEN_MEM_FUNCS(dcbz),
4129 },
4130 };
4131
4132 static always_inline void handler_dcbz (DisasContext *ctx,
4133 int dcache_line_size)
4134 {
4135 int n;
4136
4137 switch (dcache_line_size) {
4138 case 32:
4139 n = 0;
4140 break;
4141 case 64:
4142 n = 1;
4143 break;
4144 case 128:
4145 n = 2;
4146 break;
4147 default:
4148 n = 3;
4149 break;
4150 }
4151 op_dcbz(n);
4152 }
4153
4154 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4155 {
4156 gen_addr_reg_index(cpu_T[0], ctx);
4157 handler_dcbz(ctx, ctx->dcache_line_size);
4158 gen_op_check_reservation();
4159 }
4160
4161 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4162 {
4163 gen_addr_reg_index(cpu_T[0], ctx);
4164 if (ctx->opcode & 0x00200000)
4165 handler_dcbz(ctx, ctx->dcache_line_size);
4166 else
4167 handler_dcbz(ctx, -1);
4168 gen_op_check_reservation();
4169 }
4170
4171 /* icbi */
4172 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
4173 #define gen_op_icbi_le_raw gen_op_icbi_raw
4174 #define gen_op_icbi_le_user gen_op_icbi_user
4175 #define gen_op_icbi_le_kernel gen_op_icbi_kernel
4176 #define gen_op_icbi_le_hypv gen_op_icbi_hypv
4177 #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4178 #define gen_op_icbi_le_64_user gen_op_icbi_64_user
4179 #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4180 #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4181 static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4182 GEN_MEM_FUNCS(icbi),
4183 };
4184
4185 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
4186 {
4187 /* NIP cannot be restored if the memory exception comes from an helper */
4188 gen_update_nip(ctx, ctx->nip - 4);
4189 gen_addr_reg_index(cpu_T[0], ctx);
4190 op_icbi();
4191 }
4192
4193 /* Optional: */
4194 /* dcba */
4195 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
4196 {
4197 /* interpreted as no-op */
4198 /* XXX: specification say this is treated as a store by the MMU
4199 * but does not generate any exception
4200 */
4201 }
4202
4203 /*** Segment register manipulation ***/
4204 /* Supervisor only: */
4205 /* mfsr */
4206 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4207 {
4208 #if defined(CONFIG_USER_ONLY)
4209 GEN_EXCP_PRIVREG(ctx);
4210 #else
4211 if (unlikely(!ctx->supervisor)) {
4212 GEN_EXCP_PRIVREG(ctx);
4213 return;
4214 }
4215 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4216 gen_op_load_sr();
4217 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4218 #endif
4219 }
4220
4221 /* mfsrin */
4222 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4223 {
4224 #if defined(CONFIG_USER_ONLY)
4225 GEN_EXCP_PRIVREG(ctx);
4226 #else
4227 if (unlikely(!ctx->supervisor)) {
4228 GEN_EXCP_PRIVREG(ctx);
4229 return;
4230 }
4231 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4232 gen_op_srli_T1(28);
4233 gen_op_load_sr();
4234 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4235 #endif
4236 }
4237
4238 /* mtsr */
4239 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4240 {
4241 #if defined(CONFIG_USER_ONLY)
4242 GEN_EXCP_PRIVREG(ctx);
4243 #else
4244 if (unlikely(!ctx->supervisor)) {
4245 GEN_EXCP_PRIVREG(ctx);
4246 return;
4247 }
4248 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4249 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4250 gen_op_store_sr();
4251 #endif
4252 }
4253
4254 /* mtsrin */
4255 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4256 {
4257 #if defined(CONFIG_USER_ONLY)
4258 GEN_EXCP_PRIVREG(ctx);
4259 #else
4260 if (unlikely(!ctx->supervisor)) {
4261 GEN_EXCP_PRIVREG(ctx);
4262 return;
4263 }
4264 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4265 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4266 gen_op_srli_T1(28);
4267 gen_op_store_sr();
4268 #endif
4269 }
4270
4271 #if defined(TARGET_PPC64)
4272 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4273 /* mfsr */
4274 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4275 {
4276 #if defined(CONFIG_USER_ONLY)
4277 GEN_EXCP_PRIVREG(ctx);
4278 #else
4279 if (unlikely(!ctx->supervisor)) {
4280 GEN_EXCP_PRIVREG(ctx);
4281 return;
4282 }
4283 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4284 gen_op_load_slb();
4285 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4286 #endif
4287 }
4288
4289 /* mfsrin */
4290 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4291 PPC_SEGMENT_64B)
4292 {
4293 #if defined(CONFIG_USER_ONLY)
4294 GEN_EXCP_PRIVREG(ctx);
4295 #else
4296 if (unlikely(!ctx->supervisor)) {
4297 GEN_EXCP_PRIVREG(ctx);
4298 return;
4299 }
4300 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4301 gen_op_srli_T1(28);
4302 gen_op_load_slb();
4303 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4304 #endif
4305 }
4306
4307 /* mtsr */
4308 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4309 {
4310 #if defined(CONFIG_USER_ONLY)
4311 GEN_EXCP_PRIVREG(ctx);
4312 #else
4313 if (unlikely(!ctx->supervisor)) {
4314 GEN_EXCP_PRIVREG(ctx);
4315 return;
4316 }
4317 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4318 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
4319 gen_op_store_slb();
4320 #endif
4321 }
4322
4323 /* mtsrin */
4324 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4325 PPC_SEGMENT_64B)
4326 {
4327 #if defined(CONFIG_USER_ONLY)
4328 GEN_EXCP_PRIVREG(ctx);
4329 #else
4330 if (unlikely(!ctx->supervisor)) {
4331 GEN_EXCP_PRIVREG(ctx);
4332 return;
4333 }
4334 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4335 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4336 gen_op_srli_T1(28);
4337 gen_op_store_slb();
4338 #endif
4339 }
4340 #endif /* defined(TARGET_PPC64) */
4341
4342 /*** Lookaside buffer management ***/
4343 /* Optional & supervisor only: */
4344 /* tlbia */
4345 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4346 {
4347 #if defined(CONFIG_USER_ONLY)
4348 GEN_EXCP_PRIVOPC(ctx);
4349 #else
4350 if (unlikely(!ctx->supervisor)) {
4351 GEN_EXCP_PRIVOPC(ctx);
4352 return;
4353 }
4354 gen_op_tlbia();
4355 #endif
4356 }
4357
4358 /* tlbie */
4359 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4360 {
4361 #if defined(CONFIG_USER_ONLY)
4362 GEN_EXCP_PRIVOPC(ctx);
4363 #else
4364 if (unlikely(!ctx->supervisor)) {
4365 GEN_EXCP_PRIVOPC(ctx);
4366 return;
4367 }
4368 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4369 #if defined(TARGET_PPC64)
4370 if (ctx->sf_mode)
4371 gen_op_tlbie_64();
4372 else
4373 #endif
4374 gen_op_tlbie();
4375 #endif
4376 }
4377
4378 /* tlbsync */
4379 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4380 {
4381 #if defined(CONFIG_USER_ONLY)
4382 GEN_EXCP_PRIVOPC(ctx);
4383 #else
4384 if (unlikely(!ctx->supervisor)) {
4385 GEN_EXCP_PRIVOPC(ctx);
4386 return;
4387 }
4388 /* This has no effect: it should ensure that all previous
4389 * tlbie have completed
4390 */
4391 GEN_STOP(ctx);
4392 #endif
4393 }
4394
4395 #if defined(TARGET_PPC64)
4396 /* slbia */
4397 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4398 {
4399 #if defined(CONFIG_USER_ONLY)
4400 GEN_EXCP_PRIVOPC(ctx);
4401 #else
4402 if (unlikely(!ctx->supervisor)) {
4403 GEN_EXCP_PRIVOPC(ctx);
4404 return;
4405 }
4406 gen_op_slbia();
4407 #endif
4408 }
4409
4410 /* slbie */
4411 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4412 {
4413 #if defined(CONFIG_USER_ONLY)
4414 GEN_EXCP_PRIVOPC(ctx);
4415 #else
4416 if (unlikely(!ctx->supervisor)) {
4417 GEN_EXCP_PRIVOPC(ctx);
4418 return;
4419 }
4420 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4421 gen_op_slbie();
4422 #endif
4423 }
4424 #endif
4425
4426 /*** External control ***/
4427 /* Optional: */
4428 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4429 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4430 static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4431 GEN_MEM_FUNCS(eciwx),
4432 };
4433 static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4434 GEN_MEM_FUNCS(ecowx),
4435 };
4436
4437 /* eciwx */
4438 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4439 {
4440 /* Should check EAR[E] & alignment ! */
4441 gen_addr_reg_index(cpu_T[0], ctx);
4442 op_eciwx();
4443 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4444 }
4445
4446 /* ecowx */
4447 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4448 {
4449 /* Should check EAR[E] & alignment ! */
4450 gen_addr_reg_index(cpu_T[0], ctx);
4451 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4452 op_ecowx();
4453 }
4454
4455 /* PowerPC 601 specific instructions */
4456 /* abs - abs. */
4457 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4458 {
4459 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4460 gen_op_POWER_abs();
4461 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4462 if (unlikely(Rc(ctx->opcode) != 0))
4463 gen_set_Rc0(ctx, cpu_T[0]);
4464 }
4465
4466 /* abso - abso. */
4467 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4468 {
4469 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4470 gen_op_POWER_abso();
4471 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4472 if (unlikely(Rc(ctx->opcode) != 0))
4473 gen_set_Rc0(ctx, cpu_T[0]);
4474 }
4475
4476 /* clcs */
4477 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4478 {
4479 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4480 gen_op_POWER_clcs();
4481 /* Rc=1 sets CR0 to an undefined state */
4482 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4483 }
4484
4485 /* div - div. */
4486 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4487 {
4488 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4489 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4490 gen_op_POWER_div();
4491 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4492 if (unlikely(Rc(ctx->opcode) != 0))
4493 gen_set_Rc0(ctx, cpu_T[0]);
4494 }
4495
4496 /* divo - divo. */
4497 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4498 {
4499 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4500 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4501 gen_op_POWER_divo();
4502 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4503 if (unlikely(Rc(ctx->opcode) != 0))
4504 gen_set_Rc0(ctx, cpu_T[0]);
4505 }
4506
4507 /* divs - divs. */
4508 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4509 {
4510 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4511 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4512 gen_op_POWER_divs();
4513 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4514 if (unlikely(Rc(ctx->opcode) != 0))
4515 gen_set_Rc0(ctx, cpu_T[0]);
4516 }
4517
4518 /* divso - divso. */
4519 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4520 {
4521 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4522 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4523 gen_op_POWER_divso();
4524 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4525 if (unlikely(Rc(ctx->opcode) != 0))
4526 gen_set_Rc0(ctx, cpu_T[0]);
4527 }
4528
4529 /* doz - doz. */
4530 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4531 {
4532 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4533 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4534 gen_op_POWER_doz();
4535 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4536 if (unlikely(Rc(ctx->opcode) != 0))
4537 gen_set_Rc0(ctx, cpu_T[0]);
4538 }
4539
4540 /* dozo - dozo. */
4541 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4542 {
4543 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4544 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4545 gen_op_POWER_dozo();
4546 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4547 if (unlikely(Rc(ctx->opcode) != 0))
4548 gen_set_Rc0(ctx, cpu_T[0]);
4549 }
4550
4551 /* dozi */
4552 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4553 {
4554 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4555 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
4556 gen_op_POWER_doz();
4557 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4558 }
4559
4560 /* As lscbx load from memory byte after byte, it's always endian safe.
4561 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4562 */
4563 #define op_POWER_lscbx(start, ra, rb) \
4564 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4565 #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4566 #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4567 #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4568 #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4569 #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4570 #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4571 #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4572 #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4573 #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4574 #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4575 #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4576 #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4577 static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4578 GEN_MEM_FUNCS(POWER_lscbx),
4579 };
4580
4581 /* lscbx - lscbx. */
4582 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4583 {
4584 int ra = rA(ctx->opcode);
4585 int rb = rB(ctx->opcode);
4586
4587 gen_addr_reg_index(cpu_T[0], ctx);
4588 if (ra == 0) {
4589 ra = rb;
4590 }
4591 /* NIP cannot be restored if the memory exception comes from an helper */
4592 gen_update_nip(ctx, ctx->nip - 4);
4593 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4594 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4595 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
4596 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4597 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4598 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
4599 if (unlikely(Rc(ctx->opcode) != 0))
4600 gen_set_Rc0(ctx, cpu_T[0]);
4601 }
4602
4603 /* maskg - maskg. */
4604 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4605 {
4606 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4607 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4608 gen_op_POWER_maskg();
4609 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4610 if (unlikely(Rc(ctx->opcode) != 0))
4611 gen_set_Rc0(ctx, cpu_T[0]);
4612 }
4613
4614 /* maskir - maskir. */
4615 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4616 {
4617 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4618 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4619 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4620 gen_op_POWER_maskir();
4621 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4622 if (unlikely(Rc(ctx->opcode) != 0))
4623 gen_set_Rc0(ctx, cpu_T[0]);
4624 }
4625
4626 /* mul - mul. */
4627 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4628 {
4629 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4630 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4631 gen_op_POWER_mul();
4632 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4633 if (unlikely(Rc(ctx->opcode) != 0))
4634 gen_set_Rc0(ctx, cpu_T[0]);
4635 }
4636
4637 /* mulo - mulo. */
4638 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4639 {
4640 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4641 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4642 gen_op_POWER_mulo();
4643 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4644 if (unlikely(Rc(ctx->opcode) != 0))
4645 gen_set_Rc0(ctx, cpu_T[0]);
4646 }
4647
4648 /* nabs - nabs. */
4649 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4650 {
4651 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4652 gen_op_POWER_nabs();
4653 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4654 if (unlikely(Rc(ctx->opcode) != 0))
4655 gen_set_Rc0(ctx, cpu_T[0]);
4656 }
4657
4658 /* nabso - nabso. */
4659 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4660 {
4661 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4662 gen_op_POWER_nabso();
4663 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4664 if (unlikely(Rc(ctx->opcode) != 0))
4665 gen_set_Rc0(ctx, cpu_T[0]);
4666 }
4667
4668 /* rlmi - rlmi. */
4669 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4670 {
4671 uint32_t mb, me;
4672
4673 mb = MB(ctx->opcode);
4674 me = ME(ctx->opcode);
4675 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4676 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4677 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4678 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4679 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4680 if (unlikely(Rc(ctx->opcode) != 0))
4681 gen_set_Rc0(ctx, cpu_T[0]);
4682 }
4683
4684 /* rrib - rrib. */
4685 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4686 {
4687 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4688 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4689 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4690 gen_op_POWER_rrib();
4691 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4692 if (unlikely(Rc(ctx->opcode) != 0))
4693 gen_set_Rc0(ctx, cpu_T[0]);
4694 }
4695
4696 /* sle - sle. */
4697 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4698 {
4699 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4700 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4701 gen_op_POWER_sle();
4702 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4703 if (unlikely(Rc(ctx->opcode) != 0))
4704 gen_set_Rc0(ctx, cpu_T[0]);
4705 }
4706
4707 /* sleq - sleq. */
4708 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4709 {
4710 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4711 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4712 gen_op_POWER_sleq();
4713 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4714 if (unlikely(Rc(ctx->opcode) != 0))
4715 gen_set_Rc0(ctx, cpu_T[0]);
4716 }
4717
4718 /* sliq - sliq. */
4719 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4720 {
4721 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4722 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4723 gen_op_POWER_sle();
4724 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4725 if (unlikely(Rc(ctx->opcode) != 0))
4726 gen_set_Rc0(ctx, cpu_T[0]);
4727 }
4728
4729 /* slliq - slliq. */
4730 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4731 {
4732 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4733 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4734 gen_op_POWER_sleq();
4735 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4736 if (unlikely(Rc(ctx->opcode) != 0))
4737 gen_set_Rc0(ctx, cpu_T[0]);
4738 }
4739
4740 /* sllq - sllq. */
4741 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4742 {
4743 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4744 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4745 gen_op_POWER_sllq();
4746 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4747 if (unlikely(Rc(ctx->opcode) != 0))
4748 gen_set_Rc0(ctx, cpu_T[0]);
4749 }
4750
4751 /* slq - slq. */
4752 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4753 {
4754 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4755 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4756 gen_op_POWER_slq();
4757 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4758 if (unlikely(Rc(ctx->opcode) != 0))
4759 gen_set_Rc0(ctx, cpu_T[0]);
4760 }
4761
4762 /* sraiq - sraiq. */
4763 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4764 {
4765 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4766 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4767 gen_op_POWER_sraq();
4768 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4769 if (unlikely(Rc(ctx->opcode) != 0))
4770 gen_set_Rc0(ctx, cpu_T[0]);
4771 }
4772
4773 /* sraq - sraq. */
4774 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4775 {
4776 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4777 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4778 gen_op_POWER_sraq();
4779 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4780 if (unlikely(Rc(ctx->opcode) != 0))
4781 gen_set_Rc0(ctx, cpu_T[0]);
4782 }
4783
4784 /* sre - sre. */
4785 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4786 {
4787 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4788 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4789 gen_op_POWER_sre();
4790 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4791 if (unlikely(Rc(ctx->opcode) != 0))
4792 gen_set_Rc0(ctx, cpu_T[0]);
4793 }
4794
4795 /* srea - srea. */
4796 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4797 {
4798 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4799 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4800 gen_op_POWER_srea();
4801 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4802 if (unlikely(Rc(ctx->opcode) != 0))
4803 gen_set_Rc0(ctx, cpu_T[0]);
4804 }
4805
4806 /* sreq */
4807 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4808 {
4809 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4810 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4811 gen_op_POWER_sreq();
4812 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4813 if (unlikely(Rc(ctx->opcode) != 0))
4814 gen_set_Rc0(ctx, cpu_T[0]);
4815 }
4816
4817 /* sriq */
4818 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4819 {
4820 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4821 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4822 gen_op_POWER_srq();
4823 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4824 if (unlikely(Rc(ctx->opcode) != 0))
4825 gen_set_Rc0(ctx, cpu_T[0]);
4826 }
4827
4828 /* srliq */
4829 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4830 {
4831 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4832 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4833 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4834 gen_op_POWER_srlq();
4835 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4836 if (unlikely(Rc(ctx->opcode) != 0))
4837 gen_set_Rc0(ctx, cpu_T[0]);
4838 }
4839
4840 /* srlq */
4841 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4842 {
4843 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4844 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4845 gen_op_POWER_srlq();
4846 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4847 if (unlikely(Rc(ctx->opcode) != 0))
4848 gen_set_Rc0(ctx, cpu_T[0]);
4849 }
4850
4851 /* srq */
4852 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4853 {
4854 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4855 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4856 gen_op_POWER_srq();
4857 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4858 if (unlikely(Rc(ctx->opcode) != 0))
4859 gen_set_Rc0(ctx, cpu_T[0]);
4860 }
4861
4862 /* PowerPC 602 specific instructions */
4863 /* dsa */
4864 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4865 {
4866 /* XXX: TODO */
4867 GEN_EXCP_INVAL(ctx);
4868 }
4869
4870 /* esa */
4871 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4872 {
4873 /* XXX: TODO */
4874 GEN_EXCP_INVAL(ctx);
4875 }
4876
4877 /* mfrom */
4878 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4879 {
4880 #if defined(CONFIG_USER_ONLY)
4881 GEN_EXCP_PRIVOPC(ctx);
4882 #else
4883 if (unlikely(!ctx->supervisor)) {
4884 GEN_EXCP_PRIVOPC(ctx);
4885 return;
4886 }
4887 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4888 gen_op_602_mfrom();
4889 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4890 #endif
4891 }
4892
4893 /* 602 - 603 - G2 TLB management */
4894 /* tlbld */
4895 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4896 {
4897 #if defined(CONFIG_USER_ONLY)
4898 GEN_EXCP_PRIVOPC(ctx);
4899 #else
4900 if (unlikely(!ctx->supervisor)) {
4901 GEN_EXCP_PRIVOPC(ctx);
4902 return;
4903 }
4904 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4905 gen_op_6xx_tlbld();
4906 #endif
4907 }
4908
4909 /* tlbli */
4910 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4911 {
4912 #if defined(CONFIG_USER_ONLY)
4913 GEN_EXCP_PRIVOPC(ctx);
4914 #else
4915 if (unlikely(!ctx->supervisor)) {
4916 GEN_EXCP_PRIVOPC(ctx);
4917 return;
4918 }
4919 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4920 gen_op_6xx_tlbli();
4921 #endif
4922 }
4923
4924 /* 74xx TLB management */
4925 /* tlbld */
4926 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4927 {
4928 #if defined(CONFIG_USER_ONLY)
4929 GEN_EXCP_PRIVOPC(ctx);
4930 #else
4931 if (unlikely(!ctx->supervisor)) {
4932 GEN_EXCP_PRIVOPC(ctx);
4933 return;
4934 }
4935 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4936 gen_op_74xx_tlbld();
4937 #endif
4938 }
4939
4940 /* tlbli */
4941 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4942 {
4943 #if defined(CONFIG_USER_ONLY)
4944 GEN_EXCP_PRIVOPC(ctx);
4945 #else
4946 if (unlikely(!ctx->supervisor)) {
4947 GEN_EXCP_PRIVOPC(ctx);
4948 return;
4949 }
4950 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4951 gen_op_74xx_tlbli();
4952 #endif
4953 }
4954
4955 /* POWER instructions not in PowerPC 601 */
4956 /* clf */
4957 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4958 {
4959 /* Cache line flush: implemented as no-op */
4960 }
4961
4962 /* cli */
4963 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4964 {
4965 /* Cache line invalidate: privileged and treated as no-op */
4966 #if defined(CONFIG_USER_ONLY)
4967 GEN_EXCP_PRIVOPC(ctx);
4968 #else
4969 if (unlikely(!ctx->supervisor)) {
4970 GEN_EXCP_PRIVOPC(ctx);
4971 return;
4972 }
4973 #endif
4974 }
4975
4976 /* dclst */
4977 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4978 {
4979 /* Data cache line store: treated as no-op */
4980 }
4981
4982 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4983 {
4984 #if defined(CONFIG_USER_ONLY)
4985 GEN_EXCP_PRIVOPC(ctx);
4986 #else
4987 if (unlikely(!ctx->supervisor)) {
4988 GEN_EXCP_PRIVOPC(ctx);
4989 return;
4990 }
4991 int ra = rA(ctx->opcode);
4992 int rd = rD(ctx->opcode);
4993
4994 gen_addr_reg_index(cpu_T[0], ctx);
4995 gen_op_POWER_mfsri();
4996 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
4997 if (ra != 0 && ra != rd)
4998 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
4999 #endif
5000 }
5001
5002 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5003 {
5004 #if defined(CONFIG_USER_ONLY)
5005 GEN_EXCP_PRIVOPC(ctx);
5006 #else
5007 if (unlikely(!ctx->supervisor)) {
5008 GEN_EXCP_PRIVOPC(ctx);
5009 return;
5010 }
5011 gen_addr_reg_index(cpu_T[0], ctx);
5012 gen_op_POWER_rac();
5013 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5014 #endif
5015 }
5016
5017 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5018 {
5019 #if defined(CONFIG_USER_ONLY)
5020 GEN_EXCP_PRIVOPC(ctx);
5021 #else
5022 if (unlikely(!ctx->supervisor)) {
5023 GEN_EXCP_PRIVOPC(ctx);
5024 return;
5025 }
5026 gen_op_POWER_rfsvc();
5027 GEN_SYNC(ctx);
5028 #endif
5029 }
5030
5031 /* svc is not implemented for now */
5032
5033 /* POWER2 specific instructions */
5034 /* Quad manipulation (load/store two floats at a time) */
5035 /* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
5036 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
5037 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
5038 #define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
5039 #define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
5040 #define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
5041 #define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
5042 #define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
5043 #define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
5044 #define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
5045 #define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
5046 #define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
5047 #define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
5048 #define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
5049 #define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
5050 #define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
5051 #define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
5052 #define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
5053 #define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
5054 static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
5055 GEN_MEM_FUNCS(POWER2_lfq),
5056 };
5057 static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
5058 GEN_MEM_FUNCS(POWER2_stfq),
5059 };
5060
5061 /* lfq */
5062 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5063 {
5064 /* NIP cannot be restored if the memory exception comes from an helper */
5065 gen_update_nip(ctx, ctx->nip - 4);
5066 gen_addr_imm_index(cpu_T[0], ctx, 0);
5067 op_POWER2_lfq();
5068 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5069 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
5070 }
5071
5072 /* lfqu */
5073 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5074 {
5075 int ra = rA(ctx->opcode);
5076
5077 /* NIP cannot be restored if the memory exception comes from an helper */
5078 gen_update_nip(ctx, ctx->nip - 4);
5079 gen_addr_imm_index(cpu_T[0], ctx, 0);
5080 op_POWER2_lfq();
5081 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5082 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
5083 if (ra != 0)
5084 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
5085 }
5086
5087 /* lfqux */
5088 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5089 {
5090 int ra = rA(ctx->opcode);
5091
5092 /* NIP cannot be restored if the memory exception comes from an helper */
5093 gen_update_nip(ctx, ctx->nip - 4);
5094 gen_addr_reg_index(cpu_T[0], ctx);
5095 op_POWER2_lfq();
5096 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5097 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
5098 if (ra != 0)
5099 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
5100 }
5101
5102 /* lfqx */
5103 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5104 {
5105 /* NIP cannot be restored if the memory exception comes from an helper */
5106 gen_update_nip(ctx, ctx->nip - 4);
5107 gen_addr_reg_index(cpu_T[0], ctx);
5108 op_POWER2_lfq();
5109 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5110 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
5111 }
5112
5113 /* stfq */
5114 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5115 {
5116 /* NIP cannot be restored if the memory exception comes from an helper */
5117 gen_update_nip(ctx, ctx->nip - 4);
5118 gen_addr_imm_index(cpu_T[0], ctx, 0);
5119 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5120 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5121 op_POWER2_stfq();
5122 }
5123
5124 /* stfqu */
5125 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5126 {
5127 int ra = rA(ctx->opcode);
5128
5129 /* NIP cannot be restored if the memory exception comes from an helper */
5130 gen_update_nip(ctx, ctx->nip - 4);
5131 gen_addr_imm_index(cpu_T[0], ctx, 0);
5132 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5133 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5134 op_POWER2_stfq();
5135 if (ra != 0)
5136 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
5137 }
5138
5139 /* stfqux */
5140 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5141 {
5142 int ra = rA(ctx->opcode);
5143
5144 /* NIP cannot be restored if the memory exception comes from an helper */
5145 gen_update_nip(ctx, ctx->nip - 4);
5146 gen_addr_reg_index(cpu_T[0], ctx);
5147 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5148 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5149 op_POWER2_stfq();
5150 if (ra != 0)
5151 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
5152 }
5153
5154 /* stfqx */
5155 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5156 {
5157 /* NIP cannot be restored if the memory exception comes from an helper */
5158 gen_update_nip(ctx, ctx->nip - 4);
5159 gen_addr_reg_index(cpu_T[0], ctx);
5160 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5161 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
5162 op_POWER2_stfq();
5163 }
5164
5165 /* BookE specific instructions */
5166 /* XXX: not implemented on 440 ? */
5167 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
5168 {
5169 /* XXX: TODO */
5170 GEN_EXCP_INVAL(ctx);
5171 }
5172
5173 /* XXX: not implemented on 440 ? */
5174 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
5175 {
5176 #if defined(CONFIG_USER_ONLY)
5177 GEN_EXCP_PRIVOPC(ctx);
5178 #else
5179 if (unlikely(!ctx->supervisor)) {
5180 GEN_EXCP_PRIVOPC(ctx);
5181 return;
5182 }
5183 gen_addr_reg_index(cpu_T[0], ctx);
5184 /* Use the same micro-ops as for tlbie */
5185 #if defined(TARGET_PPC64)
5186 if (ctx->sf_mode)
5187 gen_op_tlbie_64();
5188 else
5189 #endif
5190 gen_op_tlbie();
5191 #endif
5192 }
5193
5194 /* All 405 MAC instructions are translated here */
5195 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5196 int opc2, int opc3,
5197 int ra, int rb, int rt, int Rc)
5198 {
5199 TCGv t0, t1;
5200
5201 t0 = tcg_temp_local_new(TCG_TYPE_TL);
5202 t1 = tcg_temp_local_new(TCG_TYPE_TL);
5203
5204 switch (opc3 & 0x0D) {
5205 case 0x05:
5206 /* macchw - macchw. - macchwo - macchwo. */
5207 /* macchws - macchws. - macchwso - macchwso. */
5208 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5209 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5210 /* mulchw - mulchw. */
5211 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5212 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5213 tcg_gen_ext16s_tl(t1, t1);
5214 break;
5215 case 0x04:
5216 /* macchwu - macchwu. - macchwuo - macchwuo. */
5217 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5218 /* mulchwu - mulchwu. */
5219 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5220 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5221 tcg_gen_ext16u_tl(t1, t1);
5222 break;
5223 case 0x01:
5224 /* machhw - machhw. - machhwo - machhwo. */
5225 /* machhws - machhws. - machhwso - machhwso. */
5226 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5227 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5228 /* mulhhw - mulhhw. */
5229 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5230 tcg_gen_ext16s_tl(t0, t0);
5231 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5232 tcg_gen_ext16s_tl(t1, t1);
5233 break;
5234 case 0x00:
5235 /* machhwu - machhwu. - machhwuo - machhwuo. */
5236 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5237 /* mulhhwu - mulhhwu. */
5238 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5239 tcg_gen_ext16u_tl(t0, t0);
5240 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5241 tcg_gen_ext16u_tl(t1, t1);
5242 break;
5243 case 0x0D:
5244 /* maclhw - maclhw. - maclhwo - maclhwo. */
5245 /* maclhws - maclhws. - maclhwso - maclhwso. */
5246 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5247 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5248 /* mullhw - mullhw. */
5249 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5250 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5251 break;
5252 case 0x0C:
5253 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5254 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5255 /* mullhwu - mullhwu. */
5256 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5257 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5258 break;
5259 }
5260 if (opc2 & 0x04) {
5261 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5262 tcg_gen_mul_tl(t1, t0, t1);
5263 if (opc2 & 0x02) {
5264 /* nmultiply-and-accumulate (0x0E) */
5265 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5266 } else {
5267 /* multiply-and-accumulate (0x0C) */
5268 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5269 }
5270
5271 if (opc3 & 0x12) {
5272 /* Check overflow and/or saturate */
5273 int l1 = gen_new_label();
5274
5275 if (opc3 & 0x10) {
5276 /* Start with XER OV disabled, the most likely case */
5277 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5278 }
5279 if (opc3 & 0x01) {
5280 /* Signed */
5281 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5282 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5283 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5284 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5285 if (opc3 & 0x02) {
5286 /* Saturate */
5287 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5288 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5289 }
5290 } else {
5291 /* Unsigned */
5292 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5293 if (opc3 & 0x02) {
5294 /* Saturate */
5295 tcg_gen_movi_tl(t0, UINT32_MAX);
5296 }
5297 }
5298 if (opc3 & 0x10) {
5299 /* Check overflow */
5300 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5301 }
5302 gen_set_label(l1);
5303 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5304 }
5305 } else {
5306 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5307 }
5308 tcg_temp_free(t0);
5309 tcg_temp_free(t1);
5310 if (unlikely(Rc) != 0) {
5311 /* Update Rc0 */
5312 gen_set_Rc0(ctx, cpu_gpr[rt]);
5313 }
5314 }
5315
5316 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5317 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5318 { \
5319 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5320 rD(ctx->opcode), Rc(ctx->opcode)); \
5321 }
5322
5323 /* macchw - macchw. */
5324 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5325 /* macchwo - macchwo. */
5326 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5327 /* macchws - macchws. */
5328 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5329 /* macchwso - macchwso. */
5330 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5331 /* macchwsu - macchwsu. */
5332 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5333 /* macchwsuo - macchwsuo. */
5334 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5335 /* macchwu - macchwu. */
5336 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5337 /* macchwuo - macchwuo. */
5338 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5339 /* machhw - machhw. */
5340 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5341 /* machhwo - machhwo. */
5342 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5343 /* machhws - machhws. */
5344 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5345 /* machhwso - machhwso. */
5346 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5347 /* machhwsu - machhwsu. */
5348 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5349 /* machhwsuo - machhwsuo. */
5350 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5351 /* machhwu - machhwu. */
5352 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5353 /* machhwuo - machhwuo. */
5354 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5355 /* maclhw - maclhw. */
5356 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5357 /* maclhwo - maclhwo. */
5358 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5359 /* maclhws - maclhws. */
5360 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5361 /* maclhwso - maclhwso. */
5362 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5363 /* maclhwu - maclhwu. */
5364 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5365 /* maclhwuo - maclhwuo. */
5366 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5367 /* maclhwsu - maclhwsu. */
5368 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5369 /* maclhwsuo - maclhwsuo. */
5370 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5371 /* nmacchw - nmacchw. */
5372 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5373 /* nmacchwo - nmacchwo. */
5374 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5375 /* nmacchws - nmacchws. */
5376 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5377 /* nmacchwso - nmacchwso. */
5378 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5379 /* nmachhw - nmachhw. */
5380 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5381 /* nmachhwo - nmachhwo. */
5382 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5383 /* nmachhws - nmachhws. */
5384 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5385 /* nmachhwso - nmachhwso. */
5386 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5387 /* nmaclhw - nmaclhw. */
5388 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5389 /* nmaclhwo - nmaclhwo. */
5390 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5391 /* nmaclhws - nmaclhws. */
5392 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5393 /* nmaclhwso - nmaclhwso. */
5394 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5395
5396 /* mulchw - mulchw. */
5397 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5398 /* mulchwu - mulchwu. */
5399 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5400 /* mulhhw - mulhhw. */
5401 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5402 /* mulhhwu - mulhhwu. */
5403 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5404 /* mullhw - mullhw. */
5405 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5406 /* mullhwu - mullhwu. */
5407 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5408
5409 /* mfdcr */
5410 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5411 {
5412 #if defined(CONFIG_USER_ONLY)
5413 GEN_EXCP_PRIVREG(ctx);
5414 #else
5415 uint32_t dcrn = SPR(ctx->opcode);
5416
5417 if (unlikely(!ctx->supervisor)) {
5418 GEN_EXCP_PRIVREG(ctx);
5419 return;
5420 }
5421 tcg_gen_movi_tl(cpu_T[0], dcrn);
5422 gen_op_load_dcr();
5423 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5424 #endif
5425 }
5426
5427 /* mtdcr */
5428 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5429 {
5430 #if defined(CONFIG_USER_ONLY)
5431 GEN_EXCP_PRIVREG(ctx);
5432 #else
5433 uint32_t dcrn = SPR(ctx->opcode);
5434
5435 if (unlikely(!ctx->supervisor)) {
5436 GEN_EXCP_PRIVREG(ctx);
5437 return;
5438 }
5439 tcg_gen_movi_tl(cpu_T[0], dcrn);
5440 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5441 gen_op_store_dcr();
5442 #endif
5443 }
5444
5445 /* mfdcrx */
5446 /* XXX: not implemented on 440 ? */
5447 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5448 {
5449 #if defined(CONFIG_USER_ONLY)
5450 GEN_EXCP_PRIVREG(ctx);
5451 #else
5452 if (unlikely(!ctx->supervisor)) {
5453 GEN_EXCP_PRIVREG(ctx);
5454 return;
5455 }
5456 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5457 gen_op_load_dcr();
5458 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5459 /* Note: Rc update flag set leads to undefined state of Rc0 */
5460 #endif
5461 }
5462
5463 /* mtdcrx */
5464 /* XXX: not implemented on 440 ? */
5465 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5466 {
5467 #if defined(CONFIG_USER_ONLY)
5468 GEN_EXCP_PRIVREG(ctx);
5469 #else
5470 if (unlikely(!ctx->supervisor)) {
5471 GEN_EXCP_PRIVREG(ctx);
5472 return;
5473 }
5474 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5475 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5476 gen_op_store_dcr();
5477 /* Note: Rc update flag set leads to undefined state of Rc0 */
5478 #endif
5479 }
5480
5481 /* mfdcrux (PPC 460) : user-mode access to DCR */
5482 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5483 {
5484 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5485 gen_op_load_dcr();
5486 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5487 /* Note: Rc update flag set leads to undefined state of Rc0 */
5488 }
5489
5490 /* mtdcrux (PPC 460) : user-mode access to DCR */
5491 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5492 {
5493 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5494 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5495 gen_op_store_dcr();
5496 /* Note: Rc update flag set leads to undefined state of Rc0 */
5497 }
5498
5499 /* dccci */
5500 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5501 {
5502 #if defined(CONFIG_USER_ONLY)
5503 GEN_EXCP_PRIVOPC(ctx);
5504 #else
5505 if (unlikely(!ctx->supervisor)) {
5506 GEN_EXCP_PRIVOPC(ctx);
5507 return;
5508 }
5509 /* interpreted as no-op */
5510 #endif
5511 }
5512
5513 /* dcread */
5514 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5515 {
5516 #if defined(CONFIG_USER_ONLY)
5517 GEN_EXCP_PRIVOPC(ctx);
5518 #else
5519 TCGv EA, val;
5520 if (unlikely(!ctx->supervisor)) {
5521 GEN_EXCP_PRIVOPC(ctx);
5522 return;
5523 }
5524 EA = tcg_temp_new(TCG_TYPE_TL);
5525 gen_addr_reg_index(EA, ctx);
5526 val = tcg_temp_new(TCG_TYPE_TL);
5527 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5528 tcg_temp_free(val);
5529 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5530 tcg_temp_free(EA);
5531 #endif
5532 }
5533
5534 /* icbt */
5535 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5536 {
5537 /* interpreted as no-op */
5538 /* XXX: specification say this is treated as a load by the MMU
5539 * but does not generate any exception
5540 */
5541 }
5542
5543 /* iccci */
5544 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5545 {
5546 #if defined(CONFIG_USER_ONLY)
5547 GEN_EXCP_PRIVOPC(ctx);
5548 #else
5549 if (unlikely(!ctx->supervisor)) {
5550 GEN_EXCP_PRIVOPC(ctx);
5551 return;
5552 }
5553 /* interpreted as no-op */
5554 #endif
5555 }
5556
5557 /* icread */
5558 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5559 {
5560 #if defined(CONFIG_USER_ONLY)
5561 GEN_EXCP_PRIVOPC(ctx);
5562 #else
5563 if (unlikely(!ctx->supervisor)) {
5564 GEN_EXCP_PRIVOPC(ctx);
5565 return;
5566 }
5567 /* interpreted as no-op */
5568 #endif
5569 }
5570
5571 /* rfci (supervisor only) */
5572 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5573 {
5574 #if defined(CONFIG_USER_ONLY)
5575 GEN_EXCP_PRIVOPC(ctx);
5576 #else
5577 if (unlikely(!ctx->supervisor)) {
5578 GEN_EXCP_PRIVOPC(ctx);
5579 return;
5580 }
5581 /* Restore CPU state */
5582 gen_op_40x_rfci();
5583 GEN_SYNC(ctx);
5584 #endif
5585 }
5586
5587 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5588 {
5589 #if defined(CONFIG_USER_ONLY)
5590 GEN_EXCP_PRIVOPC(ctx);
5591 #else
5592 if (unlikely(!ctx->supervisor)) {
5593 GEN_EXCP_PRIVOPC(ctx);
5594 return;
5595 }
5596 /* Restore CPU state */
5597 gen_op_rfci();
5598 GEN_SYNC(ctx);
5599 #endif
5600 }
5601
5602 /* BookE specific */
5603 /* XXX: not implemented on 440 ? */
5604 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5605 {
5606 #if defined(CONFIG_USER_ONLY)
5607 GEN_EXCP_PRIVOPC(ctx);
5608 #else
5609 if (unlikely(!ctx->supervisor)) {
5610 GEN_EXCP_PRIVOPC(ctx);
5611 return;
5612 }
5613 /* Restore CPU state */
5614 gen_op_rfdi();
5615 GEN_SYNC(ctx);
5616 #endif
5617 }
5618
5619 /* XXX: not implemented on 440 ? */
5620 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5621 {
5622 #if defined(CONFIG_USER_ONLY)
5623 GEN_EXCP_PRIVOPC(ctx);
5624 #else
5625 if (unlikely(!ctx->supervisor)) {
5626 GEN_EXCP_PRIVOPC(ctx);
5627 return;
5628 }
5629 /* Restore CPU state */
5630 gen_op_rfmci();
5631 GEN_SYNC(ctx);
5632 #endif
5633 }
5634
5635 /* TLB management - PowerPC 405 implementation */
5636 /* tlbre */
5637 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5638 {
5639 #if defined(CONFIG_USER_ONLY)
5640 GEN_EXCP_PRIVOPC(ctx);
5641 #else
5642 if (unlikely(!ctx->supervisor)) {
5643 GEN_EXCP_PRIVOPC(ctx);
5644 return;
5645 }
5646 switch (rB(ctx->opcode)) {
5647 case 0:
5648 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5649 gen_op_4xx_tlbre_hi();
5650 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5651 break;
5652 case 1:
5653 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5654 gen_op_4xx_tlbre_lo();
5655 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5656 break;
5657 default:
5658 GEN_EXCP_INVAL(ctx);
5659 break;
5660 }
5661 #endif
5662 }
5663
5664 /* tlbsx - tlbsx. */
5665 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5666 {
5667 #if defined(CONFIG_USER_ONLY)
5668 GEN_EXCP_PRIVOPC(ctx);
5669 #else
5670 if (unlikely(!ctx->supervisor)) {
5671 GEN_EXCP_PRIVOPC(ctx);
5672 return;
5673 }
5674 gen_addr_reg_index(cpu_T[0], ctx);
5675 gen_op_4xx_tlbsx();
5676 if (Rc(ctx->opcode))
5677 gen_op_4xx_tlbsx_check();
5678 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5679 #endif
5680 }
5681
5682 /* tlbwe */
5683 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5684 {
5685 #if defined(CONFIG_USER_ONLY)
5686 GEN_EXCP_PRIVOPC(ctx);
5687 #else
5688 if (unlikely(!ctx->supervisor)) {
5689 GEN_EXCP_PRIVOPC(ctx);
5690 return;
5691 }
5692 switch (rB(ctx->opcode)) {
5693 case 0:
5694 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5695 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5696 gen_op_4xx_tlbwe_hi();
5697 break;
5698 case 1:
5699 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5700 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5701 gen_op_4xx_tlbwe_lo();
5702 break;
5703 default:
5704 GEN_EXCP_INVAL(ctx);
5705 break;
5706 }
5707 #endif
5708 }
5709
5710 /* TLB management - PowerPC 440 implementation */
5711 /* tlbre */
5712 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5713 {
5714 #if defined(CONFIG_USER_ONLY)
5715 GEN_EXCP_PRIVOPC(ctx);
5716 #else
5717 if (unlikely(!ctx->supervisor)) {
5718 GEN_EXCP_PRIVOPC(ctx);
5719 return;
5720 }
5721 switch (rB(ctx->opcode)) {
5722 case 0:
5723 case 1:
5724 case 2:
5725 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5726 gen_op_440_tlbre(rB(ctx->opcode));
5727 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5728 break;
5729 default:
5730 GEN_EXCP_INVAL(ctx);
5731 break;
5732 }
5733 #endif
5734 }
5735
5736 /* tlbsx - tlbsx. */
5737 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5738 {
5739 #if defined(CONFIG_USER_ONLY)
5740 GEN_EXCP_PRIVOPC(ctx);
5741 #else
5742 if (unlikely(!ctx->supervisor)) {
5743 GEN_EXCP_PRIVOPC(ctx);
5744 return;
5745 }
5746 gen_addr_reg_index(cpu_T[0], ctx);
5747 gen_op_440_tlbsx();
5748 if (Rc(ctx->opcode))
5749 gen_op_4xx_tlbsx_check();
5750 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5751 #endif
5752 }
5753
5754 /* tlbwe */
5755 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5756 {
5757 #if defined(CONFIG_USER_ONLY)
5758 GEN_EXCP_PRIVOPC(ctx);
5759 #else
5760 if (unlikely(!ctx->supervisor)) {
5761 GEN_EXCP_PRIVOPC(ctx);
5762 return;
5763 }
5764 switch (rB(ctx->opcode)) {
5765 case 0:
5766 case 1:
5767 case 2:
5768 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5769 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5770 gen_op_440_tlbwe(rB(ctx->opcode));
5771 break;
5772 default:
5773 GEN_EXCP_INVAL(ctx);
5774 break;
5775 }
5776 #endif
5777 }
5778
5779 /* wrtee */
5780 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5781 {
5782 #if defined(CONFIG_USER_ONLY)
5783 GEN_EXCP_PRIVOPC(ctx);
5784 #else
5785 if (unlikely(!ctx->supervisor)) {
5786 GEN_EXCP_PRIVOPC(ctx);
5787 return;
5788 }
5789 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
5790 gen_op_wrte();
5791 /* Stop translation to have a chance to raise an exception
5792 * if we just set msr_ee to 1
5793 */
5794 GEN_STOP(ctx);
5795 #endif
5796 }
5797
5798 /* wrteei */
5799 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
5800 {
5801 #if defined(CONFIG_USER_ONLY)
5802 GEN_EXCP_PRIVOPC(ctx);
5803 #else
5804 if (unlikely(!ctx->supervisor)) {
5805 GEN_EXCP_PRIVOPC(ctx);
5806 return;
5807 }
5808 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
5809 gen_op_wrte();
5810 /* Stop translation to have a chance to raise an exception
5811 * if we just set msr_ee to 1
5812 */
5813 GEN_STOP(ctx);
5814 #endif
5815 }
5816
5817 /* PowerPC 440 specific instructions */
5818 /* dlmzb */
5819 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5820 {
5821 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5822 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
5823 gen_op_440_dlmzb();
5824 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
5825 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5826 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
5827 if (Rc(ctx->opcode)) {
5828 gen_op_440_dlmzb_update_Rc();
5829 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
5830 }
5831 }
5832
5833 /* mbar replaces eieio on 440 */
5834 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5835 {
5836 /* interpreted as no-op */
5837 }
5838
5839 /* msync replaces sync on 440 */
5840 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5841 {
5842 /* interpreted as no-op */
5843 }
5844
5845 /* icbt */
5846 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5847 {
5848 /* interpreted as no-op */
5849 /* XXX: specification say this is treated as a load by the MMU
5850 * but does not generate any exception
5851 */
5852 }
5853
5854 /*** Altivec vector extension ***/
5855 /* Altivec registers moves */
5856
5857 static always_inline void gen_load_avr(int t, int reg) {
5858 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5859 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5860 }
5861
5862 static always_inline void gen_store_avr(int reg, int t) {
5863 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5864 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5865 }
5866
5867 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5868 #define OP_VR_LD_TABLE(name) \
5869 static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5870 GEN_MEM_FUNCS(vr_l##name), \
5871 };
5872 #define OP_VR_ST_TABLE(name) \
5873 static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5874 GEN_MEM_FUNCS(vr_st##name), \
5875 };
5876
5877 #define GEN_VR_LDX(name, opc2, opc3) \
5878 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5879 { \
5880 if (unlikely(!ctx->altivec_enabled)) { \
5881 GEN_EXCP_NO_VR(ctx); \
5882 return; \
5883 } \
5884 gen_addr_reg_index(cpu_T[0], ctx); \
5885 op_vr_ldst(vr_l##name); \
5886 gen_store_avr(rD(ctx->opcode), 0); \
5887 }
5888
5889 #define GEN_VR_STX(name, opc2, opc3) \
5890 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5891 { \
5892 if (unlikely(!ctx->altivec_enabled)) { \
5893 GEN_EXCP_NO_VR(ctx); \
5894 return; \
5895 } \
5896 gen_addr_reg_index(cpu_T[0], ctx); \
5897 gen_load_avr(0, rS(ctx->opcode)); \
5898 op_vr_ldst(vr_st##name); \
5899 }
5900
5901 OP_VR_LD_TABLE(vx);
5902 GEN_VR_LDX(vx, 0x07, 0x03);
5903 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5904 #define gen_op_vr_lvxl gen_op_vr_lvx
5905 GEN_VR_LDX(vxl, 0x07, 0x0B);
5906
5907 OP_VR_ST_TABLE(vx);
5908 GEN_VR_STX(vx, 0x07, 0x07);
5909 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5910 #define gen_op_vr_stvxl gen_op_vr_stvx
5911 GEN_VR_STX(vxl, 0x07, 0x0F);
5912
5913 /*** SPE extension ***/
5914 /* Register moves */
5915
5916 static always_inline void gen_load_gpr64(TCGv t, int reg) {
5917 #if defined(TARGET_PPC64)
5918 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5919 #else
5920 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
5921 #endif
5922 }
5923
5924 static always_inline void gen_store_gpr64(int reg, TCGv t) {
5925 #if defined(TARGET_PPC64)
5926 tcg_gen_mov_i64(cpu_gpr[reg], t);
5927 #else
5928 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
5929 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
5930 tcg_gen_shri_i64(tmp, t, 32);
5931 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5932 tcg_temp_free(tmp);
5933 #endif
5934 }
5935
5936 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5937 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5938 { \
5939 if (Rc(ctx->opcode)) \
5940 gen_##name1(ctx); \
5941 else \
5942 gen_##name0(ctx); \
5943 }
5944
5945 /* Handler for undefined SPE opcodes */
5946 static always_inline void gen_speundef (DisasContext *ctx)
5947 {
5948 GEN_EXCP_INVAL(ctx);
5949 }
5950
5951 /* SPE load and stores */
5952 static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
5953 {
5954 target_long simm = rB(ctx->opcode);
5955
5956 if (rA(ctx->opcode) == 0)
5957 tcg_gen_movi_tl(EA, simm << sh);
5958 else if (likely(simm != 0))
5959 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5960 else
5961 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
5962 }
5963
5964 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5965 #define OP_SPE_LD_TABLE(name) \
5966 static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5967 GEN_MEM_FUNCS(spe_l##name), \
5968 };
5969 #define OP_SPE_ST_TABLE(name) \
5970 static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5971 GEN_MEM_FUNCS(spe_st##name), \
5972 };
5973
5974 #define GEN_SPE_LD(name, sh) \
5975 static always_inline void gen_evl##name (DisasContext *ctx) \
5976 { \
5977 if (unlikely(!ctx->spe_enabled)) { \
5978 GEN_EXCP_NO_AP(ctx); \
5979 return; \
5980 } \
5981 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
5982 op_spe_ldst(spe_l##name); \
5983 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5984 }
5985
5986 #define GEN_SPE_LDX(name) \
5987 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5988 { \
5989 if (unlikely(!ctx->spe_enabled)) { \
5990 GEN_EXCP_NO_AP(ctx); \
5991 return; \
5992 } \
5993 gen_addr_reg_index(cpu_T[0], ctx); \
5994 op_spe_ldst(spe_l##name); \
5995 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5996 }
5997
5998 #define GEN_SPEOP_LD(name, sh) \
5999 OP_SPE_LD_TABLE(name); \
6000 GEN_SPE_LD(name, sh); \
6001 GEN_SPE_LDX(name)
6002
6003 #define GEN_SPE_ST(name, sh) \
6004 static always_inline void gen_evst##name (DisasContext *ctx) \
6005 { \
6006 if (unlikely(!ctx->spe_enabled)) { \
6007 GEN_EXCP_NO_AP(ctx); \
6008 return; \
6009 } \
6010 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
6011 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
6012 op_spe_ldst(spe_st##name); \
6013 }
6014
6015 #define GEN_SPE_STX(name) \
6016 static always_inline void gen_evst##name##x (DisasContext *ctx) \
6017 { \
6018 if (unlikely(!ctx->spe_enabled)) { \
6019 GEN_EXCP_NO_AP(ctx); \
6020 return; \
6021 } \
6022 gen_addr_reg_index(cpu_T[0], ctx); \
6023 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
6024 op_spe_ldst(spe_st##name); \
6025 }
6026
6027 #define GEN_SPEOP_ST(name, sh) \
6028 OP_SPE_ST_TABLE(name); \
6029 GEN_SPE_ST(name, sh); \
6030 GEN_SPE_STX(name)
6031
6032 #define GEN_SPEOP_LDST(name, sh) \
6033 GEN_SPEOP_LD(name, sh); \
6034 GEN_SPEOP_ST(name, sh)
6035
6036 /* SPE arithmetic and logic */
6037 #define GEN_SPEOP_ARITH2(name) \
6038 static always_inline void gen_##name (DisasContext *ctx) \
6039 { \
6040 if (unlikely(!ctx->spe_enabled)) { \
6041 GEN_EXCP_NO_AP(ctx); \
6042 return; \
6043 } \
6044 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6045 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
6046 gen_op_##name(); \
6047 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
6048 }
6049
6050 #define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
6051 static always_inline void gen_##name (DisasContext *ctx) \
6052 { \
6053 if (unlikely(!ctx->spe_enabled)) { \
6054 GEN_EXCP_NO_AP(ctx); \
6055 return; \
6056 } \
6057 TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
6058 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
6059 gen_load_gpr64(t0, rA(ctx->opcode)); \
6060 gen_load_gpr64(t1, rB(ctx->opcode)); \
6061 tcg_op(t0, t0, t1); \
6062 gen_store_gpr64(rD(ctx->opcode), t0); \
6063 tcg_temp_free(t0); \
6064 tcg_temp_free(t1); \
6065 }
6066
6067 #define GEN_SPEOP_ARITH1(name) \
6068 static always_inline void gen_##name (DisasContext *ctx) \
6069 { \
6070 if (unlikely(!ctx->spe_enabled)) { \
6071 GEN_EXCP_NO_AP(ctx); \
6072 return; \
6073 } \
6074 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6075 gen_op_##name(); \
6076 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
6077 }
6078
6079 #define GEN_SPEOP_COMP(name) \
6080 static always_inline void gen_##name (DisasContext *ctx) \
6081 { \
6082 if (unlikely(!ctx->spe_enabled)) { \
6083 GEN_EXCP_NO_AP(ctx); \
6084 return; \
6085 } \
6086 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6087 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
6088 gen_op_##name(); \
6089 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
6090 }
6091
6092 /* Logical */
6093 GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
6094 GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
6095 GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
6096 GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
6097 GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
6098 GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
6099 GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
6100 GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
6101 GEN_SPEOP_ARITH2(evsrwu);
6102 GEN_SPEOP_ARITH2(evsrws);
6103 GEN_SPEOP_ARITH2(evslw);
6104 GEN_SPEOP_ARITH2(evrlw);
6105 GEN_SPEOP_ARITH2(evmergehi);
6106 GEN_SPEOP_ARITH2(evmergelo);
6107 GEN_SPEOP_ARITH2(evmergehilo);
6108 GEN_SPEOP_ARITH2(evmergelohi);
6109
6110 /* Arithmetic */
6111 GEN_SPEOP_ARITH2(evaddw);
6112 GEN_SPEOP_ARITH2(evsubfw);
6113 GEN_SPEOP_ARITH1(evabs);
6114 GEN_SPEOP_ARITH1(evneg);
6115 GEN_SPEOP_ARITH1(evextsb);
6116 GEN_SPEOP_ARITH1(evextsh);
6117 GEN_SPEOP_ARITH1(evrndw);
6118 GEN_SPEOP_ARITH1(evcntlzw);
6119 GEN_SPEOP_ARITH1(evcntlsw);
6120 static always_inline void gen_brinc (DisasContext *ctx)
6121 {
6122 /* Note: brinc is usable even if SPE is disabled */
6123 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
6124 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
6125 gen_op_brinc();
6126 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
6127 }
6128
6129 #define GEN_SPEOP_ARITH_IMM2(name) \
6130 static always_inline void gen_##name##i (DisasContext *ctx) \
6131 { \
6132 if (unlikely(!ctx->spe_enabled)) { \
6133 GEN_EXCP_NO_AP(ctx); \
6134 return; \
6135 } \
6136 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
6137 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
6138 gen_op_##name(); \
6139 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
6140 }
6141
6142 #define GEN_SPEOP_LOGIC_IMM2(name) \
6143 static always_inline void gen_##name##i (DisasContext *ctx) \
6144 { \
6145 if (unlikely(!ctx->spe_enabled)) { \
6146 GEN_EXCP_NO_AP(ctx); \
6147 return; \
6148 } \
6149 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6150 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6151 gen_op_##name(); \
6152 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
6153 }
6154
6155 GEN_SPEOP_ARITH_IMM2(evaddw);
6156 #define gen_evaddiw gen_evaddwi
6157 GEN_SPEOP_ARITH_IMM2(evsubfw);
6158 #define gen_evsubifw gen_evsubfwi
6159 GEN_SPEOP_LOGIC_IMM2(evslw);
6160 GEN_SPEOP_LOGIC_IMM2(evsrwu);
6161 #define gen_evsrwis gen_evsrwsi
6162 GEN_SPEOP_LOGIC_IMM2(evsrws);
6163 #define gen_evsrwiu gen_evsrwui
6164 GEN_SPEOP_LOGIC_IMM2(evrlw);
6165
6166 static always_inline void gen_evsplati (DisasContext *ctx)
6167 {
6168 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6169
6170 gen_op_splatwi_T0_64(imm);
6171 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
6172 }
6173
6174 static always_inline void gen_evsplatfi (DisasContext *ctx)
6175 {
6176 uint32_t imm = rA(ctx->opcode) << 27;
6177
6178 gen_op_splatwi_T0_64(imm);
6179 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
6180 }
6181
6182 /* Comparison */
6183 GEN_SPEOP_COMP(evcmpgtu);
6184 GEN_SPEOP_COMP(evcmpgts);
6185 GEN_SPEOP_COMP(evcmpltu);
6186 GEN_SPEOP_COMP(evcmplts);
6187 GEN_SPEOP_COMP(evcmpeq);
6188
6189 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6190 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6191 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6192 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6193 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6194 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6195 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6196 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6197 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6198 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6199 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6200 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6201 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6202 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6203 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6204 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6205 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6206 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6207 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6208 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6209 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6210 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6211 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6212 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6213 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6214
6215 static always_inline void gen_evsel (DisasContext *ctx)
6216 {
6217 if (unlikely(!ctx->spe_enabled)) {
6218 GEN_EXCP_NO_AP(ctx);
6219 return;
6220 }
6221 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
6222 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
6223 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
6224 gen_op_evsel();
6225 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
6226 }
6227
6228 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6229 {
6230 gen_evsel(ctx);
6231 }
6232 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6233 {
6234 gen_evsel(ctx);
6235 }
6236 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6237 {
6238 gen_evsel(ctx);
6239 }
6240 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6241 {
6242 gen_evsel(ctx);
6243 }
6244
6245 /* Load and stores */
6246 GEN_SPEOP_LDST(dd, 3);
6247 GEN_SPEOP_LDST(dw, 3);
6248 GEN_SPEOP_LDST(dh, 3);
6249 GEN_SPEOP_LDST(whe, 2);
6250 GEN_SPEOP_LD(whou, 2);
6251 GEN_SPEOP_LD(whos, 2);
6252 GEN_SPEOP_ST(who, 2);
6253
6254 #define _GEN_OP_SPE_STWWE(suffix) \
6255 static always_inline void gen_op_spe_stwwe_##suffix (void) \
6256 { \
6257 gen_op_srli32_T1_64(); \
6258 gen_op_spe_stwwo_##suffix(); \
6259 }
6260 #define _GEN_OP_SPE_STWWE_LE(suffix) \
6261 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
6262 { \
6263 gen_op_srli32_T1_64(); \
6264 gen_op_spe_stwwo_le_##suffix(); \
6265 }
6266 #if defined(TARGET_PPC64)
6267 #define GEN_OP_SPE_STWWE(suffix) \
6268 _GEN_OP_SPE_STWWE(suffix); \
6269 _GEN_OP_SPE_STWWE_LE(suffix); \
6270 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
6271 { \
6272 gen_op_srli32_T1_64(); \
6273 gen_op_spe_stwwo_64_##suffix(); \
6274 } \
6275 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
6276 { \
6277 gen_op_srli32_T1_64(); \
6278 gen_op_spe_stwwo_le_64_##suffix(); \
6279 }
6280 #else
6281 #define GEN_OP_SPE_STWWE(suffix) \
6282 _GEN_OP_SPE_STWWE(suffix); \
6283 _GEN_OP_SPE_STWWE_LE(suffix)
6284 #endif
6285 #if defined(CONFIG_USER_ONLY)
6286 GEN_OP_SPE_STWWE(raw);
6287 #else /* defined(CONFIG_USER_ONLY) */
6288 GEN_OP_SPE_STWWE(user);
6289 GEN_OP_SPE_STWWE(kernel);
6290 GEN_OP_SPE_STWWE(hypv);
6291 #endif /* defined(CONFIG_USER_ONLY) */
6292 GEN_SPEOP_ST(wwe, 2);
6293 GEN_SPEOP_ST(wwo, 2);
6294
6295 #define GEN_SPE_LDSPLAT(name, op, suffix) \
6296 static always_inline void gen_op_spe_l##name##_##suffix (void) \
6297 { \
6298 gen_op_##op##_##suffix(); \
6299 gen_op_splatw_T1_64(); \
6300 }
6301
6302 #define GEN_OP_SPE_LHE(suffix) \
6303 static always_inline void gen_op_spe_lhe_##suffix (void) \
6304 { \
6305 gen_op_spe_lh_##suffix(); \
6306 gen_op_sli16_T1_64(); \
6307 }
6308
6309 #define GEN_OP_SPE_LHX(suffix) \
6310 static always_inline void gen_op_spe_lhx_##suffix (void) \
6311 { \
6312 gen_op_spe_lh_##suffix(); \
6313 gen_op_extsh_T1_64(); \
6314 }
6315
6316 #if defined(CONFIG_USER_ONLY)
6317 GEN_OP_SPE_LHE(raw);
6318 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6319 GEN_OP_SPE_LHE(le_raw);
6320 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6321 GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6322 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6323 GEN_OP_SPE_LHX(raw);
6324 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6325 GEN_OP_SPE_LHX(le_raw);
6326 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6327 #if defined(TARGET_PPC64)
6328 GEN_OP_SPE_LHE(64_raw);
6329 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6330 GEN_OP_SPE_LHE(le_64_raw);
6331 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6332 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6333 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6334 GEN_OP_SPE_LHX(64_raw);
6335 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6336 GEN_OP_SPE_LHX(le_64_raw);
6337 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6338 #endif
6339 #else
6340 GEN_OP_SPE_LHE(user);
6341 GEN_OP_SPE_LHE(kernel);
6342 GEN_OP_SPE_LHE(hypv);
6343 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
6344 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6345 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
6346 GEN_OP_SPE_LHE(le_user);
6347 GEN_OP_SPE_LHE(le_kernel);
6348 GEN_OP_SPE_LHE(le_hypv);
6349 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
6350 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6351 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
6352 GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
6353 GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6354 GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
6355 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
6356 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6357 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
6358 GEN_OP_SPE_LHX(user);
6359 GEN_OP_SPE_LHX(kernel);
6360 GEN_OP_SPE_LHX(hypv);
6361 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
6362 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6363 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
6364 GEN_OP_SPE_LHX(le_user);
6365 GEN_OP_SPE_LHX(le_kernel);
6366 GEN_OP_SPE_LHX(le_hypv);
6367 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6368 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6369 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
6370 #if defined(TARGET_PPC64)
6371 GEN_OP_SPE_LHE(64_user);
6372 GEN_OP_SPE_LHE(64_kernel);
6373 GEN_OP_SPE_LHE(64_hypv);
6374 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
6375 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6376 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
6377 GEN_OP_SPE_LHE(le_64_user);
6378 GEN_OP_SPE_LHE(le_64_kernel);
6379 GEN_OP_SPE_LHE(le_64_hypv);
6380 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
6381 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6382 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
6383 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
6384 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6385 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
6386 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
6387 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6388 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
6389 GEN_OP_SPE_LHX(64_user);
6390 GEN_OP_SPE_LHX(64_kernel);
6391 GEN_OP_SPE_LHX(64_hypv);
6392 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
6393 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6394 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
6395 GEN_OP_SPE_LHX(le_64_user);
6396 GEN_OP_SPE_LHX(le_64_kernel);
6397 GEN_OP_SPE_LHX(le_64_hypv);
6398 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6399 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6400 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
6401 #endif
6402 #endif
6403 GEN_SPEOP_LD(hhesplat, 1);
6404 GEN_SPEOP_LD(hhousplat, 1);
6405 GEN_SPEOP_LD(hhossplat, 1);
6406 GEN_SPEOP_LD(wwsplat, 2);
6407 GEN_SPEOP_LD(whsplat, 2);
6408
6409 GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6410 GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6411 GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6412 GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6413 GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6414 GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6415 GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6416 GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6417 GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6418 GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6419 GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6420 GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6421 GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6422 GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6423 GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6424 GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6425 GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6426 GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6427
6428 /* Multiply and add - TODO */
6429 #if 0
6430 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6431 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6432 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6433 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6434 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6435 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6436 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6437 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6438 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6439 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6440 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6441 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6442
6443 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6444 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6445 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6446 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6447 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6448 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6449 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6450 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6451 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6452 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6453 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6454 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6455 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6456 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6457
6458 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6459 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6460 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6461 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6462 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6463 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6464
6465 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6466 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6467 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6468 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6469 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6470 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6471 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6472 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6473 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6474 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6475 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6476 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6477
6478 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6479 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6480 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6481 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6482 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6483
6484 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6485 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6486 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6487 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6488 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6489 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6490 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6491 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6492 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6493 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6494 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6495 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6496
6497 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6498 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6499 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6500 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6501 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6502 #endif
6503
6504 /*** SPE floating-point extension ***/
6505 #define GEN_SPEFPUOP_CONV(name) \
6506 static always_inline void gen_##name (DisasContext *ctx) \
6507 { \
6508 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
6509 gen_op_##name(); \
6510 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
6511 }
6512
6513 /* Single precision floating-point vectors operations */
6514 /* Arithmetic */
6515 GEN_SPEOP_ARITH2(evfsadd);
6516 GEN_SPEOP_ARITH2(evfssub);
6517 GEN_SPEOP_ARITH2(evfsmul);
6518 GEN_SPEOP_ARITH2(evfsdiv);
6519 GEN_SPEOP_ARITH1(evfsabs);
6520 GEN_SPEOP_ARITH1(evfsnabs);
6521 GEN_SPEOP_ARITH1(evfsneg);
6522 /* Conversion */
6523 GEN_SPEFPUOP_CONV(evfscfui);
6524 GEN_SPEFPUOP_CONV(evfscfsi);
6525 GEN_SPEFPUOP_CONV(evfscfuf);
6526 GEN_SPEFPUOP_CONV(evfscfsf);
6527 GEN_SPEFPUOP_CONV(evfsctui);
6528 GEN_SPEFPUOP_CONV(evfsctsi);
6529 GEN_SPEFPUOP_CONV(evfsctuf);
6530 GEN_SPEFPUOP_CONV(evfsctsf);
6531 GEN_SPEFPUOP_CONV(evfsctuiz);
6532 GEN_SPEFPUOP_CONV(evfsctsiz);
6533 /* Comparison */
6534 GEN_SPEOP_COMP(evfscmpgt);
6535 GEN_SPEOP_COMP(evfscmplt);
6536 GEN_SPEOP_COMP(evfscmpeq);
6537 GEN_SPEOP_COMP(evfststgt);
6538 GEN_SPEOP_COMP(evfststlt);
6539 GEN_SPEOP_COMP(evfststeq);
6540
6541 /* Opcodes definitions */
6542 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6543 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6544 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6545 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6546 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6547 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6548 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6549 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6550 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6551 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6552 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6553 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6554 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6555 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6556
6557 /* Single precision floating-point operations */
6558 /* Arithmetic */
6559 GEN_SPEOP_ARITH2(efsadd);
6560 GEN_SPEOP_ARITH2(efssub);
6561 GEN_SPEOP_ARITH2(efsmul);
6562 GEN_SPEOP_ARITH2(efsdiv);
6563 GEN_SPEOP_ARITH1(efsabs);
6564 GEN_SPEOP_ARITH1(efsnabs);
6565 GEN_SPEOP_ARITH1(efsneg);
6566 /* Conversion */
6567 GEN_SPEFPUOP_CONV(efscfui);
6568 GEN_SPEFPUOP_CONV(efscfsi);
6569 GEN_SPEFPUOP_CONV(efscfuf);
6570 GEN_SPEFPUOP_CONV(efscfsf);
6571 GEN_SPEFPUOP_CONV(efsctui);
6572 GEN_SPEFPUOP_CONV(efsctsi);
6573 GEN_SPEFPUOP_CONV(efsctuf);
6574 GEN_SPEFPUOP_CONV(efsctsf);
6575 GEN_SPEFPUOP_CONV(efsctuiz);
6576 GEN_SPEFPUOP_CONV(efsctsiz);
6577 GEN_SPEFPUOP_CONV(efscfd);
6578 /* Comparison */
6579 GEN_SPEOP_COMP(efscmpgt);
6580 GEN_SPEOP_COMP(efscmplt);
6581 GEN_SPEOP_COMP(efscmpeq);
6582 GEN_SPEOP_COMP(efststgt);
6583 GEN_SPEOP_COMP(efststlt);
6584 GEN_SPEOP_COMP(efststeq);
6585
6586 /* Opcodes definitions */
6587 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
6588 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6589 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6590 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6591 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6592 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6593 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6594 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6595 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6596 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
6597 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6598 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
6599 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6600 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6601
6602 /* Double precision floating-point operations */
6603 /* Arithmetic */
6604 GEN_SPEOP_ARITH2(efdadd);
6605 GEN_SPEOP_ARITH2(efdsub);
6606 GEN_SPEOP_ARITH2(efdmul);
6607 GEN_SPEOP_ARITH2(efddiv);
6608 GEN_SPEOP_ARITH1(efdabs);
6609 GEN_SPEOP_ARITH1(efdnabs);
6610 GEN_SPEOP_ARITH1(efdneg);
6611 /* Conversion */
6612
6613 GEN_SPEFPUOP_CONV(efdcfui);
6614 GEN_SPEFPUOP_CONV(efdcfsi);
6615 GEN_SPEFPUOP_CONV(efdcfuf);
6616 GEN_SPEFPUOP_CONV(efdcfsf);
6617 GEN_SPEFPUOP_CONV(efdctui);
6618 GEN_SPEFPUOP_CONV(efdctsi);
6619 GEN_SPEFPUOP_CONV(efdctuf);
6620 GEN_SPEFPUOP_CONV(efdctsf);
6621 GEN_SPEFPUOP_CONV(efdctuiz);
6622 GEN_SPEFPUOP_CONV(efdctsiz);
6623 GEN_SPEFPUOP_CONV(efdcfs);
6624 GEN_SPEFPUOP_CONV(efdcfuid);
6625 GEN_SPEFPUOP_CONV(efdcfsid);
6626 GEN_SPEFPUOP_CONV(efdctuidz);
6627 GEN_SPEFPUOP_CONV(efdctsidz);
6628 /* Comparison */
6629 GEN_SPEOP_COMP(efdcmpgt);
6630 GEN_SPEOP_COMP(efdcmplt);
6631 GEN_SPEOP_COMP(efdcmpeq);
6632 GEN_SPEOP_COMP(efdtstgt);
6633 GEN_SPEOP_COMP(efdtstlt);
6634 GEN_SPEOP_COMP(efdtsteq);
6635
6636 /* Opcodes definitions */
6637 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6638 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6639 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6640 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6641 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6642 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6643 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6644 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6645 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6646 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6647 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6648 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6649 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6650 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6651 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6652 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
6653
6654 /* End opcode list */
6655 GEN_OPCODE_MARK(end);
6656
6657 #include "translate_init.c"
6658 #include "helper_regs.h"
6659
6660 /*****************************************************************************/
6661 /* Misc PowerPC helpers */
6662 void cpu_dump_state (CPUState *env, FILE *f,
6663 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6664 int flags)
6665 {
6666 #define RGPL 4
6667 #define RFPL 4
6668
6669 int i;
6670
6671 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6672 env->nip, env->lr, env->ctr, env->xer);
6673 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6674 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
6675 #if !defined(NO_TIMER_DUMP)
6676 cpu_fprintf(f, "TB %08x %08x "
6677 #if !defined(CONFIG_USER_ONLY)
6678 "DECR %08x"
6679 #endif
6680 "\n",
6681 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6682 #if !defined(CONFIG_USER_ONLY)
6683 , cpu_ppc_load_decr(env)
6684 #endif
6685 );
6686 #endif
6687 for (i = 0; i < 32; i++) {
6688 if ((i & (RGPL - 1)) == 0)
6689 cpu_fprintf(f, "GPR%02d", i);
6690 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
6691 if ((i & (RGPL - 1)) == (RGPL - 1))
6692 cpu_fprintf(f, "\n");
6693 }
6694 cpu_fprintf(f, "CR ");
6695 for (i = 0; i < 8; i++)
6696 cpu_fprintf(f, "%01x", env->crf[i]);
6697 cpu_fprintf(f, " [");
6698 for (i = 0; i < 8; i++) {
6699 char a = '-';
6700 if (env->crf[i] & 0x08)
6701 a = 'L';
6702 else if (env->crf[i] & 0x04)
6703 a = 'G';
6704 else if (env->crf[i] & 0x02)
6705 a = 'E';
6706 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6707 }
6708 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
6709 for (i = 0; i < 32; i++) {
6710 if ((i & (RFPL - 1)) == 0)
6711 cpu_fprintf(f, "FPR%02d", i);
6712 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6713 if ((i & (RFPL - 1)) == (RFPL - 1))
6714 cpu_fprintf(f, "\n");
6715 }
6716 #if !defined(CONFIG_USER_ONLY)
6717 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
6718 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
6719 #endif
6720
6721 #undef RGPL
6722 #undef RFPL
6723 }
6724
6725 void cpu_dump_statistics (CPUState *env, FILE*f,
6726 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6727 int flags)
6728 {
6729 #if defined(DO_PPC_STATISTICS)
6730 opc_handler_t **t1, **t2, **t3, *handler;
6731 int op1, op2, op3;
6732
6733 t1 = env->opcodes;
6734 for (op1 = 0; op1 < 64; op1++) {
6735 handler = t1[op1];
6736 if (is_indirect_opcode(handler)) {
6737 t2 = ind_table(handler);
6738 for (op2 = 0; op2 < 32; op2++) {
6739 handler = t2[op2];
6740 if (is_indirect_opcode(handler)) {
6741 t3 = ind_table(handler);
6742 for (op3 = 0; op3 < 32; op3++) {
6743 handler = t3[op3];
6744 if (handler->count == 0)
6745 continue;
6746 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6747 "%016llx %lld\n",
6748 op1, op2, op3, op1, (op3 << 5) | op2,
6749 handler->oname,
6750 handler->count, handler->count);
6751 }
6752 } else {
6753 if (handler->count == 0)
6754 continue;
6755 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6756 "%016llx %lld\n",
6757 op1, op2, op1, op2, handler->oname,
6758 handler->count, handler->count);
6759 }
6760 }
6761 } else {
6762 if (handler->count == 0)
6763 continue;
6764 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6765 op1, op1, handler->oname,
6766 handler->count, handler->count);
6767 }
6768 }
6769 #endif
6770 }
6771
6772 /*****************************************************************************/
6773 static always_inline void gen_intermediate_code_internal (CPUState *env,
6774 TranslationBlock *tb,
6775 int search_pc)
6776 {
6777 DisasContext ctx, *ctxp = &ctx;
6778 opc_handler_t **table, *handler;
6779 target_ulong pc_start;
6780 uint16_t *gen_opc_end;
6781 int supervisor, little_endian;
6782 int j, lj = -1;
6783 int num_insns;
6784 int max_insns;
6785
6786 pc_start = tb->pc;
6787 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6788 #if defined(OPTIMIZE_FPRF_UPDATE)
6789 gen_fprf_ptr = gen_fprf_buf;
6790 #endif
6791 ctx.nip = pc_start;
6792 ctx.tb = tb;
6793 ctx.exception = POWERPC_EXCP_NONE;
6794 ctx.spr_cb = env->spr_cb;
6795 supervisor = env->mmu_idx;
6796 #if !defined(CONFIG_USER_ONLY)
6797 ctx.supervisor = supervisor;
6798 #endif
6799 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
6800 #if defined(TARGET_PPC64)
6801 ctx.sf_mode = msr_sf;
6802 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
6803 #else
6804 ctx.mem_idx = (supervisor << 1) | little_endian;
6805 #endif
6806 ctx.dcache_line_size = env->dcache_line_size;
6807 ctx.fpu_enabled = msr_fp;
6808 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6809 ctx.spe_enabled = msr_spe;
6810 else
6811 ctx.spe_enabled = 0;
6812 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6813 ctx.altivec_enabled = msr_vr;
6814 else
6815 ctx.altivec_enabled = 0;
6816 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6817 ctx.singlestep_enabled = CPU_SINGLE_STEP;
6818 else
6819 ctx.singlestep_enabled = 0;
6820 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6821 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6822 if (unlikely(env->singlestep_enabled))
6823 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6824 #if defined (DO_SINGLE_STEP) && 0
6825 /* Single step trace mode */
6826 msr_se = 1;
6827 #endif
6828 num_insns = 0;
6829 max_insns = tb->cflags & CF_COUNT_MASK;
6830 if (max_insns == 0)
6831 max_insns = CF_COUNT_MASK;
6832
6833 gen_icount_start();
6834 /* Set env in case of segfault during code fetch */
6835 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
6836 if (unlikely(env->nb_breakpoints > 0)) {
6837 for (j = 0; j < env->nb_breakpoints; j++) {
6838 if (env->breakpoints[j] == ctx.nip) {
6839 gen_update_nip(&ctx, ctx.nip);
6840 gen_op_debug();
6841 break;
6842 }
6843 }
6844 }
6845 if (unlikely(search_pc)) {
6846 j = gen_opc_ptr - gen_opc_buf;
6847 if (lj < j) {
6848 lj++;
6849 while (lj < j)
6850 gen_opc_instr_start[lj++] = 0;
6851 gen_opc_pc[lj] = ctx.nip;
6852 gen_opc_instr_start[lj] = 1;
6853 gen_opc_icount[lj] = num_insns;
6854 }
6855 }
6856 #if defined PPC_DEBUG_DISAS
6857 if (loglevel & CPU_LOG_TB_IN_ASM) {
6858 fprintf(logfile, "----------------\n");
6859 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
6860 ctx.nip, supervisor, (int)msr_ir);
6861 }
6862 #endif
6863 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6864 gen_io_start();
6865 if (unlikely(little_endian)) {
6866 ctx.opcode = bswap32(ldl_code(ctx.nip));
6867 } else {
6868 ctx.opcode = ldl_code(ctx.nip);
6869 }
6870 #if defined PPC_DEBUG_DISAS
6871 if (loglevel & CPU_LOG_TB_IN_ASM) {
6872 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6873 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
6874 opc3(ctx.opcode), little_endian ? "little" : "big");
6875 }
6876 #endif
6877 ctx.nip += 4;
6878 table = env->opcodes;
6879 num_insns++;
6880 handler = table[opc1(ctx.opcode)];
6881 if (is_indirect_opcode(handler)) {
6882 table = ind_table(handler);
6883 handler = table[opc2(ctx.opcode)];
6884 if (is_indirect_opcode(handler)) {
6885 table = ind_table(handler);
6886 handler = table[opc3(ctx.opcode)];
6887 }
6888 }
6889 /* Is opcode *REALLY* valid ? */
6890 if (unlikely(handler->handler == &gen_invalid)) {
6891 if (loglevel != 0) {
6892 fprintf(logfile, "invalid/unsupported opcode: "
6893 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
6894 opc1(ctx.opcode), opc2(ctx.opcode),
6895 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6896 } else {
6897 printf("invalid/unsupported opcode: "
6898 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
6899 opc1(ctx.opcode), opc2(ctx.opcode),
6900 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6901 }
6902 } else {
6903 if (unlikely((ctx.opcode & handler->inval) != 0)) {
6904 if (loglevel != 0) {
6905 fprintf(logfile, "invalid bits: %08x for opcode: "
6906 "%02x - %02x - %02x (%08x) " ADDRX "\n",
6907 ctx.opcode & handler->inval, opc1(ctx.opcode),
6908 opc2(ctx.opcode), opc3(ctx.opcode),
6909 ctx.opcode, ctx.nip - 4);
6910 } else {
6911 printf("invalid bits: %08x for opcode: "
6912 "%02x - %02x - %02x (%08x) " ADDRX "\n",
6913 ctx.opcode & handler->inval, opc1(ctx.opcode),
6914 opc2(ctx.opcode), opc3(ctx.opcode),
6915 ctx.opcode, ctx.nip - 4);
6916 }
6917 GEN_EXCP_INVAL(ctxp);
6918 break;
6919 }
6920 }
6921 (*(handler->handler))(&ctx);
6922 #if defined(DO_PPC_STATISTICS)
6923 handler->count++;
6924 #endif
6925 /* Check trace mode exceptions */
6926 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6927 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6928 ctx.exception != POWERPC_SYSCALL &&
6929 ctx.exception != POWERPC_EXCP_TRAP &&
6930 ctx.exception != POWERPC_EXCP_BRANCH)) {
6931 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6932 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6933 (env->singlestep_enabled) ||
6934 num_insns >= max_insns)) {
6935 /* if we reach a page boundary or are single stepping, stop
6936 * generation
6937 */
6938 break;
6939 }
6940 #if defined (DO_SINGLE_STEP)
6941 break;
6942 #endif
6943 }
6944 if (tb->cflags & CF_LAST_IO)
6945 gen_io_end();
6946 if (ctx.exception == POWERPC_EXCP_NONE) {
6947 gen_goto_tb(&ctx, 0, ctx.nip);
6948 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
6949 if (unlikely(env->singlestep_enabled)) {
6950 gen_update_nip(&ctx, ctx.nip);
6951 gen_op_debug();
6952 }
6953 /* Generate the return instruction */
6954 tcg_gen_exit_tb(0);
6955 }
6956 gen_icount_end(tb, num_insns);
6957 *gen_opc_ptr = INDEX_op_end;
6958 if (unlikely(search_pc)) {
6959 j = gen_opc_ptr - gen_opc_buf;
6960 lj++;
6961 while (lj <= j)
6962 gen_opc_instr_start[lj++] = 0;
6963 } else {
6964 tb->size = ctx.nip - pc_start;
6965 tb->icount = num_insns;
6966 }
6967 #if defined(DEBUG_DISAS)
6968 if (loglevel & CPU_LOG_TB_CPU) {
6969 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
6970 cpu_dump_state(env, logfile, fprintf, 0);
6971 }
6972 if (loglevel & CPU_LOG_TB_IN_ASM) {
6973 int flags;
6974 flags = env->bfd_mach;
6975 flags |= little_endian << 16;
6976 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6977 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
6978 fprintf(logfile, "\n");
6979 }
6980 #endif
6981 }
6982
6983 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
6984 {
6985 gen_intermediate_code_internal(env, tb, 0);
6986 }
6987
6988 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
6989 {
6990 gen_intermediate_code_internal(env, tb, 1);
6991 }
6992
6993 void gen_pc_load(CPUState *env, TranslationBlock *tb,
6994 unsigned long searched_pc, int pc_pos, void *puc)
6995 {
6996 int type, c;
6997 /* for PPC, we need to look at the micro operation to get the
6998 * access type */
6999 env->nip = gen_opc_pc[pc_pos];
7000 c = gen_opc_buf[pc_pos];
7001 switch(c) {
7002 #if defined(CONFIG_USER_ONLY)
7003 #define CASE3(op)\
7004 case INDEX_op_ ## op ## _raw
7005 #else
7006 #define CASE3(op)\
7007 case INDEX_op_ ## op ## _user:\
7008 case INDEX_op_ ## op ## _kernel:\
7009 case INDEX_op_ ## op ## _hypv
7010 #endif
7011
7012 CASE3(stfd):
7013 CASE3(stfs):
7014 CASE3(lfd):
7015 CASE3(lfs):
7016 type = ACCESS_FLOAT;
7017 break;
7018 CASE3(lwarx):
7019 type = ACCESS_RES;
7020 break;
7021 CASE3(stwcx):
7022 type = ACCESS_RES;
7023 break;
7024 CASE3(eciwx):
7025 CASE3(ecowx):
7026 type = ACCESS_EXT;
7027 break;
7028 default:
7029 type = ACCESS_INT;
7030 break;
7031 }
7032 env->access_type = type;
7033 }
Samsung s3c2440 and arm920t support for the mini2440 dev board