hw/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "sh.h"
  28 #include "devices.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31
  32 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  33 #define SDRAM_SIZE 0x04000000
  34
  35 #define SM501_VRAM_SIZE 0x800000
  36
  37 #define PA_POWOFF       0x30
  38 #define PA_VERREG       0x32
  39 #define PA_OUTPORT      0x36
  40
  41 typedef struct {
  42     target_phys_addr_t base;
  43
  44     uint16_t bcr;
  45     uint16_t irlmon;
  46     uint16_t cfctl;
  47     uint16_t cfpow;
  48     uint16_t dispctl;
  49     uint16_t sdmpow;
  50     uint16_t rtcce;
  51     uint16_t pcicd;
  52     uint16_t voyagerrts;
  53     uint16_t cfrst;
  54     uint16_t admrts;
  55     uint16_t extrst;
  56     uint16_t cfcdintclr;
  57     uint16_t keyctlclr;
  58     uint16_t pad0;
  59     uint16_t pad1;
  60     uint16_t powoff;
  61     uint16_t verreg;
  62     uint16_t inport;
  63     uint16_t outport;
  64     uint16_t bverreg;
  65 } r2d_fpga_t;
  66
  67 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
  68 {
  69     r2d_fpga_t *s = opaque;
  70
  71     addr -= s->base;
  72
  73     switch (addr) {
  74     case PA_OUTPORT:
  75         return s->outport;
  76     case PA_POWOFF:
  77         return s->powoff;
  78     case PA_VERREG:
  79         return 0x10;
  80     }
  81
  82     return 0;
  83 }
  84
  85 static void
  86 r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
  87 {
  88     r2d_fpga_t *s = opaque;
  89
  90     addr -= s->base;
  91
  92     switch (addr) {
  93     case PA_OUTPORT:
  94         s->outport = value;
  95         break;
  96     case PA_POWOFF:
  97         s->powoff = value;
  98         break;
  99     case PA_VERREG:
 100         /* Discard writes */
 101         break;
 102     }
 103 }
 104
 105 static CPUReadMemoryFunc *r2d_fpga_readfn[] = {
 106     r2d_fpga_read,
 107     r2d_fpga_read,
 108     NULL,
 109 };
 110
 111 static CPUWriteMemoryFunc *r2d_fpga_writefn[] = {
 112     r2d_fpga_write,
 113     r2d_fpga_write,
 114     NULL,
 115 };
 116
 117 static void r2d_fpga_init(target_phys_addr_t base)
 118 {
 119     int iomemtype;
 120     r2d_fpga_t *s;
 121
 122     s = qemu_mallocz(sizeof(r2d_fpga_t));
 123     if (!s)
 124         return;
 125
 126     s->base = base;
 127     iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
 128                                        r2d_fpga_writefn, s);
 129     cpu_register_physical_memory(base, 0x40, iomemtype);
 130 }
 131
 132 static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
 133               const char *boot_device, DisplayState * ds,
 134               const char *kernel_filename, const char *kernel_cmdline,
 135               const char *initrd_filename, const char *cpu_model)
 136 {
 137     CPUState *env;
 138     struct SH7750State *s;
 139     ram_addr_t sdram_addr, sm501_vga_ram_addr;
 140
 141     if (!cpu_model)
 142         cpu_model = "SH7751R";
 143
 144     env = cpu_init(cpu_model);
 145     if (!env) {
 146         fprintf(stderr, "Unable to find CPU definition\n");
 147         exit(1);
 148     }
 149
 150     /* Allocate memory space */
 151     sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
 152     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
 153     /* Register peripherals */
 154     r2d_fpga_init(0x04000000);
 155     s = sh7750_init(env);
 156     sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
 157     sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
 158                serial_hds[2]);
 159     /* Todo: register on board registers */
 160     {
 161       int kernel_size;
 162
 163       kernel_size = load_image(kernel_filename, phys_ram_base);
 164
 165       if (kernel_size < 0) {
 166         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 167         exit(1);
 168       }
 169
 170       env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
 171     }
 172 }
 173
 174 QEMUMachine r2d_machine = {
 175     .name = "r2d",
 176     .desc = "r2d-plus board",
 177     .init = r2d_init,
 178     .ram_require = (SDRAM_SIZE + SM501_VRAM_SIZE) | RAMSIZE_FIXED,
 179 };