hw/s3c24xx_lcd.c

   1 /*
   2  * Samsung S3C24xx series LCD controller.
   3  *
   4  * Copyright (c) 2007 OpenMoko, Inc.
   5  * Author: Andrzej Zaborowski <andrew@openedhand.com>
   6  *
   7  * This code is licenced under the GNU GPL v2.
   8  */
   9
  10 #include "s3c.h"
  11 #include "hw.h"
  12 #include "console.h"
  13
  14 typedef void (*s3c_drawfn_t)(uint32_t *, uint8_t *, const uint8_t *, int, int);
  15
  16 struct s3c_lcd_state_s {
  17     target_phys_addr_t base;
  18     void *irq;
  19     DisplayState *ds;
  20     s3c_drawfn_t *line_fn;
  21
  22     uint32_t con[5];
  23     uint32_t saddr[3];
  24     uint32_t r;
  25     uint32_t g;
  26     uint16_t b;
  27     uint32_t dithmode;
  28     uint32_t tpal;
  29     uint8_t intpnd;
  30     uint8_t srcpnd;
  31     uint8_t intmsk;
  32     uint8_t lpcsel;
  33
  34     uint16_t raw_pal[0x100];
  35
  36     int width;
  37     int height;
  38     int bpp;
  39     int enable;
  40     int msb;
  41     int frm565;
  42     void *fb;
  43     uint32_t palette[0x100];
  44     int invalidate;
  45     int invalidatep;
  46     int src_width;
  47     int dest_width;
  48     s3c_drawfn_t fn;
  49 };
  50
  51 static void s3c_lcd_update(struct s3c_lcd_state_s *s)
  52 {
  53     s->intpnd |= s->srcpnd & ~s->intmsk;
  54     qemu_set_irq(s->irq, !!s->intpnd);
  55 }
  56
  57 void s3c_lcd_reset(struct s3c_lcd_state_s *s)
  58 {
  59     s->enable = 0;
  60     s->invalidate = 1;
  61     s->invalidatep = 1;
  62     s->width = -1;
  63     s->height = -1;
  64
  65     s->con[0] = 0x00000000;
  66     s->con[1] = 0x00000000;
  67     s->con[2] = 0x00000000;
  68     s->con[3] = 0x00000000;
  69     s->con[4] = 0x00000000;
  70     s->saddr[0] = 0x00000000;
  71     s->saddr[1] = 0x00000000;
  72     s->saddr[2] = 0x00000000;
  73     s->r = 0x00000000;
  74     s->g = 0x00000000;
  75     s->b = 0x0000;
  76     s->dithmode = 0x00000;
  77     s->tpal = 0x00000000;
  78     s->intpnd = 0;
  79     s->srcpnd = 0;
  80     s->intmsk = 3;
  81     s->lpcsel = 4;
  82     s3c_lcd_update(s);
  83 }
  84
  85 #define S3C_LCDCON1     0x00    /* LCD Control register 1 */
  86 #define S3C_LCDCON2     0x04    /* LCD Control register 2 */
  87 #define S3C_LCDCON3     0x08    /* LCD Control register 3 */
  88 #define S3C_LCDCON4     0x0c    /* LCD Control register 4 */
  89 #define S3C_LCDCON5     0x10    /* LCD Control register 5 */
  90 #define S3C_LCDSADDR1   0x14    /* Framebuffer Start Address 1 register */
  91 #define S3C_LCDSADDR2   0x18    /* Framebuffer Start Address 2 register */
  92 #define S3C_LCDSADDR3   0x1c    /* Framebuffer Start Address 3 register */
  93 #define S3C_REDLUT      0x20    /* Red Lookup Table register */
  94 #define S3C_GREENLUT    0x24    /* Green Lookup Table register */
  95 #define S3C_BLUELUT     0x28    /* Blue Lookup Table register */
  96 #define S3C_DITHMODE    0x4c    /* Dithering Mode register */
  97 #define S3C_TPAL        0x50    /* Temporary Palette register */
  98 #define S3C_LCDINTPND   0x54    /* LCD Interrupt Pending register */
  99 #define S3C_LCDSRCPND   0x58    /* LCD Interrupt Source Pending register */
 100 #define S3C_LCDINTMSK   0x5c    /* LCD Interrupt Mask register */
 101 #define S3C_LPCSEL      0x60    /* LPC3600 Control register */
 102
 103 #define S3C_PALETTE     0x400   /* Palette IO start offset */
 104 #define S3C_PALETTEEND  0x5ff   /* Palette IO end offset */
 105
 106 static uint32_t s3c_lcd_read(void *opaque, target_phys_addr_t addr)
 107 {
 108     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 109
 110     switch (addr) {
 111     case S3C_LCDCON1:
 112         return s->con[0];               /* XXX Return random LINECNT? */
 113     case S3C_LCDCON2:
 114         return s->con[1];
 115     case S3C_LCDCON3:
 116         return s->con[2];
 117     case S3C_LCDCON4:
 118         return s->con[3];
 119     case S3C_LCDCON5:
 120         return s->con[4];               /* XXX Return random STATUS? */
 121     case S3C_LCDSADDR1:
 122         return s->saddr[0];
 123     case S3C_LCDSADDR2:
 124         return s->saddr[1];
 125     case S3C_LCDSADDR3:
 126         return s->saddr[2];
 127     case S3C_REDLUT:
 128         return s->r;
 129     case S3C_GREENLUT:
 130         return s->g;
 131     case S3C_BLUELUT:
 132         return s->b;
 133     case S3C_DITHMODE:
 134         return s->dithmode;
 135     case S3C_TPAL:
 136         return s->tpal;
 137     case S3C_LCDINTPND:
 138         return s->intpnd;
 139     case S3C_LCDSRCPND:
 140         return s->srcpnd;
 141     case S3C_LCDINTMSK:
 142         return s->intmsk;
 143     case S3C_LPCSEL:
 144         return s->lpcsel;
 145     case S3C_PALETTE ... S3C_PALETTEEND:
 146         /* XXX assuming 16bit access */
 147         return s->raw_pal[(addr - S3C_PALETTE) >> 1];
 148     default:
 149         printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
 150         break;
 151     }
 152     return 0;
 153 }
 154
 155 static void s3c_lcd_write(void *opaque, target_phys_addr_t addr,
 156                 uint32_t value)
 157 {
 158     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 159
 160     switch (addr) {
 161     case S3C_LCDCON1:
 162         s->con[0] = value & 0x0003ffff;
 163         s->enable = value & 1;
 164         s->bpp = (value >> 1) & 0xf;
 165         s->invalidate = 1;
 166         s->invalidatep = 1;
 167         break;
 168     case S3C_LCDCON2:
 169         s->con[1] = value;
 170         s->invalidate = 1;
 171         break;
 172     case S3C_LCDCON3:
 173         s->con[2] = value;
 174         s->invalidate = 1;
 175         break;
 176     case S3C_LCDCON4:
 177         s->con[3] = value & 0xffff;
 178         break;
 179     case S3C_LCDCON5:
 180         s->con[4] = value & 0x1fff;
 181         s->frm565 = (value >> 11) & 1;
 182         s->msb = (value >> 12) & 1;
 183         s->invalidatep = 1;
 184         s->invalidate = 1;
 185         break;
 186     case S3C_LCDSADDR1:
 187         s->saddr[0] = value;
 188         s->fb = phys_ram_base +
 189                 (((s->saddr[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE);
 190         s->invalidate = 1;
 191         break;
 192     case S3C_LCDSADDR2:
 193         s->saddr[1] = value;
 194         s->invalidate = 1;
 195         break;
 196     case S3C_LCDSADDR3:
 197         s->saddr[2] = value;
 198         s->invalidate = 1;
 199         break;
 200     case S3C_REDLUT:
 201         s->r = value;
 202         s->invalidatep = 1;
 203         s->invalidate = 1;
 204         break;
 205     case S3C_GREENLUT:
 206         s->g = value;
 207         s->invalidatep = 1;
 208         s->invalidate = 1;
 209         break;
 210     case S3C_BLUELUT:
 211         s->b = value;
 212         s->invalidatep = 1;
 213         s->invalidate = 1;
 214         break;
 215     case S3C_DITHMODE:
 216         s->dithmode = value;
 217         break;
 218     case S3C_TPAL:
 219         s->tpal = value;
 220         s->invalidatep = 1;
 221         s->invalidate = 1;
 222         break;
 223     case S3C_LCDINTPND:
 224         s->intpnd = value & 3;
 225         break;
 226     case S3C_LCDSRCPND:
 227         s->srcpnd = value & 3;
 228         break;
 229     case S3C_LCDINTMSK:
 230         s->intmsk = value & 7;
 231         s3c_lcd_update(s);
 232         break;
 233     case S3C_LPCSEL:
 234         s->lpcsel = (value & 3) | 4;
 235         if (value & 1)
 236             printf("%s: attempt to enable LPC3600\n", __FUNCTION__);
 237         break;
 238     case S3C_PALETTE ... S3C_PALETTEEND:
 239         /* XXX assuming 16bit access */
 240         s->raw_pal[(addr - S3C_PALETTE) >> 1] = value;
 241         break;
 242     default:
 243         printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
 244     }
 245 }
 246
 247 static CPUReadMemoryFunc *s3c_lcd_readfn[] = {
 248     s3c_lcd_read,
 249     s3c_lcd_read,
 250     s3c_lcd_read,
 251 };
 252
 253 static CPUWriteMemoryFunc *s3c_lcd_writefn[] = {
 254     s3c_lcd_write,
 255     s3c_lcd_write,
 256     s3c_lcd_write,
 257 };
 258
 259 static inline void s3c_lcd_resize(struct s3c_lcd_state_s *s)
 260 {
 261     int new_width, new_height;
 262     new_height = ((s->con[1] >> 14) & 0x3ff) + 1;
 263     new_width = ((s->con[2] >> 8) & 0x7ff) + 1;
 264     if (s->width != new_width || s->height != new_height) {
 265         s->width = new_width;
 266         s->height = new_height;
 267        // dpy_resize(s->ds, s->width, s->height);
 268         qemu_console_resize(s->ds, s->width, s->height);
 269         s->invalidate = 1;
 270     }
 271 }
 272
 273 static inline
 274 uint32_t s3c_rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
 275 {
 276     return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
 277 }
 278
 279 static inline
 280 uint32_t s3c_rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
 281 {
 282     return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
 283 }
 284
 285 static inline
 286 uint32_t s3c_rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
 287 {
 288     return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
 289 }
 290
 291 static inline
 292 uint32_t s3c_rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
 293 {
 294     return (r << 16) | (g << 8) | b;
 295 }
 296
 297 static inline
 298 uint32_t s3c_rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
 299 {
 300     return (r << 16) | (g << 8) | b;
 301 }
 302
 303 static inline uint32_t s3c_rgb(struct s3c_lcd_state_s *s,
 304                 unsigned int r, unsigned int g, unsigned b)
 305 {
 306     switch (ds_get_bits_per_pixel(s->ds)) {
 307     case 8:
 308         return s3c_rgb_to_pixel32(r << 2, g << 2, b << 2);
 309     case 15:
 310         return s3c_rgb_to_pixel15(r << 2, g << 2, b << 2);
 311     case 16:
 312         return s3c_rgb_to_pixel16(r << 2, g << 2, b << 2);
 313     case 24:
 314         return s3c_rgb_to_pixel24(r << 2, g << 2, b << 2);
 315     case 32:
 316         return s3c_rgb_to_pixel32(r << 2, g << 2, b << 2);
 317     default:
 318         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 319         exit(1);
 320     }
 321 }
 322
 323 static void s3c_lcd_palette_load(struct s3c_lcd_state_s *s)
 324 {
 325     int i, n;
 326     switch (s->bpp) {
 327     case 0:
 328     case 8:
 329         n = 2;
 330         s->src_width = s->width >> 3;
 331         s->fn = s->line_fn[0];
 332         break;
 333     case 1:
 334     case 9:
 335         n = 4;
 336         s->src_width = s->width >> 2;
 337         s->fn = s->line_fn[1];
 338         break;
 339     case 2:
 340     case 10:
 341         n = 16;
 342         s->src_width = s->width >> 1;
 343         s->fn = s->line_fn[2];
 344         break;
 345     case 3:
 346     case 11:
 347         n = 256;
 348         s->src_width = s->width >> 0;
 349         s->fn = s->line_fn[3];
 350         break;
 351     case 6:
 352         s->src_width = (s->width * 3) >> 1;
 353         s->fn = s->line_fn[4];
 354         return;
 355     case 12:
 356         s->src_width = s->width << 1;
 357         if (s->frm565)
 358             s->fn = s->line_fn[5];
 359         else
 360             s->fn = s->line_fn[6];
 361         return;
 362     case 13:
 363         s->src_width = s->width << 2;
 364         s->fn = s->line_fn[7];
 365         return;
 366     default:
 367         return;
 368     }
 369     if (s->bpp & 8) {
 370         for (i = 0; i < n; i ++)
 371             if (s->frm565)
 372                 s->palette[i] = s3c_rgb(s,
 373                         (s->raw_pal[i] >> 10) & 0x3e,
 374                         (s->raw_pal[i] >> 5) & 0x3f,
 375                         (s->raw_pal[i] << 1) & 0x3e);
 376             else
 377                 s->palette[i] = s3c_rgb(s,
 378                         ((s->raw_pal[i] >> 10) & 0x3e) | (s->raw_pal[i] & 1),
 379                         ((s->raw_pal[i] >> 6) & 0x3e) | (s->raw_pal[i] & 1),
 380                         s->raw_pal[i] & 0x3f);
 381     } else {
 382         for (i = 0; i < n; i ++)
 383             if (n < 256)
 384                 s->palette[i] = s3c_rgb(s,
 385                         ((s->r >> (i * 4)) & 0xf) << 2,
 386                         ((s->g >> (i * 4)) & 0xf) << 2,
 387                         ((s->b >> (i * 4)) & 0xf) << 2);
 388             else
 389                 s->palette[i] = s3c_rgb(s,
 390                         ((s->r >> (((i >> 5) & 7) * 4)) & 0xf) << 2,
 391                         ((s->g >> (((i >> 2) & 7) * 4)) & 0xf) << 2,
 392                         ((s->b >> ((i & 3) * 4)) & 0xf) << 2);
 393     }
 394 }
 395
 396 static void s3c_update_display(void *opaque)
 397 {
 398     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 399     int y, src_width, dest_width, dirty[2], miny, maxy;
 400     ram_addr_t x, addr, new_addr, start, end;
 401     uint8_t *src, *dest;
 402     if (!s->enable || !s->dest_width)
 403         return;
 404
 405     s3c_lcd_resize(s);
 406
 407     if (s->invalidatep) {
 408         s3c_lcd_palette_load(s);
 409         s->invalidatep = 0;
 410     }
 411
 412     src = s->fb;
 413     src_width = s->src_width;
 414
 415     dest = ds_get_data(s->ds);
 416     dest_width = s->width * s->dest_width;
 417
 418     addr = (ram_addr_t) (s->fb - (void *) phys_ram_base);
 419     start = addr + s->height * src_width;
 420     end = addr;
 421     dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
 422     miny = s->height;
 423     maxy = 0;
 424     for (y = 0; y < s->height; y ++) {
 425         new_addr = addr + src_width;
 426         for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
 427                         x += TARGET_PAGE_SIZE) {
 428             dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
 429             dirty[0] |= dirty[1];
 430         }
 431         if (dirty[0] || s->invalidate) {
 432             s->fn(s->palette, dest, src, s->width, s->dest_width);
 433             maxy = y;
 434             end = new_addr;
 435             if (y < miny) {
 436                 miny = y;
 437                 start = addr;
 438             }
 439         }
 440         addr = new_addr;
 441         dirty[0] = dirty[1];
 442         src += src_width;
 443         dest += dest_width;
 444     }
 445
 446     s->invalidate = 0;
 447     if (end > start)
 448         cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
 449     s->srcpnd |= (1 << 1);                      /* INT_FrSyn */
 450     s3c_lcd_update(s);
 451     dpy_update(s->ds, 0, miny, s->width, maxy);
 452 }
 453
 454 static void s3c_invalidate_display(void *opaque)
 455 {
 456     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 457     s->invalidate = 1;
 458 }
 459
 460 static void s3c_screen_dump(void *opaque, const char *filename)
 461 {
 462     /* TODO */
 463 }
 464
 465 #define BITS 8
 466 #include "s3c24xx_template.h"
 467 #define BITS 15
 468 #include "s3c24xx_template.h"
 469 #define BITS 16
 470 #include "s3c24xx_template.h"
 471 #define BITS 24
 472 #include "s3c24xx_template.h"
 473 #define BITS 32
 474 #include "s3c24xx_template.h"
 475
 476 static void s3c_lcd_save(QEMUFile *f, void *opaque)
 477 {
 478     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 479     int i;
 480     for (i = 0; i < 5; i ++)
 481         qemu_put_be32s(f, &s->con[i]);
 482     for (i = 0; i < 3; i ++)
 483         qemu_put_be32s(f, &s->saddr[i]);
 484     qemu_put_be32s(f, &s->r);
 485     qemu_put_be32s(f, &s->g);
 486     qemu_put_be16s(f, &s->b);
 487     qemu_put_be32s(f, &s->dithmode);
 488     qemu_put_be32s(f, &s->tpal);
 489     qemu_put_8s(f, &s->intpnd);
 490     qemu_put_8s(f, &s->srcpnd);
 491     qemu_put_8s(f, &s->intmsk);
 492     qemu_put_8s(f, &s->lpcsel);
 493     for (i = 0; i < 0x100; i ++)
 494         qemu_put_be16s(f, &s->raw_pal[i]);
 495 }
 496
 497 static int s3c_lcd_load(QEMUFile *f, void *opaque, int version_id)
 498 {
 499     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 500     int i;
 501     for (i = 0; i < 5; i ++)
 502         qemu_get_be32s(f, &s->con[i]);
 503     for (i = 0; i < 3; i ++)
 504         qemu_get_be32s(f, &s->saddr[i]);
 505     qemu_get_be32s(f, &s->r);
 506     qemu_get_be32s(f, &s->g);
 507     qemu_get_be16s(f, &s->b);
 508     qemu_get_be32s(f, &s->dithmode);
 509     qemu_get_be32s(f, &s->tpal);
 510     qemu_get_8s(f, &s->intpnd);
 511     qemu_get_8s(f, &s->srcpnd);
 512     qemu_get_8s(f, &s->intmsk);
 513     qemu_get_8s(f, &s->lpcsel);
 514
 515     s->invalidate = 1;
 516     s->invalidatep = 1;
 517     s->width = -1;
 518     s->height = -1;
 519     s->bpp = (s->con[0] >> 1) & 0xf;
 520     s->enable = s->con[0] & 1;
 521     s->msb = (s->con[4] >> 12) & 1;
 522     s->frm565 = (s->con[4] >> 11) & 1;
 523     s->fb = phys_ram_base + (((s->saddr[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE);
 524
 525     for (i = 0; i < 0x100; i ++)
 526         qemu_get_be16s(f, &s->raw_pal[i]);
 527
 528     return 0;
 529 }
 530
 531 struct s3c_lcd_state_s *s3c_lcd_init(target_phys_addr_t base,
 532                 qemu_irq irq)
 533 {
 534     int iomemtype;
 535     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *)
 536             qemu_mallocz(sizeof(struct s3c_lcd_state_s));
 537
 538     s->base = base;
 539     s->irq = irq;
 540
 541     s3c_lcd_reset(s);
 542
 543     s->ds = graphic_console_init(
 544                                 s3c_update_display,
 545                     s3c_invalidate_display,
 546                     s3c_screen_dump, NULL, s);
 547
 548     iomemtype = cpu_register_io_memory(0, s3c_lcd_readfn,
 549                     s3c_lcd_writefn, s);
 550     cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
 551
 552     register_savevm("s3c24xx_lcd", 0, 0, s3c_lcd_save, s3c_lcd_load, s);
 553
 554     switch (ds_get_bits_per_pixel(s->ds)) {
 555     case 0:
 556         s->dest_width = 0;
 557         break;
 558     case 8:
 559         s->line_fn = s3c_draw_fn_8;
 560         s->dest_width = 1;
 561         break;
 562     case 15:
 563         s->line_fn = s3c_draw_fn_15;
 564         s->dest_width = 2;
 565         break;
 566     case 16:
 567         s->line_fn = s3c_draw_fn_16;
 568         s->dest_width = 2;
 569         break;
 570     case 24:
 571         s->line_fn = s3c_draw_fn_24;
 572         s->dest_width = 3;
 573         break;
 574     case 32:
 575         s->line_fn = s3c_draw_fn_32;
 576         s->dest_width = 4;
 577         break;
 578     default:
 579         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 580         exit(1);
 581     }
 582     return s;
 583 }