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Account for MacOS X ABI reserved space in linkage area (Andreas Faerber)
[qemu/mini2440.git] / tcg / ppc / tcg-target.c
blob0fe3021e8fcce4467c2e79b7ff4769d616e388fb
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #ifdef __APPLE__
28 #define LINKAGE_AREA_SIZE 24
29 #define BACK_CHAIN_OFFSET 8
30 #else
31 #define LINKAGE_AREA_SIZE 8
32 #define BACK_CHAIN_OFFSET 4
33 #endif
34
35 #define FAST_PATH
36 #if TARGET_PHYS_ADDR_BITS <= 32
37 #define ADDEND_OFFSET 0
38 #else
39 #define ADDEND_OFFSET 4
40 #endif
41
42 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
43 "r0",
44 "r1",
45 "rp",
46 "r3",
47 "r4",
48 "r5",
49 "r6",
50 "r7",
51 "r8",
52 "r9",
53 "r10",
54 "r11",
55 "r12",
56 "r13",
57 "r14",
58 "r15",
59 "r16",
60 "r17",
61 "r18",
62 "r19",
63 "r20",
64 "r21",
65 "r22",
66 "r23",
67 "r24",
68 "r25",
69 "r26",
70 "r27",
71 "r28",
72 "r29",
73 "r30",
74 "r31"
75 };
76
77 static const int tcg_target_reg_alloc_order[] = {
78 TCG_REG_R14,
79 TCG_REG_R15,
80 TCG_REG_R16,
81 TCG_REG_R17,
82 TCG_REG_R18,
83 TCG_REG_R19,
84 TCG_REG_R20,
85 TCG_REG_R21,
86 TCG_REG_R22,
87 TCG_REG_R23,
88 TCG_REG_R28,
89 TCG_REG_R29,
90 TCG_REG_R30,
91 TCG_REG_R31,
92 #ifdef __APPLE__
93 TCG_REG_R2,
94 #endif
95 TCG_REG_R3,
96 TCG_REG_R4,
97 TCG_REG_R5,
98 TCG_REG_R6,
99 TCG_REG_R7,
100 TCG_REG_R8,
101 TCG_REG_R9,
102 TCG_REG_R10,
103 #ifndef __APPLE__
104 TCG_REG_R11,
105 #endif
106 TCG_REG_R12,
107 TCG_REG_R13,
108 TCG_REG_R0,
109 TCG_REG_R1,
110 TCG_REG_R2,
111 TCG_REG_R24,
112 TCG_REG_R25,
113 TCG_REG_R26,
114 TCG_REG_R27
115 };
116
117 static const int tcg_target_call_iarg_regs[] = {
118 TCG_REG_R3,
119 TCG_REG_R4,
120 TCG_REG_R5,
121 TCG_REG_R6,
122 TCG_REG_R7,
123 TCG_REG_R8,
124 TCG_REG_R9,
125 TCG_REG_R10
126 };
127
128 static const int tcg_target_call_oarg_regs[2] = {
129 TCG_REG_R3,
130 TCG_REG_R4
131 };
132
133 static const int tcg_target_callee_save_regs[] = {
134 #ifdef __APPLE__
135 TCG_REG_R11,
136 TCG_REG_R13,
137 #endif
138 TCG_REG_R14,
139 TCG_REG_R15,
140 TCG_REG_R16,
141 TCG_REG_R17,
142 TCG_REG_R18,
143 TCG_REG_R19,
144 TCG_REG_R20,
145 TCG_REG_R21,
146 TCG_REG_R22,
147 TCG_REG_R23,
148 TCG_REG_R28,
149 TCG_REG_R29,
150 TCG_REG_R30,
151 TCG_REG_R31
152 };
153
154 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
155 {
156 tcg_target_long disp;
157
158 disp = target - (tcg_target_long) pc;
159 if ((disp << 6) >> 6 != disp)
160 tcg_abort ();
161
162 return disp & 0x3fffffc;
163 }
164
165 static void reloc_pc24 (void *pc, tcg_target_long target)
166 {
167 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
168 | reloc_pc24_val (pc, target);
169 }
170
171 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
172 {
173 tcg_target_long disp;
174
175 disp = target - (tcg_target_long) pc;
176 if (disp != (int16_t) disp)
177 tcg_abort ();
178
179 return disp & 0xfffc;
180 }
181
182 static void reloc_pc14 (void *pc, tcg_target_long target)
183 {
184 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
185 | reloc_pc14_val (pc, target);
186 }
187
188 static void patch_reloc(uint8_t *code_ptr, int type,
189 tcg_target_long value, tcg_target_long addend)
190 {
191 value += addend;
192 switch (type) {
193 case R_PPC_REL14:
194 reloc_pc14 (code_ptr, value);
195 break;
196 case R_PPC_REL24:
197 reloc_pc24 (code_ptr, value);
198 break;
199 default:
200 tcg_abort();
201 }
202 }
203
204 /* maximum number of register used for input function arguments */
205 static int tcg_target_get_call_iarg_regs_count(int flags)
206 {
207 return sizeof (tcg_target_call_iarg_regs) / sizeof (tcg_target_call_iarg_regs[0]);
208 }
209
210 /* parse target specific constraints */
211 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
212 {
213 const char *ct_str;
214
215 ct_str = *pct_str;
216 switch (ct_str[0]) {
217 case 'A': case 'B': case 'C': case 'D':
218 ct->ct |= TCG_CT_REG;
219 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
220 break;
221 case 'r':
222 ct->ct |= TCG_CT_REG;
223 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
224 break;
225 case 'L': /* qemu_ld constraint */
226 ct->ct |= TCG_CT_REG;
227 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
228 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
229 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
230 break;
231 case 'K': /* qemu_st[8..32] constraint */
232 ct->ct |= TCG_CT_REG;
233 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
234 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
235 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
236 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
237 #if TARGET_LONG_BITS == 64
238 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
239 #endif
240 break;
241 case 'M': /* qemu_st64 constraint */
242 ct->ct |= TCG_CT_REG;
243 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
244 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
245 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
246 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
247 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
248 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
249 break;
250 default:
251 return -1;
252 }
253 ct_str++;
254 *pct_str = ct_str;
255 return 0;
256 }
257
258 /* test if a constant matches the constraint */
259 static int tcg_target_const_match(tcg_target_long val,
260 const TCGArgConstraint *arg_ct)
261 {
262 int ct;
263
264 ct = arg_ct->ct;
265 if (ct & TCG_CT_CONST)
266 return 1;
267 return 0;
268 }
269
270 #define OPCD(opc) ((opc)<<26)
271 #define XO31(opc) (OPCD(31)|((opc)<<1))
272 #define XO19(opc) (OPCD(19)|((opc)<<1))
273
274 #define B OPCD(18)
275 #define BC OPCD(16)
276 #define LBZ OPCD(34)
277 #define LHZ OPCD(40)
278 #define LHA OPCD(42)
279 #define LWZ OPCD(32)
280 #define STB OPCD(38)
281 #define STH OPCD(44)
282 #define STW OPCD(36)
283
284 #define ADDI OPCD(14)
285 #define ADDIS OPCD(15)
286 #define ORI OPCD(24)
287 #define ORIS OPCD(25)
288 #define XORI OPCD(26)
289 #define XORIS OPCD(27)
290 #define ANDI OPCD(28)
291 #define ANDIS OPCD(29)
292 #define MULLI OPCD( 7)
293 #define CMPLI OPCD(10)
294 #define CMPI OPCD(11)
295
296 #define LWZU OPCD(33)
297 #define STWU OPCD(37)
298
299 #define RLWINM OPCD(21)
300
301 #define BCLR XO19( 16)
302 #define BCCTR XO19(528)
303 #define CRAND XO19(257)
304 #define CRANDC XO19(129)
305 #define CRNAND XO19(225)
306 #define CROR XO19(449)
307
308 #define EXTSB XO31(954)
309 #define EXTSH XO31(922)
310 #define ADD XO31(266)
311 #define ADDE XO31(138)
312 #define ADDC XO31( 10)
313 #define AND XO31( 28)
314 #define SUBF XO31( 40)
315 #define SUBFC XO31( 8)
316 #define SUBFE XO31(136)
317 #define OR XO31(444)
318 #define XOR XO31(316)
319 #define MULLW XO31(235)
320 #define MULHWU XO31( 11)
321 #define DIVW XO31(491)
322 #define DIVWU XO31(459)
323 #define CMP XO31( 0)
324 #define CMPL XO31( 32)
325 #define LHBRX XO31(790)
326 #define LWBRX XO31(534)
327 #define STHBRX XO31(918)
328 #define STWBRX XO31(662)
329 #define MFSPR XO31(339)
330 #define MTSPR XO31(467)
331 #define SRAWI XO31(824)
332 #define NEG XO31(104)
333
334 #define LBZX XO31( 87)
335 #define LHZX XO31(276)
336 #define LHAX XO31(343)
337 #define LWZX XO31( 23)
338 #define STBX XO31(215)
339 #define STHX XO31(407)
340 #define STWX XO31(151)
341
342 #define SPR(a,b) ((((a)<<5)|(b))<<11)
343 #define LR SPR(8, 0)
344 #define CTR SPR(9, 0)
345
346 #define SLW XO31( 24)
347 #define SRW XO31(536)
348 #define SRAW XO31(792)
349
350 #define LMW OPCD(46)
351 #define STMW OPCD(47)
352
353 #define TW XO31(4)
354 #define TRAP (TW | TO (31))
355
356 #define RT(r) ((r)<<21)
357 #define RS(r) ((r)<<21)
358 #define RA(r) ((r)<<16)
359 #define RB(r) ((r)<<11)
360 #define TO(t) ((t)<<21)
361 #define SH(s) ((s)<<11)
362 #define MB(b) ((b)<<6)
363 #define ME(e) ((e)<<1)
364 #define BO(o) ((o)<<21)
365
366 #define LK 1
367
368 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
369 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
370
371 #define BF(n) ((n)<<23)
372 #define BI(n, c) (((c)+((n)*4))<<16)
373 #define BT(n, c) (((c)+((n)*4))<<21)
374 #define BA(n, c) (((c)+((n)*4))<<16)
375 #define BB(n, c) (((c)+((n)*4))<<11)
376
377 #define BO_COND_TRUE BO (12)
378 #define BO_COND_FALSE BO (4)
379 #define BO_ALWAYS BO (20)
380
381 enum {
382 CR_LT,
383 CR_GT,
384 CR_EQ,
385 CR_SO
386 };
387
388 static const uint32_t tcg_to_bc[10] = {
389 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
390 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
391 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
392 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
393 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
394 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
395 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
396 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
397 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
398 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
399 };
400
401 static void tcg_out_mov(TCGContext *s, int ret, int arg)
402 {
403 tcg_out32 (s, OR | SAB (arg, ret, arg));
404 }
405
406 static void tcg_out_movi(TCGContext *s, TCGType type,
407 int ret, tcg_target_long arg)
408 {
409 if (arg == (int16_t) arg)
410 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
411 else {
412 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
413 if (arg & 0xffff)
414 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
415 }
416 }
417
418 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
419 int offset, int op1, int op2)
420 {
421 if (offset == (int16_t) offset)
422 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
423 else {
424 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
425 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
426 }
427 }
428
429 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
430 {
431 tcg_target_long disp;
432
433 disp = target - (tcg_target_long) s->code_ptr;
434 if ((disp << 6) >> 6 == disp)
435 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
436 else {
437 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
438 tcg_out32 (s, MTSPR | RS (0) | CTR);
439 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
440 }
441 }
442
443 #if defined(CONFIG_SOFTMMU)
444 extern void __ldb_mmu(void);
445 extern void __ldw_mmu(void);
446 extern void __ldl_mmu(void);
447 extern void __ldq_mmu(void);
448
449 extern void __stb_mmu(void);
450 extern void __stw_mmu(void);
451 extern void __stl_mmu(void);
452 extern void __stq_mmu(void);
453
454 static void *qemu_ld_helpers[4] = {
455 __ldb_mmu,
456 __ldw_mmu,
457 __ldl_mmu,
458 __ldq_mmu,
459 };
460
461 static void *qemu_st_helpers[4] = {
462 __stb_mmu,
463 __stw_mmu,
464 __stl_mmu,
465 __stq_mmu,
466 };
467 #endif
468
469 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
470 {
471 int addr_reg, data_reg, data_reg2, r0, mem_index, s_bits, bswap;
472 #ifdef CONFIG_SOFTMMU
473 int r1, r2;
474 void *label1_ptr, *label2_ptr;
475 #endif
476 #if TARGET_LONG_BITS == 64
477 int addr_reg2;
478 #endif
479
480 data_reg = *args++;
481 if (opc == 3)
482 data_reg2 = *args++;
483 else
484 data_reg2 = 0;
485 addr_reg = *args++;
486 #if TARGET_LONG_BITS == 64
487 addr_reg2 = *args++;
488 #endif
489 mem_index = *args;
490 s_bits = opc & 3;
491
492 #ifdef CONFIG_SOFTMMU
493 r0 = 3;
494 r1 = 4;
495 r2 = 0;
496
497 tcg_out32 (s, (RLWINM
498 | RA (r0)
499 | RS (addr_reg)
500 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
501 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
502 | ME (31 - CPU_TLB_ENTRY_BITS)
503 )
504 );
505 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
506 tcg_out32 (s, (LWZU
507 | RT (r1)
508 | RA (r0)
509 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
510 )
511 );
512 tcg_out32 (s, (RLWINM
513 | RA (r2)
514 | RS (addr_reg)
515 | SH (0)
516 | MB ((32 - s_bits) & 31)
517 | ME (31 - TARGET_PAGE_BITS)
518 )
519 );
520
521 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
522 #if TARGET_LONG_BITS == 64
523 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
524 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
525 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
526 #endif
527
528 label1_ptr = s->code_ptr;
529 #ifdef FAST_PATH
530 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
531 #endif
532
533 /* slow path */
534 #if TARGET_LONG_BITS == 32
535 tcg_out_mov (s, 3, addr_reg);
536 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
537 #else
538 tcg_out_mov (s, 3, addr_reg2);
539 tcg_out_mov (s, 4, addr_reg);
540 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
541 #endif
542
543 tcg_out_b (s, LK, (tcg_target_long) qemu_ld_helpers[s_bits]);
544 switch (opc) {
545 case 0|4:
546 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
547 break;
548 case 1|4:
549 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
550 break;
551 case 0:
552 case 1:
553 case 2:
554 if (data_reg != 3)
555 tcg_out_mov (s, data_reg, 3);
556 break;
557 case 3:
558 if (data_reg == 3) {
559 if (data_reg2 == 4) {
560 tcg_out_mov (s, 0, 4);
561 tcg_out_mov (s, 4, 3);
562 tcg_out_mov (s, 3, 0);
563 }
564 else {
565 tcg_out_mov (s, data_reg2, 3);
566 tcg_out_mov (s, 3, 4);
567 }
568 }
569 else {
570 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
571 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
572 }
573 break;
574 }
575 label2_ptr = s->code_ptr;
576 tcg_out32 (s, B);
577
578 /* label1: fast path */
579 #ifdef FAST_PATH
580 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
581 #endif
582
583 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
584 tcg_out32 (s, (LWZ
585 | RT (r0)
586 | RA (r0)
587 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
588 - offsetof (CPUTLBEntry, addr_read))
589 ));
590 /* r0 = env->tlb_table[mem_index][index].addend */
591 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
592 /* r0 = env->tlb_table[mem_index][index].addend + addr */
593
594 #else /* !CONFIG_SOFTMMU */
595 r0 = addr_reg;
596 #endif
597
598 #ifdef TARGET_WORDS_BIGENDIAN
599 bswap = 0;
600 #else
601 bswap = 1;
602 #endif
603 switch (opc) {
604 default:
605 case 0:
606 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
607 break;
608 case 0|4:
609 tcg_out32 (s, LBZ | RT (data_reg) | RA (r0));
610 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
611 break;
612 case 1:
613 if (bswap) tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
614 else tcg_out32 (s, LHZ | RT (data_reg) | RA (r0));
615 break;
616 case 1|4:
617 if (bswap) {
618 tcg_out32 (s, LHBRX | RT (data_reg) | RB (r0));
619 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
620 }
621 else tcg_out32 (s, LHA | RT (data_reg) | RA (r0));
622 break;
623 case 2:
624 if (bswap) tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
625 else tcg_out32 (s, LWZ | RT (data_reg)| RA (r0));
626 break;
627 case 3:
628 if (bswap) {
629 if (r0 == data_reg) {
630 tcg_out32 (s, LWBRX | RT (0) | RB (r0));
631 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
632 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
633 tcg_out_mov (s, data_reg, 0);
634 }
635 else {
636 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
637 tcg_out32 (s, ADDI | RT (r0) | RA (r0) | 4);
638 tcg_out32 (s, LWBRX | RT (data_reg2) | RB (r0));
639 }
640 }
641 else {
642 if (r0 == data_reg2) {
643 tcg_out32 (s, LWZ | RT (0) | RA (r0));
644 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
645 tcg_out_mov (s, data_reg2, 0);
646 }
647 else {
648 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
649 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
650 }
651 }
652 break;
653 }
654
655 #ifdef CONFIG_SOFTMMU
656 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
657 #endif
658 }
659
660 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
661 {
662 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap;
663 #ifdef CONFIG_SOFTMMU
664 int r2, ir;
665 void *label1_ptr, *label2_ptr;
666 #endif
667 #if TARGET_LONG_BITS == 64
668 int addr_reg2;
669 #endif
670
671 data_reg = *args++;
672 if (opc == 3)
673 data_reg2 = *args++;
674 else
675 data_reg2 = 0;
676 addr_reg = *args++;
677 #if TARGET_LONG_BITS == 64
678 addr_reg2 = *args++;
679 #endif
680 mem_index = *args;
681
682 #ifdef CONFIG_SOFTMMU
683 r0 = 3;
684 r1 = 4;
685 r2 = 0;
686
687 tcg_out32 (s, (RLWINM
688 | RA (r0)
689 | RS (addr_reg)
690 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
691 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
692 | ME (31 - CPU_TLB_ENTRY_BITS)
693 )
694 );
695 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
696 tcg_out32 (s, (LWZU
697 | RT (r1)
698 | RA (r0)
699 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
700 )
701 );
702 tcg_out32 (s, (RLWINM
703 | RA (r2)
704 | RS (addr_reg)
705 | SH (0)
706 | MB ((32 - opc) & 31)
707 | ME (31 - TARGET_PAGE_BITS)
708 )
709 );
710
711 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
712 #if TARGET_LONG_BITS == 64
713 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
714 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
715 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
716 #endif
717
718 label1_ptr = s->code_ptr;
719 #ifdef FAST_PATH
720 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
721 #endif
722
723 /* slow path */
724 #if TARGET_LONG_BITS == 32
725 tcg_out_mov (s, 3, addr_reg);
726 ir = 4;
727 #else
728 tcg_out_mov (s, 3, addr_reg2);
729 tcg_out_mov (s, 4, addr_reg);
730 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
731 ir = 5;
732 #else
733 ir = 4;
734 #endif
735 #endif
736
737 switch (opc) {
738 case 0:
739 tcg_out32 (s, (RLWINM
740 | RA (ir)
741 | RS (data_reg)
742 | SH (0)
743 | MB (24)
744 | ME (31)));
745 break;
746 case 1:
747 tcg_out32 (s, (RLWINM
748 | RA (ir)
749 | RS (data_reg)
750 | SH (0)
751 | MB (16)
752 | ME (31)));
753 break;
754 case 2:
755 tcg_out_mov (s, ir, data_reg);
756 break;
757 case 3:
758 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
759 ir = 5;
760 #endif
761 tcg_out_mov (s, ir++, data_reg2);
762 tcg_out_mov (s, ir, data_reg);
763 break;
764 }
765 ir++;
766
767 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
768 tcg_out_b (s, LK, (tcg_target_long) qemu_st_helpers[opc]);
769 label2_ptr = s->code_ptr;
770 tcg_out32 (s, B);
771
772 /* label1: fast path */
773 #ifdef FAST_PATH
774 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
775 #endif
776
777 tcg_out32 (s, (LWZ
778 | RT (r0)
779 | RA (r0)
780 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
781 - offsetof (CPUTLBEntry, addr_write))
782 ));
783 /* r0 = env->tlb_table[mem_index][index].addend */
784 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
785 /* r0 = env->tlb_table[mem_index][index].addend + addr */
786
787 #else /* !CONFIG_SOFTMMU */
788 r1 = 4;
789 r0 = addr_reg;
790 #endif
791
792 #ifdef TARGET_WORDS_BIGENDIAN
793 bswap = 0;
794 #else
795 bswap = 1;
796 #endif
797 switch (opc) {
798 case 0:
799 tcg_out32 (s, STB | RS (data_reg) | RA (r0));
800 break;
801 case 1:
802 if (bswap) tcg_out32 (s, STHBRX | RS (data_reg) | RA (0) | RB (r0));
803 else tcg_out32 (s, STH | RS (data_reg) | RA (r0));
804 break;
805 case 2:
806 if (bswap) tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
807 else tcg_out32 (s, STW | RS (data_reg) | RA (r0));
808 break;
809 case 3:
810 if (bswap) {
811 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
812 tcg_out32 (s, STWBRX | RS (data_reg) | RA (0) | RB (r0));
813 tcg_out32 (s, STWBRX | RS (data_reg2) | RA (0) | RB (r1));
814 }
815 else {
816 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
817 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
818 }
819 break;
820 }
821
822 #ifdef CONFIG_SOFTMMU
823 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
824 #endif
825 }
826
827 void tcg_target_qemu_prologue (TCGContext *s)
828 {
829 int i, frame_size;
830
831 frame_size = 0
832 + LINKAGE_AREA_SIZE
833 + TCG_STATIC_CALL_ARGS_SIZE
834 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
835 ;
836 frame_size = (frame_size + 15) & ~15;
837
838 tcg_out32 (s, MFSPR | RT (0) | LR);
839 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
840 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
841 tcg_out32 (s, (STW
842 | RS (tcg_target_callee_save_regs[i])
843 | RA (1)
844 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
845 )
846 );
847 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + BACK_CHAIN_OFFSET));
848
849 tcg_out32 (s, MTSPR | RS (3) | CTR);
850 tcg_out32 (s, BCCTR | BO_ALWAYS);
851 tb_ret_addr = s->code_ptr;
852
853 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
854 tcg_out32 (s, (LWZ
855 | RT (tcg_target_callee_save_regs[i])
856 | RA (1)
857 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
858 )
859 );
860 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + BACK_CHAIN_OFFSET));
861 tcg_out32 (s, MTSPR | RS (0) | LR);
862 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
863 tcg_out32 (s, BCLR | BO_ALWAYS);
864 }
865
866 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
867 tcg_target_long arg2)
868 {
869 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
870 }
871
872 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
873 tcg_target_long arg2)
874 {
875 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
876 }
877
878 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
879 {
880 if (!si && rt == ra)
881 return;
882
883 if (si == (int16_t) si)
884 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
885 else {
886 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
887 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
888 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
889 }
890 }
891
892 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
893 {
894 ppc_addi (s, reg, reg, val);
895 }
896
897 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
898 int const_arg2, int cr)
899 {
900 int imm;
901 uint32_t op;
902
903 switch (cond) {
904 case TCG_COND_EQ:
905 case TCG_COND_NE:
906 if (const_arg2) {
907 if ((int16_t) arg2 == arg2) {
908 op = CMPI;
909 imm = 1;
910 break;
911 }
912 else if ((uint16_t) arg2 == arg2) {
913 op = CMPLI;
914 imm = 1;
915 break;
916 }
917 }
918 op = CMPL;
919 imm = 0;
920 break;
921
922 case TCG_COND_LT:
923 case TCG_COND_GE:
924 case TCG_COND_LE:
925 case TCG_COND_GT:
926 if (const_arg2) {
927 if ((int16_t) arg2 == arg2) {
928 op = CMPI;
929 imm = 1;
930 break;
931 }
932 }
933 op = CMP;
934 imm = 0;
935 break;
936
937 case TCG_COND_LTU:
938 case TCG_COND_GEU:
939 case TCG_COND_LEU:
940 case TCG_COND_GTU:
941 if (const_arg2) {
942 if ((uint16_t) arg2 == arg2) {
943 op = CMPLI;
944 imm = 1;
945 break;
946 }
947 }
948 op = CMPL;
949 imm = 0;
950 break;
951
952 default:
953 tcg_abort ();
954 }
955 op |= BF (cr);
956
957 if (imm)
958 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
959 else {
960 if (const_arg2) {
961 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
962 tcg_out32 (s, op | RA (arg1) | RB (0));
963 }
964 else
965 tcg_out32 (s, op | RA (arg1) | RB (arg2));
966 }
967
968 }
969
970 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
971 {
972 TCGLabel *l = &s->labels[label_index];
973
974 if (l->has_value)
975 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
976 else {
977 uint16_t val = *(uint16_t *) &s->code_ptr[2];
978
979 /* Thanks to Andrzej Zaborowski */
980 tcg_out32 (s, bc | (val & 0xfffc));
981 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
982 }
983 }
984
985 static void tcg_out_brcond (TCGContext *s, int cond,
986 TCGArg arg1, TCGArg arg2, int const_arg2,
987 int label_index)
988 {
989 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
990 tcg_out_bc (s, tcg_to_bc[cond], label_index);
991 }
992
993 /* XXX: we implement it at the target level to avoid having to
994 handle cross basic blocks temporaries */
995 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
996 const int *const_args)
997 {
998 int cond = args[4], label_index = args[5], op;
999 struct { int bit1; int bit2; int cond2; } bits[] = {
1000 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1001 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1002 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1003 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1004 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1005 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1006 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1007 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1008 }, *b = &bits[cond];
1009
1010 switch (cond) {
1011 case TCG_COND_EQ:
1012 case TCG_COND_NE:
1013 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1014 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1015 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1016 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1017 break;
1018 case TCG_COND_LT:
1019 case TCG_COND_LE:
1020 case TCG_COND_GT:
1021 case TCG_COND_GE:
1022 case TCG_COND_LTU:
1023 case TCG_COND_LEU:
1024 case TCG_COND_GTU:
1025 case TCG_COND_GEU:
1026 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1027 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1028 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1029 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1030 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1031 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1032 break;
1033 default:
1034 tcg_abort();
1035 }
1036
1037 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), label_index);
1038 }
1039
1040 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1041 {
1042 uint32_t *ptr;
1043 long disp = addr - jmp_addr;
1044 unsigned long patch_size;
1045
1046 ptr = (uint32_t *)jmp_addr;
1047
1048 if ((disp << 6) >> 6 != disp) {
1049 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1050 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1051 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1052 ptr[3] = 0x4e800420; /* brctr */
1053 patch_size = 16;
1054 } else {
1055 /* patch the branch destination */
1056 if (disp != 16) {
1057 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1058 patch_size = 4;
1059 } else {
1060 ptr[0] = 0x60000000; /* nop */
1061 ptr[1] = 0x60000000;
1062 ptr[2] = 0x60000000;
1063 ptr[3] = 0x60000000;
1064 patch_size = 16;
1065 }
1066 }
1067 /* flush icache */
1068 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1069 }
1070
1071 static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1072 const int *const_args)
1073 {
1074 switch (opc) {
1075 case INDEX_op_exit_tb:
1076 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1077 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1078 break;
1079 case INDEX_op_goto_tb:
1080 if (s->tb_jmp_offset) {
1081 /* direct jump method */
1082
1083 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1084 s->code_ptr += 16;
1085 }
1086 else {
1087 tcg_abort ();
1088 }
1089 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1090 break;
1091 case INDEX_op_br:
1092 {
1093 TCGLabel *l = &s->labels[args[0]];
1094
1095 if (l->has_value) {
1096 tcg_out_b (s, 0, l->u.value);
1097 }
1098 else {
1099 uint32_t val = *(uint32_t *) s->code_ptr;
1100
1101 /* Thanks to Andrzej Zaborowski */
1102 tcg_out32 (s, B | (val & 0x3fffffc));
1103 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1104 }
1105 }
1106 break;
1107 case INDEX_op_call:
1108 if (const_args[0]) {
1109 tcg_out_b (s, LK, args[0]);
1110 }
1111 else {
1112 tcg_out32 (s, MTSPR | RS (args[0]) | LR);
1113 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
1114 }
1115 break;
1116 case INDEX_op_jmp:
1117 if (const_args[0]) {
1118 tcg_out_b (s, 0, args[0]);
1119 }
1120 else {
1121 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1122 tcg_out32 (s, BCCTR | BO_ALWAYS);
1123 }
1124 break;
1125 case INDEX_op_movi_i32:
1126 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1127 break;
1128 case INDEX_op_ld8u_i32:
1129 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1130 break;
1131 case INDEX_op_ld8s_i32:
1132 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1133 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1134 break;
1135 case INDEX_op_ld16u_i32:
1136 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1137 break;
1138 case INDEX_op_ld16s_i32:
1139 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1140 break;
1141 case INDEX_op_ld_i32:
1142 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1143 break;
1144 case INDEX_op_st8_i32:
1145 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1146 break;
1147 case INDEX_op_st16_i32:
1148 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1149 break;
1150 case INDEX_op_st_i32:
1151 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1152 break;
1153
1154 case INDEX_op_add_i32:
1155 if (const_args[2])
1156 ppc_addi (s, args[0], args[1], args[2]);
1157 else
1158 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1159 break;
1160 case INDEX_op_sub_i32:
1161 if (const_args[2])
1162 ppc_addi (s, args[0], args[1], -args[2]);
1163 else
1164 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1165 break;
1166
1167 case INDEX_op_and_i32:
1168 if (const_args[2]) {
1169 if ((args[2] & 0xffff) == args[2])
1170 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1171 else if ((args[2] & 0xffff0000) == args[2])
1172 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1173 | ((args[2] >> 16) & 0xffff));
1174 else {
1175 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1176 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1177 }
1178 }
1179 else
1180 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1181 break;
1182 case INDEX_op_or_i32:
1183 if (const_args[2]) {
1184 if (args[2] & 0xffff) {
1185 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1186 | (args[2] & 0xffff));
1187 if (args[2] >> 16)
1188 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1189 | ((args[2] >> 16) & 0xffff));
1190 }
1191 else {
1192 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1193 | ((args[2] >> 16) & 0xffff));
1194 }
1195 }
1196 else
1197 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1198 break;
1199 case INDEX_op_xor_i32:
1200 if (const_args[2]) {
1201 if ((args[2] & 0xffff) == args[2])
1202 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1203 | (args[2] & 0xffff));
1204 else if ((args[2] & 0xffff0000) == args[2])
1205 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1206 | ((args[2] >> 16) & 0xffff));
1207 else {
1208 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1209 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1210 }
1211 }
1212 else
1213 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1214 break;
1215
1216 case INDEX_op_mul_i32:
1217 if (const_args[2]) {
1218 if (args[2] == (int16_t) args[2])
1219 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1220 | (args[2] & 0xffff));
1221 else {
1222 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1223 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1224 }
1225 }
1226 else
1227 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1228 break;
1229
1230 case INDEX_op_div_i32:
1231 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1232 break;
1233
1234 case INDEX_op_divu_i32:
1235 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1236 break;
1237
1238 case INDEX_op_rem_i32:
1239 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1240 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1241 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1242 break;
1243
1244 case INDEX_op_remu_i32:
1245 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1246 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1247 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1248 break;
1249
1250 case INDEX_op_mulu2_i32:
1251 if (args[0] == args[2] || args[0] == args[3]) {
1252 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1253 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1254 tcg_out_mov (s, args[0], 0);
1255 }
1256 else {
1257 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1258 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1259 }
1260 break;
1261
1262 case INDEX_op_shl_i32:
1263 if (const_args[2]) {
1264 tcg_out32 (s, (RLWINM
1265 | RA (args[0])
1266 | RS (args[1])
1267 | SH (args[2])
1268 | MB (0)
1269 | ME (31 - args[2])
1270 )
1271 );
1272 }
1273 else
1274 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1275 break;
1276 case INDEX_op_shr_i32:
1277 if (const_args[2]) {
1278 tcg_out32 (s, (RLWINM
1279 | RA (args[0])
1280 | RS (args[1])
1281 | SH (32 - args[2])
1282 | MB (args[2])
1283 | ME (31)
1284 )
1285 );
1286 }
1287 else
1288 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1289 break;
1290 case INDEX_op_sar_i32:
1291 if (const_args[2])
1292 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1293 else
1294 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1295 break;
1296
1297 case INDEX_op_add2_i32:
1298 if (args[0] == args[3] || args[0] == args[5]) {
1299 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1300 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1301 tcg_out_mov (s, args[0], 0);
1302 }
1303 else {
1304 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1305 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1306 }
1307 break;
1308 case INDEX_op_sub2_i32:
1309 if (args[0] == args[3] || args[0] == args[5]) {
1310 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1311 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1312 tcg_out_mov (s, args[0], 0);
1313 }
1314 else {
1315 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1316 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1317 }
1318 break;
1319
1320 case INDEX_op_brcond_i32:
1321 /*
1322 args[0] = r0
1323 args[1] = r1
1324 args[2] = cond
1325 args[3] = r1 is const
1326 args[4] = label_index
1327 */
1328 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1329 break;
1330 case INDEX_op_brcond2_i32:
1331 tcg_out_brcond2(s, args, const_args);
1332 break;
1333
1334 case INDEX_op_neg_i32:
1335 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1336 break;
1337
1338 case INDEX_op_qemu_ld8u:
1339 tcg_out_qemu_ld(s, args, 0);
1340 break;
1341 case INDEX_op_qemu_ld8s:
1342 tcg_out_qemu_ld(s, args, 0 | 4);
1343 break;
1344 case INDEX_op_qemu_ld16u:
1345 tcg_out_qemu_ld(s, args, 1);
1346 break;
1347 case INDEX_op_qemu_ld16s:
1348 tcg_out_qemu_ld(s, args, 1 | 4);
1349 break;
1350 case INDEX_op_qemu_ld32u:
1351 tcg_out_qemu_ld(s, args, 2);
1352 break;
1353 case INDEX_op_qemu_ld64:
1354 tcg_out_qemu_ld(s, args, 3);
1355 break;
1356 case INDEX_op_qemu_st8:
1357 tcg_out_qemu_st(s, args, 0);
1358 break;
1359 case INDEX_op_qemu_st16:
1360 tcg_out_qemu_st(s, args, 1);
1361 break;
1362 case INDEX_op_qemu_st32:
1363 tcg_out_qemu_st(s, args, 2);
1364 break;
1365 case INDEX_op_qemu_st64:
1366 tcg_out_qemu_st(s, args, 3);
1367 break;
1368
1369 case INDEX_op_ext8s_i32:
1370 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1371 break;
1372 case INDEX_op_ext16s_i32:
1373 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1374 break;
1375
1376 default:
1377 tcg_dump_ops (s, stderr);
1378 tcg_abort ();
1379 }
1380 }
1381
1382 static const TCGTargetOpDef ppc_op_defs[] = {
1383 { INDEX_op_exit_tb, { } },
1384 { INDEX_op_goto_tb, { } },
1385 { INDEX_op_call, { "ri" } },
1386 { INDEX_op_jmp, { "ri" } },
1387 { INDEX_op_br, { } },
1388
1389 { INDEX_op_mov_i32, { "r", "r" } },
1390 { INDEX_op_movi_i32, { "r" } },
1391 { INDEX_op_ld8u_i32, { "r", "r" } },
1392 { INDEX_op_ld8s_i32, { "r", "r" } },
1393 { INDEX_op_ld16u_i32, { "r", "r" } },
1394 { INDEX_op_ld16s_i32, { "r", "r" } },
1395 { INDEX_op_ld_i32, { "r", "r" } },
1396 { INDEX_op_st8_i32, { "r", "r" } },
1397 { INDEX_op_st16_i32, { "r", "r" } },
1398 { INDEX_op_st_i32, { "r", "r" } },
1399
1400 { INDEX_op_add_i32, { "r", "r", "ri" } },
1401 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1402 { INDEX_op_div_i32, { "r", "r", "r" } },
1403 { INDEX_op_divu_i32, { "r", "r", "r" } },
1404 { INDEX_op_rem_i32, { "r", "r", "r" } },
1405 { INDEX_op_remu_i32, { "r", "r", "r" } },
1406 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1407 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1408 { INDEX_op_and_i32, { "r", "r", "ri" } },
1409 { INDEX_op_or_i32, { "r", "r", "ri" } },
1410 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1411
1412 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1413 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1414 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1415
1416 { INDEX_op_brcond_i32, { "r", "ri" } },
1417
1418 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1419 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1420 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1421
1422 { INDEX_op_neg_i32, { "r", "r" } },
1423
1424 #if TARGET_LONG_BITS == 32
1425 { INDEX_op_qemu_ld8u, { "r", "L" } },
1426 { INDEX_op_qemu_ld8s, { "r", "L" } },
1427 { INDEX_op_qemu_ld16u, { "r", "L" } },
1428 { INDEX_op_qemu_ld16s, { "r", "L" } },
1429 { INDEX_op_qemu_ld32u, { "r", "L" } },
1430 { INDEX_op_qemu_ld32s, { "r", "L" } },
1431 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1432
1433 { INDEX_op_qemu_st8, { "K", "K" } },
1434 { INDEX_op_qemu_st16, { "K", "K" } },
1435 { INDEX_op_qemu_st32, { "K", "K" } },
1436 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1437 #else
1438 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1439 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1440 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1441 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1442 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1443 { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1444 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1445
1446 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1447 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1448 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1449 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1450 #endif
1451
1452 { INDEX_op_ext8s_i32, { "r", "r" } },
1453 { INDEX_op_ext16s_i32, { "r", "r" } },
1454
1455 { -1 },
1456 };
1457
1458 void tcg_target_init(TCGContext *s)
1459 {
1460 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1461 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1462 (1 << TCG_REG_R0) |
1463 #ifdef __APPLE__
1464 (1 << TCG_REG_R2) |
1465 #endif
1466 (1 << TCG_REG_R3) |
1467 (1 << TCG_REG_R4) |
1468 (1 << TCG_REG_R5) |
1469 (1 << TCG_REG_R6) |
1470 (1 << TCG_REG_R7) |
1471 (1 << TCG_REG_R8) |
1472 (1 << TCG_REG_R9) |
1473 (1 << TCG_REG_R10) |
1474 (1 << TCG_REG_R11) |
1475 (1 << TCG_REG_R12)
1476 );
1477
1478 tcg_regset_clear(s->reserved_regs);
1479 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1480 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1481 #ifndef __APPLE__
1482 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1483 #endif
1484
1485 tcg_add_target_add_op_defs(ppc_op_defs);
1486 }
Samsung s3c2440 and arm920t support for the mini2440 dev board