hw/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "qemu-common.h"
   5
   6 /* PC-style peripherals (also used by other machines).  */
   7
   8 /* serial.c */
   9
  10 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
  11                          CharDriverState *chr);
  12 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
  13                              qemu_irq irq, int baudbase,
  14                              CharDriverState *chr, int ioregister);
  15 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
  16 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
  17 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
  18 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
  19 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
  20 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
  21
  22 /* parallel.c */
  23
  24 typedef struct ParallelState ParallelState;
  25 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
  26 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
  27
  28 /* i8259.c */
  29
  30 typedef struct PicState2 PicState2;
  31 extern PicState2 *isa_pic;
  32 void pic_set_irq(int irq, int level);
  33 void pic_set_irq_new(void *opaque, int irq, int level);
  34 qemu_irq *i8259_init(qemu_irq parent_irq);
  35 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
  36                           void *alt_irq_opaque);
  37 int pic_read_irq(PicState2 *s);
  38 void pic_update_irq(PicState2 *s);
  39 uint32_t pic_intack_read(PicState2 *s);
  40 void pic_info(Monitor *mon);
  41 void irq_info(Monitor *mon);
  42
  43 /* APIC */
  44 typedef struct IOAPICState IOAPICState;
  45
  46 int apic_init(CPUState *env);
  47 int apic_accept_pic_intr(CPUState *env);
  48 void apic_deliver_pic_intr(CPUState *env, int level);
  49 int apic_get_interrupt(CPUState *env);
  50 IOAPICState *ioapic_init(void);
  51 void ioapic_set_irq(void *opaque, int vector, int level);
  52 void apic_reset_irq_delivered(void);
  53 int apic_get_irq_delivered(void);
  54
  55 /* i8254.c */
  56
  57 #define PIT_FREQ 1193182
  58
  59 typedef struct PITState PITState;
  60
  61 PITState *pit_init(int base, qemu_irq irq);
  62 void pit_set_gate(PITState *pit, int channel, int val);
  63 int pit_get_gate(PITState *pit, int channel);
  64 int pit_get_initial_count(PITState *pit, int channel);
  65 int pit_get_mode(PITState *pit, int channel);
  66 int pit_get_out(PITState *pit, int channel, int64_t current_time);
  67
  68 void hpet_pit_disable(void);
  69 void hpet_pit_enable(void);
  70
  71 /* vmport.c */
  72 void vmport_init(void);
  73 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
  74
  75 /* vmmouse.c */
  76 void *vmmouse_init(void *m);
  77
  78 /* pckbd.c */
  79
  80 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
  81 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  82                    target_phys_addr_t base, ram_addr_t size,
  83                    target_phys_addr_t mask);
  84
  85 /* mc146818rtc.c */
  86
  87 typedef struct RTCState RTCState;
  88
  89 RTCState *rtc_init(int base, qemu_irq irq, int base_year);
  90 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
  91                       int base_year);
  92 void rtc_set_memory(RTCState *s, int addr, int val);
  93 void rtc_set_date(RTCState *s, const struct tm *tm);
  94 void cmos_set_s3_resume(void);
  95
  96 /* pc.c */
  97 extern int fd_bootchk;
  98
  99 void ioport_set_a20(int enable);
 100 int ioport_get_a20(void);
 101
 102 /* acpi.c */
 103 extern int acpi_enabled;
 104 extern char *acpi_tables;
 105 extern size_t acpi_tables_len;
 106
 107 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 108                        qemu_irq sci_irq);
 109 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 110 void acpi_bios_init(void);
 111 int acpi_table_add(const char *table_desc);
 112
 113 /* hpet.c */
 114 extern int no_hpet;
 115
 116 /* pcspk.c */
 117 void pcspk_init(PITState *);
 118 int pcspk_audio_init(AudioState *, qemu_irq *pic);
 119
 120 /* piix_pci.c */
 121 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
 122 void i440fx_set_smm(PCIDevice *d, int val);
 123 int piix3_init(PCIBus *bus, int devfn);
 124 void i440fx_init_memory_mappings(PCIDevice *d);
 125
 126 extern PCIDevice *piix4_dev;
 127 int piix4_init(PCIBus *bus, int devfn);
 128
 129 /* vga.c */
 130 enum vga_retrace_method {
 131     VGA_RETRACE_DUMB,
 132     VGA_RETRACE_PRECISE
 133 };
 134
 135 extern enum vga_retrace_method vga_retrace_method;
 136
 137 #if !defined(TARGET_SPARC) || defined(TARGET_SPARC64)
 138 #define VGA_RAM_SIZE (8192 * 1024)
 139 #else
 140 #define VGA_RAM_SIZE (9 * 1024 * 1024)
 141 #endif
 142
 143 int isa_vga_init(uint8_t *vga_ram_base,
 144                  unsigned long vga_ram_offset, int vga_ram_size);
 145 int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
 146                  unsigned long vga_ram_offset, int vga_ram_size,
 147                  unsigned long vga_bios_offset, int vga_bios_size);
 148 int isa_vga_mm_init(uint8_t *vga_ram_base,
 149                     unsigned long vga_ram_offset, int vga_ram_size,
 150                     target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
 151                     int it_shift);
 152
 153 /* cirrus_vga.c */
 154 void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
 155                          ram_addr_t vga_ram_offset, int vga_ram_size);
 156 void isa_cirrus_vga_init(uint8_t *vga_ram_base,
 157                          ram_addr_t vga_ram_offset, int vga_ram_size);
 158
 159 /* ide.c */
 160 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
 161                   BlockDriverState *hd0, BlockDriverState *hd1);
 162 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
 163                          int secondary_ide_enabled);
 164 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 165                         qemu_irq *pic);
 166 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 167                         qemu_irq *pic);
 168
 169 /* ne2000.c */
 170
 171 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
 172
 173 #endif