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Do not use load_seg_vm to load CS in real mode iret handling
[qemu/mini2440.git] / target-i386 / translate.c
blob88d0173487b5b9ee697144e8443c6774950fdd9b
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "disas.h"
31 #include "helper.h"
32 #include "tcg-op.h"
33
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
39
40 #ifdef TARGET_X86_64
41 #define X86_64_ONLY(x) x
42 #define X86_64_DEF(x...) x
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
46 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
47 #if 1
48 #define BUGGY_64(x) NULL
49 #endif
50 #else
51 #define X86_64_ONLY(x) NULL
52 #define X86_64_DEF(x...)
53 #define CODE64(s) 0
54 #define REX_X(s) 0
55 #define REX_B(s) 0
56 #endif
57
58 //#define MACRO_TEST 1
59
60 /* global register indexes */
61 static TCGv cpu_env, cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
62 /* local temps */
63 static TCGv cpu_T[2], cpu_T3;
64 /* local register indexes (only used inside old micro ops) */
65 static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;
66 static TCGv cpu_tmp5, cpu_tmp6;
67
68 #include "gen-icount.h"
69
70 #ifdef TARGET_X86_64
71 static int x86_64_hregs;
72 #endif
73
74 typedef struct DisasContext {
75 /* current insn context */
76 int override; /* -1 if no override */
77 int prefix;
78 int aflag, dflag;
79 target_ulong pc; /* pc = eip + cs_base */
80 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
81 static state change (stop translation) */
82 /* current block context */
83 target_ulong cs_base; /* base of CS segment */
84 int pe; /* protected mode */
85 int code32; /* 32 bit code segment */
86 #ifdef TARGET_X86_64
87 int lma; /* long mode active */
88 int code64; /* 64 bit code segment */
89 int rex_x, rex_b;
90 #endif
91 int ss32; /* 32 bit stack segment */
92 int cc_op; /* current CC operation */
93 int addseg; /* non zero if either DS/ES/SS have a non zero base */
94 int f_st; /* currently unused */
95 int vm86; /* vm86 mode */
96 int cpl;
97 int iopl;
98 int tf; /* TF cpu flag */
99 int singlestep_enabled; /* "hardware" single step enabled */
100 int jmp_opt; /* use direct block chaining for direct jumps */
101 int mem_index; /* select memory access functions */
102 uint64_t flags; /* all execution flags */
103 struct TranslationBlock *tb;
104 int popl_esp_hack; /* for correct popl with esp base handling */
105 int rip_offset; /* only used in x86_64, but left for simplicity */
106 int cpuid_features;
107 int cpuid_ext_features;
108 int cpuid_ext2_features;
109 int cpuid_ext3_features;
110 } DisasContext;
111
112 static void gen_eob(DisasContext *s);
113 static void gen_jmp(DisasContext *s, target_ulong eip);
114 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
115
116 /* i386 arith/logic operations */
117 enum {
118 OP_ADDL,
119 OP_ORL,
120 OP_ADCL,
121 OP_SBBL,
122 OP_ANDL,
123 OP_SUBL,
124 OP_XORL,
125 OP_CMPL,
126 };
127
128 /* i386 shift ops */
129 enum {
130 OP_ROL,
131 OP_ROR,
132 OP_RCL,
133 OP_RCR,
134 OP_SHL,
135 OP_SHR,
136 OP_SHL1, /* undocumented */
137 OP_SAR = 7,
138 };
139
140 enum {
141 JCC_O,
142 JCC_B,
143 JCC_Z,
144 JCC_BE,
145 JCC_S,
146 JCC_P,
147 JCC_L,
148 JCC_LE,
149 };
150
151 /* operand size */
152 enum {
153 OT_BYTE = 0,
154 OT_WORD,
155 OT_LONG,
156 OT_QUAD,
157 };
158
159 enum {
160 /* I386 int registers */
161 OR_EAX, /* MUST be even numbered */
162 OR_ECX,
163 OR_EDX,
164 OR_EBX,
165 OR_ESP,
166 OR_EBP,
167 OR_ESI,
168 OR_EDI,
169
170 OR_TMP0 = 16, /* temporary operand register */
171 OR_TMP1,
172 OR_A0, /* temporary register used when doing address evaluation */
173 };
174
175 static inline void gen_op_movl_T0_0(void)
176 {
177 tcg_gen_movi_tl(cpu_T[0], 0);
178 }
179
180 static inline void gen_op_movl_T0_im(int32_t val)
181 {
182 tcg_gen_movi_tl(cpu_T[0], val);
183 }
184
185 static inline void gen_op_movl_T0_imu(uint32_t val)
186 {
187 tcg_gen_movi_tl(cpu_T[0], val);
188 }
189
190 static inline void gen_op_movl_T1_im(int32_t val)
191 {
192 tcg_gen_movi_tl(cpu_T[1], val);
193 }
194
195 static inline void gen_op_movl_T1_imu(uint32_t val)
196 {
197 tcg_gen_movi_tl(cpu_T[1], val);
198 }
199
200 static inline void gen_op_movl_A0_im(uint32_t val)
201 {
202 tcg_gen_movi_tl(cpu_A0, val);
203 }
204
205 #ifdef TARGET_X86_64
206 static inline void gen_op_movq_A0_im(int64_t val)
207 {
208 tcg_gen_movi_tl(cpu_A0, val);
209 }
210 #endif
211
212 static inline void gen_movtl_T0_im(target_ulong val)
213 {
214 tcg_gen_movi_tl(cpu_T[0], val);
215 }
216
217 static inline void gen_movtl_T1_im(target_ulong val)
218 {
219 tcg_gen_movi_tl(cpu_T[1], val);
220 }
221
222 static inline void gen_op_andl_T0_ffff(void)
223 {
224 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
225 }
226
227 static inline void gen_op_andl_T0_im(uint32_t val)
228 {
229 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
230 }
231
232 static inline void gen_op_movl_T0_T1(void)
233 {
234 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
235 }
236
237 static inline void gen_op_andl_A0_ffff(void)
238 {
239 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
240 }
241
242 #ifdef TARGET_X86_64
243
244 #define NB_OP_SIZES 4
245
246 #else /* !TARGET_X86_64 */
247
248 #define NB_OP_SIZES 3
249
250 #endif /* !TARGET_X86_64 */
251
252 #if defined(WORDS_BIGENDIAN)
253 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
254 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
255 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
256 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
257 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
258 #else
259 #define REG_B_OFFSET 0
260 #define REG_H_OFFSET 1
261 #define REG_W_OFFSET 0
262 #define REG_L_OFFSET 0
263 #define REG_LH_OFFSET 4
264 #endif
265
266 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
267 {
268 switch(ot) {
269 case OT_BYTE:
270 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
271 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
272 } else {
273 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
274 }
275 break;
276 case OT_WORD:
277 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
278 break;
279 #ifdef TARGET_X86_64
280 case OT_LONG:
281 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
282 /* high part of register set to zero */
283 tcg_gen_movi_tl(cpu_tmp0, 0);
284 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
285 break;
286 default:
287 case OT_QUAD:
288 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
289 break;
290 #else
291 default:
292 case OT_LONG:
293 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
294 break;
295 #endif
296 }
297 }
298
299 static inline void gen_op_mov_reg_T0(int ot, int reg)
300 {
301 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
302 }
303
304 static inline void gen_op_mov_reg_T1(int ot, int reg)
305 {
306 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
307 }
308
309 static inline void gen_op_mov_reg_A0(int size, int reg)
310 {
311 switch(size) {
312 case 0:
313 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
314 break;
315 #ifdef TARGET_X86_64
316 case 1:
317 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
318 /* high part of register set to zero */
319 tcg_gen_movi_tl(cpu_tmp0, 0);
320 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
321 break;
322 default:
323 case 2:
324 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
325 break;
326 #else
327 default:
328 case 1:
329 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
330 break;
331 #endif
332 }
333 }
334
335 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
336 {
337 switch(ot) {
338 case OT_BYTE:
339 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
340 goto std_case;
341 } else {
342 tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
343 }
344 break;
345 default:
346 std_case:
347 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
348 break;
349 }
350 }
351
352 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
353 {
354 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
355 }
356
357 static inline void gen_op_movl_A0_reg(int reg)
358 {
359 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
360 }
361
362 static inline void gen_op_addl_A0_im(int32_t val)
363 {
364 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
365 #ifdef TARGET_X86_64
366 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
367 #endif
368 }
369
370 #ifdef TARGET_X86_64
371 static inline void gen_op_addq_A0_im(int64_t val)
372 {
373 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
374 }
375 #endif
376
377 static void gen_add_A0_im(DisasContext *s, int val)
378 {
379 #ifdef TARGET_X86_64
380 if (CODE64(s))
381 gen_op_addq_A0_im(val);
382 else
383 #endif
384 gen_op_addl_A0_im(val);
385 }
386
387 static inline void gen_op_addl_T0_T1(void)
388 {
389 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
390 }
391
392 static inline void gen_op_jmp_T0(void)
393 {
394 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
395 }
396
397 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
398 {
399 switch(size) {
400 case 0:
401 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
402 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
403 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
404 break;
405 case 1:
406 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
407 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
408 #ifdef TARGET_X86_64
409 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
410 #endif
411 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
412 break;
413 #ifdef TARGET_X86_64
414 case 2:
415 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
416 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
417 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
418 break;
419 #endif
420 }
421 }
422
423 static inline void gen_op_add_reg_T0(int size, int reg)
424 {
425 switch(size) {
426 case 0:
427 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
428 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
429 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
430 break;
431 case 1:
432 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
433 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
434 #ifdef TARGET_X86_64
435 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
436 #endif
437 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
438 break;
439 #ifdef TARGET_X86_64
440 case 2:
441 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
442 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
443 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
444 break;
445 #endif
446 }
447 }
448
449 static inline void gen_op_set_cc_op(int32_t val)
450 {
451 tcg_gen_movi_i32(cpu_cc_op, val);
452 }
453
454 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
455 {
456 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
457 if (shift != 0)
458 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
459 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
460 #ifdef TARGET_X86_64
461 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
462 #endif
463 }
464
465 static inline void gen_op_movl_A0_seg(int reg)
466 {
467 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
468 }
469
470 static inline void gen_op_addl_A0_seg(int reg)
471 {
472 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
473 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
474 #ifdef TARGET_X86_64
475 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
476 #endif
477 }
478
479 #ifdef TARGET_X86_64
480 static inline void gen_op_movq_A0_seg(int reg)
481 {
482 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
483 }
484
485 static inline void gen_op_addq_A0_seg(int reg)
486 {
487 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
488 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
489 }
490
491 static inline void gen_op_movq_A0_reg(int reg)
492 {
493 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
494 }
495
496 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
497 {
498 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
499 if (shift != 0)
500 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
501 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
502 }
503 #endif
504
505 static inline void gen_op_lds_T0_A0(int idx)
506 {
507 int mem_index = (idx >> 2) - 1;
508 switch(idx & 3) {
509 case 0:
510 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
511 break;
512 case 1:
513 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
514 break;
515 default:
516 case 2:
517 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
518 break;
519 }
520 }
521
522 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
523 {
524 int mem_index = (idx >> 2) - 1;
525 switch(idx & 3) {
526 case 0:
527 tcg_gen_qemu_ld8u(t0, a0, mem_index);
528 break;
529 case 1:
530 tcg_gen_qemu_ld16u(t0, a0, mem_index);
531 break;
532 case 2:
533 tcg_gen_qemu_ld32u(t0, a0, mem_index);
534 break;
535 default:
536 case 3:
537 tcg_gen_qemu_ld64(t0, a0, mem_index);
538 break;
539 }
540 }
541
542 /* XXX: always use ldu or lds */
543 static inline void gen_op_ld_T0_A0(int idx)
544 {
545 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
546 }
547
548 static inline void gen_op_ldu_T0_A0(int idx)
549 {
550 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
551 }
552
553 static inline void gen_op_ld_T1_A0(int idx)
554 {
555 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
556 }
557
558 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
559 {
560 int mem_index = (idx >> 2) - 1;
561 switch(idx & 3) {
562 case 0:
563 tcg_gen_qemu_st8(t0, a0, mem_index);
564 break;
565 case 1:
566 tcg_gen_qemu_st16(t0, a0, mem_index);
567 break;
568 case 2:
569 tcg_gen_qemu_st32(t0, a0, mem_index);
570 break;
571 default:
572 case 3:
573 tcg_gen_qemu_st64(t0, a0, mem_index);
574 break;
575 }
576 }
577
578 static inline void gen_op_st_T0_A0(int idx)
579 {
580 gen_op_st_v(idx, cpu_T[0], cpu_A0);
581 }
582
583 static inline void gen_op_st_T1_A0(int idx)
584 {
585 gen_op_st_v(idx, cpu_T[1], cpu_A0);
586 }
587
588 static inline void gen_jmp_im(target_ulong pc)
589 {
590 tcg_gen_movi_tl(cpu_tmp0, pc);
591 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
592 }
593
594 static inline void gen_string_movl_A0_ESI(DisasContext *s)
595 {
596 int override;
597
598 override = s->override;
599 #ifdef TARGET_X86_64
600 if (s->aflag == 2) {
601 if (override >= 0) {
602 gen_op_movq_A0_seg(override);
603 gen_op_addq_A0_reg_sN(0, R_ESI);
604 } else {
605 gen_op_movq_A0_reg(R_ESI);
606 }
607 } else
608 #endif
609 if (s->aflag) {
610 /* 32 bit address */
611 if (s->addseg && override < 0)
612 override = R_DS;
613 if (override >= 0) {
614 gen_op_movl_A0_seg(override);
615 gen_op_addl_A0_reg_sN(0, R_ESI);
616 } else {
617 gen_op_movl_A0_reg(R_ESI);
618 }
619 } else {
620 /* 16 address, always override */
621 if (override < 0)
622 override = R_DS;
623 gen_op_movl_A0_reg(R_ESI);
624 gen_op_andl_A0_ffff();
625 gen_op_addl_A0_seg(override);
626 }
627 }
628
629 static inline void gen_string_movl_A0_EDI(DisasContext *s)
630 {
631 #ifdef TARGET_X86_64
632 if (s->aflag == 2) {
633 gen_op_movq_A0_reg(R_EDI);
634 } else
635 #endif
636 if (s->aflag) {
637 if (s->addseg) {
638 gen_op_movl_A0_seg(R_ES);
639 gen_op_addl_A0_reg_sN(0, R_EDI);
640 } else {
641 gen_op_movl_A0_reg(R_EDI);
642 }
643 } else {
644 gen_op_movl_A0_reg(R_EDI);
645 gen_op_andl_A0_ffff();
646 gen_op_addl_A0_seg(R_ES);
647 }
648 }
649
650 static inline void gen_op_movl_T0_Dshift(int ot)
651 {
652 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
653 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
654 };
655
656 static void gen_extu(int ot, TCGv reg)
657 {
658 switch(ot) {
659 case OT_BYTE:
660 tcg_gen_ext8u_tl(reg, reg);
661 break;
662 case OT_WORD:
663 tcg_gen_ext16u_tl(reg, reg);
664 break;
665 case OT_LONG:
666 tcg_gen_ext32u_tl(reg, reg);
667 break;
668 default:
669 break;
670 }
671 }
672
673 static void gen_exts(int ot, TCGv reg)
674 {
675 switch(ot) {
676 case OT_BYTE:
677 tcg_gen_ext8s_tl(reg, reg);
678 break;
679 case OT_WORD:
680 tcg_gen_ext16s_tl(reg, reg);
681 break;
682 case OT_LONG:
683 tcg_gen_ext32s_tl(reg, reg);
684 break;
685 default:
686 break;
687 }
688 }
689
690 static inline void gen_op_jnz_ecx(int size, int label1)
691 {
692 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
693 gen_extu(size + 1, cpu_tmp0);
694 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
695 }
696
697 static inline void gen_op_jz_ecx(int size, int label1)
698 {
699 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
700 gen_extu(size + 1, cpu_tmp0);
701 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
702 }
703
704 static void *helper_in_func[3] = {
705 helper_inb,
706 helper_inw,
707 helper_inl,
708 };
709
710 static void *helper_out_func[3] = {
711 helper_outb,
712 helper_outw,
713 helper_outl,
714 };
715
716 static void *gen_check_io_func[3] = {
717 helper_check_iob,
718 helper_check_iow,
719 helper_check_iol,
720 };
721
722 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
723 uint32_t svm_flags)
724 {
725 int state_saved;
726 target_ulong next_eip;
727
728 state_saved = 0;
729 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
730 if (s->cc_op != CC_OP_DYNAMIC)
731 gen_op_set_cc_op(s->cc_op);
732 gen_jmp_im(cur_eip);
733 state_saved = 1;
734 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
735 tcg_gen_helper_0_1(gen_check_io_func[ot],
736 cpu_tmp2_i32);
737 }
738 if(s->flags & HF_SVMI_MASK) {
739 if (!state_saved) {
740 if (s->cc_op != CC_OP_DYNAMIC)
741 gen_op_set_cc_op(s->cc_op);
742 gen_jmp_im(cur_eip);
743 state_saved = 1;
744 }
745 svm_flags |= (1 << (4 + ot));
746 next_eip = s->pc - s->cs_base;
747 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
748 tcg_gen_helper_0_3(helper_svm_check_io,
749 cpu_tmp2_i32,
750 tcg_const_i32(svm_flags),
751 tcg_const_i32(next_eip - cur_eip));
752 }
753 }
754
755 static inline void gen_movs(DisasContext *s, int ot)
756 {
757 gen_string_movl_A0_ESI(s);
758 gen_op_ld_T0_A0(ot + s->mem_index);
759 gen_string_movl_A0_EDI(s);
760 gen_op_st_T0_A0(ot + s->mem_index);
761 gen_op_movl_T0_Dshift(ot);
762 gen_op_add_reg_T0(s->aflag, R_ESI);
763 gen_op_add_reg_T0(s->aflag, R_EDI);
764 }
765
766 static inline void gen_update_cc_op(DisasContext *s)
767 {
768 if (s->cc_op != CC_OP_DYNAMIC) {
769 gen_op_set_cc_op(s->cc_op);
770 s->cc_op = CC_OP_DYNAMIC;
771 }
772 }
773
774 static void gen_op_update1_cc(void)
775 {
776 tcg_gen_discard_tl(cpu_cc_src);
777 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
778 }
779
780 static void gen_op_update2_cc(void)
781 {
782 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
783 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
784 }
785
786 static inline void gen_op_cmpl_T0_T1_cc(void)
787 {
788 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
789 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
790 }
791
792 static inline void gen_op_testl_T0_T1_cc(void)
793 {
794 tcg_gen_discard_tl(cpu_cc_src);
795 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
796 }
797
798 static void gen_op_update_neg_cc(void)
799 {
800 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
801 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
802 }
803
804 /* compute eflags.C to reg */
805 static void gen_compute_eflags_c(TCGv reg)
806 {
807 #if TCG_TARGET_REG_BITS == 32
808 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
809 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
810 (long)cc_table + offsetof(CCTable, compute_c));
811 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
812 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
813 1, &cpu_tmp2_i32, 0, NULL);
814 #else
815 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
816 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
817 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
818 (long)cc_table + offsetof(CCTable, compute_c));
819 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
820 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
821 1, &cpu_tmp2_i32, 0, NULL);
822 #endif
823 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
824 }
825
826 /* compute all eflags to cc_src */
827 static void gen_compute_eflags(TCGv reg)
828 {
829 #if TCG_TARGET_REG_BITS == 32
830 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
831 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
832 (long)cc_table + offsetof(CCTable, compute_all));
833 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
834 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
835 1, &cpu_tmp2_i32, 0, NULL);
836 #else
837 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
838 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
839 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
840 (long)cc_table + offsetof(CCTable, compute_all));
841 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
842 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
843 1, &cpu_tmp2_i32, 0, NULL);
844 #endif
845 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
846 }
847
848 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
849 {
850 if (s->cc_op != CC_OP_DYNAMIC)
851 gen_op_set_cc_op(s->cc_op);
852 switch(jcc_op) {
853 case JCC_O:
854 gen_compute_eflags(cpu_T[0]);
855 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
856 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
857 break;
858 case JCC_B:
859 gen_compute_eflags_c(cpu_T[0]);
860 break;
861 case JCC_Z:
862 gen_compute_eflags(cpu_T[0]);
863 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
864 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865 break;
866 case JCC_BE:
867 gen_compute_eflags(cpu_tmp0);
868 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
869 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
870 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
871 break;
872 case JCC_S:
873 gen_compute_eflags(cpu_T[0]);
874 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
875 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
876 break;
877 case JCC_P:
878 gen_compute_eflags(cpu_T[0]);
879 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
880 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
881 break;
882 case JCC_L:
883 gen_compute_eflags(cpu_tmp0);
884 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
885 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
886 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
887 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
888 break;
889 default:
890 case JCC_LE:
891 gen_compute_eflags(cpu_tmp0);
892 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
893 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
894 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
895 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
896 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
897 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
898 break;
899 }
900 }
901
902 /* return true if setcc_slow is not needed (WARNING: must be kept in
903 sync with gen_jcc1) */
904 static int is_fast_jcc_case(DisasContext *s, int b)
905 {
906 int jcc_op;
907 jcc_op = (b >> 1) & 7;
908 switch(s->cc_op) {
909 /* we optimize the cmp/jcc case */
910 case CC_OP_SUBB:
911 case CC_OP_SUBW:
912 case CC_OP_SUBL:
913 case CC_OP_SUBQ:
914 if (jcc_op == JCC_O || jcc_op == JCC_P)
915 goto slow_jcc;
916 break;
917
918 /* some jumps are easy to compute */
919 case CC_OP_ADDB:
920 case CC_OP_ADDW:
921 case CC_OP_ADDL:
922 case CC_OP_ADDQ:
923
924 case CC_OP_LOGICB:
925 case CC_OP_LOGICW:
926 case CC_OP_LOGICL:
927 case CC_OP_LOGICQ:
928
929 case CC_OP_INCB:
930 case CC_OP_INCW:
931 case CC_OP_INCL:
932 case CC_OP_INCQ:
933
934 case CC_OP_DECB:
935 case CC_OP_DECW:
936 case CC_OP_DECL:
937 case CC_OP_DECQ:
938
939 case CC_OP_SHLB:
940 case CC_OP_SHLW:
941 case CC_OP_SHLL:
942 case CC_OP_SHLQ:
943 if (jcc_op != JCC_Z && jcc_op != JCC_S)
944 goto slow_jcc;
945 break;
946 default:
947 slow_jcc:
948 return 0;
949 }
950 return 1;
951 }
952
953 /* generate a conditional jump to label 'l1' according to jump opcode
954 value 'b'. In the fast case, T0 is guaranted not to be used. */
955 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
956 {
957 int inv, jcc_op, size, cond;
958 TCGv t0;
959
960 inv = b & 1;
961 jcc_op = (b >> 1) & 7;
962
963 switch(cc_op) {
964 /* we optimize the cmp/jcc case */
965 case CC_OP_SUBB:
966 case CC_OP_SUBW:
967 case CC_OP_SUBL:
968 case CC_OP_SUBQ:
969
970 size = cc_op - CC_OP_SUBB;
971 switch(jcc_op) {
972 case JCC_Z:
973 fast_jcc_z:
974 switch(size) {
975 case 0:
976 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
977 t0 = cpu_tmp0;
978 break;
979 case 1:
980 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
981 t0 = cpu_tmp0;
982 break;
983 #ifdef TARGET_X86_64
984 case 2:
985 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
986 t0 = cpu_tmp0;
987 break;
988 #endif
989 default:
990 t0 = cpu_cc_dst;
991 break;
992 }
993 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
994 break;
995 case JCC_S:
996 fast_jcc_s:
997 switch(size) {
998 case 0:
999 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
1000 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1001 0, l1);
1002 break;
1003 case 1:
1004 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
1005 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1006 0, l1);
1007 break;
1008 #ifdef TARGET_X86_64
1009 case 2:
1010 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1011 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1012 0, l1);
1013 break;
1014 #endif
1015 default:
1016 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1017 0, l1);
1018 break;
1019 }
1020 break;
1021
1022 case JCC_B:
1023 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1024 goto fast_jcc_b;
1025 case JCC_BE:
1026 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1027 fast_jcc_b:
1028 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1029 switch(size) {
1030 case 0:
1031 t0 = cpu_tmp0;
1032 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1033 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1034 break;
1035 case 1:
1036 t0 = cpu_tmp0;
1037 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1038 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1039 break;
1040 #ifdef TARGET_X86_64
1041 case 2:
1042 t0 = cpu_tmp0;
1043 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1044 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1045 break;
1046 #endif
1047 default:
1048 t0 = cpu_cc_src;
1049 break;
1050 }
1051 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1052 break;
1053
1054 case JCC_L:
1055 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1056 goto fast_jcc_l;
1057 case JCC_LE:
1058 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1059 fast_jcc_l:
1060 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1061 switch(size) {
1062 case 0:
1063 t0 = cpu_tmp0;
1064 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1065 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1066 break;
1067 case 1:
1068 t0 = cpu_tmp0;
1069 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1070 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1071 break;
1072 #ifdef TARGET_X86_64
1073 case 2:
1074 t0 = cpu_tmp0;
1075 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1076 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1077 break;
1078 #endif
1079 default:
1080 t0 = cpu_cc_src;
1081 break;
1082 }
1083 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1084 break;
1085
1086 default:
1087 goto slow_jcc;
1088 }
1089 break;
1090
1091 /* some jumps are easy to compute */
1092 case CC_OP_ADDB:
1093 case CC_OP_ADDW:
1094 case CC_OP_ADDL:
1095 case CC_OP_ADDQ:
1096
1097 case CC_OP_ADCB:
1098 case CC_OP_ADCW:
1099 case CC_OP_ADCL:
1100 case CC_OP_ADCQ:
1101
1102 case CC_OP_SBBB:
1103 case CC_OP_SBBW:
1104 case CC_OP_SBBL:
1105 case CC_OP_SBBQ:
1106
1107 case CC_OP_LOGICB:
1108 case CC_OP_LOGICW:
1109 case CC_OP_LOGICL:
1110 case CC_OP_LOGICQ:
1111
1112 case CC_OP_INCB:
1113 case CC_OP_INCW:
1114 case CC_OP_INCL:
1115 case CC_OP_INCQ:
1116
1117 case CC_OP_DECB:
1118 case CC_OP_DECW:
1119 case CC_OP_DECL:
1120 case CC_OP_DECQ:
1121
1122 case CC_OP_SHLB:
1123 case CC_OP_SHLW:
1124 case CC_OP_SHLL:
1125 case CC_OP_SHLQ:
1126
1127 case CC_OP_SARB:
1128 case CC_OP_SARW:
1129 case CC_OP_SARL:
1130 case CC_OP_SARQ:
1131 switch(jcc_op) {
1132 case JCC_Z:
1133 size = (cc_op - CC_OP_ADDB) & 3;
1134 goto fast_jcc_z;
1135 case JCC_S:
1136 size = (cc_op - CC_OP_ADDB) & 3;
1137 goto fast_jcc_s;
1138 default:
1139 goto slow_jcc;
1140 }
1141 break;
1142 default:
1143 slow_jcc:
1144 gen_setcc_slow_T0(s, jcc_op);
1145 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1146 cpu_T[0], 0, l1);
1147 break;
1148 }
1149 }
1150
1151 /* XXX: does not work with gdbstub "ice" single step - not a
1152 serious problem */
1153 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1154 {
1155 int l1, l2;
1156
1157 l1 = gen_new_label();
1158 l2 = gen_new_label();
1159 gen_op_jnz_ecx(s->aflag, l1);
1160 gen_set_label(l2);
1161 gen_jmp_tb(s, next_eip, 1);
1162 gen_set_label(l1);
1163 return l2;
1164 }
1165
1166 static inline void gen_stos(DisasContext *s, int ot)
1167 {
1168 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1169 gen_string_movl_A0_EDI(s);
1170 gen_op_st_T0_A0(ot + s->mem_index);
1171 gen_op_movl_T0_Dshift(ot);
1172 gen_op_add_reg_T0(s->aflag, R_EDI);
1173 }
1174
1175 static inline void gen_lods(DisasContext *s, int ot)
1176 {
1177 gen_string_movl_A0_ESI(s);
1178 gen_op_ld_T0_A0(ot + s->mem_index);
1179 gen_op_mov_reg_T0(ot, R_EAX);
1180 gen_op_movl_T0_Dshift(ot);
1181 gen_op_add_reg_T0(s->aflag, R_ESI);
1182 }
1183
1184 static inline void gen_scas(DisasContext *s, int ot)
1185 {
1186 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1187 gen_string_movl_A0_EDI(s);
1188 gen_op_ld_T1_A0(ot + s->mem_index);
1189 gen_op_cmpl_T0_T1_cc();
1190 gen_op_movl_T0_Dshift(ot);
1191 gen_op_add_reg_T0(s->aflag, R_EDI);
1192 }
1193
1194 static inline void gen_cmps(DisasContext *s, int ot)
1195 {
1196 gen_string_movl_A0_ESI(s);
1197 gen_op_ld_T0_A0(ot + s->mem_index);
1198 gen_string_movl_A0_EDI(s);
1199 gen_op_ld_T1_A0(ot + s->mem_index);
1200 gen_op_cmpl_T0_T1_cc();
1201 gen_op_movl_T0_Dshift(ot);
1202 gen_op_add_reg_T0(s->aflag, R_ESI);
1203 gen_op_add_reg_T0(s->aflag, R_EDI);
1204 }
1205
1206 static inline void gen_ins(DisasContext *s, int ot)
1207 {
1208 if (use_icount)
1209 gen_io_start();
1210 gen_string_movl_A0_EDI(s);
1211 /* Note: we must do this dummy write first to be restartable in
1212 case of page fault. */
1213 gen_op_movl_T0_0();
1214 gen_op_st_T0_A0(ot + s->mem_index);
1215 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1216 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1217 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1218 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32);
1219 gen_op_st_T0_A0(ot + s->mem_index);
1220 gen_op_movl_T0_Dshift(ot);
1221 gen_op_add_reg_T0(s->aflag, R_EDI);
1222 if (use_icount)
1223 gen_io_end();
1224 }
1225
1226 static inline void gen_outs(DisasContext *s, int ot)
1227 {
1228 if (use_icount)
1229 gen_io_start();
1230 gen_string_movl_A0_ESI(s);
1231 gen_op_ld_T0_A0(ot + s->mem_index);
1232
1233 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1234 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1235 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1236 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1237 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
1238
1239 gen_op_movl_T0_Dshift(ot);
1240 gen_op_add_reg_T0(s->aflag, R_ESI);
1241 if (use_icount)
1242 gen_io_end();
1243 }
1244
1245 /* same method as Valgrind : we generate jumps to current or next
1246 instruction */
1247 #define GEN_REPZ(op) \
1248 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1249 target_ulong cur_eip, target_ulong next_eip) \
1250 { \
1251 int l2;\
1252 gen_update_cc_op(s); \
1253 l2 = gen_jz_ecx_string(s, next_eip); \
1254 gen_ ## op(s, ot); \
1255 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1256 /* a loop would cause two single step exceptions if ECX = 1 \
1257 before rep string_insn */ \
1258 if (!s->jmp_opt) \
1259 gen_op_jz_ecx(s->aflag, l2); \
1260 gen_jmp(s, cur_eip); \
1261 }
1262
1263 #define GEN_REPZ2(op) \
1264 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1265 target_ulong cur_eip, \
1266 target_ulong next_eip, \
1267 int nz) \
1268 { \
1269 int l2;\
1270 gen_update_cc_op(s); \
1271 l2 = gen_jz_ecx_string(s, next_eip); \
1272 gen_ ## op(s, ot); \
1273 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1274 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1275 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1276 if (!s->jmp_opt) \
1277 gen_op_jz_ecx(s->aflag, l2); \
1278 gen_jmp(s, cur_eip); \
1279 }
1280
1281 GEN_REPZ(movs)
1282 GEN_REPZ(stos)
1283 GEN_REPZ(lods)
1284 GEN_REPZ(ins)
1285 GEN_REPZ(outs)
1286 GEN_REPZ2(scas)
1287 GEN_REPZ2(cmps)
1288
1289 static void *helper_fp_arith_ST0_FT0[8] = {
1290 helper_fadd_ST0_FT0,
1291 helper_fmul_ST0_FT0,
1292 helper_fcom_ST0_FT0,
1293 helper_fcom_ST0_FT0,
1294 helper_fsub_ST0_FT0,
1295 helper_fsubr_ST0_FT0,
1296 helper_fdiv_ST0_FT0,
1297 helper_fdivr_ST0_FT0,
1298 };
1299
1300 /* NOTE the exception in "r" op ordering */
1301 static void *helper_fp_arith_STN_ST0[8] = {
1302 helper_fadd_STN_ST0,
1303 helper_fmul_STN_ST0,
1304 NULL,
1305 NULL,
1306 helper_fsubr_STN_ST0,
1307 helper_fsub_STN_ST0,
1308 helper_fdivr_STN_ST0,
1309 helper_fdiv_STN_ST0,
1310 };
1311
1312 /* if d == OR_TMP0, it means memory operand (address in A0) */
1313 static void gen_op(DisasContext *s1, int op, int ot, int d)
1314 {
1315 if (d != OR_TMP0) {
1316 gen_op_mov_TN_reg(ot, 0, d);
1317 } else {
1318 gen_op_ld_T0_A0(ot + s1->mem_index);
1319 }
1320 switch(op) {
1321 case OP_ADCL:
1322 if (s1->cc_op != CC_OP_DYNAMIC)
1323 gen_op_set_cc_op(s1->cc_op);
1324 gen_compute_eflags_c(cpu_tmp4);
1325 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1326 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1327 if (d != OR_TMP0)
1328 gen_op_mov_reg_T0(ot, d);
1329 else
1330 gen_op_st_T0_A0(ot + s1->mem_index);
1331 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1332 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1333 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1334 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1335 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1336 s1->cc_op = CC_OP_DYNAMIC;
1337 break;
1338 case OP_SBBL:
1339 if (s1->cc_op != CC_OP_DYNAMIC)
1340 gen_op_set_cc_op(s1->cc_op);
1341 gen_compute_eflags_c(cpu_tmp4);
1342 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1343 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1344 if (d != OR_TMP0)
1345 gen_op_mov_reg_T0(ot, d);
1346 else
1347 gen_op_st_T0_A0(ot + s1->mem_index);
1348 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1349 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1350 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1351 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1352 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1353 s1->cc_op = CC_OP_DYNAMIC;
1354 break;
1355 case OP_ADDL:
1356 gen_op_addl_T0_T1();
1357 if (d != OR_TMP0)
1358 gen_op_mov_reg_T0(ot, d);
1359 else
1360 gen_op_st_T0_A0(ot + s1->mem_index);
1361 gen_op_update2_cc();
1362 s1->cc_op = CC_OP_ADDB + ot;
1363 break;
1364 case OP_SUBL:
1365 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1366 if (d != OR_TMP0)
1367 gen_op_mov_reg_T0(ot, d);
1368 else
1369 gen_op_st_T0_A0(ot + s1->mem_index);
1370 gen_op_update2_cc();
1371 s1->cc_op = CC_OP_SUBB + ot;
1372 break;
1373 default:
1374 case OP_ANDL:
1375 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1376 if (d != OR_TMP0)
1377 gen_op_mov_reg_T0(ot, d);
1378 else
1379 gen_op_st_T0_A0(ot + s1->mem_index);
1380 gen_op_update1_cc();
1381 s1->cc_op = CC_OP_LOGICB + ot;
1382 break;
1383 case OP_ORL:
1384 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1385 if (d != OR_TMP0)
1386 gen_op_mov_reg_T0(ot, d);
1387 else
1388 gen_op_st_T0_A0(ot + s1->mem_index);
1389 gen_op_update1_cc();
1390 s1->cc_op = CC_OP_LOGICB + ot;
1391 break;
1392 case OP_XORL:
1393 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1394 if (d != OR_TMP0)
1395 gen_op_mov_reg_T0(ot, d);
1396 else
1397 gen_op_st_T0_A0(ot + s1->mem_index);
1398 gen_op_update1_cc();
1399 s1->cc_op = CC_OP_LOGICB + ot;
1400 break;
1401 case OP_CMPL:
1402 gen_op_cmpl_T0_T1_cc();
1403 s1->cc_op = CC_OP_SUBB + ot;
1404 break;
1405 }
1406 }
1407
1408 /* if d == OR_TMP0, it means memory operand (address in A0) */
1409 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1410 {
1411 if (d != OR_TMP0)
1412 gen_op_mov_TN_reg(ot, 0, d);
1413 else
1414 gen_op_ld_T0_A0(ot + s1->mem_index);
1415 if (s1->cc_op != CC_OP_DYNAMIC)
1416 gen_op_set_cc_op(s1->cc_op);
1417 if (c > 0) {
1418 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1419 s1->cc_op = CC_OP_INCB + ot;
1420 } else {
1421 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1422 s1->cc_op = CC_OP_DECB + ot;
1423 }
1424 if (d != OR_TMP0)
1425 gen_op_mov_reg_T0(ot, d);
1426 else
1427 gen_op_st_T0_A0(ot + s1->mem_index);
1428 gen_compute_eflags_c(cpu_cc_src);
1429 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1430 }
1431
1432 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1433 int is_right, int is_arith)
1434 {
1435 target_ulong mask;
1436 int shift_label;
1437 TCGv t0, t1;
1438
1439 if (ot == OT_QUAD)
1440 mask = 0x3f;
1441 else
1442 mask = 0x1f;
1443
1444 /* load */
1445 if (op1 == OR_TMP0)
1446 gen_op_ld_T0_A0(ot + s->mem_index);
1447 else
1448 gen_op_mov_TN_reg(ot, 0, op1);
1449
1450 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1451
1452 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1453
1454 if (is_right) {
1455 if (is_arith) {
1456 gen_exts(ot, cpu_T[0]);
1457 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1458 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1459 } else {
1460 gen_extu(ot, cpu_T[0]);
1461 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1462 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1463 }
1464 } else {
1465 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1466 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1467 }
1468
1469 /* store */
1470 if (op1 == OR_TMP0)
1471 gen_op_st_T0_A0(ot + s->mem_index);
1472 else
1473 gen_op_mov_reg_T0(ot, op1);
1474
1475 /* update eflags if non zero shift */
1476 if (s->cc_op != CC_OP_DYNAMIC)
1477 gen_op_set_cc_op(s->cc_op);
1478
1479 /* XXX: inefficient */
1480 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1481 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1482
1483 tcg_gen_mov_tl(t0, cpu_T[0]);
1484 tcg_gen_mov_tl(t1, cpu_T3);
1485
1486 shift_label = gen_new_label();
1487 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1488
1489 tcg_gen_mov_tl(cpu_cc_src, t1);
1490 tcg_gen_mov_tl(cpu_cc_dst, t0);
1491 if (is_right)
1492 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1493 else
1494 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1495
1496 gen_set_label(shift_label);
1497 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1498
1499 tcg_temp_free(t0);
1500 tcg_temp_free(t1);
1501 }
1502
1503 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1504 int is_right, int is_arith)
1505 {
1506 int mask;
1507
1508 if (ot == OT_QUAD)
1509 mask = 0x3f;
1510 else
1511 mask = 0x1f;
1512
1513 /* load */
1514 if (op1 == OR_TMP0)
1515 gen_op_ld_T0_A0(ot + s->mem_index);
1516 else
1517 gen_op_mov_TN_reg(ot, 0, op1);
1518
1519 op2 &= mask;
1520 if (op2 != 0) {
1521 if (is_right) {
1522 if (is_arith) {
1523 gen_exts(ot, cpu_T[0]);
1524 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1525 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1526 } else {
1527 gen_extu(ot, cpu_T[0]);
1528 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1529 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1530 }
1531 } else {
1532 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1533 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1534 }
1535 }
1536
1537 /* store */
1538 if (op1 == OR_TMP0)
1539 gen_op_st_T0_A0(ot + s->mem_index);
1540 else
1541 gen_op_mov_reg_T0(ot, op1);
1542
1543 /* update eflags if non zero shift */
1544 if (op2 != 0) {
1545 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1546 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1547 if (is_right)
1548 s->cc_op = CC_OP_SARB + ot;
1549 else
1550 s->cc_op = CC_OP_SHLB + ot;
1551 }
1552 }
1553
1554 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1555 {
1556 if (arg2 >= 0)
1557 tcg_gen_shli_tl(ret, arg1, arg2);
1558 else
1559 tcg_gen_shri_tl(ret, arg1, -arg2);
1560 }
1561
1562 /* XXX: add faster immediate case */
1563 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1564 int is_right)
1565 {
1566 target_ulong mask;
1567 int label1, label2, data_bits;
1568 TCGv t0, t1, t2, a0;
1569
1570 /* XXX: inefficient, but we must use local temps */
1571 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1572 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1573 t2 = tcg_temp_local_new(TCG_TYPE_TL);
1574 a0 = tcg_temp_local_new(TCG_TYPE_TL);
1575
1576 if (ot == OT_QUAD)
1577 mask = 0x3f;
1578 else
1579 mask = 0x1f;
1580
1581 /* load */
1582 if (op1 == OR_TMP0) {
1583 tcg_gen_mov_tl(a0, cpu_A0);
1584 gen_op_ld_v(ot + s->mem_index, t0, a0);
1585 } else {
1586 gen_op_mov_v_reg(ot, t0, op1);
1587 }
1588
1589 tcg_gen_mov_tl(t1, cpu_T[1]);
1590
1591 tcg_gen_andi_tl(t1, t1, mask);
1592
1593 /* Must test zero case to avoid using undefined behaviour in TCG
1594 shifts. */
1595 label1 = gen_new_label();
1596 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1597
1598 if (ot <= OT_WORD)
1599 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1600 else
1601 tcg_gen_mov_tl(cpu_tmp0, t1);
1602
1603 gen_extu(ot, t0);
1604 tcg_gen_mov_tl(t2, t0);
1605
1606 data_bits = 8 << ot;
1607 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1608 fix TCG definition) */
1609 if (is_right) {
1610 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1611 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1612 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1613 } else {
1614 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1615 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1616 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1617 }
1618 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1619
1620 gen_set_label(label1);
1621 /* store */
1622 if (op1 == OR_TMP0) {
1623 gen_op_st_v(ot + s->mem_index, t0, a0);
1624 } else {
1625 gen_op_mov_reg_v(ot, op1, t0);
1626 }
1627
1628 /* update eflags */
1629 if (s->cc_op != CC_OP_DYNAMIC)
1630 gen_op_set_cc_op(s->cc_op);
1631
1632 label2 = gen_new_label();
1633 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1634
1635 gen_compute_eflags(cpu_cc_src);
1636 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1637 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1638 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1639 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1640 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1641 if (is_right) {
1642 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1643 }
1644 tcg_gen_andi_tl(t0, t0, CC_C);
1645 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1646
1647 tcg_gen_discard_tl(cpu_cc_dst);
1648 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1649
1650 gen_set_label(label2);
1651 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1652
1653 tcg_temp_free(t0);
1654 tcg_temp_free(t1);
1655 tcg_temp_free(t2);
1656 tcg_temp_free(a0);
1657 }
1658
1659 static void *helper_rotc[8] = {
1660 helper_rclb,
1661 helper_rclw,
1662 helper_rcll,
1663 X86_64_ONLY(helper_rclq),
1664 helper_rcrb,
1665 helper_rcrw,
1666 helper_rcrl,
1667 X86_64_ONLY(helper_rcrq),
1668 };
1669
1670 /* XXX: add faster immediate = 1 case */
1671 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1672 int is_right)
1673 {
1674 int label1;
1675
1676 if (s->cc_op != CC_OP_DYNAMIC)
1677 gen_op_set_cc_op(s->cc_op);
1678
1679 /* load */
1680 if (op1 == OR_TMP0)
1681 gen_op_ld_T0_A0(ot + s->mem_index);
1682 else
1683 gen_op_mov_TN_reg(ot, 0, op1);
1684
1685 tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)],
1686 cpu_T[0], cpu_T[0], cpu_T[1]);
1687 /* store */
1688 if (op1 == OR_TMP0)
1689 gen_op_st_T0_A0(ot + s->mem_index);
1690 else
1691 gen_op_mov_reg_T0(ot, op1);
1692
1693 /* update eflags */
1694 label1 = gen_new_label();
1695 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1696
1697 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1698 tcg_gen_discard_tl(cpu_cc_dst);
1699 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1700
1701 gen_set_label(label1);
1702 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1703 }
1704
1705 /* XXX: add faster immediate case */
1706 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1707 int is_right)
1708 {
1709 int label1, label2, data_bits;
1710 target_ulong mask;
1711 TCGv t0, t1, t2, a0;
1712
1713 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1714 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1715 t2 = tcg_temp_local_new(TCG_TYPE_TL);
1716 a0 = tcg_temp_local_new(TCG_TYPE_TL);
1717
1718 if (ot == OT_QUAD)
1719 mask = 0x3f;
1720 else
1721 mask = 0x1f;
1722
1723 /* load */
1724 if (op1 == OR_TMP0) {
1725 tcg_gen_mov_tl(a0, cpu_A0);
1726 gen_op_ld_v(ot + s->mem_index, t0, a0);
1727 } else {
1728 gen_op_mov_v_reg(ot, t0, op1);
1729 }
1730
1731 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1732
1733 tcg_gen_mov_tl(t1, cpu_T[1]);
1734 tcg_gen_mov_tl(t2, cpu_T3);
1735
1736 /* Must test zero case to avoid using undefined behaviour in TCG
1737 shifts. */
1738 label1 = gen_new_label();
1739 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1740
1741 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1742 if (ot == OT_WORD) {
1743 /* Note: we implement the Intel behaviour for shift count > 16 */
1744 if (is_right) {
1745 tcg_gen_andi_tl(t0, t0, 0xffff);
1746 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1747 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1748 tcg_gen_ext32u_tl(t0, t0);
1749
1750 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1751
1752 /* only needed if count > 16, but a test would complicate */
1753 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1754 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1755
1756 tcg_gen_shr_tl(t0, t0, t2);
1757
1758 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1759 } else {
1760 /* XXX: not optimal */
1761 tcg_gen_andi_tl(t0, t0, 0xffff);
1762 tcg_gen_shli_tl(t1, t1, 16);
1763 tcg_gen_or_tl(t1, t1, t0);
1764 tcg_gen_ext32u_tl(t1, t1);
1765
1766 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1767 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
1768 tcg_gen_shr_tl(cpu_tmp6, t1, cpu_tmp0);
1769 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);
1770
1771 tcg_gen_shl_tl(t0, t0, t2);
1772 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1773 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1774 tcg_gen_or_tl(t0, t0, t1);
1775 }
1776 } else {
1777 data_bits = 8 << ot;
1778 if (is_right) {
1779 if (ot == OT_LONG)
1780 tcg_gen_ext32u_tl(t0, t0);
1781
1782 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1783
1784 tcg_gen_shr_tl(t0, t0, t2);
1785 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1786 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1787 tcg_gen_or_tl(t0, t0, t1);
1788
1789 } else {
1790 if (ot == OT_LONG)
1791 tcg_gen_ext32u_tl(t1, t1);
1792
1793 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1794
1795 tcg_gen_shl_tl(t0, t0, t2);
1796 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1797 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1798 tcg_gen_or_tl(t0, t0, t1);
1799 }
1800 }
1801 tcg_gen_mov_tl(t1, cpu_tmp4);
1802
1803 gen_set_label(label1);
1804 /* store */
1805 if (op1 == OR_TMP0) {
1806 gen_op_st_v(ot + s->mem_index, t0, a0);
1807 } else {
1808 gen_op_mov_reg_v(ot, op1, t0);
1809 }
1810
1811 /* update eflags */
1812 if (s->cc_op != CC_OP_DYNAMIC)
1813 gen_op_set_cc_op(s->cc_op);
1814
1815 label2 = gen_new_label();
1816 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1817
1818 tcg_gen_mov_tl(cpu_cc_src, t1);
1819 tcg_gen_mov_tl(cpu_cc_dst, t0);
1820 if (is_right) {
1821 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1822 } else {
1823 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1824 }
1825 gen_set_label(label2);
1826 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1827
1828 tcg_temp_free(t0);
1829 tcg_temp_free(t1);
1830 tcg_temp_free(t2);
1831 tcg_temp_free(a0);
1832 }
1833
1834 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1835 {
1836 if (s != OR_TMP1)
1837 gen_op_mov_TN_reg(ot, 1, s);
1838 switch(op) {
1839 case OP_ROL:
1840 gen_rot_rm_T1(s1, ot, d, 0);
1841 break;
1842 case OP_ROR:
1843 gen_rot_rm_T1(s1, ot, d, 1);
1844 break;
1845 case OP_SHL:
1846 case OP_SHL1:
1847 gen_shift_rm_T1(s1, ot, d, 0, 0);
1848 break;
1849 case OP_SHR:
1850 gen_shift_rm_T1(s1, ot, d, 1, 0);
1851 break;
1852 case OP_SAR:
1853 gen_shift_rm_T1(s1, ot, d, 1, 1);
1854 break;
1855 case OP_RCL:
1856 gen_rotc_rm_T1(s1, ot, d, 0);
1857 break;
1858 case OP_RCR:
1859 gen_rotc_rm_T1(s1, ot, d, 1);
1860 break;
1861 }
1862 }
1863
1864 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1865 {
1866 switch(op) {
1867 case OP_SHL:
1868 case OP_SHL1:
1869 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1870 break;
1871 case OP_SHR:
1872 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1873 break;
1874 case OP_SAR:
1875 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1876 break;
1877 default:
1878 /* currently not optimized */
1879 gen_op_movl_T1_im(c);
1880 gen_shift(s1, op, ot, d, OR_TMP1);
1881 break;
1882 }
1883 }
1884
1885 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1886 {
1887 target_long disp;
1888 int havesib;
1889 int base;
1890 int index;
1891 int scale;
1892 int opreg;
1893 int mod, rm, code, override, must_add_seg;
1894
1895 override = s->override;
1896 must_add_seg = s->addseg;
1897 if (override >= 0)
1898 must_add_seg = 1;
1899 mod = (modrm >> 6) & 3;
1900 rm = modrm & 7;
1901
1902 if (s->aflag) {
1903
1904 havesib = 0;
1905 base = rm;
1906 index = 0;
1907 scale = 0;
1908
1909 if (base == 4) {
1910 havesib = 1;
1911 code = ldub_code(s->pc++);
1912 scale = (code >> 6) & 3;
1913 index = ((code >> 3) & 7) | REX_X(s);
1914 base = (code & 7);
1915 }
1916 base |= REX_B(s);
1917
1918 switch (mod) {
1919 case 0:
1920 if ((base & 7) == 5) {
1921 base = -1;
1922 disp = (int32_t)ldl_code(s->pc);
1923 s->pc += 4;
1924 if (CODE64(s) && !havesib) {
1925 disp += s->pc + s->rip_offset;
1926 }
1927 } else {
1928 disp = 0;
1929 }
1930 break;
1931 case 1:
1932 disp = (int8_t)ldub_code(s->pc++);
1933 break;
1934 default:
1935 case 2:
1936 disp = ldl_code(s->pc);
1937 s->pc += 4;
1938 break;
1939 }
1940
1941 if (base >= 0) {
1942 /* for correct popl handling with esp */
1943 if (base == 4 && s->popl_esp_hack)
1944 disp += s->popl_esp_hack;
1945 #ifdef TARGET_X86_64
1946 if (s->aflag == 2) {
1947 gen_op_movq_A0_reg(base);
1948 if (disp != 0) {
1949 gen_op_addq_A0_im(disp);
1950 }
1951 } else
1952 #endif
1953 {
1954 gen_op_movl_A0_reg(base);
1955 if (disp != 0)
1956 gen_op_addl_A0_im(disp);
1957 }
1958 } else {
1959 #ifdef TARGET_X86_64
1960 if (s->aflag == 2) {
1961 gen_op_movq_A0_im(disp);
1962 } else
1963 #endif
1964 {
1965 gen_op_movl_A0_im(disp);
1966 }
1967 }
1968 /* XXX: index == 4 is always invalid */
1969 if (havesib && (index != 4 || scale != 0)) {
1970 #ifdef TARGET_X86_64
1971 if (s->aflag == 2) {
1972 gen_op_addq_A0_reg_sN(scale, index);
1973 } else
1974 #endif
1975 {
1976 gen_op_addl_A0_reg_sN(scale, index);
1977 }
1978 }
1979 if (must_add_seg) {
1980 if (override < 0) {
1981 if (base == R_EBP || base == R_ESP)
1982 override = R_SS;
1983 else
1984 override = R_DS;
1985 }
1986 #ifdef TARGET_X86_64
1987 if (s->aflag == 2) {
1988 gen_op_addq_A0_seg(override);
1989 } else
1990 #endif
1991 {
1992 gen_op_addl_A0_seg(override);
1993 }
1994 }
1995 } else {
1996 switch (mod) {
1997 case 0:
1998 if (rm == 6) {
1999 disp = lduw_code(s->pc);
2000 s->pc += 2;
2001 gen_op_movl_A0_im(disp);
2002 rm = 0; /* avoid SS override */
2003 goto no_rm;
2004 } else {
2005 disp = 0;
2006 }
2007 break;
2008 case 1:
2009 disp = (int8_t)ldub_code(s->pc++);
2010 break;
2011 default:
2012 case 2:
2013 disp = lduw_code(s->pc);
2014 s->pc += 2;
2015 break;
2016 }
2017 switch(rm) {
2018 case 0:
2019 gen_op_movl_A0_reg(R_EBX);
2020 gen_op_addl_A0_reg_sN(0, R_ESI);
2021 break;
2022 case 1:
2023 gen_op_movl_A0_reg(R_EBX);
2024 gen_op_addl_A0_reg_sN(0, R_EDI);
2025 break;
2026 case 2:
2027 gen_op_movl_A0_reg(R_EBP);
2028 gen_op_addl_A0_reg_sN(0, R_ESI);
2029 break;
2030 case 3:
2031 gen_op_movl_A0_reg(R_EBP);
2032 gen_op_addl_A0_reg_sN(0, R_EDI);
2033 break;
2034 case 4:
2035 gen_op_movl_A0_reg(R_ESI);
2036 break;
2037 case 5:
2038 gen_op_movl_A0_reg(R_EDI);
2039 break;
2040 case 6:
2041 gen_op_movl_A0_reg(R_EBP);
2042 break;
2043 default:
2044 case 7:
2045 gen_op_movl_A0_reg(R_EBX);
2046 break;
2047 }
2048 if (disp != 0)
2049 gen_op_addl_A0_im(disp);
2050 gen_op_andl_A0_ffff();
2051 no_rm:
2052 if (must_add_seg) {
2053 if (override < 0) {
2054 if (rm == 2 || rm == 3 || rm == 6)
2055 override = R_SS;
2056 else
2057 override = R_DS;
2058 }
2059 gen_op_addl_A0_seg(override);
2060 }
2061 }
2062
2063 opreg = OR_A0;
2064 disp = 0;
2065 *reg_ptr = opreg;
2066 *offset_ptr = disp;
2067 }
2068
2069 static void gen_nop_modrm(DisasContext *s, int modrm)
2070 {
2071 int mod, rm, base, code;
2072
2073 mod = (modrm >> 6) & 3;
2074 if (mod == 3)
2075 return;
2076 rm = modrm & 7;
2077
2078 if (s->aflag) {
2079
2080 base = rm;
2081
2082 if (base == 4) {
2083 code = ldub_code(s->pc++);
2084 base = (code & 7);
2085 }
2086
2087 switch (mod) {
2088 case 0:
2089 if (base == 5) {
2090 s->pc += 4;
2091 }
2092 break;
2093 case 1:
2094 s->pc++;
2095 break;
2096 default:
2097 case 2:
2098 s->pc += 4;
2099 break;
2100 }
2101 } else {
2102 switch (mod) {
2103 case 0:
2104 if (rm == 6) {
2105 s->pc += 2;
2106 }
2107 break;
2108 case 1:
2109 s->pc++;
2110 break;
2111 default:
2112 case 2:
2113 s->pc += 2;
2114 break;
2115 }
2116 }
2117 }
2118
2119 /* used for LEA and MOV AX, mem */
2120 static void gen_add_A0_ds_seg(DisasContext *s)
2121 {
2122 int override, must_add_seg;
2123 must_add_seg = s->addseg;
2124 override = R_DS;
2125 if (s->override >= 0) {
2126 override = s->override;
2127 must_add_seg = 1;
2128 } else {
2129 override = R_DS;
2130 }
2131 if (must_add_seg) {
2132 #ifdef TARGET_X86_64
2133 if (CODE64(s)) {
2134 gen_op_addq_A0_seg(override);
2135 } else
2136 #endif
2137 {
2138 gen_op_addl_A0_seg(override);
2139 }
2140 }
2141 }
2142
2143 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
2144 OR_TMP0 */
2145 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2146 {
2147 int mod, rm, opreg, disp;
2148
2149 mod = (modrm >> 6) & 3;
2150 rm = (modrm & 7) | REX_B(s);
2151 if (mod == 3) {
2152 if (is_store) {
2153 if (reg != OR_TMP0)
2154 gen_op_mov_TN_reg(ot, 0, reg);
2155 gen_op_mov_reg_T0(ot, rm);
2156 } else {
2157 gen_op_mov_TN_reg(ot, 0, rm);
2158 if (reg != OR_TMP0)
2159 gen_op_mov_reg_T0(ot, reg);
2160 }
2161 } else {
2162 gen_lea_modrm(s, modrm, &opreg, &disp);
2163 if (is_store) {
2164 if (reg != OR_TMP0)
2165 gen_op_mov_TN_reg(ot, 0, reg);
2166 gen_op_st_T0_A0(ot + s->mem_index);
2167 } else {
2168 gen_op_ld_T0_A0(ot + s->mem_index);
2169 if (reg != OR_TMP0)
2170 gen_op_mov_reg_T0(ot, reg);
2171 }
2172 }
2173 }
2174
2175 static inline uint32_t insn_get(DisasContext *s, int ot)
2176 {
2177 uint32_t ret;
2178
2179 switch(ot) {
2180 case OT_BYTE:
2181 ret = ldub_code(s->pc);
2182 s->pc++;
2183 break;
2184 case OT_WORD:
2185 ret = lduw_code(s->pc);
2186 s->pc += 2;
2187 break;
2188 default:
2189 case OT_LONG:
2190 ret = ldl_code(s->pc);
2191 s->pc += 4;
2192 break;
2193 }
2194 return ret;
2195 }
2196
2197 static inline int insn_const_size(unsigned int ot)
2198 {
2199 if (ot <= OT_LONG)
2200 return 1 << ot;
2201 else
2202 return 4;
2203 }
2204
2205 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2206 {
2207 TranslationBlock *tb;
2208 target_ulong pc;
2209
2210 pc = s->cs_base + eip;
2211 tb = s->tb;
2212 /* NOTE: we handle the case where the TB spans two pages here */
2213 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2214 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2215 /* jump to same page: we can use a direct jump */
2216 tcg_gen_goto_tb(tb_num);
2217 gen_jmp_im(eip);
2218 tcg_gen_exit_tb((long)tb + tb_num);
2219 } else {
2220 /* jump to another page: currently not optimized */
2221 gen_jmp_im(eip);
2222 gen_eob(s);
2223 }
2224 }
2225
2226 static inline void gen_jcc(DisasContext *s, int b,
2227 target_ulong val, target_ulong next_eip)
2228 {
2229 int l1, l2, cc_op;
2230
2231 cc_op = s->cc_op;
2232 if (s->cc_op != CC_OP_DYNAMIC) {
2233 gen_op_set_cc_op(s->cc_op);
2234 s->cc_op = CC_OP_DYNAMIC;
2235 }
2236 if (s->jmp_opt) {
2237 l1 = gen_new_label();
2238 gen_jcc1(s, cc_op, b, l1);
2239
2240 gen_goto_tb(s, 0, next_eip);
2241
2242 gen_set_label(l1);
2243 gen_goto_tb(s, 1, val);
2244 s->is_jmp = 3;
2245 } else {
2246
2247 l1 = gen_new_label();
2248 l2 = gen_new_label();
2249 gen_jcc1(s, cc_op, b, l1);
2250
2251 gen_jmp_im(next_eip);
2252 tcg_gen_br(l2);
2253
2254 gen_set_label(l1);
2255 gen_jmp_im(val);
2256 gen_set_label(l2);
2257 gen_eob(s);
2258 }
2259 }
2260
2261 static void gen_setcc(DisasContext *s, int b)
2262 {
2263 int inv, jcc_op, l1;
2264 TCGv t0;
2265
2266 if (is_fast_jcc_case(s, b)) {
2267 /* nominal case: we use a jump */
2268 /* XXX: make it faster by adding new instructions in TCG */
2269 t0 = tcg_temp_local_new(TCG_TYPE_TL);
2270 tcg_gen_movi_tl(t0, 0);
2271 l1 = gen_new_label();
2272 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2273 tcg_gen_movi_tl(t0, 1);
2274 gen_set_label(l1);
2275 tcg_gen_mov_tl(cpu_T[0], t0);
2276 tcg_temp_free(t0);
2277 } else {
2278 /* slow case: it is more efficient not to generate a jump,
2279 although it is questionnable whether this optimization is
2280 worth to */
2281 inv = b & 1;
2282 jcc_op = (b >> 1) & 7;
2283 gen_setcc_slow_T0(s, jcc_op);
2284 if (inv) {
2285 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2286 }
2287 }
2288 }
2289
2290 static inline void gen_op_movl_T0_seg(int seg_reg)
2291 {
2292 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2293 offsetof(CPUX86State,segs[seg_reg].selector));
2294 }
2295
2296 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2297 {
2298 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2299 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2300 offsetof(CPUX86State,segs[seg_reg].selector));
2301 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2302 tcg_gen_st_tl(cpu_T[0], cpu_env,
2303 offsetof(CPUX86State,segs[seg_reg].base));
2304 }
2305
2306 /* move T0 to seg_reg and compute if the CPU state may change. Never
2307 call this function with seg_reg == R_CS */
2308 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2309 {
2310 if (s->pe && !s->vm86) {
2311 /* XXX: optimize by finding processor state dynamically */
2312 if (s->cc_op != CC_OP_DYNAMIC)
2313 gen_op_set_cc_op(s->cc_op);
2314 gen_jmp_im(cur_eip);
2315 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2316 tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2317 /* abort translation because the addseg value may change or
2318 because ss32 may change. For R_SS, translation must always
2319 stop as a special handling must be done to disable hardware
2320 interrupts for the next instruction */
2321 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2322 s->is_jmp = 3;
2323 } else {
2324 gen_op_movl_seg_T0_vm(seg_reg);
2325 if (seg_reg == R_SS)
2326 s->is_jmp = 3;
2327 }
2328 }
2329
2330 static inline int svm_is_rep(int prefixes)
2331 {
2332 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2333 }
2334
2335 static inline void
2336 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2337 uint32_t type, uint64_t param)
2338 {
2339 /* no SVM activated; fast case */
2340 if (likely(!(s->flags & HF_SVMI_MASK)))
2341 return;
2342 if (s->cc_op != CC_OP_DYNAMIC)
2343 gen_op_set_cc_op(s->cc_op);
2344 gen_jmp_im(pc_start - s->cs_base);
2345 tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2346 tcg_const_i32(type), tcg_const_i64(param));
2347 }
2348
2349 static inline void
2350 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2351 {
2352 gen_svm_check_intercept_param(s, pc_start, type, 0);
2353 }
2354
2355 static inline void gen_stack_update(DisasContext *s, int addend)
2356 {
2357 #ifdef TARGET_X86_64
2358 if (CODE64(s)) {
2359 gen_op_add_reg_im(2, R_ESP, addend);
2360 } else
2361 #endif
2362 if (s->ss32) {
2363 gen_op_add_reg_im(1, R_ESP, addend);
2364 } else {
2365 gen_op_add_reg_im(0, R_ESP, addend);
2366 }
2367 }
2368
2369 /* generate a push. It depends on ss32, addseg and dflag */
2370 static void gen_push_T0(DisasContext *s)
2371 {
2372 #ifdef TARGET_X86_64
2373 if (CODE64(s)) {
2374 gen_op_movq_A0_reg(R_ESP);
2375 if (s->dflag) {
2376 gen_op_addq_A0_im(-8);
2377 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2378 } else {
2379 gen_op_addq_A0_im(-2);
2380 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2381 }
2382 gen_op_mov_reg_A0(2, R_ESP);
2383 } else
2384 #endif
2385 {
2386 gen_op_movl_A0_reg(R_ESP);
2387 if (!s->dflag)
2388 gen_op_addl_A0_im(-2);
2389 else
2390 gen_op_addl_A0_im(-4);
2391 if (s->ss32) {
2392 if (s->addseg) {
2393 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2394 gen_op_addl_A0_seg(R_SS);
2395 }
2396 } else {
2397 gen_op_andl_A0_ffff();
2398 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2399 gen_op_addl_A0_seg(R_SS);
2400 }
2401 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2402 if (s->ss32 && !s->addseg)
2403 gen_op_mov_reg_A0(1, R_ESP);
2404 else
2405 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2406 }
2407 }
2408
2409 /* generate a push. It depends on ss32, addseg and dflag */
2410 /* slower version for T1, only used for call Ev */
2411 static void gen_push_T1(DisasContext *s)
2412 {
2413 #ifdef TARGET_X86_64
2414 if (CODE64(s)) {
2415 gen_op_movq_A0_reg(R_ESP);
2416 if (s->dflag) {
2417 gen_op_addq_A0_im(-8);
2418 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2419 } else {
2420 gen_op_addq_A0_im(-2);
2421 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2422 }
2423 gen_op_mov_reg_A0(2, R_ESP);
2424 } else
2425 #endif
2426 {
2427 gen_op_movl_A0_reg(R_ESP);
2428 if (!s->dflag)
2429 gen_op_addl_A0_im(-2);
2430 else
2431 gen_op_addl_A0_im(-4);
2432 if (s->ss32) {
2433 if (s->addseg) {
2434 gen_op_addl_A0_seg(R_SS);
2435 }
2436 } else {
2437 gen_op_andl_A0_ffff();
2438 gen_op_addl_A0_seg(R_SS);
2439 }
2440 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2441
2442 if (s->ss32 && !s->addseg)
2443 gen_op_mov_reg_A0(1, R_ESP);
2444 else
2445 gen_stack_update(s, (-2) << s->dflag);
2446 }
2447 }
2448
2449 /* two step pop is necessary for precise exceptions */
2450 static void gen_pop_T0(DisasContext *s)
2451 {
2452 #ifdef TARGET_X86_64
2453 if (CODE64(s)) {
2454 gen_op_movq_A0_reg(R_ESP);
2455 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2456 } else
2457 #endif
2458 {
2459 gen_op_movl_A0_reg(R_ESP);
2460 if (s->ss32) {
2461 if (s->addseg)
2462 gen_op_addl_A0_seg(R_SS);
2463 } else {
2464 gen_op_andl_A0_ffff();
2465 gen_op_addl_A0_seg(R_SS);
2466 }
2467 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2468 }
2469 }
2470
2471 static void gen_pop_update(DisasContext *s)
2472 {
2473 #ifdef TARGET_X86_64
2474 if (CODE64(s) && s->dflag) {
2475 gen_stack_update(s, 8);
2476 } else
2477 #endif
2478 {
2479 gen_stack_update(s, 2 << s->dflag);
2480 }
2481 }
2482
2483 static void gen_stack_A0(DisasContext *s)
2484 {
2485 gen_op_movl_A0_reg(R_ESP);
2486 if (!s->ss32)
2487 gen_op_andl_A0_ffff();
2488 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2489 if (s->addseg)
2490 gen_op_addl_A0_seg(R_SS);
2491 }
2492
2493 /* NOTE: wrap around in 16 bit not fully handled */
2494 static void gen_pusha(DisasContext *s)
2495 {
2496 int i;
2497 gen_op_movl_A0_reg(R_ESP);
2498 gen_op_addl_A0_im(-16 << s->dflag);
2499 if (!s->ss32)
2500 gen_op_andl_A0_ffff();
2501 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2502 if (s->addseg)
2503 gen_op_addl_A0_seg(R_SS);
2504 for(i = 0;i < 8; i++) {
2505 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2506 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2507 gen_op_addl_A0_im(2 << s->dflag);
2508 }
2509 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2510 }
2511
2512 /* NOTE: wrap around in 16 bit not fully handled */
2513 static void gen_popa(DisasContext *s)
2514 {
2515 int i;
2516 gen_op_movl_A0_reg(R_ESP);
2517 if (!s->ss32)
2518 gen_op_andl_A0_ffff();
2519 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2520 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2521 if (s->addseg)
2522 gen_op_addl_A0_seg(R_SS);
2523 for(i = 0;i < 8; i++) {
2524 /* ESP is not reloaded */
2525 if (i != 3) {
2526 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2527 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2528 }
2529 gen_op_addl_A0_im(2 << s->dflag);
2530 }
2531 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2532 }
2533
2534 static void gen_enter(DisasContext *s, int esp_addend, int level)
2535 {
2536 int ot, opsize;
2537
2538 level &= 0x1f;
2539 #ifdef TARGET_X86_64
2540 if (CODE64(s)) {
2541 ot = s->dflag ? OT_QUAD : OT_WORD;
2542 opsize = 1 << ot;
2543
2544 gen_op_movl_A0_reg(R_ESP);
2545 gen_op_addq_A0_im(-opsize);
2546 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2547
2548 /* push bp */
2549 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2550 gen_op_st_T0_A0(ot + s->mem_index);
2551 if (level) {
2552 /* XXX: must save state */
2553 tcg_gen_helper_0_3(helper_enter64_level,
2554 tcg_const_i32(level),
2555 tcg_const_i32((ot == OT_QUAD)),
2556 cpu_T[1]);
2557 }
2558 gen_op_mov_reg_T1(ot, R_EBP);
2559 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2560 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2561 } else
2562 #endif
2563 {
2564 ot = s->dflag + OT_WORD;
2565 opsize = 2 << s->dflag;
2566
2567 gen_op_movl_A0_reg(R_ESP);
2568 gen_op_addl_A0_im(-opsize);
2569 if (!s->ss32)
2570 gen_op_andl_A0_ffff();
2571 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2572 if (s->addseg)
2573 gen_op_addl_A0_seg(R_SS);
2574 /* push bp */
2575 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2576 gen_op_st_T0_A0(ot + s->mem_index);
2577 if (level) {
2578 /* XXX: must save state */
2579 tcg_gen_helper_0_3(helper_enter_level,
2580 tcg_const_i32(level),
2581 tcg_const_i32(s->dflag),
2582 cpu_T[1]);
2583 }
2584 gen_op_mov_reg_T1(ot, R_EBP);
2585 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2586 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2587 }
2588 }
2589
2590 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2591 {
2592 if (s->cc_op != CC_OP_DYNAMIC)
2593 gen_op_set_cc_op(s->cc_op);
2594 gen_jmp_im(cur_eip);
2595 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno));
2596 s->is_jmp = 3;
2597 }
2598
2599 /* an interrupt is different from an exception because of the
2600 privilege checks */
2601 static void gen_interrupt(DisasContext *s, int intno,
2602 target_ulong cur_eip, target_ulong next_eip)
2603 {
2604 if (s->cc_op != CC_OP_DYNAMIC)
2605 gen_op_set_cc_op(s->cc_op);
2606 gen_jmp_im(cur_eip);
2607 tcg_gen_helper_0_2(helper_raise_interrupt,
2608 tcg_const_i32(intno),
2609 tcg_const_i32(next_eip - cur_eip));
2610 s->is_jmp = 3;
2611 }
2612
2613 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2614 {
2615 if (s->cc_op != CC_OP_DYNAMIC)
2616 gen_op_set_cc_op(s->cc_op);
2617 gen_jmp_im(cur_eip);
2618 tcg_gen_helper_0_0(helper_debug);
2619 s->is_jmp = 3;
2620 }
2621
2622 /* generate a generic end of block. Trace exception is also generated
2623 if needed */
2624 static void gen_eob(DisasContext *s)
2625 {
2626 if (s->cc_op != CC_OP_DYNAMIC)
2627 gen_op_set_cc_op(s->cc_op);
2628 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2629 tcg_gen_helper_0_0(helper_reset_inhibit_irq);
2630 }
2631 if (s->singlestep_enabled) {
2632 tcg_gen_helper_0_0(helper_debug);
2633 } else if (s->tf) {
2634 tcg_gen_helper_0_0(helper_single_step);
2635 } else {
2636 tcg_gen_exit_tb(0);
2637 }
2638 s->is_jmp = 3;
2639 }
2640
2641 /* generate a jump to eip. No segment change must happen before as a
2642 direct call to the next block may occur */
2643 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2644 {
2645 if (s->jmp_opt) {
2646 if (s->cc_op != CC_OP_DYNAMIC) {
2647 gen_op_set_cc_op(s->cc_op);
2648 s->cc_op = CC_OP_DYNAMIC;
2649 }
2650 gen_goto_tb(s, tb_num, eip);
2651 s->is_jmp = 3;
2652 } else {
2653 gen_jmp_im(eip);
2654 gen_eob(s);
2655 }
2656 }
2657
2658 static void gen_jmp(DisasContext *s, target_ulong eip)
2659 {
2660 gen_jmp_tb(s, eip, 0);
2661 }
2662
2663 static inline void gen_ldq_env_A0(int idx, int offset)
2664 {
2665 int mem_index = (idx >> 2) - 1;
2666 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2667 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2668 }
2669
2670 static inline void gen_stq_env_A0(int idx, int offset)
2671 {
2672 int mem_index = (idx >> 2) - 1;
2673 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2674 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2675 }
2676
2677 static inline void gen_ldo_env_A0(int idx, int offset)
2678 {
2679 int mem_index = (idx >> 2) - 1;
2680 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2681 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2682 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2683 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2684 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2685 }
2686
2687 static inline void gen_sto_env_A0(int idx, int offset)
2688 {
2689 int mem_index = (idx >> 2) - 1;
2690 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2691 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2692 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2693 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2694 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2695 }
2696
2697 static inline void gen_op_movo(int d_offset, int s_offset)
2698 {
2699 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2700 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2701 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2702 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2703 }
2704
2705 static inline void gen_op_movq(int d_offset, int s_offset)
2706 {
2707 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2708 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2709 }
2710
2711 static inline void gen_op_movl(int d_offset, int s_offset)
2712 {
2713 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2714 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2715 }
2716
2717 static inline void gen_op_movq_env_0(int d_offset)
2718 {
2719 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2720 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2721 }
2722
2723 #define SSE_SPECIAL ((void *)1)
2724 #define SSE_DUMMY ((void *)2)
2725
2726 #define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm }
2727 #define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \
2728 helper_ ## x ## ss, helper_ ## x ## sd, }
2729
2730 static void *sse_op_table1[256][4] = {
2731 /* 3DNow! extensions */
2732 [0x0e] = { SSE_DUMMY }, /* femms */
2733 [0x0f] = { SSE_DUMMY }, /* pf... */
2734 /* pure SSE operations */
2735 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2736 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2737 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2738 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2739 [0x14] = { helper_punpckldq_xmm, helper_punpcklqdq_xmm },
2740 [0x15] = { helper_punpckhdq_xmm, helper_punpckhqdq_xmm },
2741 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2742 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2743
2744 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2745 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2746 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2747 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2748 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2749 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2750 [0x2e] = { helper_ucomiss, helper_ucomisd },
2751 [0x2f] = { helper_comiss, helper_comisd },
2752 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2753 [0x51] = SSE_FOP(sqrt),
2754 [0x52] = { helper_rsqrtps, NULL, helper_rsqrtss, NULL },
2755 [0x53] = { helper_rcpps, NULL, helper_rcpss, NULL },
2756 [0x54] = { helper_pand_xmm, helper_pand_xmm }, /* andps, andpd */
2757 [0x55] = { helper_pandn_xmm, helper_pandn_xmm }, /* andnps, andnpd */
2758 [0x56] = { helper_por_xmm, helper_por_xmm }, /* orps, orpd */
2759 [0x57] = { helper_pxor_xmm, helper_pxor_xmm }, /* xorps, xorpd */
2760 [0x58] = SSE_FOP(add),
2761 [0x59] = SSE_FOP(mul),
2762 [0x5a] = { helper_cvtps2pd, helper_cvtpd2ps,
2763 helper_cvtss2sd, helper_cvtsd2ss },
2764 [0x5b] = { helper_cvtdq2ps, helper_cvtps2dq, helper_cvttps2dq },
2765 [0x5c] = SSE_FOP(sub),
2766 [0x5d] = SSE_FOP(min),
2767 [0x5e] = SSE_FOP(div),
2768 [0x5f] = SSE_FOP(max),
2769
2770 [0xc2] = SSE_FOP(cmpeq),
2771 [0xc6] = { helper_shufps, helper_shufpd },
2772
2773 [0x38] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3 */
2774 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3 */
2775
2776 /* MMX ops and their SSE extensions */
2777 [0x60] = MMX_OP2(punpcklbw),
2778 [0x61] = MMX_OP2(punpcklwd),
2779 [0x62] = MMX_OP2(punpckldq),
2780 [0x63] = MMX_OP2(packsswb),
2781 [0x64] = MMX_OP2(pcmpgtb),
2782 [0x65] = MMX_OP2(pcmpgtw),
2783 [0x66] = MMX_OP2(pcmpgtl),
2784 [0x67] = MMX_OP2(packuswb),
2785 [0x68] = MMX_OP2(punpckhbw),
2786 [0x69] = MMX_OP2(punpckhwd),
2787 [0x6a] = MMX_OP2(punpckhdq),
2788 [0x6b] = MMX_OP2(packssdw),
2789 [0x6c] = { NULL, helper_punpcklqdq_xmm },
2790 [0x6d] = { NULL, helper_punpckhqdq_xmm },
2791 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2792 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2793 [0x70] = { helper_pshufw_mmx,
2794 helper_pshufd_xmm,
2795 helper_pshufhw_xmm,
2796 helper_pshuflw_xmm },
2797 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2798 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2799 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2800 [0x74] = MMX_OP2(pcmpeqb),
2801 [0x75] = MMX_OP2(pcmpeqw),
2802 [0x76] = MMX_OP2(pcmpeql),
2803 [0x77] = { SSE_DUMMY }, /* emms */
2804 [0x7c] = { NULL, helper_haddpd, NULL, helper_haddps },
2805 [0x7d] = { NULL, helper_hsubpd, NULL, helper_hsubps },
2806 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2807 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2808 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2809 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2810 [0xd0] = { NULL, helper_addsubpd, NULL, helper_addsubps },
2811 [0xd1] = MMX_OP2(psrlw),
2812 [0xd2] = MMX_OP2(psrld),
2813 [0xd3] = MMX_OP2(psrlq),
2814 [0xd4] = MMX_OP2(paddq),
2815 [0xd5] = MMX_OP2(pmullw),
2816 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2817 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2818 [0xd8] = MMX_OP2(psubusb),
2819 [0xd9] = MMX_OP2(psubusw),
2820 [0xda] = MMX_OP2(pminub),
2821 [0xdb] = MMX_OP2(pand),
2822 [0xdc] = MMX_OP2(paddusb),
2823 [0xdd] = MMX_OP2(paddusw),
2824 [0xde] = MMX_OP2(pmaxub),
2825 [0xdf] = MMX_OP2(pandn),
2826 [0xe0] = MMX_OP2(pavgb),
2827 [0xe1] = MMX_OP2(psraw),
2828 [0xe2] = MMX_OP2(psrad),
2829 [0xe3] = MMX_OP2(pavgw),
2830 [0xe4] = MMX_OP2(pmulhuw),
2831 [0xe5] = MMX_OP2(pmulhw),
2832 [0xe6] = { NULL, helper_cvttpd2dq, helper_cvtdq2pd, helper_cvtpd2dq },
2833 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2834 [0xe8] = MMX_OP2(psubsb),
2835 [0xe9] = MMX_OP2(psubsw),
2836 [0xea] = MMX_OP2(pminsw),
2837 [0xeb] = MMX_OP2(por),
2838 [0xec] = MMX_OP2(paddsb),
2839 [0xed] = MMX_OP2(paddsw),
2840 [0xee] = MMX_OP2(pmaxsw),
2841 [0xef] = MMX_OP2(pxor),
2842 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2843 [0xf1] = MMX_OP2(psllw),
2844 [0xf2] = MMX_OP2(pslld),
2845 [0xf3] = MMX_OP2(psllq),
2846 [0xf4] = MMX_OP2(pmuludq),
2847 [0xf5] = MMX_OP2(pmaddwd),
2848 [0xf6] = MMX_OP2(psadbw),
2849 [0xf7] = MMX_OP2(maskmov),
2850 [0xf8] = MMX_OP2(psubb),
2851 [0xf9] = MMX_OP2(psubw),
2852 [0xfa] = MMX_OP2(psubl),
2853 [0xfb] = MMX_OP2(psubq),
2854 [0xfc] = MMX_OP2(paddb),
2855 [0xfd] = MMX_OP2(paddw),
2856 [0xfe] = MMX_OP2(paddl),
2857 };
2858
2859 static void *sse_op_table2[3 * 8][2] = {
2860 [0 + 2] = MMX_OP2(psrlw),
2861 [0 + 4] = MMX_OP2(psraw),
2862 [0 + 6] = MMX_OP2(psllw),
2863 [8 + 2] = MMX_OP2(psrld),
2864 [8 + 4] = MMX_OP2(psrad),
2865 [8 + 6] = MMX_OP2(pslld),
2866 [16 + 2] = MMX_OP2(psrlq),
2867 [16 + 3] = { NULL, helper_psrldq_xmm },
2868 [16 + 6] = MMX_OP2(psllq),
2869 [16 + 7] = { NULL, helper_pslldq_xmm },
2870 };
2871
2872 static void *sse_op_table3[4 * 3] = {
2873 helper_cvtsi2ss,
2874 helper_cvtsi2sd,
2875 X86_64_ONLY(helper_cvtsq2ss),
2876 X86_64_ONLY(helper_cvtsq2sd),
2877
2878 helper_cvttss2si,
2879 helper_cvttsd2si,
2880 X86_64_ONLY(helper_cvttss2sq),
2881 X86_64_ONLY(helper_cvttsd2sq),
2882
2883 helper_cvtss2si,
2884 helper_cvtsd2si,
2885 X86_64_ONLY(helper_cvtss2sq),
2886 X86_64_ONLY(helper_cvtsd2sq),
2887 };
2888
2889 static void *sse_op_table4[8][4] = {
2890 SSE_FOP(cmpeq),
2891 SSE_FOP(cmplt),
2892 SSE_FOP(cmple),
2893 SSE_FOP(cmpunord),
2894 SSE_FOP(cmpneq),
2895 SSE_FOP(cmpnlt),
2896 SSE_FOP(cmpnle),
2897 SSE_FOP(cmpord),
2898 };
2899
2900 static void *sse_op_table5[256] = {
2901 [0x0c] = helper_pi2fw,
2902 [0x0d] = helper_pi2fd,
2903 [0x1c] = helper_pf2iw,
2904 [0x1d] = helper_pf2id,
2905 [0x8a] = helper_pfnacc,
2906 [0x8e] = helper_pfpnacc,
2907 [0x90] = helper_pfcmpge,
2908 [0x94] = helper_pfmin,
2909 [0x96] = helper_pfrcp,
2910 [0x97] = helper_pfrsqrt,
2911 [0x9a] = helper_pfsub,
2912 [0x9e] = helper_pfadd,
2913 [0xa0] = helper_pfcmpgt,
2914 [0xa4] = helper_pfmax,
2915 [0xa6] = helper_movq, /* pfrcpit1; no need to actually increase precision */
2916 [0xa7] = helper_movq, /* pfrsqit1 */
2917 [0xaa] = helper_pfsubr,
2918 [0xae] = helper_pfacc,
2919 [0xb0] = helper_pfcmpeq,
2920 [0xb4] = helper_pfmul,
2921 [0xb6] = helper_movq, /* pfrcpit2 */
2922 [0xb7] = helper_pmulhrw_mmx,
2923 [0xbb] = helper_pswapd,
2924 [0xbf] = helper_pavgb_mmx /* pavgusb */
2925 };
2926
2927 static void *sse_op_table6[256][2] = {
2928 [0x00] = MMX_OP2(pshufb),
2929 [0x01] = MMX_OP2(phaddw),
2930 [0x02] = MMX_OP2(phaddd),
2931 [0x03] = MMX_OP2(phaddsw),
2932 [0x04] = MMX_OP2(pmaddubsw),
2933 [0x05] = MMX_OP2(phsubw),
2934 [0x06] = MMX_OP2(phsubd),
2935 [0x07] = MMX_OP2(phsubsw),
2936 [0x08] = MMX_OP2(psignb),
2937 [0x09] = MMX_OP2(psignw),
2938 [0x0a] = MMX_OP2(psignd),
2939 [0x0b] = MMX_OP2(pmulhrsw),
2940 [0x1c] = MMX_OP2(pabsb),
2941 [0x1d] = MMX_OP2(pabsw),
2942 [0x1e] = MMX_OP2(pabsd),
2943 };
2944
2945 static void *sse_op_table7[256][2] = {
2946 [0x0f] = MMX_OP2(palignr),
2947 };
2948
2949 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2950 {
2951 int b1, op1_offset, op2_offset, is_xmm, val, ot;
2952 int modrm, mod, rm, reg, reg_addr, offset_addr;
2953 void *sse_op2;
2954
2955 b &= 0xff;
2956 if (s->prefix & PREFIX_DATA)
2957 b1 = 1;
2958 else if (s->prefix & PREFIX_REPZ)
2959 b1 = 2;
2960 else if (s->prefix & PREFIX_REPNZ)
2961 b1 = 3;
2962 else
2963 b1 = 0;
2964 sse_op2 = sse_op_table1[b][b1];
2965 if (!sse_op2)
2966 goto illegal_op;
2967 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
2968 is_xmm = 1;
2969 } else {
2970 if (b1 == 0) {
2971 /* MMX case */
2972 is_xmm = 0;
2973 } else {
2974 is_xmm = 1;
2975 }
2976 }
2977 /* simple MMX/SSE operation */
2978 if (s->flags & HF_TS_MASK) {
2979 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2980 return;
2981 }
2982 if (s->flags & HF_EM_MASK) {
2983 illegal_op:
2984 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2985 return;
2986 }
2987 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2988 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
2989 goto illegal_op;
2990 if (b == 0x0e) {
2991 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
2992 goto illegal_op;
2993 /* femms */
2994 tcg_gen_helper_0_0(helper_emms);
2995 return;
2996 }
2997 if (b == 0x77) {
2998 /* emms */
2999 tcg_gen_helper_0_0(helper_emms);
3000 return;
3001 }
3002 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3003 the static cpu state) */
3004 if (!is_xmm) {
3005 tcg_gen_helper_0_0(helper_enter_mmx);
3006 }
3007
3008 modrm = ldub_code(s->pc++);
3009 reg = ((modrm >> 3) & 7);
3010 if (is_xmm)
3011 reg |= rex_r;
3012 mod = (modrm >> 6) & 3;
3013 if (sse_op2 == SSE_SPECIAL) {
3014 b |= (b1 << 8);
3015 switch(b) {
3016 case 0x0e7: /* movntq */
3017 if (mod == 3)
3018 goto illegal_op;
3019 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3020 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3021 break;
3022 case 0x1e7: /* movntdq */
3023 case 0x02b: /* movntps */
3024 case 0x12b: /* movntps */
3025 case 0x3f0: /* lddqu */
3026 if (mod == 3)
3027 goto illegal_op;
3028 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3029 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3030 break;
3031 case 0x6e: /* movd mm, ea */
3032 #ifdef TARGET_X86_64
3033 if (s->dflag == 2) {
3034 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3035 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3036 } else
3037 #endif
3038 {
3039 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3040 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3041 offsetof(CPUX86State,fpregs[reg].mmx));
3042 tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]);
3043 }
3044 break;
3045 case 0x16e: /* movd xmm, ea */
3046 #ifdef TARGET_X86_64
3047 if (s->dflag == 2) {
3048 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3049 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3050 offsetof(CPUX86State,xmm_regs[reg]));
3051 tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]);
3052 } else
3053 #endif
3054 {
3055 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3056 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3057 offsetof(CPUX86State,xmm_regs[reg]));
3058 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3059 tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32);
3060 }
3061 break;
3062 case 0x6f: /* movq mm, ea */
3063 if (mod != 3) {
3064 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3065 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3066 } else {
3067 rm = (modrm & 7);
3068 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3069 offsetof(CPUX86State,fpregs[rm].mmx));
3070 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3071 offsetof(CPUX86State,fpregs[reg].mmx));
3072 }
3073 break;
3074 case 0x010: /* movups */
3075 case 0x110: /* movupd */
3076 case 0x028: /* movaps */
3077 case 0x128: /* movapd */
3078 case 0x16f: /* movdqa xmm, ea */
3079 case 0x26f: /* movdqu xmm, ea */
3080 if (mod != 3) {
3081 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3082 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3083 } else {
3084 rm = (modrm & 7) | REX_B(s);
3085 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3086 offsetof(CPUX86State,xmm_regs[rm]));
3087 }
3088 break;
3089 case 0x210: /* movss xmm, ea */
3090 if (mod != 3) {
3091 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3092 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3093 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3094 gen_op_movl_T0_0();
3095 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3096 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3097 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3098 } else {
3099 rm = (modrm & 7) | REX_B(s);
3100 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3101 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3102 }
3103 break;
3104 case 0x310: /* movsd xmm, ea */
3105 if (mod != 3) {
3106 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3107 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3108 gen_op_movl_T0_0();
3109 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3110 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3111 } else {
3112 rm = (modrm & 7) | REX_B(s);
3113 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3114 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3115 }
3116 break;
3117 case 0x012: /* movlps */
3118 case 0x112: /* movlpd */
3119 if (mod != 3) {
3120 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3121 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3122 } else {
3123 /* movhlps */
3124 rm = (modrm & 7) | REX_B(s);
3125 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3126 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3127 }
3128 break;
3129 case 0x212: /* movsldup */
3130 if (mod != 3) {
3131 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3132 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3133 } else {
3134 rm = (modrm & 7) | REX_B(s);
3135 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3136 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3137 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3138 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3139 }
3140 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3141 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3142 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3143 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3144 break;
3145 case 0x312: /* movddup */
3146 if (mod != 3) {
3147 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3148 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3149 } else {
3150 rm = (modrm & 7) | REX_B(s);
3151 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3152 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3153 }
3154 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3155 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3156 break;
3157 case 0x016: /* movhps */
3158 case 0x116: /* movhpd */
3159 if (mod != 3) {
3160 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3161 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3162 } else {
3163 /* movlhps */
3164 rm = (modrm & 7) | REX_B(s);
3165 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3166 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3167 }
3168 break;
3169 case 0x216: /* movshdup */
3170 if (mod != 3) {
3171 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3172 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3173 } else {
3174 rm = (modrm & 7) | REX_B(s);
3175 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3176 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3177 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3178 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3179 }
3180 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3181 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3182 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3183 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3184 break;
3185 case 0x7e: /* movd ea, mm */
3186 #ifdef TARGET_X86_64
3187 if (s->dflag == 2) {
3188 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3189 offsetof(CPUX86State,fpregs[reg].mmx));
3190 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3191 } else
3192 #endif
3193 {
3194 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3195 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3196 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3197 }
3198 break;
3199 case 0x17e: /* movd ea, xmm */
3200 #ifdef TARGET_X86_64
3201 if (s->dflag == 2) {
3202 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3203 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3204 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3205 } else
3206 #endif
3207 {
3208 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3209 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3210 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3211 }
3212 break;
3213 case 0x27e: /* movq xmm, ea */
3214 if (mod != 3) {
3215 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3216 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3217 } else {
3218 rm = (modrm & 7) | REX_B(s);
3219 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3220 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3221 }
3222 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3223 break;
3224 case 0x7f: /* movq ea, mm */
3225 if (mod != 3) {
3226 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3227 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3228 } else {
3229 rm = (modrm & 7);
3230 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3231 offsetof(CPUX86State,fpregs[reg].mmx));
3232 }
3233 break;
3234 case 0x011: /* movups */
3235 case 0x111: /* movupd */
3236 case 0x029: /* movaps */
3237 case 0x129: /* movapd */
3238 case 0x17f: /* movdqa ea, xmm */
3239 case 0x27f: /* movdqu ea, xmm */
3240 if (mod != 3) {
3241 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3242 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3243 } else {
3244 rm = (modrm & 7) | REX_B(s);
3245 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3246 offsetof(CPUX86State,xmm_regs[reg]));
3247 }
3248 break;
3249 case 0x211: /* movss ea, xmm */
3250 if (mod != 3) {
3251 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3252 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3253 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3254 } else {
3255 rm = (modrm & 7) | REX_B(s);
3256 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3257 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3258 }
3259 break;
3260 case 0x311: /* movsd ea, xmm */
3261 if (mod != 3) {
3262 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3263 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3264 } else {
3265 rm = (modrm & 7) | REX_B(s);
3266 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3267 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3268 }
3269 break;
3270 case 0x013: /* movlps */
3271 case 0x113: /* movlpd */
3272 if (mod != 3) {
3273 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3274 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3275 } else {
3276 goto illegal_op;
3277 }
3278 break;
3279 case 0x017: /* movhps */
3280 case 0x117: /* movhpd */
3281 if (mod != 3) {
3282 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3283 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3284 } else {
3285 goto illegal_op;
3286 }
3287 break;
3288 case 0x71: /* shift mm, im */
3289 case 0x72:
3290 case 0x73:
3291 case 0x171: /* shift xmm, im */
3292 case 0x172:
3293 case 0x173:
3294 val = ldub_code(s->pc++);
3295 if (is_xmm) {
3296 gen_op_movl_T0_im(val);
3297 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3298 gen_op_movl_T0_0();
3299 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3300 op1_offset = offsetof(CPUX86State,xmm_t0);
3301 } else {
3302 gen_op_movl_T0_im(val);
3303 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3304 gen_op_movl_T0_0();
3305 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3306 op1_offset = offsetof(CPUX86State,mmx_t0);
3307 }
3308 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3309 if (!sse_op2)
3310 goto illegal_op;
3311 if (is_xmm) {
3312 rm = (modrm & 7) | REX_B(s);
3313 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3314 } else {
3315 rm = (modrm & 7);
3316 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3317 }
3318 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3319 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3320 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3321 break;
3322 case 0x050: /* movmskps */
3323 rm = (modrm & 7) | REX_B(s);
3324 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3325 offsetof(CPUX86State,xmm_regs[rm]));
3326 tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0);
3327 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3328 gen_op_mov_reg_T0(OT_LONG, reg);
3329 break;
3330 case 0x150: /* movmskpd */
3331 rm = (modrm & 7) | REX_B(s);
3332 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3333 offsetof(CPUX86State,xmm_regs[rm]));
3334 tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0);
3335 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3336 gen_op_mov_reg_T0(OT_LONG, reg);
3337 break;
3338 case 0x02a: /* cvtpi2ps */
3339 case 0x12a: /* cvtpi2pd */
3340 tcg_gen_helper_0_0(helper_enter_mmx);
3341 if (mod != 3) {
3342 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3343 op2_offset = offsetof(CPUX86State,mmx_t0);
3344 gen_ldq_env_A0(s->mem_index, op2_offset);
3345 } else {
3346 rm = (modrm & 7);
3347 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3348 }
3349 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3350 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3351 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3352 switch(b >> 8) {
3353 case 0x0:
3354 tcg_gen_helper_0_2(helper_cvtpi2ps, cpu_ptr0, cpu_ptr1);
3355 break;
3356 default:
3357 case 0x1:
3358 tcg_gen_helper_0_2(helper_cvtpi2pd, cpu_ptr0, cpu_ptr1);
3359 break;
3360 }
3361 break;
3362 case 0x22a: /* cvtsi2ss */
3363 case 0x32a: /* cvtsi2sd */
3364 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3365 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3366 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3367 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3368 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3369 if (ot == OT_LONG) {
3370 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3371 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32);
3372 } else {
3373 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_T[0]);
3374 }
3375 break;
3376 case 0x02c: /* cvttps2pi */
3377 case 0x12c: /* cvttpd2pi */
3378 case 0x02d: /* cvtps2pi */
3379 case 0x12d: /* cvtpd2pi */
3380 tcg_gen_helper_0_0(helper_enter_mmx);
3381 if (mod != 3) {
3382 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3383 op2_offset = offsetof(CPUX86State,xmm_t0);
3384 gen_ldo_env_A0(s->mem_index, op2_offset);
3385 } else {
3386 rm = (modrm & 7) | REX_B(s);
3387 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3388 }
3389 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3390 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3391 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3392 switch(b) {
3393 case 0x02c:
3394 tcg_gen_helper_0_2(helper_cvttps2pi, cpu_ptr0, cpu_ptr1);
3395 break;
3396 case 0x12c:
3397 tcg_gen_helper_0_2(helper_cvttpd2pi, cpu_ptr0, cpu_ptr1);
3398 break;
3399 case 0x02d:
3400 tcg_gen_helper_0_2(helper_cvtps2pi, cpu_ptr0, cpu_ptr1);
3401 break;
3402 case 0x12d:
3403 tcg_gen_helper_0_2(helper_cvtpd2pi, cpu_ptr0, cpu_ptr1);
3404 break;
3405 }
3406 break;
3407 case 0x22c: /* cvttss2si */
3408 case 0x32c: /* cvttsd2si */
3409 case 0x22d: /* cvtss2si */
3410 case 0x32d: /* cvtsd2si */
3411 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3412 if (mod != 3) {
3413 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3414 if ((b >> 8) & 1) {
3415 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3416 } else {
3417 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3418 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3419 }
3420 op2_offset = offsetof(CPUX86State,xmm_t0);
3421 } else {
3422 rm = (modrm & 7) | REX_B(s);
3423 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3424 }
3425 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3426 (b & 1) * 4];
3427 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3428 if (ot == OT_LONG) {
3429 tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0);
3430 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3431 } else {
3432 tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0);
3433 }
3434 gen_op_mov_reg_T0(ot, reg);
3435 break;
3436 case 0xc4: /* pinsrw */
3437 case 0x1c4:
3438 s->rip_offset = 1;
3439 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3440 val = ldub_code(s->pc++);
3441 if (b1) {
3442 val &= 7;
3443 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3444 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3445 } else {
3446 val &= 3;
3447 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3448 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3449 }
3450 break;
3451 case 0xc5: /* pextrw */
3452 case 0x1c5:
3453 if (mod != 3)
3454 goto illegal_op;
3455 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3456 val = ldub_code(s->pc++);
3457 if (b1) {
3458 val &= 7;
3459 rm = (modrm & 7) | REX_B(s);
3460 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3461 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3462 } else {
3463 val &= 3;
3464 rm = (modrm & 7);
3465 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3466 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3467 }
3468 reg = ((modrm >> 3) & 7) | rex_r;
3469 gen_op_mov_reg_T0(ot, reg);
3470 break;
3471 case 0x1d6: /* movq ea, xmm */
3472 if (mod != 3) {
3473 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3474 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3475 } else {
3476 rm = (modrm & 7) | REX_B(s);
3477 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3478 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3479 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3480 }
3481 break;
3482 case 0x2d6: /* movq2dq */
3483 tcg_gen_helper_0_0(helper_enter_mmx);
3484 rm = (modrm & 7);
3485 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3486 offsetof(CPUX86State,fpregs[rm].mmx));
3487 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3488 break;
3489 case 0x3d6: /* movdq2q */
3490 tcg_gen_helper_0_0(helper_enter_mmx);
3491 rm = (modrm & 7) | REX_B(s);
3492 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3493 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3494 break;
3495 case 0xd7: /* pmovmskb */
3496 case 0x1d7:
3497 if (mod != 3)
3498 goto illegal_op;
3499 if (b1) {
3500 rm = (modrm & 7) | REX_B(s);
3501 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3502 tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0);
3503 } else {
3504 rm = (modrm & 7);
3505 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3506 tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0);
3507 }
3508 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3509 reg = ((modrm >> 3) & 7) | rex_r;
3510 gen_op_mov_reg_T0(OT_LONG, reg);
3511 break;
3512 case 0x038:
3513 case 0x138:
3514 if (!(s->cpuid_ext_features & CPUID_EXT_SSSE3))
3515 goto illegal_op;
3516
3517 b = modrm;
3518 modrm = ldub_code(s->pc++);
3519 rm = modrm & 7;
3520 reg = ((modrm >> 3) & 7) | rex_r;
3521 mod = (modrm >> 6) & 3;
3522
3523 sse_op2 = sse_op_table6[b][b1];
3524 if (!sse_op2)
3525 goto illegal_op;
3526
3527 if (b1) {
3528 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3529 if (mod == 3) {
3530 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3531 } else {
3532 op2_offset = offsetof(CPUX86State,xmm_t0);
3533 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3534 gen_ldo_env_A0(s->mem_index, op2_offset);
3535 }
3536 } else {
3537 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3538 if (mod == 3) {
3539 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3540 } else {
3541 op2_offset = offsetof(CPUX86State,mmx_t0);
3542 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3543 gen_ldq_env_A0(s->mem_index, op2_offset);
3544 }
3545 }
3546 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3547 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3548 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3549 break;
3550 case 0x03a:
3551 case 0x13a:
3552 if (!(s->cpuid_ext_features & CPUID_EXT_SSSE3))
3553 goto illegal_op;
3554
3555 b = modrm;
3556 modrm = ldub_code(s->pc++);
3557 rm = modrm & 7;
3558 reg = ((modrm >> 3) & 7) | rex_r;
3559 mod = (modrm >> 6) & 3;
3560
3561 sse_op2 = sse_op_table7[b][b1];
3562 if (!sse_op2)
3563 goto illegal_op;
3564
3565 if (b1) {
3566 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3567 if (mod == 3) {
3568 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3569 } else {
3570 op2_offset = offsetof(CPUX86State,xmm_t0);
3571 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3572 gen_ldo_env_A0(s->mem_index, op2_offset);
3573 }
3574 } else {
3575 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3576 if (mod == 3) {
3577 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3578 } else {
3579 op2_offset = offsetof(CPUX86State,mmx_t0);
3580 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3581 gen_ldq_env_A0(s->mem_index, op2_offset);
3582 }
3583 }
3584 val = ldub_code(s->pc++);
3585
3586 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3587 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3588 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3589 break;
3590 default:
3591 goto illegal_op;
3592 }
3593 } else {
3594 /* generic MMX or SSE operation */
3595 switch(b) {
3596 case 0x70: /* pshufx insn */
3597 case 0xc6: /* pshufx insn */
3598 case 0xc2: /* compare insns */
3599 s->rip_offset = 1;
3600 break;
3601 default:
3602 break;
3603 }
3604 if (is_xmm) {
3605 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3606 if (mod != 3) {
3607 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3608 op2_offset = offsetof(CPUX86State,xmm_t0);
3609 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3610 b == 0xc2)) {
3611 /* specific case for SSE single instructions */
3612 if (b1 == 2) {
3613 /* 32 bit access */
3614 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3615 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3616 } else {
3617 /* 64 bit access */
3618 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3619 }
3620 } else {
3621 gen_ldo_env_A0(s->mem_index, op2_offset);
3622 }
3623 } else {
3624 rm = (modrm & 7) | REX_B(s);
3625 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3626 }
3627 } else {
3628 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3629 if (mod != 3) {
3630 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3631 op2_offset = offsetof(CPUX86State,mmx_t0);
3632 gen_ldq_env_A0(s->mem_index, op2_offset);
3633 } else {
3634 rm = (modrm & 7);
3635 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3636 }
3637 }
3638 switch(b) {
3639 case 0x0f: /* 3DNow! data insns */
3640 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3641 goto illegal_op;
3642 val = ldub_code(s->pc++);
3643 sse_op2 = sse_op_table5[val];
3644 if (!sse_op2)
3645 goto illegal_op;
3646 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3647 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3648 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3649 break;
3650 case 0x70: /* pshufx insn */
3651 case 0xc6: /* pshufx insn */
3652 val = ldub_code(s->pc++);
3653 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3654 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3655 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3656 break;
3657 case 0xc2:
3658 /* compare insns */
3659 val = ldub_code(s->pc++);
3660 if (val >= 8)
3661 goto illegal_op;
3662 sse_op2 = sse_op_table4[val][b1];
3663 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3664 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3665 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3666 break;
3667 case 0xf7:
3668 /* maskmov : we must prepare A0 */
3669 if (mod != 3)
3670 goto illegal_op;
3671 #ifdef TARGET_X86_64
3672 if (s->aflag == 2) {
3673 gen_op_movq_A0_reg(R_EDI);
3674 } else
3675 #endif
3676 {
3677 gen_op_movl_A0_reg(R_EDI);
3678 if (s->aflag == 0)
3679 gen_op_andl_A0_ffff();
3680 }
3681 gen_add_A0_ds_seg(s);
3682
3683 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3684 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3685 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, cpu_A0);
3686 break;
3687 default:
3688 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3689 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3690 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3691 break;
3692 }
3693 if (b == 0x2e || b == 0x2f) {
3694 s->cc_op = CC_OP_EFLAGS;
3695 }
3696 }
3697 }
3698
3699 /* convert one instruction. s->is_jmp is set if the translation must
3700 be stopped. Return the next pc value */
3701 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3702 {
3703 int b, prefixes, aflag, dflag;
3704 int shift, ot;
3705 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
3706 target_ulong next_eip, tval;
3707 int rex_w, rex_r;
3708
3709 if (unlikely(loglevel & CPU_LOG_TB_OP))
3710 tcg_gen_debug_insn_start(pc_start);
3711 s->pc = pc_start;
3712 prefixes = 0;
3713 aflag = s->code32;
3714 dflag = s->code32;
3715 s->override = -1;
3716 rex_w = -1;
3717 rex_r = 0;
3718 #ifdef TARGET_X86_64
3719 s->rex_x = 0;
3720 s->rex_b = 0;
3721 x86_64_hregs = 0;
3722 #endif
3723 s->rip_offset = 0; /* for relative ip address */
3724 next_byte:
3725 b = ldub_code(s->pc);
3726 s->pc++;
3727 /* check prefixes */
3728 #ifdef TARGET_X86_64
3729 if (CODE64(s)) {
3730 switch (b) {
3731 case 0xf3:
3732 prefixes |= PREFIX_REPZ;
3733 goto next_byte;
3734 case 0xf2:
3735 prefixes |= PREFIX_REPNZ;
3736 goto next_byte;
3737 case 0xf0:
3738 prefixes |= PREFIX_LOCK;
3739 goto next_byte;
3740 case 0x2e:
3741 s->override = R_CS;
3742 goto next_byte;
3743 case 0x36:
3744 s->override = R_SS;
3745 goto next_byte;
3746 case 0x3e:
3747 s->override = R_DS;
3748 goto next_byte;
3749 case 0x26:
3750 s->override = R_ES;
3751 goto next_byte;
3752 case 0x64:
3753 s->override = R_FS;
3754 goto next_byte;
3755 case 0x65:
3756 s->override = R_GS;
3757 goto next_byte;
3758 case 0x66:
3759 prefixes |= PREFIX_DATA;
3760 goto next_byte;
3761 case 0x67:
3762 prefixes |= PREFIX_ADR;
3763 goto next_byte;
3764 case 0x40 ... 0x4f:
3765 /* REX prefix */
3766 rex_w = (b >> 3) & 1;
3767 rex_r = (b & 0x4) << 1;
3768 s->rex_x = (b & 0x2) << 2;
3769 REX_B(s) = (b & 0x1) << 3;
3770 x86_64_hregs = 1; /* select uniform byte register addressing */
3771 goto next_byte;
3772 }
3773 if (rex_w == 1) {
3774 /* 0x66 is ignored if rex.w is set */
3775 dflag = 2;
3776 } else {
3777 if (prefixes & PREFIX_DATA)
3778 dflag ^= 1;
3779 }
3780 if (!(prefixes & PREFIX_ADR))
3781 aflag = 2;
3782 } else
3783 #endif
3784 {
3785 switch (b) {
3786 case 0xf3:
3787 prefixes |= PREFIX_REPZ;
3788 goto next_byte;
3789 case 0xf2:
3790 prefixes |= PREFIX_REPNZ;
3791 goto next_byte;
3792 case 0xf0:
3793 prefixes |= PREFIX_LOCK;
3794 goto next_byte;
3795 case 0x2e:
3796 s->override = R_CS;
3797 goto next_byte;
3798 case 0x36:
3799 s->override = R_SS;
3800 goto next_byte;
3801 case 0x3e:
3802 s->override = R_DS;
3803 goto next_byte;
3804 case 0x26:
3805 s->override = R_ES;
3806 goto next_byte;
3807 case 0x64:
3808 s->override = R_FS;
3809 goto next_byte;
3810 case 0x65:
3811 s->override = R_GS;
3812 goto next_byte;
3813 case 0x66:
3814 prefixes |= PREFIX_DATA;
3815 goto next_byte;
3816 case 0x67:
3817 prefixes |= PREFIX_ADR;
3818 goto next_byte;
3819 }
3820 if (prefixes & PREFIX_DATA)
3821 dflag ^= 1;
3822 if (prefixes & PREFIX_ADR)
3823 aflag ^= 1;
3824 }
3825
3826 s->prefix = prefixes;
3827 s->aflag = aflag;
3828 s->dflag = dflag;
3829
3830 /* lock generation */
3831 if (prefixes & PREFIX_LOCK)
3832 tcg_gen_helper_0_0(helper_lock);
3833
3834 /* now check op code */
3835 reswitch:
3836 switch(b) {
3837 case 0x0f:
3838 /**************************/
3839 /* extended op code */
3840 b = ldub_code(s->pc++) | 0x100;
3841 goto reswitch;
3842
3843 /**************************/
3844 /* arith & logic */
3845 case 0x00 ... 0x05:
3846 case 0x08 ... 0x0d:
3847 case 0x10 ... 0x15:
3848 case 0x18 ... 0x1d:
3849 case 0x20 ... 0x25:
3850 case 0x28 ... 0x2d:
3851 case 0x30 ... 0x35:
3852 case 0x38 ... 0x3d:
3853 {
3854 int op, f, val;
3855 op = (b >> 3) & 7;
3856 f = (b >> 1) & 3;
3857
3858 if ((b & 1) == 0)
3859 ot = OT_BYTE;
3860 else
3861 ot = dflag + OT_WORD;
3862
3863 switch(f) {
3864 case 0: /* OP Ev, Gv */
3865 modrm = ldub_code(s->pc++);
3866 reg = ((modrm >> 3) & 7) | rex_r;
3867 mod = (modrm >> 6) & 3;
3868 rm = (modrm & 7) | REX_B(s);
3869 if (mod != 3) {
3870 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3871 opreg = OR_TMP0;
3872 } else if (op == OP_XORL && rm == reg) {
3873 xor_zero:
3874 /* xor reg, reg optimisation */
3875 gen_op_movl_T0_0();
3876 s->cc_op = CC_OP_LOGICB + ot;
3877 gen_op_mov_reg_T0(ot, reg);
3878 gen_op_update1_cc();
3879 break;
3880 } else {
3881 opreg = rm;
3882 }
3883 gen_op_mov_TN_reg(ot, 1, reg);
3884 gen_op(s, op, ot, opreg);
3885 break;
3886 case 1: /* OP Gv, Ev */
3887 modrm = ldub_code(s->pc++);
3888 mod = (modrm >> 6) & 3;
3889 reg = ((modrm >> 3) & 7) | rex_r;
3890 rm = (modrm & 7) | REX_B(s);
3891 if (mod != 3) {
3892 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3893 gen_op_ld_T1_A0(ot + s->mem_index);
3894 } else if (op == OP_XORL && rm == reg) {
3895 goto xor_zero;
3896 } else {
3897 gen_op_mov_TN_reg(ot, 1, rm);
3898 }
3899 gen_op(s, op, ot, reg);
3900 break;
3901 case 2: /* OP A, Iv */
3902 val = insn_get(s, ot);
3903 gen_op_movl_T1_im(val);
3904 gen_op(s, op, ot, OR_EAX);
3905 break;
3906 }
3907 }
3908 break;
3909
3910 case 0x82:
3911 if (CODE64(s))
3912 goto illegal_op;
3913 case 0x80: /* GRP1 */
3914 case 0x81:
3915 case 0x83:
3916 {
3917 int val;
3918
3919 if ((b & 1) == 0)
3920 ot = OT_BYTE;
3921 else
3922 ot = dflag + OT_WORD;
3923
3924 modrm = ldub_code(s->pc++);
3925 mod = (modrm >> 6) & 3;
3926 rm = (modrm & 7) | REX_B(s);
3927 op = (modrm >> 3) & 7;
3928
3929 if (mod != 3) {
3930 if (b == 0x83)
3931 s->rip_offset = 1;
3932 else
3933 s->rip_offset = insn_const_size(ot);
3934 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3935 opreg = OR_TMP0;
3936 } else {
3937 opreg = rm;
3938 }
3939
3940 switch(b) {
3941 default:
3942 case 0x80:
3943 case 0x81:
3944 case 0x82:
3945 val = insn_get(s, ot);
3946 break;
3947 case 0x83:
3948 val = (int8_t)insn_get(s, OT_BYTE);
3949 break;
3950 }
3951 gen_op_movl_T1_im(val);
3952 gen_op(s, op, ot, opreg);
3953 }
3954 break;
3955
3956 /**************************/
3957 /* inc, dec, and other misc arith */
3958 case 0x40 ... 0x47: /* inc Gv */
3959 ot = dflag ? OT_LONG : OT_WORD;
3960 gen_inc(s, ot, OR_EAX + (b & 7), 1);
3961 break;
3962 case 0x48 ... 0x4f: /* dec Gv */
3963 ot = dflag ? OT_LONG : OT_WORD;
3964 gen_inc(s, ot, OR_EAX + (b & 7), -1);
3965 break;
3966 case 0xf6: /* GRP3 */
3967 case 0xf7:
3968 if ((b & 1) == 0)
3969 ot = OT_BYTE;
3970 else
3971 ot = dflag + OT_WORD;
3972
3973 modrm = ldub_code(s->pc++);
3974 mod = (modrm >> 6) & 3;
3975 rm = (modrm & 7) | REX_B(s);
3976 op = (modrm >> 3) & 7;
3977 if (mod != 3) {
3978 if (op == 0)
3979 s->rip_offset = insn_const_size(ot);
3980 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3981 gen_op_ld_T0_A0(ot + s->mem_index);
3982 } else {
3983 gen_op_mov_TN_reg(ot, 0, rm);
3984 }
3985
3986 switch(op) {
3987 case 0: /* test */
3988 val = insn_get(s, ot);
3989 gen_op_movl_T1_im(val);
3990 gen_op_testl_T0_T1_cc();
3991 s->cc_op = CC_OP_LOGICB + ot;
3992 break;
3993 case 2: /* not */
3994 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
3995 if (mod != 3) {
3996 gen_op_st_T0_A0(ot + s->mem_index);
3997 } else {
3998 gen_op_mov_reg_T0(ot, rm);
3999 }
4000 break;
4001 case 3: /* neg */
4002 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4003 if (mod != 3) {
4004 gen_op_st_T0_A0(ot + s->mem_index);
4005 } else {
4006 gen_op_mov_reg_T0(ot, rm);
4007 }
4008 gen_op_update_neg_cc();
4009 s->cc_op = CC_OP_SUBB + ot;
4010 break;
4011 case 4: /* mul */
4012 switch(ot) {
4013 case OT_BYTE:
4014 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4015 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4016 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4017 /* XXX: use 32 bit mul which could be faster */
4018 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4019 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4020 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4021 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4022 s->cc_op = CC_OP_MULB;
4023 break;
4024 case OT_WORD:
4025 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4026 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4027 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4028 /* XXX: use 32 bit mul which could be faster */
4029 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4030 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4031 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4032 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4033 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4034 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4035 s->cc_op = CC_OP_MULW;
4036 break;
4037 default:
4038 case OT_LONG:
4039 #ifdef TARGET_X86_64
4040 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4041 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4042 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4043 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4044 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4045 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4046 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4047 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4048 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4049 #else
4050 {
4051 TCGv t0, t1;
4052 t0 = tcg_temp_new(TCG_TYPE_I64);
4053 t1 = tcg_temp_new(TCG_TYPE_I64);
4054 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4055 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4056 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4057 tcg_gen_mul_i64(t0, t0, t1);
4058 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4059 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4060 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4061 tcg_gen_shri_i64(t0, t0, 32);
4062 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4063 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4064 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4065 }
4066 #endif
4067 s->cc_op = CC_OP_MULL;
4068 break;
4069 #ifdef TARGET_X86_64
4070 case OT_QUAD:
4071 tcg_gen_helper_0_1(helper_mulq_EAX_T0, cpu_T[0]);
4072 s->cc_op = CC_OP_MULQ;
4073 break;
4074 #endif
4075 }
4076 break;
4077 case 5: /* imul */
4078 switch(ot) {
4079 case OT_BYTE:
4080 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4081 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4082 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4083 /* XXX: use 32 bit mul which could be faster */
4084 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4085 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4086 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4087 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4088 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4089 s->cc_op = CC_OP_MULB;
4090 break;
4091 case OT_WORD:
4092 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4093 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4094 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4095 /* XXX: use 32 bit mul which could be faster */
4096 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4097 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4098 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4099 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4100 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4101 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4102 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4103 s->cc_op = CC_OP_MULW;
4104 break;
4105 default:
4106 case OT_LONG:
4107 #ifdef TARGET_X86_64
4108 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4109 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4110 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4111 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4112 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4113 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4114 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4115 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4116 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4117 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4118 #else
4119 {
4120 TCGv t0, t1;
4121 t0 = tcg_temp_new(TCG_TYPE_I64);
4122 t1 = tcg_temp_new(TCG_TYPE_I64);
4123 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4124 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4125 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4126 tcg_gen_mul_i64(t0, t0, t1);
4127 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4128 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4129 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4130 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4131 tcg_gen_shri_i64(t0, t0, 32);
4132 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4133 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4134 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4135 }
4136 #endif
4137 s->cc_op = CC_OP_MULL;
4138 break;
4139 #ifdef TARGET_X86_64
4140 case OT_QUAD:
4141 tcg_gen_helper_0_1(helper_imulq_EAX_T0, cpu_T[0]);
4142 s->cc_op = CC_OP_MULQ;
4143 break;
4144 #endif
4145 }
4146 break;
4147 case 6: /* div */
4148 switch(ot) {
4149 case OT_BYTE:
4150 gen_jmp_im(pc_start - s->cs_base);
4151 tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]);
4152 break;
4153 case OT_WORD:
4154 gen_jmp_im(pc_start - s->cs_base);
4155 tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]);
4156 break;
4157 default:
4158 case OT_LONG:
4159 gen_jmp_im(pc_start - s->cs_base);
4160 tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]);
4161 break;
4162 #ifdef TARGET_X86_64
4163 case OT_QUAD:
4164 gen_jmp_im(pc_start - s->cs_base);
4165 tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]);
4166 break;
4167 #endif
4168 }
4169 break;
4170 case 7: /* idiv */
4171 switch(ot) {
4172 case OT_BYTE:
4173 gen_jmp_im(pc_start - s->cs_base);
4174 tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]);
4175 break;
4176 case OT_WORD:
4177 gen_jmp_im(pc_start - s->cs_base);
4178 tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]);
4179 break;
4180 default:
4181 case OT_LONG:
4182 gen_jmp_im(pc_start - s->cs_base);
4183 tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]);
4184 break;
4185 #ifdef TARGET_X86_64
4186 case OT_QUAD:
4187 gen_jmp_im(pc_start - s->cs_base);
4188 tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]);
4189 break;
4190 #endif
4191 }
4192 break;
4193 default:
4194 goto illegal_op;
4195 }
4196 break;
4197
4198 case 0xfe: /* GRP4 */
4199 case 0xff: /* GRP5 */
4200 if ((b & 1) == 0)
4201 ot = OT_BYTE;
4202 else
4203 ot = dflag + OT_WORD;
4204
4205 modrm = ldub_code(s->pc++);
4206 mod = (modrm >> 6) & 3;
4207 rm = (modrm & 7) | REX_B(s);
4208 op = (modrm >> 3) & 7;
4209 if (op >= 2 && b == 0xfe) {
4210 goto illegal_op;
4211 }
4212 if (CODE64(s)) {
4213 if (op == 2 || op == 4) {
4214 /* operand size for jumps is 64 bit */
4215 ot = OT_QUAD;
4216 } else if (op == 3 || op == 5) {
4217 /* for call calls, the operand is 16 or 32 bit, even
4218 in long mode */
4219 ot = dflag ? OT_LONG : OT_WORD;
4220 } else if (op == 6) {
4221 /* default push size is 64 bit */
4222 ot = dflag ? OT_QUAD : OT_WORD;
4223 }
4224 }
4225 if (mod != 3) {
4226 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4227 if (op >= 2 && op != 3 && op != 5)
4228 gen_op_ld_T0_A0(ot + s->mem_index);
4229 } else {
4230 gen_op_mov_TN_reg(ot, 0, rm);
4231 }
4232
4233 switch(op) {
4234 case 0: /* inc Ev */
4235 if (mod != 3)
4236 opreg = OR_TMP0;
4237 else
4238 opreg = rm;
4239 gen_inc(s, ot, opreg, 1);
4240 break;
4241 case 1: /* dec Ev */
4242 if (mod != 3)
4243 opreg = OR_TMP0;
4244 else
4245 opreg = rm;
4246 gen_inc(s, ot, opreg, -1);
4247 break;
4248 case 2: /* call Ev */
4249 /* XXX: optimize if memory (no 'and' is necessary) */
4250 if (s->dflag == 0)
4251 gen_op_andl_T0_ffff();
4252 next_eip = s->pc - s->cs_base;
4253 gen_movtl_T1_im(next_eip);
4254 gen_push_T1(s);
4255 gen_op_jmp_T0();
4256 gen_eob(s);
4257 break;
4258 case 3: /* lcall Ev */
4259 gen_op_ld_T1_A0(ot + s->mem_index);
4260 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4261 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4262 do_lcall:
4263 if (s->pe && !s->vm86) {
4264 if (s->cc_op != CC_OP_DYNAMIC)
4265 gen_op_set_cc_op(s->cc_op);
4266 gen_jmp_im(pc_start - s->cs_base);
4267 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4268 tcg_gen_helper_0_4(helper_lcall_protected,
4269 cpu_tmp2_i32, cpu_T[1],
4270 tcg_const_i32(dflag),
4271 tcg_const_i32(s->pc - pc_start));
4272 } else {
4273 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4274 tcg_gen_helper_0_4(helper_lcall_real,
4275 cpu_tmp2_i32, cpu_T[1],
4276 tcg_const_i32(dflag),
4277 tcg_const_i32(s->pc - s->cs_base));
4278 }
4279 gen_eob(s);
4280 break;
4281 case 4: /* jmp Ev */
4282 if (s->dflag == 0)
4283 gen_op_andl_T0_ffff();
4284 gen_op_jmp_T0();
4285 gen_eob(s);
4286 break;
4287 case 5: /* ljmp Ev */
4288 gen_op_ld_T1_A0(ot + s->mem_index);
4289 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4290 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4291 do_ljmp:
4292 if (s->pe && !s->vm86) {
4293 if (s->cc_op != CC_OP_DYNAMIC)
4294 gen_op_set_cc_op(s->cc_op);
4295 gen_jmp_im(pc_start - s->cs_base);
4296 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4297 tcg_gen_helper_0_3(helper_ljmp_protected,
4298 cpu_tmp2_i32,
4299 cpu_T[1],
4300 tcg_const_i32(s->pc - pc_start));
4301 } else {
4302 gen_op_movl_seg_T0_vm(R_CS);
4303 gen_op_movl_T0_T1();
4304 gen_op_jmp_T0();
4305 }
4306 gen_eob(s);
4307 break;
4308 case 6: /* push Ev */
4309 gen_push_T0(s);
4310 break;
4311 default:
4312 goto illegal_op;
4313 }
4314 break;
4315
4316 case 0x84: /* test Ev, Gv */
4317 case 0x85:
4318 if ((b & 1) == 0)
4319 ot = OT_BYTE;
4320 else
4321 ot = dflag + OT_WORD;
4322
4323 modrm = ldub_code(s->pc++);
4324 mod = (modrm >> 6) & 3;
4325 rm = (modrm & 7) | REX_B(s);
4326 reg = ((modrm >> 3) & 7) | rex_r;
4327
4328 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4329 gen_op_mov_TN_reg(ot, 1, reg);
4330 gen_op_testl_T0_T1_cc();
4331 s->cc_op = CC_OP_LOGICB + ot;
4332 break;
4333
4334 case 0xa8: /* test eAX, Iv */
4335 case 0xa9:
4336 if ((b & 1) == 0)
4337 ot = OT_BYTE;
4338 else
4339 ot = dflag + OT_WORD;
4340 val = insn_get(s, ot);
4341
4342 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4343 gen_op_movl_T1_im(val);
4344 gen_op_testl_T0_T1_cc();
4345 s->cc_op = CC_OP_LOGICB + ot;
4346 break;
4347
4348 case 0x98: /* CWDE/CBW */
4349 #ifdef TARGET_X86_64
4350 if (dflag == 2) {
4351 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4352 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4353 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4354 } else
4355 #endif
4356 if (dflag == 1) {
4357 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4358 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4359 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4360 } else {
4361 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4362 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4363 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4364 }
4365 break;
4366 case 0x99: /* CDQ/CWD */
4367 #ifdef TARGET_X86_64
4368 if (dflag == 2) {
4369 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4370 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4371 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4372 } else
4373 #endif
4374 if (dflag == 1) {
4375 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4376 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4377 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4378 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4379 } else {
4380 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4381 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4382 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4383 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4384 }
4385 break;
4386 case 0x1af: /* imul Gv, Ev */
4387 case 0x69: /* imul Gv, Ev, I */
4388 case 0x6b:
4389 ot = dflag + OT_WORD;
4390 modrm = ldub_code(s->pc++);
4391 reg = ((modrm >> 3) & 7) | rex_r;
4392 if (b == 0x69)
4393 s->rip_offset = insn_const_size(ot);
4394 else if (b == 0x6b)
4395 s->rip_offset = 1;
4396 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4397 if (b == 0x69) {
4398 val = insn_get(s, ot);
4399 gen_op_movl_T1_im(val);
4400 } else if (b == 0x6b) {
4401 val = (int8_t)insn_get(s, OT_BYTE);
4402 gen_op_movl_T1_im(val);
4403 } else {
4404 gen_op_mov_TN_reg(ot, 1, reg);
4405 }
4406
4407 #ifdef TARGET_X86_64
4408 if (ot == OT_QUAD) {
4409 tcg_gen_helper_1_2(helper_imulq_T0_T1, cpu_T[0], cpu_T[0], cpu_T[1]);
4410 } else
4411 #endif
4412 if (ot == OT_LONG) {
4413 #ifdef TARGET_X86_64
4414 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4415 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4416 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4417 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4418 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4419 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4420 #else
4421 {
4422 TCGv t0, t1;
4423 t0 = tcg_temp_new(TCG_TYPE_I64);
4424 t1 = tcg_temp_new(TCG_TYPE_I64);
4425 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4426 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4427 tcg_gen_mul_i64(t0, t0, t1);
4428 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4429 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4430 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4431 tcg_gen_shri_i64(t0, t0, 32);
4432 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4433 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4434 }
4435 #endif
4436 } else {
4437 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4438 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4439 /* XXX: use 32 bit mul which could be faster */
4440 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4441 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4442 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4443 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4444 }
4445 gen_op_mov_reg_T0(ot, reg);
4446 s->cc_op = CC_OP_MULB + ot;
4447 break;
4448 case 0x1c0:
4449 case 0x1c1: /* xadd Ev, Gv */
4450 if ((b & 1) == 0)
4451 ot = OT_BYTE;
4452 else
4453 ot = dflag + OT_WORD;
4454 modrm = ldub_code(s->pc++);
4455 reg = ((modrm >> 3) & 7) | rex_r;
4456 mod = (modrm >> 6) & 3;
4457 if (mod == 3) {
4458 rm = (modrm & 7) | REX_B(s);
4459 gen_op_mov_TN_reg(ot, 0, reg);
4460 gen_op_mov_TN_reg(ot, 1, rm);
4461 gen_op_addl_T0_T1();
4462 gen_op_mov_reg_T1(ot, reg);
4463 gen_op_mov_reg_T0(ot, rm);
4464 } else {
4465 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4466 gen_op_mov_TN_reg(ot, 0, reg);
4467 gen_op_ld_T1_A0(ot + s->mem_index);
4468 gen_op_addl_T0_T1();
4469 gen_op_st_T0_A0(ot + s->mem_index);
4470 gen_op_mov_reg_T1(ot, reg);
4471 }
4472 gen_op_update2_cc();
4473 s->cc_op = CC_OP_ADDB + ot;
4474 break;
4475 case 0x1b0:
4476 case 0x1b1: /* cmpxchg Ev, Gv */
4477 {
4478 int label1, label2;
4479 TCGv t0, t1, t2, a0;
4480
4481 if ((b & 1) == 0)
4482 ot = OT_BYTE;
4483 else
4484 ot = dflag + OT_WORD;
4485 modrm = ldub_code(s->pc++);
4486 reg = ((modrm >> 3) & 7) | rex_r;
4487 mod = (modrm >> 6) & 3;
4488 t0 = tcg_temp_local_new(TCG_TYPE_TL);
4489 t1 = tcg_temp_local_new(TCG_TYPE_TL);
4490 t2 = tcg_temp_local_new(TCG_TYPE_TL);
4491 a0 = tcg_temp_local_new(TCG_TYPE_TL);
4492 gen_op_mov_v_reg(ot, t1, reg);
4493 if (mod == 3) {
4494 rm = (modrm & 7) | REX_B(s);
4495 gen_op_mov_v_reg(ot, t0, rm);
4496 } else {
4497 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4498 tcg_gen_mov_tl(a0, cpu_A0);
4499 gen_op_ld_v(ot + s->mem_index, t0, a0);
4500 rm = 0; /* avoid warning */
4501 }
4502 label1 = gen_new_label();
4503 tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX]));
4504 tcg_gen_sub_tl(t2, t2, t0);
4505 gen_extu(ot, t2);
4506 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4507 if (mod == 3) {
4508 label2 = gen_new_label();
4509 gen_op_mov_reg_v(ot, R_EAX, t0);
4510 tcg_gen_br(label2);
4511 gen_set_label(label1);
4512 gen_op_mov_reg_v(ot, rm, t1);
4513 gen_set_label(label2);
4514 } else {
4515 tcg_gen_mov_tl(t1, t0);
4516 gen_op_mov_reg_v(ot, R_EAX, t0);
4517 gen_set_label(label1);
4518 /* always store */
4519 gen_op_st_v(ot + s->mem_index, t1, a0);
4520 }
4521 tcg_gen_mov_tl(cpu_cc_src, t0);
4522 tcg_gen_mov_tl(cpu_cc_dst, t2);
4523 s->cc_op = CC_OP_SUBB + ot;
4524 tcg_temp_free(t0);
4525 tcg_temp_free(t1);
4526 tcg_temp_free(t2);
4527 tcg_temp_free(a0);
4528 }
4529 break;
4530 case 0x1c7: /* cmpxchg8b */
4531 modrm = ldub_code(s->pc++);
4532 mod = (modrm >> 6) & 3;
4533 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4534 goto illegal_op;
4535 #ifdef TARGET_X86_64
4536 if (dflag == 2) {
4537 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4538 goto illegal_op;
4539 gen_jmp_im(pc_start - s->cs_base);
4540 if (s->cc_op != CC_OP_DYNAMIC)
4541 gen_op_set_cc_op(s->cc_op);
4542 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4543 tcg_gen_helper_0_1(helper_cmpxchg16b, cpu_A0);
4544 } else
4545 #endif
4546 {
4547 if (!(s->cpuid_features & CPUID_CX8))
4548 goto illegal_op;
4549 gen_jmp_im(pc_start - s->cs_base);
4550 if (s->cc_op != CC_OP_DYNAMIC)
4551 gen_op_set_cc_op(s->cc_op);
4552 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4553 tcg_gen_helper_0_1(helper_cmpxchg8b, cpu_A0);
4554 }
4555 s->cc_op = CC_OP_EFLAGS;
4556 break;
4557
4558 /**************************/
4559 /* push/pop */
4560 case 0x50 ... 0x57: /* push */
4561 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4562 gen_push_T0(s);
4563 break;
4564 case 0x58 ... 0x5f: /* pop */
4565 if (CODE64(s)) {
4566 ot = dflag ? OT_QUAD : OT_WORD;
4567 } else {
4568 ot = dflag + OT_WORD;
4569 }
4570 gen_pop_T0(s);
4571 /* NOTE: order is important for pop %sp */
4572 gen_pop_update(s);
4573 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4574 break;
4575 case 0x60: /* pusha */
4576 if (CODE64(s))
4577 goto illegal_op;
4578 gen_pusha(s);
4579 break;
4580 case 0x61: /* popa */
4581 if (CODE64(s))
4582 goto illegal_op;
4583 gen_popa(s);
4584 break;
4585 case 0x68: /* push Iv */
4586 case 0x6a:
4587 if (CODE64(s)) {
4588 ot = dflag ? OT_QUAD : OT_WORD;
4589 } else {
4590 ot = dflag + OT_WORD;
4591 }
4592 if (b == 0x68)
4593 val = insn_get(s, ot);
4594 else
4595 val = (int8_t)insn_get(s, OT_BYTE);
4596 gen_op_movl_T0_im(val);
4597 gen_push_T0(s);
4598 break;
4599 case 0x8f: /* pop Ev */
4600 if (CODE64(s)) {
4601 ot = dflag ? OT_QUAD : OT_WORD;
4602 } else {
4603 ot = dflag + OT_WORD;
4604 }
4605 modrm = ldub_code(s->pc++);
4606 mod = (modrm >> 6) & 3;
4607 gen_pop_T0(s);
4608 if (mod == 3) {
4609 /* NOTE: order is important for pop %sp */
4610 gen_pop_update(s);
4611 rm = (modrm & 7) | REX_B(s);
4612 gen_op_mov_reg_T0(ot, rm);
4613 } else {
4614 /* NOTE: order is important too for MMU exceptions */
4615 s->popl_esp_hack = 1 << ot;
4616 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4617 s->popl_esp_hack = 0;
4618 gen_pop_update(s);
4619 }
4620 break;
4621 case 0xc8: /* enter */
4622 {
4623 int level;
4624 val = lduw_code(s->pc);
4625 s->pc += 2;
4626 level = ldub_code(s->pc++);
4627 gen_enter(s, val, level);
4628 }
4629 break;
4630 case 0xc9: /* leave */
4631 /* XXX: exception not precise (ESP is updated before potential exception) */
4632 if (CODE64(s)) {
4633 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
4634 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
4635 } else if (s->ss32) {
4636 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
4637 gen_op_mov_reg_T0(OT_LONG, R_ESP);
4638 } else {
4639 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
4640 gen_op_mov_reg_T0(OT_WORD, R_ESP);
4641 }
4642 gen_pop_T0(s);
4643 if (CODE64(s)) {
4644 ot = dflag ? OT_QUAD : OT_WORD;
4645 } else {
4646 ot = dflag + OT_WORD;
4647 }
4648 gen_op_mov_reg_T0(ot, R_EBP);
4649 gen_pop_update(s);
4650 break;
4651 case 0x06: /* push es */
4652 case 0x0e: /* push cs */
4653 case 0x16: /* push ss */
4654 case 0x1e: /* push ds */
4655 if (CODE64(s))
4656 goto illegal_op;
4657 gen_op_movl_T0_seg(b >> 3);
4658 gen_push_T0(s);
4659 break;
4660 case 0x1a0: /* push fs */
4661 case 0x1a8: /* push gs */
4662 gen_op_movl_T0_seg((b >> 3) & 7);
4663 gen_push_T0(s);
4664 break;
4665 case 0x07: /* pop es */
4666 case 0x17: /* pop ss */
4667 case 0x1f: /* pop ds */
4668 if (CODE64(s))
4669 goto illegal_op;
4670 reg = b >> 3;
4671 gen_pop_T0(s);
4672 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4673 gen_pop_update(s);
4674 if (reg == R_SS) {
4675 /* if reg == SS, inhibit interrupts/trace. */
4676 /* If several instructions disable interrupts, only the
4677 _first_ does it */
4678 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4679 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4680 s->tf = 0;
4681 }
4682 if (s->is_jmp) {
4683 gen_jmp_im(s->pc - s->cs_base);
4684 gen_eob(s);
4685 }
4686 break;
4687 case 0x1a1: /* pop fs */
4688 case 0x1a9: /* pop gs */
4689 gen_pop_T0(s);
4690 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
4691 gen_pop_update(s);
4692 if (s->is_jmp) {
4693 gen_jmp_im(s->pc - s->cs_base);
4694 gen_eob(s);
4695 }
4696 break;
4697
4698 /**************************/
4699 /* mov */
4700 case 0x88:
4701 case 0x89: /* mov Gv, Ev */
4702 if ((b & 1) == 0)
4703 ot = OT_BYTE;
4704 else
4705 ot = dflag + OT_WORD;
4706 modrm = ldub_code(s->pc++);
4707 reg = ((modrm >> 3) & 7) | rex_r;
4708
4709 /* generate a generic store */
4710 gen_ldst_modrm(s, modrm, ot, reg, 1);
4711 break;
4712 case 0xc6:
4713 case 0xc7: /* mov Ev, Iv */
4714 if ((b & 1) == 0)
4715 ot = OT_BYTE;
4716 else
4717 ot = dflag + OT_WORD;
4718 modrm = ldub_code(s->pc++);
4719 mod = (modrm >> 6) & 3;
4720 if (mod != 3) {
4721 s->rip_offset = insn_const_size(ot);
4722 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4723 }
4724 val = insn_get(s, ot);
4725 gen_op_movl_T0_im(val);
4726 if (mod != 3)
4727 gen_op_st_T0_A0(ot + s->mem_index);
4728 else
4729 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
4730 break;
4731 case 0x8a:
4732 case 0x8b: /* mov Ev, Gv */
4733 if ((b & 1) == 0)
4734 ot = OT_BYTE;
4735 else
4736 ot = OT_WORD + dflag;
4737 modrm = ldub_code(s->pc++);
4738 reg = ((modrm >> 3) & 7) | rex_r;
4739
4740 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4741 gen_op_mov_reg_T0(ot, reg);
4742 break;
4743 case 0x8e: /* mov seg, Gv */
4744 modrm = ldub_code(s->pc++);
4745 reg = (modrm >> 3) & 7;
4746 if (reg >= 6 || reg == R_CS)
4747 goto illegal_op;
4748 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
4749 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4750 if (reg == R_SS) {
4751 /* if reg == SS, inhibit interrupts/trace */
4752 /* If several instructions disable interrupts, only the
4753 _first_ does it */
4754 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4755 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4756 s->tf = 0;
4757 }
4758 if (s->is_jmp) {
4759 gen_jmp_im(s->pc - s->cs_base);
4760 gen_eob(s);
4761 }
4762 break;
4763 case 0x8c: /* mov Gv, seg */
4764 modrm = ldub_code(s->pc++);
4765 reg = (modrm >> 3) & 7;
4766 mod = (modrm >> 6) & 3;
4767 if (reg >= 6)
4768 goto illegal_op;
4769 gen_op_movl_T0_seg(reg);
4770 if (mod == 3)
4771 ot = OT_WORD + dflag;
4772 else
4773 ot = OT_WORD;
4774 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4775 break;
4776
4777 case 0x1b6: /* movzbS Gv, Eb */
4778 case 0x1b7: /* movzwS Gv, Eb */
4779 case 0x1be: /* movsbS Gv, Eb */
4780 case 0x1bf: /* movswS Gv, Eb */
4781 {
4782 int d_ot;
4783 /* d_ot is the size of destination */
4784 d_ot = dflag + OT_WORD;
4785 /* ot is the size of source */
4786 ot = (b & 1) + OT_BYTE;
4787 modrm = ldub_code(s->pc++);
4788 reg = ((modrm >> 3) & 7) | rex_r;
4789 mod = (modrm >> 6) & 3;
4790 rm = (modrm & 7) | REX_B(s);
4791
4792 if (mod == 3) {
4793 gen_op_mov_TN_reg(ot, 0, rm);
4794 switch(ot | (b & 8)) {
4795 case OT_BYTE:
4796 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4797 break;
4798 case OT_BYTE | 8:
4799 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4800 break;
4801 case OT_WORD:
4802 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4803 break;
4804 default:
4805 case OT_WORD | 8:
4806 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4807 break;
4808 }
4809 gen_op_mov_reg_T0(d_ot, reg);
4810 } else {
4811 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4812 if (b & 8) {
4813 gen_op_lds_T0_A0(ot + s->mem_index);
4814 } else {
4815 gen_op_ldu_T0_A0(ot + s->mem_index);
4816 }
4817 gen_op_mov_reg_T0(d_ot, reg);
4818 }
4819 }
4820 break;
4821
4822 case 0x8d: /* lea */
4823 ot = dflag + OT_WORD;
4824 modrm = ldub_code(s->pc++);
4825 mod = (modrm >> 6) & 3;
4826 if (mod == 3)
4827 goto illegal_op;
4828 reg = ((modrm >> 3) & 7) | rex_r;
4829 /* we must ensure that no segment is added */
4830 s->override = -1;
4831 val = s->addseg;
4832 s->addseg = 0;
4833 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4834 s->addseg = val;
4835 gen_op_mov_reg_A0(ot - OT_WORD, reg);
4836 break;
4837
4838 case 0xa0: /* mov EAX, Ov */
4839 case 0xa1:
4840 case 0xa2: /* mov Ov, EAX */
4841 case 0xa3:
4842 {
4843 target_ulong offset_addr;
4844
4845 if ((b & 1) == 0)
4846 ot = OT_BYTE;
4847 else
4848 ot = dflag + OT_WORD;
4849 #ifdef TARGET_X86_64
4850 if (s->aflag == 2) {
4851 offset_addr = ldq_code(s->pc);
4852 s->pc += 8;
4853 gen_op_movq_A0_im(offset_addr);
4854 } else
4855 #endif
4856 {
4857 if (s->aflag) {
4858 offset_addr = insn_get(s, OT_LONG);
4859 } else {
4860 offset_addr = insn_get(s, OT_WORD);
4861 }
4862 gen_op_movl_A0_im(offset_addr);
4863 }
4864 gen_add_A0_ds_seg(s);
4865 if ((b & 2) == 0) {
4866 gen_op_ld_T0_A0(ot + s->mem_index);
4867 gen_op_mov_reg_T0(ot, R_EAX);
4868 } else {
4869 gen_op_mov_TN_reg(ot, 0, R_EAX);
4870 gen_op_st_T0_A0(ot + s->mem_index);
4871 }
4872 }
4873 break;
4874 case 0xd7: /* xlat */
4875 #ifdef TARGET_X86_64
4876 if (s->aflag == 2) {
4877 gen_op_movq_A0_reg(R_EBX);
4878 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4879 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
4880 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4881 } else
4882 #endif
4883 {
4884 gen_op_movl_A0_reg(R_EBX);
4885 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4886 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
4887 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4888 if (s->aflag == 0)
4889 gen_op_andl_A0_ffff();
4890 else
4891 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
4892 }
4893 gen_add_A0_ds_seg(s);
4894 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
4895 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
4896 break;
4897 case 0xb0 ... 0xb7: /* mov R, Ib */
4898 val = insn_get(s, OT_BYTE);
4899 gen_op_movl_T0_im(val);
4900 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
4901 break;
4902 case 0xb8 ... 0xbf: /* mov R, Iv */
4903 #ifdef TARGET_X86_64
4904 if (dflag == 2) {
4905 uint64_t tmp;
4906 /* 64 bit case */
4907 tmp = ldq_code(s->pc);
4908 s->pc += 8;
4909 reg = (b & 7) | REX_B(s);
4910 gen_movtl_T0_im(tmp);
4911 gen_op_mov_reg_T0(OT_QUAD, reg);
4912 } else
4913 #endif
4914 {
4915 ot = dflag ? OT_LONG : OT_WORD;
4916 val = insn_get(s, ot);
4917 reg = (b & 7) | REX_B(s);
4918 gen_op_movl_T0_im(val);
4919 gen_op_mov_reg_T0(ot, reg);
4920 }
4921 break;
4922
4923 case 0x91 ... 0x97: /* xchg R, EAX */
4924 ot = dflag + OT_WORD;
4925 reg = (b & 7) | REX_B(s);
4926 rm = R_EAX;
4927 goto do_xchg_reg;
4928 case 0x86:
4929 case 0x87: /* xchg Ev, Gv */
4930 if ((b & 1) == 0)
4931 ot = OT_BYTE;
4932 else
4933 ot = dflag + OT_WORD;
4934 modrm = ldub_code(s->pc++);
4935 reg = ((modrm >> 3) & 7) | rex_r;
4936 mod = (modrm >> 6) & 3;
4937 if (mod == 3) {
4938 rm = (modrm & 7) | REX_B(s);
4939 do_xchg_reg:
4940 gen_op_mov_TN_reg(ot, 0, reg);
4941 gen_op_mov_TN_reg(ot, 1, rm);
4942 gen_op_mov_reg_T0(ot, rm);
4943 gen_op_mov_reg_T1(ot, reg);
4944 } else {
4945 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4946 gen_op_mov_TN_reg(ot, 0, reg);
4947 /* for xchg, lock is implicit */
4948 if (!(prefixes & PREFIX_LOCK))
4949 tcg_gen_helper_0_0(helper_lock);
4950 gen_op_ld_T1_A0(ot + s->mem_index);
4951 gen_op_st_T0_A0(ot + s->mem_index);
4952 if (!(prefixes & PREFIX_LOCK))
4953 tcg_gen_helper_0_0(helper_unlock);
4954 gen_op_mov_reg_T1(ot, reg);
4955 }
4956 break;
4957 case 0xc4: /* les Gv */
4958 if (CODE64(s))
4959 goto illegal_op;
4960 op = R_ES;
4961 goto do_lxx;
4962 case 0xc5: /* lds Gv */
4963 if (CODE64(s))
4964 goto illegal_op;
4965 op = R_DS;
4966 goto do_lxx;
4967 case 0x1b2: /* lss Gv */
4968 op = R_SS;
4969 goto do_lxx;
4970 case 0x1b4: /* lfs Gv */
4971 op = R_FS;
4972 goto do_lxx;
4973 case 0x1b5: /* lgs Gv */
4974 op = R_GS;
4975 do_lxx:
4976 ot = dflag ? OT_LONG : OT_WORD;
4977 modrm = ldub_code(s->pc++);
4978 reg = ((modrm >> 3) & 7) | rex_r;
4979 mod = (modrm >> 6) & 3;
4980 if (mod == 3)
4981 goto illegal_op;
4982 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4983 gen_op_ld_T1_A0(ot + s->mem_index);
4984 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4985 /* load the segment first to handle exceptions properly */
4986 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4987 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4988 /* then put the data */
4989 gen_op_mov_reg_T1(ot, reg);
4990 if (s->is_jmp) {
4991 gen_jmp_im(s->pc - s->cs_base);
4992 gen_eob(s);
4993 }
4994 break;
4995
4996 /************************/
4997 /* shifts */
4998 case 0xc0:
4999 case 0xc1:
5000 /* shift Ev,Ib */
5001 shift = 2;
5002 grp2:
5003 {
5004 if ((b & 1) == 0)
5005 ot = OT_BYTE;
5006 else
5007 ot = dflag + OT_WORD;
5008
5009 modrm = ldub_code(s->pc++);
5010 mod = (modrm >> 6) & 3;
5011 op = (modrm >> 3) & 7;
5012
5013 if (mod != 3) {
5014 if (shift == 2) {
5015 s->rip_offset = 1;
5016 }
5017 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5018 opreg = OR_TMP0;
5019 } else {
5020 opreg = (modrm & 7) | REX_B(s);
5021 }
5022
5023 /* simpler op */
5024 if (shift == 0) {
5025 gen_shift(s, op, ot, opreg, OR_ECX);
5026 } else {
5027 if (shift == 2) {
5028 shift = ldub_code(s->pc++);
5029 }
5030 gen_shifti(s, op, ot, opreg, shift);
5031 }
5032 }
5033 break;
5034 case 0xd0:
5035 case 0xd1:
5036 /* shift Ev,1 */
5037 shift = 1;
5038 goto grp2;
5039 case 0xd2:
5040 case 0xd3:
5041 /* shift Ev,cl */
5042 shift = 0;
5043 goto grp2;
5044
5045 case 0x1a4: /* shld imm */
5046 op = 0;
5047 shift = 1;
5048 goto do_shiftd;
5049 case 0x1a5: /* shld cl */
5050 op = 0;
5051 shift = 0;
5052 goto do_shiftd;
5053 case 0x1ac: /* shrd imm */
5054 op = 1;
5055 shift = 1;
5056 goto do_shiftd;
5057 case 0x1ad: /* shrd cl */
5058 op = 1;
5059 shift = 0;
5060 do_shiftd:
5061 ot = dflag + OT_WORD;
5062 modrm = ldub_code(s->pc++);
5063 mod = (modrm >> 6) & 3;
5064 rm = (modrm & 7) | REX_B(s);
5065 reg = ((modrm >> 3) & 7) | rex_r;
5066 if (mod != 3) {
5067 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5068 opreg = OR_TMP0;
5069 } else {
5070 opreg = rm;
5071 }
5072 gen_op_mov_TN_reg(ot, 1, reg);
5073
5074 if (shift) {
5075 val = ldub_code(s->pc++);
5076 tcg_gen_movi_tl(cpu_T3, val);
5077 } else {
5078 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
5079 }
5080 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5081 break;
5082
5083 /************************/
5084 /* floats */
5085 case 0xd8 ... 0xdf:
5086 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5087 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5088 /* XXX: what to do if illegal op ? */
5089 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5090 break;
5091 }
5092 modrm = ldub_code(s->pc++);
5093 mod = (modrm >> 6) & 3;
5094 rm = modrm & 7;
5095 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5096 if (mod != 3) {
5097 /* memory op */
5098 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5099 switch(op) {
5100 case 0x00 ... 0x07: /* fxxxs */
5101 case 0x10 ... 0x17: /* fixxxl */
5102 case 0x20 ... 0x27: /* fxxxl */
5103 case 0x30 ... 0x37: /* fixxx */
5104 {
5105 int op1;
5106 op1 = op & 7;
5107
5108 switch(op >> 4) {
5109 case 0:
5110 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5111 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5112 tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32);
5113 break;
5114 case 1:
5115 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5116 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5117 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
5118 break;
5119 case 2:
5120 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5121 (s->mem_index >> 2) - 1);
5122 tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64);
5123 break;
5124 case 3:
5125 default:
5126 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5127 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5128 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
5129 break;
5130 }
5131
5132 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
5133 if (op1 == 3) {
5134 /* fcomp needs pop */
5135 tcg_gen_helper_0_0(helper_fpop);
5136 }
5137 }
5138 break;
5139 case 0x08: /* flds */
5140 case 0x0a: /* fsts */
5141 case 0x0b: /* fstps */
5142 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5143 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5144 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5145 switch(op & 7) {
5146 case 0:
5147 switch(op >> 4) {
5148 case 0:
5149 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5150 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5151 tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32);
5152 break;
5153 case 1:
5154 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5155 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5156 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
5157 break;
5158 case 2:
5159 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5160 (s->mem_index >> 2) - 1);
5161 tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64);
5162 break;
5163 case 3:
5164 default:
5165 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5166 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5167 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
5168 break;
5169 }
5170 break;
5171 case 1:
5172 /* XXX: the corresponding CPUID bit must be tested ! */
5173 switch(op >> 4) {
5174 case 1:
5175 tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32);
5176 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5177 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5178 break;
5179 case 2:
5180 tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64);
5181 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5182 (s->mem_index >> 2) - 1);
5183 break;
5184 case 3:
5185 default:
5186 tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32);
5187 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5188 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5189 break;
5190 }
5191 tcg_gen_helper_0_0(helper_fpop);
5192 break;
5193 default:
5194 switch(op >> 4) {
5195 case 0:
5196 tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32);
5197 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5198 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5199 break;
5200 case 1:
5201 tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32);
5202 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5203 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5204 break;
5205 case 2:
5206 tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64);
5207 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5208 (s->mem_index >> 2) - 1);
5209 break;
5210 case 3:
5211 default:
5212 tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32);
5213 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5214 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5215 break;
5216 }
5217 if ((op & 7) == 3)
5218 tcg_gen_helper_0_0(helper_fpop);
5219 break;
5220 }
5221 break;
5222 case 0x0c: /* fldenv mem */
5223 if (s->cc_op != CC_OP_DYNAMIC)
5224 gen_op_set_cc_op(s->cc_op);
5225 gen_jmp_im(pc_start - s->cs_base);
5226 tcg_gen_helper_0_2(helper_fldenv,
5227 cpu_A0, tcg_const_i32(s->dflag));
5228 break;
5229 case 0x0d: /* fldcw mem */
5230 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5231 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5232 tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32);
5233 break;
5234 case 0x0e: /* fnstenv mem */
5235 if (s->cc_op != CC_OP_DYNAMIC)
5236 gen_op_set_cc_op(s->cc_op);
5237 gen_jmp_im(pc_start - s->cs_base);
5238 tcg_gen_helper_0_2(helper_fstenv,
5239 cpu_A0, tcg_const_i32(s->dflag));
5240 break;
5241 case 0x0f: /* fnstcw mem */
5242 tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32);
5243 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5244 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5245 break;
5246 case 0x1d: /* fldt mem */
5247 if (s->cc_op != CC_OP_DYNAMIC)
5248 gen_op_set_cc_op(s->cc_op);
5249 gen_jmp_im(pc_start - s->cs_base);
5250 tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0);
5251 break;
5252 case 0x1f: /* fstpt mem */
5253 if (s->cc_op != CC_OP_DYNAMIC)
5254 gen_op_set_cc_op(s->cc_op);
5255 gen_jmp_im(pc_start - s->cs_base);
5256 tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0);
5257 tcg_gen_helper_0_0(helper_fpop);
5258 break;
5259 case 0x2c: /* frstor mem */
5260 if (s->cc_op != CC_OP_DYNAMIC)
5261 gen_op_set_cc_op(s->cc_op);
5262 gen_jmp_im(pc_start - s->cs_base);
5263 tcg_gen_helper_0_2(helper_frstor,
5264 cpu_A0, tcg_const_i32(s->dflag));
5265 break;
5266 case 0x2e: /* fnsave mem */
5267 if (s->cc_op != CC_OP_DYNAMIC)
5268 gen_op_set_cc_op(s->cc_op);
5269 gen_jmp_im(pc_start - s->cs_base);
5270 tcg_gen_helper_0_2(helper_fsave,
5271 cpu_A0, tcg_const_i32(s->dflag));
5272 break;
5273 case 0x2f: /* fnstsw mem */
5274 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5275 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5276 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5277 break;
5278 case 0x3c: /* fbld */
5279 if (s->cc_op != CC_OP_DYNAMIC)
5280 gen_op_set_cc_op(s->cc_op);
5281 gen_jmp_im(pc_start - s->cs_base);
5282 tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0);
5283 break;
5284 case 0x3e: /* fbstp */
5285 if (s->cc_op != CC_OP_DYNAMIC)
5286 gen_op_set_cc_op(s->cc_op);
5287 gen_jmp_im(pc_start - s->cs_base);
5288 tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0);
5289 tcg_gen_helper_0_0(helper_fpop);
5290 break;
5291 case 0x3d: /* fildll */
5292 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5293 (s->mem_index >> 2) - 1);
5294 tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64);
5295 break;
5296 case 0x3f: /* fistpll */
5297 tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64);
5298 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5299 (s->mem_index >> 2) - 1);
5300 tcg_gen_helper_0_0(helper_fpop);
5301 break;
5302 default:
5303 goto illegal_op;
5304 }
5305 } else {
5306 /* register float ops */
5307 opreg = rm;
5308
5309 switch(op) {
5310 case 0x08: /* fld sti */
5311 tcg_gen_helper_0_0(helper_fpush);
5312 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7));
5313 break;
5314 case 0x09: /* fxchg sti */
5315 case 0x29: /* fxchg4 sti, undocumented op */
5316 case 0x39: /* fxchg7 sti, undocumented op */
5317 tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg));
5318 break;
5319 case 0x0a: /* grp d9/2 */
5320 switch(rm) {
5321 case 0: /* fnop */
5322 /* check exceptions (FreeBSD FPU probe) */
5323 if (s->cc_op != CC_OP_DYNAMIC)
5324 gen_op_set_cc_op(s->cc_op);
5325 gen_jmp_im(pc_start - s->cs_base);
5326 tcg_gen_helper_0_0(helper_fwait);
5327 break;
5328 default:
5329 goto illegal_op;
5330 }
5331 break;
5332 case 0x0c: /* grp d9/4 */
5333 switch(rm) {
5334 case 0: /* fchs */
5335 tcg_gen_helper_0_0(helper_fchs_ST0);
5336 break;
5337 case 1: /* fabs */
5338 tcg_gen_helper_0_0(helper_fabs_ST0);
5339 break;
5340 case 4: /* ftst */
5341 tcg_gen_helper_0_0(helper_fldz_FT0);
5342 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5343 break;
5344 case 5: /* fxam */
5345 tcg_gen_helper_0_0(helper_fxam_ST0);
5346 break;
5347 default:
5348 goto illegal_op;
5349 }
5350 break;
5351 case 0x0d: /* grp d9/5 */
5352 {
5353 switch(rm) {
5354 case 0:
5355 tcg_gen_helper_0_0(helper_fpush);
5356 tcg_gen_helper_0_0(helper_fld1_ST0);
5357 break;
5358 case 1:
5359 tcg_gen_helper_0_0(helper_fpush);
5360 tcg_gen_helper_0_0(helper_fldl2t_ST0);
5361 break;
5362 case 2:
5363 tcg_gen_helper_0_0(helper_fpush);
5364 tcg_gen_helper_0_0(helper_fldl2e_ST0);
5365 break;
5366 case 3:
5367 tcg_gen_helper_0_0(helper_fpush);
5368 tcg_gen_helper_0_0(helper_fldpi_ST0);
5369 break;
5370 case 4:
5371 tcg_gen_helper_0_0(helper_fpush);
5372 tcg_gen_helper_0_0(helper_fldlg2_ST0);
5373 break;
5374 case 5:
5375 tcg_gen_helper_0_0(helper_fpush);
5376 tcg_gen_helper_0_0(helper_fldln2_ST0);
5377 break;
5378 case 6:
5379 tcg_gen_helper_0_0(helper_fpush);
5380 tcg_gen_helper_0_0(helper_fldz_ST0);
5381 break;
5382 default:
5383 goto illegal_op;
5384 }
5385 }
5386 break;
5387 case 0x0e: /* grp d9/6 */
5388 switch(rm) {
5389 case 0: /* f2xm1 */
5390 tcg_gen_helper_0_0(helper_f2xm1);
5391 break;
5392 case 1: /* fyl2x */
5393 tcg_gen_helper_0_0(helper_fyl2x);
5394 break;
5395 case 2: /* fptan */
5396 tcg_gen_helper_0_0(helper_fptan);
5397 break;
5398 case 3: /* fpatan */
5399 tcg_gen_helper_0_0(helper_fpatan);
5400 break;
5401 case 4: /* fxtract */
5402 tcg_gen_helper_0_0(helper_fxtract);
5403 break;
5404 case 5: /* fprem1 */
5405 tcg_gen_helper_0_0(helper_fprem1);
5406 break;
5407 case 6: /* fdecstp */
5408 tcg_gen_helper_0_0(helper_fdecstp);
5409 break;
5410 default:
5411 case 7: /* fincstp */
5412 tcg_gen_helper_0_0(helper_fincstp);
5413 break;
5414 }
5415 break;
5416 case 0x0f: /* grp d9/7 */
5417 switch(rm) {
5418 case 0: /* fprem */
5419 tcg_gen_helper_0_0(helper_fprem);
5420 break;
5421 case 1: /* fyl2xp1 */
5422 tcg_gen_helper_0_0(helper_fyl2xp1);
5423 break;
5424 case 2: /* fsqrt */
5425 tcg_gen_helper_0_0(helper_fsqrt);
5426 break;
5427 case 3: /* fsincos */
5428 tcg_gen_helper_0_0(helper_fsincos);
5429 break;
5430 case 5: /* fscale */
5431 tcg_gen_helper_0_0(helper_fscale);
5432 break;
5433 case 4: /* frndint */
5434 tcg_gen_helper_0_0(helper_frndint);
5435 break;
5436 case 6: /* fsin */
5437 tcg_gen_helper_0_0(helper_fsin);
5438 break;
5439 default:
5440 case 7: /* fcos */
5441 tcg_gen_helper_0_0(helper_fcos);
5442 break;
5443 }
5444 break;
5445 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5446 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5447 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5448 {
5449 int op1;
5450
5451 op1 = op & 7;
5452 if (op >= 0x20) {
5453 tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg));
5454 if (op >= 0x30)
5455 tcg_gen_helper_0_0(helper_fpop);
5456 } else {
5457 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5458 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
5459 }
5460 }
5461 break;
5462 case 0x02: /* fcom */
5463 case 0x22: /* fcom2, undocumented op */
5464 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5465 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5466 break;
5467 case 0x03: /* fcomp */
5468 case 0x23: /* fcomp3, undocumented op */
5469 case 0x32: /* fcomp5, undocumented op */
5470 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5471 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5472 tcg_gen_helper_0_0(helper_fpop);
5473 break;
5474 case 0x15: /* da/5 */
5475 switch(rm) {
5476 case 1: /* fucompp */
5477 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5478 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5479 tcg_gen_helper_0_0(helper_fpop);
5480 tcg_gen_helper_0_0(helper_fpop);
5481 break;
5482 default:
5483 goto illegal_op;
5484 }
5485 break;
5486 case 0x1c:
5487 switch(rm) {
5488 case 0: /* feni (287 only, just do nop here) */
5489 break;
5490 case 1: /* fdisi (287 only, just do nop here) */
5491 break;
5492 case 2: /* fclex */
5493 tcg_gen_helper_0_0(helper_fclex);
5494 break;
5495 case 3: /* fninit */
5496 tcg_gen_helper_0_0(helper_fninit);
5497 break;
5498 case 4: /* fsetpm (287 only, just do nop here) */
5499 break;
5500 default:
5501 goto illegal_op;
5502 }
5503 break;
5504 case 0x1d: /* fucomi */
5505 if (s->cc_op != CC_OP_DYNAMIC)
5506 gen_op_set_cc_op(s->cc_op);
5507 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5508 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5509 s->cc_op = CC_OP_EFLAGS;
5510 break;
5511 case 0x1e: /* fcomi */
5512 if (s->cc_op != CC_OP_DYNAMIC)
5513 gen_op_set_cc_op(s->cc_op);
5514 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5515 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5516 s->cc_op = CC_OP_EFLAGS;
5517 break;
5518 case 0x28: /* ffree sti */
5519 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5520 break;
5521 case 0x2a: /* fst sti */
5522 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5523 break;
5524 case 0x2b: /* fstp sti */
5525 case 0x0b: /* fstp1 sti, undocumented op */
5526 case 0x3a: /* fstp8 sti, undocumented op */
5527 case 0x3b: /* fstp9 sti, undocumented op */
5528 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5529 tcg_gen_helper_0_0(helper_fpop);
5530 break;
5531 case 0x2c: /* fucom st(i) */
5532 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5533 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5534 break;
5535 case 0x2d: /* fucomp st(i) */
5536 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5537 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5538 tcg_gen_helper_0_0(helper_fpop);
5539 break;
5540 case 0x33: /* de/3 */
5541 switch(rm) {
5542 case 1: /* fcompp */
5543 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5544 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5545 tcg_gen_helper_0_0(helper_fpop);
5546 tcg_gen_helper_0_0(helper_fpop);
5547 break;
5548 default:
5549 goto illegal_op;
5550 }
5551 break;
5552 case 0x38: /* ffreep sti, undocumented op */
5553 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5554 tcg_gen_helper_0_0(helper_fpop);
5555 break;
5556 case 0x3c: /* df/4 */
5557 switch(rm) {
5558 case 0:
5559 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5560 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5561 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5562 break;
5563 default:
5564 goto illegal_op;
5565 }
5566 break;
5567 case 0x3d: /* fucomip */
5568 if (s->cc_op != CC_OP_DYNAMIC)
5569 gen_op_set_cc_op(s->cc_op);
5570 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5571 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5572 tcg_gen_helper_0_0(helper_fpop);
5573 s->cc_op = CC_OP_EFLAGS;
5574 break;
5575 case 0x3e: /* fcomip */
5576 if (s->cc_op != CC_OP_DYNAMIC)
5577 gen_op_set_cc_op(s->cc_op);
5578 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5579 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5580 tcg_gen_helper_0_0(helper_fpop);
5581 s->cc_op = CC_OP_EFLAGS;
5582 break;
5583 case 0x10 ... 0x13: /* fcmovxx */
5584 case 0x18 ... 0x1b:
5585 {
5586 int op1, l1;
5587 static const uint8_t fcmov_cc[8] = {
5588 (JCC_B << 1),
5589 (JCC_Z << 1),
5590 (JCC_BE << 1),
5591 (JCC_P << 1),
5592 };
5593 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
5594 l1 = gen_new_label();
5595 gen_jcc1(s, s->cc_op, op1, l1);
5596 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg));
5597 gen_set_label(l1);
5598 }
5599 break;
5600 default:
5601 goto illegal_op;
5602 }
5603 }
5604 break;
5605 /************************/
5606 /* string ops */
5607
5608 case 0xa4: /* movsS */
5609 case 0xa5:
5610 if ((b & 1) == 0)
5611 ot = OT_BYTE;
5612 else
5613 ot = dflag + OT_WORD;
5614
5615 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5616 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5617 } else {
5618 gen_movs(s, ot);
5619 }
5620 break;
5621
5622 case 0xaa: /* stosS */
5623 case 0xab:
5624 if ((b & 1) == 0)
5625 ot = OT_BYTE;
5626 else
5627 ot = dflag + OT_WORD;
5628
5629 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5630 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5631 } else {
5632 gen_stos(s, ot);
5633 }
5634 break;
5635 case 0xac: /* lodsS */
5636 case 0xad:
5637 if ((b & 1) == 0)
5638 ot = OT_BYTE;
5639 else
5640 ot = dflag + OT_WORD;
5641 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5642 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5643 } else {
5644 gen_lods(s, ot);
5645 }
5646 break;
5647 case 0xae: /* scasS */
5648 case 0xaf:
5649 if ((b & 1) == 0)
5650 ot = OT_BYTE;
5651 else
5652 ot = dflag + OT_WORD;
5653 if (prefixes & PREFIX_REPNZ) {
5654 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5655 } else if (prefixes & PREFIX_REPZ) {
5656 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5657 } else {
5658 gen_scas(s, ot);
5659 s->cc_op = CC_OP_SUBB + ot;
5660 }
5661 break;
5662
5663 case 0xa6: /* cmpsS */
5664 case 0xa7:
5665 if ((b & 1) == 0)
5666 ot = OT_BYTE;
5667 else
5668 ot = dflag + OT_WORD;
5669 if (prefixes & PREFIX_REPNZ) {
5670 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5671 } else if (prefixes & PREFIX_REPZ) {
5672 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5673 } else {
5674 gen_cmps(s, ot);
5675 s->cc_op = CC_OP_SUBB + ot;
5676 }
5677 break;
5678 case 0x6c: /* insS */
5679 case 0x6d:
5680 if ((b & 1) == 0)
5681 ot = OT_BYTE;
5682 else
5683 ot = dflag ? OT_LONG : OT_WORD;
5684 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5685 gen_op_andl_T0_ffff();
5686 gen_check_io(s, ot, pc_start - s->cs_base,
5687 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
5688 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5689 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5690 } else {
5691 gen_ins(s, ot);
5692 if (use_icount) {
5693 gen_jmp(s, s->pc - s->cs_base);
5694 }
5695 }
5696 break;
5697 case 0x6e: /* outsS */
5698 case 0x6f:
5699 if ((b & 1) == 0)
5700 ot = OT_BYTE;
5701 else
5702 ot = dflag ? OT_LONG : OT_WORD;
5703 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5704 gen_op_andl_T0_ffff();
5705 gen_check_io(s, ot, pc_start - s->cs_base,
5706 svm_is_rep(prefixes) | 4);
5707 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5708 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5709 } else {
5710 gen_outs(s, ot);
5711 if (use_icount) {
5712 gen_jmp(s, s->pc - s->cs_base);
5713 }
5714 }
5715 break;
5716
5717 /************************/
5718 /* port I/O */
5719
5720 case 0xe4:
5721 case 0xe5:
5722 if ((b & 1) == 0)
5723 ot = OT_BYTE;
5724 else
5725 ot = dflag ? OT_LONG : OT_WORD;
5726 val = ldub_code(s->pc++);
5727 gen_op_movl_T0_im(val);
5728 gen_check_io(s, ot, pc_start - s->cs_base,
5729 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5730 if (use_icount)
5731 gen_io_start();
5732 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5733 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5734 gen_op_mov_reg_T1(ot, R_EAX);
5735 if (use_icount) {
5736 gen_io_end();
5737 gen_jmp(s, s->pc - s->cs_base);
5738 }
5739 break;
5740 case 0xe6:
5741 case 0xe7:
5742 if ((b & 1) == 0)
5743 ot = OT_BYTE;
5744 else
5745 ot = dflag ? OT_LONG : OT_WORD;
5746 val = ldub_code(s->pc++);
5747 gen_op_movl_T0_im(val);
5748 gen_check_io(s, ot, pc_start - s->cs_base,
5749 svm_is_rep(prefixes));
5750 gen_op_mov_TN_reg(ot, 1, R_EAX);
5751
5752 if (use_icount)
5753 gen_io_start();
5754 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5755 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5756 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5757 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5758 if (use_icount) {
5759 gen_io_end();
5760 gen_jmp(s, s->pc - s->cs_base);
5761 }
5762 break;
5763 case 0xec:
5764 case 0xed:
5765 if ((b & 1) == 0)
5766 ot = OT_BYTE;
5767 else
5768 ot = dflag ? OT_LONG : OT_WORD;
5769 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5770 gen_op_andl_T0_ffff();
5771 gen_check_io(s, ot, pc_start - s->cs_base,
5772 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5773 if (use_icount)
5774 gen_io_start();
5775 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5776 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5777 gen_op_mov_reg_T1(ot, R_EAX);
5778 if (use_icount) {
5779 gen_io_end();
5780 gen_jmp(s, s->pc - s->cs_base);
5781 }
5782 break;
5783 case 0xee:
5784 case 0xef:
5785 if ((b & 1) == 0)
5786 ot = OT_BYTE;
5787 else
5788 ot = dflag ? OT_LONG : OT_WORD;
5789 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5790 gen_op_andl_T0_ffff();
5791 gen_check_io(s, ot, pc_start - s->cs_base,
5792 svm_is_rep(prefixes));
5793 gen_op_mov_TN_reg(ot, 1, R_EAX);
5794
5795 if (use_icount)
5796 gen_io_start();
5797 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5798 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5799 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5800 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5801 if (use_icount) {
5802 gen_io_end();
5803 gen_jmp(s, s->pc - s->cs_base);
5804 }
5805 break;
5806
5807 /************************/
5808 /* control */
5809 case 0xc2: /* ret im */
5810 val = ldsw_code(s->pc);
5811 s->pc += 2;
5812 gen_pop_T0(s);
5813 if (CODE64(s) && s->dflag)
5814 s->dflag = 2;
5815 gen_stack_update(s, val + (2 << s->dflag));
5816 if (s->dflag == 0)
5817 gen_op_andl_T0_ffff();
5818 gen_op_jmp_T0();
5819 gen_eob(s);
5820 break;
5821 case 0xc3: /* ret */
5822 gen_pop_T0(s);
5823 gen_pop_update(s);
5824 if (s->dflag == 0)
5825 gen_op_andl_T0_ffff();
5826 gen_op_jmp_T0();
5827 gen_eob(s);
5828 break;
5829 case 0xca: /* lret im */
5830 val = ldsw_code(s->pc);
5831 s->pc += 2;
5832 do_lret:
5833 if (s->pe && !s->vm86) {
5834 if (s->cc_op != CC_OP_DYNAMIC)
5835 gen_op_set_cc_op(s->cc_op);
5836 gen_jmp_im(pc_start - s->cs_base);
5837 tcg_gen_helper_0_2(helper_lret_protected,
5838 tcg_const_i32(s->dflag),
5839 tcg_const_i32(val));
5840 } else {
5841 gen_stack_A0(s);
5842 /* pop offset */
5843 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5844 if (s->dflag == 0)
5845 gen_op_andl_T0_ffff();
5846 /* NOTE: keeping EIP updated is not a problem in case of
5847 exception */
5848 gen_op_jmp_T0();
5849 /* pop selector */
5850 gen_op_addl_A0_im(2 << s->dflag);
5851 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5852 gen_op_movl_seg_T0_vm(R_CS);
5853 /* add stack offset */
5854 gen_stack_update(s, val + (4 << s->dflag));
5855 }
5856 gen_eob(s);
5857 break;
5858 case 0xcb: /* lret */
5859 val = 0;
5860 goto do_lret;
5861 case 0xcf: /* iret */
5862 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
5863 if (!s->pe) {
5864 /* real mode */
5865 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5866 s->cc_op = CC_OP_EFLAGS;
5867 } else if (s->vm86) {
5868 if (s->iopl != 3) {
5869 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5870 } else {
5871 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5872 s->cc_op = CC_OP_EFLAGS;
5873 }
5874 } else {
5875 if (s->cc_op != CC_OP_DYNAMIC)
5876 gen_op_set_cc_op(s->cc_op);
5877 gen_jmp_im(pc_start - s->cs_base);
5878 tcg_gen_helper_0_2(helper_iret_protected,
5879 tcg_const_i32(s->dflag),
5880 tcg_const_i32(s->pc - s->cs_base));
5881 s->cc_op = CC_OP_EFLAGS;
5882 }
5883 gen_eob(s);
5884 break;
5885 case 0xe8: /* call im */
5886 {
5887 if (dflag)
5888 tval = (int32_t)insn_get(s, OT_LONG);
5889 else
5890 tval = (int16_t)insn_get(s, OT_WORD);
5891 next_eip = s->pc - s->cs_base;
5892 tval += next_eip;
5893 if (s->dflag == 0)
5894 tval &= 0xffff;
5895 gen_movtl_T0_im(next_eip);
5896 gen_push_T0(s);
5897 gen_jmp(s, tval);
5898 }
5899 break;
5900 case 0x9a: /* lcall im */
5901 {
5902 unsigned int selector, offset;
5903
5904 if (CODE64(s))
5905 goto illegal_op;
5906 ot = dflag ? OT_LONG : OT_WORD;
5907 offset = insn_get(s, ot);
5908 selector = insn_get(s, OT_WORD);
5909
5910 gen_op_movl_T0_im(selector);
5911 gen_op_movl_T1_imu(offset);
5912 }
5913 goto do_lcall;
5914 case 0xe9: /* jmp im */
5915 if (dflag)
5916 tval = (int32_t)insn_get(s, OT_LONG);
5917 else
5918 tval = (int16_t)insn_get(s, OT_WORD);
5919 tval += s->pc - s->cs_base;
5920 if (s->dflag == 0)
5921 tval &= 0xffff;
5922 gen_jmp(s, tval);
5923 break;
5924 case 0xea: /* ljmp im */
5925 {
5926 unsigned int selector, offset;
5927
5928 if (CODE64(s))
5929 goto illegal_op;
5930 ot = dflag ? OT_LONG : OT_WORD;
5931 offset = insn_get(s, ot);
5932 selector = insn_get(s, OT_WORD);
5933
5934 gen_op_movl_T0_im(selector);
5935 gen_op_movl_T1_imu(offset);
5936 }
5937 goto do_ljmp;
5938 case 0xeb: /* jmp Jb */
5939 tval = (int8_t)insn_get(s, OT_BYTE);
5940 tval += s->pc - s->cs_base;
5941 if (s->dflag == 0)
5942 tval &= 0xffff;
5943 gen_jmp(s, tval);
5944 break;
5945 case 0x70 ... 0x7f: /* jcc Jb */
5946 tval = (int8_t)insn_get(s, OT_BYTE);
5947 goto do_jcc;
5948 case 0x180 ... 0x18f: /* jcc Jv */
5949 if (dflag) {
5950 tval = (int32_t)insn_get(s, OT_LONG);
5951 } else {
5952 tval = (int16_t)insn_get(s, OT_WORD);
5953 }
5954 do_jcc:
5955 next_eip = s->pc - s->cs_base;
5956 tval += next_eip;
5957 if (s->dflag == 0)
5958 tval &= 0xffff;
5959 gen_jcc(s, b, tval, next_eip);
5960 break;
5961
5962 case 0x190 ... 0x19f: /* setcc Gv */
5963 modrm = ldub_code(s->pc++);
5964 gen_setcc(s, b);
5965 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
5966 break;
5967 case 0x140 ... 0x14f: /* cmov Gv, Ev */
5968 {
5969 int l1;
5970 TCGv t0;
5971
5972 ot = dflag + OT_WORD;
5973 modrm = ldub_code(s->pc++);
5974 reg = ((modrm >> 3) & 7) | rex_r;
5975 mod = (modrm >> 6) & 3;
5976 t0 = tcg_temp_local_new(TCG_TYPE_TL);
5977 if (mod != 3) {
5978 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5979 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
5980 } else {
5981 rm = (modrm & 7) | REX_B(s);
5982 gen_op_mov_v_reg(ot, t0, rm);
5983 }
5984 #ifdef TARGET_X86_64
5985 if (ot == OT_LONG) {
5986 /* XXX: specific Intel behaviour ? */
5987 l1 = gen_new_label();
5988 gen_jcc1(s, s->cc_op, b ^ 1, l1);
5989 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
5990 gen_set_label(l1);
5991 tcg_gen_movi_tl(cpu_tmp0, 0);
5992 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
5993 } else
5994 #endif
5995 {
5996 l1 = gen_new_label();
5997 gen_jcc1(s, s->cc_op, b ^ 1, l1);
5998 gen_op_mov_reg_v(ot, reg, t0);
5999 gen_set_label(l1);
6000 }
6001 tcg_temp_free(t0);
6002 }
6003 break;
6004
6005 /************************/
6006 /* flags */
6007 case 0x9c: /* pushf */
6008 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6009 if (s->vm86 && s->iopl != 3) {
6010 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6011 } else {
6012 if (s->cc_op != CC_OP_DYNAMIC)
6013 gen_op_set_cc_op(s->cc_op);
6014 tcg_gen_helper_1_0(helper_read_eflags, cpu_T[0]);
6015 gen_push_T0(s);
6016 }
6017 break;
6018 case 0x9d: /* popf */
6019 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6020 if (s->vm86 && s->iopl != 3) {
6021 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6022 } else {
6023 gen_pop_T0(s);
6024 if (s->cpl == 0) {
6025 if (s->dflag) {
6026 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6027 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
6028 } else {
6029 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6030 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
6031 }
6032 } else {
6033 if (s->cpl <= s->iopl) {
6034 if (s->dflag) {
6035 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6036 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
6037 } else {
6038 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6039 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
6040 }
6041 } else {
6042 if (s->dflag) {
6043 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6044 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
6045 } else {
6046 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6047 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
6048 }
6049 }
6050 }
6051 gen_pop_update(s);
6052 s->cc_op = CC_OP_EFLAGS;
6053 /* abort translation because TF flag may change */
6054 gen_jmp_im(s->pc - s->cs_base);
6055 gen_eob(s);
6056 }
6057 break;
6058 case 0x9e: /* sahf */
6059 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6060 goto illegal_op;
6061 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6062 if (s->cc_op != CC_OP_DYNAMIC)
6063 gen_op_set_cc_op(s->cc_op);
6064 gen_compute_eflags(cpu_cc_src);
6065 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6066 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6067 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6068 s->cc_op = CC_OP_EFLAGS;
6069 break;
6070 case 0x9f: /* lahf */
6071 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6072 goto illegal_op;
6073 if (s->cc_op != CC_OP_DYNAMIC)
6074 gen_op_set_cc_op(s->cc_op);
6075 gen_compute_eflags(cpu_T[0]);
6076 /* Note: gen_compute_eflags() only gives the condition codes */
6077 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6078 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6079 break;
6080 case 0xf5: /* cmc */
6081 if (s->cc_op != CC_OP_DYNAMIC)
6082 gen_op_set_cc_op(s->cc_op);
6083 gen_compute_eflags(cpu_cc_src);
6084 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6085 s->cc_op = CC_OP_EFLAGS;
6086 break;
6087 case 0xf8: /* clc */
6088 if (s->cc_op != CC_OP_DYNAMIC)
6089 gen_op_set_cc_op(s->cc_op);
6090 gen_compute_eflags(cpu_cc_src);
6091 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6092 s->cc_op = CC_OP_EFLAGS;
6093 break;
6094 case 0xf9: /* stc */
6095 if (s->cc_op != CC_OP_DYNAMIC)
6096 gen_op_set_cc_op(s->cc_op);
6097 gen_compute_eflags(cpu_cc_src);
6098 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6099 s->cc_op = CC_OP_EFLAGS;
6100 break;
6101 case 0xfc: /* cld */
6102 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6103 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6104 break;
6105 case 0xfd: /* std */
6106 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6107 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6108 break;
6109
6110 /************************/
6111 /* bit operations */
6112 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6113 ot = dflag + OT_WORD;
6114 modrm = ldub_code(s->pc++);
6115 op = (modrm >> 3) & 7;
6116 mod = (modrm >> 6) & 3;
6117 rm = (modrm & 7) | REX_B(s);
6118 if (mod != 3) {
6119 s->rip_offset = 1;
6120 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6121 gen_op_ld_T0_A0(ot + s->mem_index);
6122 } else {
6123 gen_op_mov_TN_reg(ot, 0, rm);
6124 }
6125 /* load shift */
6126 val = ldub_code(s->pc++);
6127 gen_op_movl_T1_im(val);
6128 if (op < 4)
6129 goto illegal_op;
6130 op -= 4;
6131 goto bt_op;
6132 case 0x1a3: /* bt Gv, Ev */
6133 op = 0;
6134 goto do_btx;
6135 case 0x1ab: /* bts */
6136 op = 1;
6137 goto do_btx;
6138 case 0x1b3: /* btr */
6139 op = 2;
6140 goto do_btx;
6141 case 0x1bb: /* btc */
6142 op = 3;
6143 do_btx:
6144 ot = dflag + OT_WORD;
6145 modrm = ldub_code(s->pc++);
6146 reg = ((modrm >> 3) & 7) | rex_r;
6147 mod = (modrm >> 6) & 3;
6148 rm = (modrm & 7) | REX_B(s);
6149 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6150 if (mod != 3) {
6151 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6152 /* specific case: we need to add a displacement */
6153 gen_exts(ot, cpu_T[1]);
6154 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6155 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6156 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6157 gen_op_ld_T0_A0(ot + s->mem_index);
6158 } else {
6159 gen_op_mov_TN_reg(ot, 0, rm);
6160 }
6161 bt_op:
6162 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6163 switch(op) {
6164 case 0:
6165 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6166 tcg_gen_movi_tl(cpu_cc_dst, 0);
6167 break;
6168 case 1:
6169 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6170 tcg_gen_movi_tl(cpu_tmp0, 1);
6171 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6172 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6173 break;
6174 case 2:
6175 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6176 tcg_gen_movi_tl(cpu_tmp0, 1);
6177 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6178 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6179 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6180 break;
6181 default:
6182 case 3:
6183 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6184 tcg_gen_movi_tl(cpu_tmp0, 1);
6185 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6186 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6187 break;
6188 }
6189 s->cc_op = CC_OP_SARB + ot;
6190 if (op != 0) {
6191 if (mod != 3)
6192 gen_op_st_T0_A0(ot + s->mem_index);
6193 else
6194 gen_op_mov_reg_T0(ot, rm);
6195 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6196 tcg_gen_movi_tl(cpu_cc_dst, 0);
6197 }
6198 break;
6199 case 0x1bc: /* bsf */
6200 case 0x1bd: /* bsr */
6201 {
6202 int label1;
6203 TCGv t0;
6204
6205 ot = dflag + OT_WORD;
6206 modrm = ldub_code(s->pc++);
6207 reg = ((modrm >> 3) & 7) | rex_r;
6208 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
6209 gen_extu(ot, cpu_T[0]);
6210 label1 = gen_new_label();
6211 tcg_gen_movi_tl(cpu_cc_dst, 0);
6212 t0 = tcg_temp_local_new(TCG_TYPE_TL);
6213 tcg_gen_mov_tl(t0, cpu_T[0]);
6214 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6215 if (b & 1) {
6216 tcg_gen_helper_1_1(helper_bsr, cpu_T[0], t0);
6217 } else {
6218 tcg_gen_helper_1_1(helper_bsf, cpu_T[0], t0);
6219 }
6220 gen_op_mov_reg_T0(ot, reg);
6221 tcg_gen_movi_tl(cpu_cc_dst, 1);
6222 gen_set_label(label1);
6223 tcg_gen_discard_tl(cpu_cc_src);
6224 s->cc_op = CC_OP_LOGICB + ot;
6225 tcg_temp_free(t0);
6226 }
6227 break;
6228 /************************/
6229 /* bcd */
6230 case 0x27: /* daa */
6231 if (CODE64(s))
6232 goto illegal_op;
6233 if (s->cc_op != CC_OP_DYNAMIC)
6234 gen_op_set_cc_op(s->cc_op);
6235 tcg_gen_helper_0_0(helper_daa);
6236 s->cc_op = CC_OP_EFLAGS;
6237 break;
6238 case 0x2f: /* das */
6239 if (CODE64(s))
6240 goto illegal_op;
6241 if (s->cc_op != CC_OP_DYNAMIC)
6242 gen_op_set_cc_op(s->cc_op);
6243 tcg_gen_helper_0_0(helper_das);
6244 s->cc_op = CC_OP_EFLAGS;
6245 break;
6246 case 0x37: /* aaa */
6247 if (CODE64(s))
6248 goto illegal_op;
6249 if (s->cc_op != CC_OP_DYNAMIC)
6250 gen_op_set_cc_op(s->cc_op);
6251 tcg_gen_helper_0_0(helper_aaa);
6252 s->cc_op = CC_OP_EFLAGS;
6253 break;
6254 case 0x3f: /* aas */
6255 if (CODE64(s))
6256 goto illegal_op;
6257 if (s->cc_op != CC_OP_DYNAMIC)
6258 gen_op_set_cc_op(s->cc_op);
6259 tcg_gen_helper_0_0(helper_aas);
6260 s->cc_op = CC_OP_EFLAGS;
6261 break;
6262 case 0xd4: /* aam */
6263 if (CODE64(s))
6264 goto illegal_op;
6265 val = ldub_code(s->pc++);
6266 if (val == 0) {
6267 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6268 } else {
6269 tcg_gen_helper_0_1(helper_aam, tcg_const_i32(val));
6270 s->cc_op = CC_OP_LOGICB;
6271 }
6272 break;
6273 case 0xd5: /* aad */
6274 if (CODE64(s))
6275 goto illegal_op;
6276 val = ldub_code(s->pc++);
6277 tcg_gen_helper_0_1(helper_aad, tcg_const_i32(val));
6278 s->cc_op = CC_OP_LOGICB;
6279 break;
6280 /************************/
6281 /* misc */
6282 case 0x90: /* nop */
6283 /* XXX: xchg + rex handling */
6284 /* XXX: correct lock test for all insn */
6285 if (prefixes & PREFIX_LOCK)
6286 goto illegal_op;
6287 if (prefixes & PREFIX_REPZ) {
6288 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6289 }
6290 break;
6291 case 0x9b: /* fwait */
6292 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6293 (HF_MP_MASK | HF_TS_MASK)) {
6294 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6295 } else {
6296 if (s->cc_op != CC_OP_DYNAMIC)
6297 gen_op_set_cc_op(s->cc_op);
6298 gen_jmp_im(pc_start - s->cs_base);
6299 tcg_gen_helper_0_0(helper_fwait);
6300 }
6301 break;
6302 case 0xcc: /* int3 */
6303 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6304 break;
6305 case 0xcd: /* int N */
6306 val = ldub_code(s->pc++);
6307 if (s->vm86 && s->iopl != 3) {
6308 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6309 } else {
6310 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6311 }
6312 break;
6313 case 0xce: /* into */
6314 if (CODE64(s))
6315 goto illegal_op;
6316 if (s->cc_op != CC_OP_DYNAMIC)
6317 gen_op_set_cc_op(s->cc_op);
6318 gen_jmp_im(pc_start - s->cs_base);
6319 tcg_gen_helper_0_1(helper_into, tcg_const_i32(s->pc - pc_start));
6320 break;
6321 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6322 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6323 #if 1
6324 gen_debug(s, pc_start - s->cs_base);
6325 #else
6326 /* start debug */
6327 tb_flush(cpu_single_env);
6328 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6329 #endif
6330 break;
6331 case 0xfa: /* cli */
6332 if (!s->vm86) {
6333 if (s->cpl <= s->iopl) {
6334 tcg_gen_helper_0_0(helper_cli);
6335 } else {
6336 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6337 }
6338 } else {
6339 if (s->iopl == 3) {
6340 tcg_gen_helper_0_0(helper_cli);
6341 } else {
6342 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6343 }
6344 }
6345 break;
6346 case 0xfb: /* sti */
6347 if (!s->vm86) {
6348 if (s->cpl <= s->iopl) {
6349 gen_sti:
6350 tcg_gen_helper_0_0(helper_sti);
6351 /* interruptions are enabled only the first insn after sti */
6352 /* If several instructions disable interrupts, only the
6353 _first_ does it */
6354 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6355 tcg_gen_helper_0_0(helper_set_inhibit_irq);
6356 /* give a chance to handle pending irqs */
6357 gen_jmp_im(s->pc - s->cs_base);
6358 gen_eob(s);
6359 } else {
6360 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6361 }
6362 } else {
6363 if (s->iopl == 3) {
6364 goto gen_sti;
6365 } else {
6366 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6367 }
6368 }
6369 break;
6370 case 0x62: /* bound */
6371 if (CODE64(s))
6372 goto illegal_op;
6373 ot = dflag ? OT_LONG : OT_WORD;
6374 modrm = ldub_code(s->pc++);
6375 reg = (modrm >> 3) & 7;
6376 mod = (modrm >> 6) & 3;
6377 if (mod == 3)
6378 goto illegal_op;
6379 gen_op_mov_TN_reg(ot, 0, reg);
6380 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6381 gen_jmp_im(pc_start - s->cs_base);
6382 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6383 if (ot == OT_WORD)
6384 tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32);
6385 else
6386 tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32);
6387 break;
6388 case 0x1c8 ... 0x1cf: /* bswap reg */
6389 reg = (b & 7) | REX_B(s);
6390 #ifdef TARGET_X86_64
6391 if (dflag == 2) {
6392 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6393 tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]);
6394 gen_op_mov_reg_T0(OT_QUAD, reg);
6395 } else
6396 {
6397 TCGv tmp0;
6398 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6399
6400 tmp0 = tcg_temp_new(TCG_TYPE_I32);
6401 tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]);
6402 tcg_gen_bswap_i32(tmp0, tmp0);
6403 tcg_gen_extu_i32_i64(cpu_T[0], tmp0);
6404 gen_op_mov_reg_T0(OT_LONG, reg);
6405 }
6406 #else
6407 {
6408 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6409 tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]);
6410 gen_op_mov_reg_T0(OT_LONG, reg);
6411 }
6412 #endif
6413 break;
6414 case 0xd6: /* salc */
6415 if (CODE64(s))
6416 goto illegal_op;
6417 if (s->cc_op != CC_OP_DYNAMIC)
6418 gen_op_set_cc_op(s->cc_op);
6419 gen_compute_eflags_c(cpu_T[0]);
6420 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6421 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6422 break;
6423 case 0xe0: /* loopnz */
6424 case 0xe1: /* loopz */
6425 case 0xe2: /* loop */
6426 case 0xe3: /* jecxz */
6427 {
6428 int l1, l2, l3;
6429
6430 tval = (int8_t)insn_get(s, OT_BYTE);
6431 next_eip = s->pc - s->cs_base;
6432 tval += next_eip;
6433 if (s->dflag == 0)
6434 tval &= 0xffff;
6435
6436 l1 = gen_new_label();
6437 l2 = gen_new_label();
6438 l3 = gen_new_label();
6439 b &= 3;
6440 switch(b) {
6441 case 0: /* loopnz */
6442 case 1: /* loopz */
6443 if (s->cc_op != CC_OP_DYNAMIC)
6444 gen_op_set_cc_op(s->cc_op);
6445 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6446 gen_op_jz_ecx(s->aflag, l3);
6447 gen_compute_eflags(cpu_tmp0);
6448 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6449 if (b == 0) {
6450 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6451 } else {
6452 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6453 }
6454 break;
6455 case 2: /* loop */
6456 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6457 gen_op_jnz_ecx(s->aflag, l1);
6458 break;
6459 default:
6460 case 3: /* jcxz */
6461 gen_op_jz_ecx(s->aflag, l1);
6462 break;
6463 }
6464
6465 gen_set_label(l3);
6466 gen_jmp_im(next_eip);
6467 tcg_gen_br(l2);
6468
6469 gen_set_label(l1);
6470 gen_jmp_im(tval);
6471 gen_set_label(l2);
6472 gen_eob(s);
6473 }
6474 break;
6475 case 0x130: /* wrmsr */
6476 case 0x132: /* rdmsr */
6477 if (s->cpl != 0) {
6478 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6479 } else {
6480 if (s->cc_op != CC_OP_DYNAMIC)
6481 gen_op_set_cc_op(s->cc_op);
6482 gen_jmp_im(pc_start - s->cs_base);
6483 if (b & 2) {
6484 tcg_gen_helper_0_0(helper_rdmsr);
6485 } else {
6486 tcg_gen_helper_0_0(helper_wrmsr);
6487 }
6488 }
6489 break;
6490 case 0x131: /* rdtsc */
6491 if (s->cc_op != CC_OP_DYNAMIC)
6492 gen_op_set_cc_op(s->cc_op);
6493 gen_jmp_im(pc_start - s->cs_base);
6494 if (use_icount)
6495 gen_io_start();
6496 tcg_gen_helper_0_0(helper_rdtsc);
6497 if (use_icount) {
6498 gen_io_end();
6499 gen_jmp(s, s->pc - s->cs_base);
6500 }
6501 break;
6502 case 0x133: /* rdpmc */
6503 if (s->cc_op != CC_OP_DYNAMIC)
6504 gen_op_set_cc_op(s->cc_op);
6505 gen_jmp_im(pc_start - s->cs_base);
6506 tcg_gen_helper_0_0(helper_rdpmc);
6507 break;
6508 case 0x134: /* sysenter */
6509 /* For Intel SYSENTER is valid on 64-bit */
6510 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6511 goto illegal_op;
6512 if (!s->pe) {
6513 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6514 } else {
6515 if (s->cc_op != CC_OP_DYNAMIC) {
6516 gen_op_set_cc_op(s->cc_op);
6517 s->cc_op = CC_OP_DYNAMIC;
6518 }
6519 gen_jmp_im(pc_start - s->cs_base);
6520 tcg_gen_helper_0_0(helper_sysenter);
6521 gen_eob(s);
6522 }
6523 break;
6524 case 0x135: /* sysexit */
6525 /* For Intel SYSEXIT is valid on 64-bit */
6526 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6527 goto illegal_op;
6528 if (!s->pe) {
6529 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6530 } else {
6531 if (s->cc_op != CC_OP_DYNAMIC) {
6532 gen_op_set_cc_op(s->cc_op);
6533 s->cc_op = CC_OP_DYNAMIC;
6534 }
6535 gen_jmp_im(pc_start - s->cs_base);
6536 tcg_gen_helper_0_1(helper_sysexit, tcg_const_i32(dflag));
6537 gen_eob(s);
6538 }
6539 break;
6540 #ifdef TARGET_X86_64
6541 case 0x105: /* syscall */
6542 /* XXX: is it usable in real mode ? */
6543 if (s->cc_op != CC_OP_DYNAMIC) {
6544 gen_op_set_cc_op(s->cc_op);
6545 s->cc_op = CC_OP_DYNAMIC;
6546 }
6547 gen_jmp_im(pc_start - s->cs_base);
6548 tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start));
6549 gen_eob(s);
6550 break;
6551 case 0x107: /* sysret */
6552 if (!s->pe) {
6553 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6554 } else {
6555 if (s->cc_op != CC_OP_DYNAMIC) {
6556 gen_op_set_cc_op(s->cc_op);
6557 s->cc_op = CC_OP_DYNAMIC;
6558 }
6559 gen_jmp_im(pc_start - s->cs_base);
6560 tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag));
6561 /* condition codes are modified only in long mode */
6562 if (s->lma)
6563 s->cc_op = CC_OP_EFLAGS;
6564 gen_eob(s);
6565 }
6566 break;
6567 #endif
6568 case 0x1a2: /* cpuid */
6569 if (s->cc_op != CC_OP_DYNAMIC)
6570 gen_op_set_cc_op(s->cc_op);
6571 gen_jmp_im(pc_start - s->cs_base);
6572 tcg_gen_helper_0_0(helper_cpuid);
6573 break;
6574 case 0xf4: /* hlt */
6575 if (s->cpl != 0) {
6576 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6577 } else {
6578 if (s->cc_op != CC_OP_DYNAMIC)
6579 gen_op_set_cc_op(s->cc_op);
6580 gen_jmp_im(pc_start - s->cs_base);
6581 tcg_gen_helper_0_1(helper_hlt, tcg_const_i32(s->pc - pc_start));
6582 s->is_jmp = 3;
6583 }
6584 break;
6585 case 0x100:
6586 modrm = ldub_code(s->pc++);
6587 mod = (modrm >> 6) & 3;
6588 op = (modrm >> 3) & 7;
6589 switch(op) {
6590 case 0: /* sldt */
6591 if (!s->pe || s->vm86)
6592 goto illegal_op;
6593 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
6594 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6595 ot = OT_WORD;
6596 if (mod == 3)
6597 ot += s->dflag;
6598 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6599 break;
6600 case 2: /* lldt */
6601 if (!s->pe || s->vm86)
6602 goto illegal_op;
6603 if (s->cpl != 0) {
6604 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6605 } else {
6606 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
6607 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6608 gen_jmp_im(pc_start - s->cs_base);
6609 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6610 tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32);
6611 }
6612 break;
6613 case 1: /* str */
6614 if (!s->pe || s->vm86)
6615 goto illegal_op;
6616 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
6617 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6618 ot = OT_WORD;
6619 if (mod == 3)
6620 ot += s->dflag;
6621 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6622 break;
6623 case 3: /* ltr */
6624 if (!s->pe || s->vm86)
6625 goto illegal_op;
6626 if (s->cpl != 0) {
6627 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6628 } else {
6629 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
6630 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6631 gen_jmp_im(pc_start - s->cs_base);
6632 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6633 tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32);
6634 }
6635 break;
6636 case 4: /* verr */
6637 case 5: /* verw */
6638 if (!s->pe || s->vm86)
6639 goto illegal_op;
6640 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6641 if (s->cc_op != CC_OP_DYNAMIC)
6642 gen_op_set_cc_op(s->cc_op);
6643 if (op == 4)
6644 tcg_gen_helper_0_1(helper_verr, cpu_T[0]);
6645 else
6646 tcg_gen_helper_0_1(helper_verw, cpu_T[0]);
6647 s->cc_op = CC_OP_EFLAGS;
6648 break;
6649 default:
6650 goto illegal_op;
6651 }
6652 break;
6653 case 0x101:
6654 modrm = ldub_code(s->pc++);
6655 mod = (modrm >> 6) & 3;
6656 op = (modrm >> 3) & 7;
6657 rm = modrm & 7;
6658 switch(op) {
6659 case 0: /* sgdt */
6660 if (mod == 3)
6661 goto illegal_op;
6662 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
6663 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6664 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
6665 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6666 gen_add_A0_im(s, 2);
6667 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
6668 if (!s->dflag)
6669 gen_op_andl_T0_im(0xffffff);
6670 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6671 break;
6672 case 1:
6673 if (mod == 3) {
6674 switch (rm) {
6675 case 0: /* monitor */
6676 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6677 s->cpl != 0)
6678 goto illegal_op;
6679 if (s->cc_op != CC_OP_DYNAMIC)
6680 gen_op_set_cc_op(s->cc_op);
6681 gen_jmp_im(pc_start - s->cs_base);
6682 #ifdef TARGET_X86_64
6683 if (s->aflag == 2) {
6684 gen_op_movq_A0_reg(R_EAX);
6685 } else
6686 #endif
6687 {
6688 gen_op_movl_A0_reg(R_EAX);
6689 if (s->aflag == 0)
6690 gen_op_andl_A0_ffff();
6691 }
6692 gen_add_A0_ds_seg(s);
6693 tcg_gen_helper_0_1(helper_monitor, cpu_A0);
6694 break;
6695 case 1: /* mwait */
6696 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6697 s->cpl != 0)
6698 goto illegal_op;
6699 if (s->cc_op != CC_OP_DYNAMIC) {
6700 gen_op_set_cc_op(s->cc_op);
6701 s->cc_op = CC_OP_DYNAMIC;
6702 }
6703 gen_jmp_im(pc_start - s->cs_base);
6704 tcg_gen_helper_0_1(helper_mwait, tcg_const_i32(s->pc - pc_start));
6705 gen_eob(s);
6706 break;
6707 default:
6708 goto illegal_op;
6709 }
6710 } else { /* sidt */
6711 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
6712 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6713 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
6714 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6715 gen_add_A0_im(s, 2);
6716 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
6717 if (!s->dflag)
6718 gen_op_andl_T0_im(0xffffff);
6719 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6720 }
6721 break;
6722 case 2: /* lgdt */
6723 case 3: /* lidt */
6724 if (mod == 3) {
6725 if (s->cc_op != CC_OP_DYNAMIC)
6726 gen_op_set_cc_op(s->cc_op);
6727 gen_jmp_im(pc_start - s->cs_base);
6728 switch(rm) {
6729 case 0: /* VMRUN */
6730 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6731 goto illegal_op;
6732 if (s->cpl != 0) {
6733 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6734 break;
6735 } else {
6736 tcg_gen_helper_0_2(helper_vmrun,
6737 tcg_const_i32(s->aflag),
6738 tcg_const_i32(s->pc - pc_start));
6739 tcg_gen_exit_tb(0);
6740 s->is_jmp = 3;
6741 }
6742 break;
6743 case 1: /* VMMCALL */
6744 if (!(s->flags & HF_SVME_MASK))
6745 goto illegal_op;
6746 tcg_gen_helper_0_0(helper_vmmcall);
6747 break;
6748 case 2: /* VMLOAD */
6749 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6750 goto illegal_op;
6751 if (s->cpl != 0) {
6752 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6753 break;
6754 } else {
6755 tcg_gen_helper_0_1(helper_vmload,
6756 tcg_const_i32(s->aflag));
6757 }
6758 break;
6759 case 3: /* VMSAVE */
6760 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6761 goto illegal_op;
6762 if (s->cpl != 0) {
6763 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6764 break;
6765 } else {
6766 tcg_gen_helper_0_1(helper_vmsave,
6767 tcg_const_i32(s->aflag));
6768 }
6769 break;
6770 case 4: /* STGI */
6771 if ((!(s->flags & HF_SVME_MASK) &&
6772 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
6773 !s->pe)
6774 goto illegal_op;
6775 if (s->cpl != 0) {
6776 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6777 break;
6778 } else {
6779 tcg_gen_helper_0_0(helper_stgi);
6780 }
6781 break;
6782 case 5: /* CLGI */
6783 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6784 goto illegal_op;
6785 if (s->cpl != 0) {
6786 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6787 break;
6788 } else {
6789 tcg_gen_helper_0_0(helper_clgi);
6790 }
6791 break;
6792 case 6: /* SKINIT */
6793 if ((!(s->flags & HF_SVME_MASK) &&
6794 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
6795 !s->pe)
6796 goto illegal_op;
6797 tcg_gen_helper_0_0(helper_skinit);
6798 break;
6799 case 7: /* INVLPGA */
6800 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6801 goto illegal_op;
6802 if (s->cpl != 0) {
6803 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6804 break;
6805 } else {
6806 tcg_gen_helper_0_1(helper_invlpga,
6807 tcg_const_i32(s->aflag));
6808 }
6809 break;
6810 default:
6811 goto illegal_op;
6812 }
6813 } else if (s->cpl != 0) {
6814 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6815 } else {
6816 gen_svm_check_intercept(s, pc_start,
6817 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
6818 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6819 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
6820 gen_add_A0_im(s, 2);
6821 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6822 if (!s->dflag)
6823 gen_op_andl_T0_im(0xffffff);
6824 if (op == 2) {
6825 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
6826 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
6827 } else {
6828 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
6829 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
6830 }
6831 }
6832 break;
6833 case 4: /* smsw */
6834 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
6835 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
6836 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
6837 break;
6838 case 6: /* lmsw */
6839 if (s->cpl != 0) {
6840 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6841 } else {
6842 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
6843 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6844 tcg_gen_helper_0_1(helper_lmsw, cpu_T[0]);
6845 gen_jmp_im(s->pc - s->cs_base);
6846 gen_eob(s);
6847 }
6848 break;
6849 case 7: /* invlpg */
6850 if (s->cpl != 0) {
6851 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6852 } else {
6853 if (mod == 3) {
6854 #ifdef TARGET_X86_64
6855 if (CODE64(s) && rm == 0) {
6856 /* swapgs */
6857 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
6858 tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
6859 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
6860 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
6861 } else
6862 #endif
6863 {
6864 goto illegal_op;
6865 }
6866 } else {
6867 if (s->cc_op != CC_OP_DYNAMIC)
6868 gen_op_set_cc_op(s->cc_op);
6869 gen_jmp_im(pc_start - s->cs_base);
6870 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6871 tcg_gen_helper_0_1(helper_invlpg, cpu_A0);
6872 gen_jmp_im(s->pc - s->cs_base);
6873 gen_eob(s);
6874 }
6875 }
6876 break;
6877 default:
6878 goto illegal_op;
6879 }
6880 break;
6881 case 0x108: /* invd */
6882 case 0x109: /* wbinvd */
6883 if (s->cpl != 0) {
6884 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6885 } else {
6886 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
6887 /* nothing to do */
6888 }
6889 break;
6890 case 0x63: /* arpl or movslS (x86_64) */
6891 #ifdef TARGET_X86_64
6892 if (CODE64(s)) {
6893 int d_ot;
6894 /* d_ot is the size of destination */
6895 d_ot = dflag + OT_WORD;
6896
6897 modrm = ldub_code(s->pc++);
6898 reg = ((modrm >> 3) & 7) | rex_r;
6899 mod = (modrm >> 6) & 3;
6900 rm = (modrm & 7) | REX_B(s);
6901
6902 if (mod == 3) {
6903 gen_op_mov_TN_reg(OT_LONG, 0, rm);
6904 /* sign extend */
6905 if (d_ot == OT_QUAD)
6906 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
6907 gen_op_mov_reg_T0(d_ot, reg);
6908 } else {
6909 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6910 if (d_ot == OT_QUAD) {
6911 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
6912 } else {
6913 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
6914 }
6915 gen_op_mov_reg_T0(d_ot, reg);
6916 }
6917 } else
6918 #endif
6919 {
6920 int label1;
6921 TCGv t0, t1, t2;
6922
6923 if (!s->pe || s->vm86)
6924 goto illegal_op;
6925 t0 = tcg_temp_local_new(TCG_TYPE_TL);
6926 t1 = tcg_temp_local_new(TCG_TYPE_TL);
6927 t2 = tcg_temp_local_new(TCG_TYPE_TL);
6928 ot = OT_WORD;
6929 modrm = ldub_code(s->pc++);
6930 reg = (modrm >> 3) & 7;
6931 mod = (modrm >> 6) & 3;
6932 rm = modrm & 7;
6933 if (mod != 3) {
6934 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6935 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6936 } else {
6937 gen_op_mov_v_reg(ot, t0, rm);
6938 }
6939 gen_op_mov_v_reg(ot, t1, reg);
6940 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
6941 tcg_gen_andi_tl(t1, t1, 3);
6942 tcg_gen_movi_tl(t2, 0);
6943 label1 = gen_new_label();
6944 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
6945 tcg_gen_andi_tl(t0, t0, ~3);
6946 tcg_gen_or_tl(t0, t0, t1);
6947 tcg_gen_movi_tl(t2, CC_Z);
6948 gen_set_label(label1);
6949 if (mod != 3) {
6950 gen_op_st_v(ot + s->mem_index, t0, cpu_A0);
6951 } else {
6952 gen_op_mov_reg_v(ot, rm, t0);
6953 }
6954 if (s->cc_op != CC_OP_DYNAMIC)
6955 gen_op_set_cc_op(s->cc_op);
6956 gen_compute_eflags(cpu_cc_src);
6957 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
6958 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
6959 s->cc_op = CC_OP_EFLAGS;
6960 tcg_temp_free(t0);
6961 tcg_temp_free(t1);
6962 tcg_temp_free(t2);
6963 }
6964 break;
6965 case 0x102: /* lar */
6966 case 0x103: /* lsl */
6967 {
6968 int label1;
6969 TCGv t0;
6970 if (!s->pe || s->vm86)
6971 goto illegal_op;
6972 ot = dflag ? OT_LONG : OT_WORD;
6973 modrm = ldub_code(s->pc++);
6974 reg = ((modrm >> 3) & 7) | rex_r;
6975 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6976 t0 = tcg_temp_local_new(TCG_TYPE_TL);
6977 if (s->cc_op != CC_OP_DYNAMIC)
6978 gen_op_set_cc_op(s->cc_op);
6979 if (b == 0x102)
6980 tcg_gen_helper_1_1(helper_lar, t0, cpu_T[0]);
6981 else
6982 tcg_gen_helper_1_1(helper_lsl, t0, cpu_T[0]);
6983 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
6984 label1 = gen_new_label();
6985 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
6986 gen_op_mov_reg_v(ot, reg, t0);
6987 gen_set_label(label1);
6988 s->cc_op = CC_OP_EFLAGS;
6989 tcg_temp_free(t0);
6990 }
6991 break;
6992 case 0x118:
6993 modrm = ldub_code(s->pc++);
6994 mod = (modrm >> 6) & 3;
6995 op = (modrm >> 3) & 7;
6996 switch(op) {
6997 case 0: /* prefetchnta */
6998 case 1: /* prefetchnt0 */
6999 case 2: /* prefetchnt0 */
7000 case 3: /* prefetchnt0 */
7001 if (mod == 3)
7002 goto illegal_op;
7003 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7004 /* nothing more to do */
7005 break;
7006 default: /* nop (multi byte) */
7007 gen_nop_modrm(s, modrm);
7008 break;
7009 }
7010 break;
7011 case 0x119 ... 0x11f: /* nop (multi byte) */
7012 modrm = ldub_code(s->pc++);
7013 gen_nop_modrm(s, modrm);
7014 break;
7015 case 0x120: /* mov reg, crN */
7016 case 0x122: /* mov crN, reg */
7017 if (s->cpl != 0) {
7018 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7019 } else {
7020 modrm = ldub_code(s->pc++);
7021 if ((modrm & 0xc0) != 0xc0)
7022 goto illegal_op;
7023 rm = (modrm & 7) | REX_B(s);
7024 reg = ((modrm >> 3) & 7) | rex_r;
7025 if (CODE64(s))
7026 ot = OT_QUAD;
7027 else
7028 ot = OT_LONG;
7029 switch(reg) {
7030 case 0:
7031 case 2:
7032 case 3:
7033 case 4:
7034 case 8:
7035 if (s->cc_op != CC_OP_DYNAMIC)
7036 gen_op_set_cc_op(s->cc_op);
7037 gen_jmp_im(pc_start - s->cs_base);
7038 if (b & 2) {
7039 gen_op_mov_TN_reg(ot, 0, rm);
7040 tcg_gen_helper_0_2(helper_write_crN,
7041 tcg_const_i32(reg), cpu_T[0]);
7042 gen_jmp_im(s->pc - s->cs_base);
7043 gen_eob(s);
7044 } else {
7045 tcg_gen_helper_1_1(helper_read_crN,
7046 cpu_T[0], tcg_const_i32(reg));
7047 gen_op_mov_reg_T0(ot, rm);
7048 }
7049 break;
7050 default:
7051 goto illegal_op;
7052 }
7053 }
7054 break;
7055 case 0x121: /* mov reg, drN */
7056 case 0x123: /* mov drN, reg */
7057 if (s->cpl != 0) {
7058 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7059 } else {
7060 modrm = ldub_code(s->pc++);
7061 if ((modrm & 0xc0) != 0xc0)
7062 goto illegal_op;
7063 rm = (modrm & 7) | REX_B(s);
7064 reg = ((modrm >> 3) & 7) | rex_r;
7065 if (CODE64(s))
7066 ot = OT_QUAD;
7067 else
7068 ot = OT_LONG;
7069 /* XXX: do it dynamically with CR4.DE bit */
7070 if (reg == 4 || reg == 5 || reg >= 8)
7071 goto illegal_op;
7072 if (b & 2) {
7073 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7074 gen_op_mov_TN_reg(ot, 0, rm);
7075 tcg_gen_helper_0_2(helper_movl_drN_T0,
7076 tcg_const_i32(reg), cpu_T[0]);
7077 gen_jmp_im(s->pc - s->cs_base);
7078 gen_eob(s);
7079 } else {
7080 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7081 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7082 gen_op_mov_reg_T0(ot, rm);
7083 }
7084 }
7085 break;
7086 case 0x106: /* clts */
7087 if (s->cpl != 0) {
7088 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7089 } else {
7090 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7091 tcg_gen_helper_0_0(helper_clts);
7092 /* abort block because static cpu state changed */
7093 gen_jmp_im(s->pc - s->cs_base);
7094 gen_eob(s);
7095 }
7096 break;
7097 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3 support */
7098 case 0x1c3: /* MOVNTI reg, mem */
7099 if (!(s->cpuid_features & CPUID_SSE2))
7100 goto illegal_op;
7101 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7102 modrm = ldub_code(s->pc++);
7103 mod = (modrm >> 6) & 3;
7104 if (mod == 3)
7105 goto illegal_op;
7106 reg = ((modrm >> 3) & 7) | rex_r;
7107 /* generate a generic store */
7108 gen_ldst_modrm(s, modrm, ot, reg, 1);
7109 break;
7110 case 0x1ae:
7111 modrm = ldub_code(s->pc++);
7112 mod = (modrm >> 6) & 3;
7113 op = (modrm >> 3) & 7;
7114 switch(op) {
7115 case 0: /* fxsave */
7116 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7117 (s->flags & HF_EM_MASK))
7118 goto illegal_op;
7119 if (s->flags & HF_TS_MASK) {
7120 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7121 break;
7122 }
7123 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7124 if (s->cc_op != CC_OP_DYNAMIC)
7125 gen_op_set_cc_op(s->cc_op);
7126 gen_jmp_im(pc_start - s->cs_base);
7127 tcg_gen_helper_0_2(helper_fxsave,
7128 cpu_A0, tcg_const_i32((s->dflag == 2)));
7129 break;
7130 case 1: /* fxrstor */
7131 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7132 (s->flags & HF_EM_MASK))
7133 goto illegal_op;
7134 if (s->flags & HF_TS_MASK) {
7135 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7136 break;
7137 }
7138 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7139 if (s->cc_op != CC_OP_DYNAMIC)
7140 gen_op_set_cc_op(s->cc_op);
7141 gen_jmp_im(pc_start - s->cs_base);
7142 tcg_gen_helper_0_2(helper_fxrstor,
7143 cpu_A0, tcg_const_i32((s->dflag == 2)));
7144 break;
7145 case 2: /* ldmxcsr */
7146 case 3: /* stmxcsr */
7147 if (s->flags & HF_TS_MASK) {
7148 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7149 break;
7150 }
7151 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7152 mod == 3)
7153 goto illegal_op;
7154 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7155 if (op == 2) {
7156 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7157 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7158 } else {
7159 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7160 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7161 }
7162 break;
7163 case 5: /* lfence */
7164 case 6: /* mfence */
7165 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
7166 goto illegal_op;
7167 break;
7168 case 7: /* sfence / clflush */
7169 if ((modrm & 0xc7) == 0xc0) {
7170 /* sfence */
7171 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7172 if (!(s->cpuid_features & CPUID_SSE))
7173 goto illegal_op;
7174 } else {
7175 /* clflush */
7176 if (!(s->cpuid_features & CPUID_CLFLUSH))
7177 goto illegal_op;
7178 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7179 }
7180 break;
7181 default:
7182 goto illegal_op;
7183 }
7184 break;
7185 case 0x10d: /* 3DNow! prefetch(w) */
7186 modrm = ldub_code(s->pc++);
7187 mod = (modrm >> 6) & 3;
7188 if (mod == 3)
7189 goto illegal_op;
7190 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7191 /* ignore for now */
7192 break;
7193 case 0x1aa: /* rsm */
7194 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7195 if (!(s->flags & HF_SMM_MASK))
7196 goto illegal_op;
7197 if (s->cc_op != CC_OP_DYNAMIC) {
7198 gen_op_set_cc_op(s->cc_op);
7199 s->cc_op = CC_OP_DYNAMIC;
7200 }
7201 gen_jmp_im(s->pc - s->cs_base);
7202 tcg_gen_helper_0_0(helper_rsm);
7203 gen_eob(s);
7204 break;
7205 case 0x10e ... 0x10f:
7206 /* 3DNow! instructions, ignore prefixes */
7207 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7208 case 0x110 ... 0x117:
7209 case 0x128 ... 0x12f:
7210 case 0x138 ... 0x13a:
7211 case 0x150 ... 0x177:
7212 case 0x17c ... 0x17f:
7213 case 0x1c2:
7214 case 0x1c4 ... 0x1c6:
7215 case 0x1d0 ... 0x1fe:
7216 gen_sse(s, b, pc_start, rex_r);
7217 break;
7218 default:
7219 goto illegal_op;
7220 }
7221 /* lock generation */
7222 if (s->prefix & PREFIX_LOCK)
7223 tcg_gen_helper_0_0(helper_unlock);
7224 return s->pc;
7225 illegal_op:
7226 if (s->prefix & PREFIX_LOCK)
7227 tcg_gen_helper_0_0(helper_unlock);
7228 /* XXX: ensure that no lock was generated */
7229 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7230 return s->pc;
7231 }
7232
7233 void optimize_flags_init(void)
7234 {
7235 #if TCG_TARGET_REG_BITS == 32
7236 assert(sizeof(CCTable) == (1 << 3));
7237 #else
7238 assert(sizeof(CCTable) == (1 << 4));
7239 #endif
7240 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
7241 cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32,
7242 TCG_AREG0, offsetof(CPUState, cc_op), "cc_op");
7243 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
7244 TCG_AREG0, offsetof(CPUState, cc_src), "cc_src");
7245 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
7246 TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst");
7247 cpu_cc_tmp = tcg_global_mem_new(TCG_TYPE_TL,
7248 TCG_AREG0, offsetof(CPUState, cc_tmp), "cc_tmp");
7249
7250 /* register helpers */
7251
7252 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
7253 #include "helper.h"
7254 }
7255
7256 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7257 basic block 'tb'. If search_pc is TRUE, also generate PC
7258 information for each intermediate instruction. */
7259 static inline void gen_intermediate_code_internal(CPUState *env,
7260 TranslationBlock *tb,
7261 int search_pc)
7262 {
7263 DisasContext dc1, *dc = &dc1;
7264 target_ulong pc_ptr;
7265 uint16_t *gen_opc_end;
7266 int j, lj, cflags;
7267 uint64_t flags;
7268 target_ulong pc_start;
7269 target_ulong cs_base;
7270 int num_insns;
7271 int max_insns;
7272
7273 /* generate intermediate code */
7274 pc_start = tb->pc;
7275 cs_base = tb->cs_base;
7276 flags = tb->flags;
7277 cflags = tb->cflags;
7278
7279 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7280 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7281 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7282 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7283 dc->f_st = 0;
7284 dc->vm86 = (flags >> VM_SHIFT) & 1;
7285 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7286 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7287 dc->tf = (flags >> TF_SHIFT) & 1;
7288 dc->singlestep_enabled = env->singlestep_enabled;
7289 dc->cc_op = CC_OP_DYNAMIC;
7290 dc->cs_base = cs_base;
7291 dc->tb = tb;
7292 dc->popl_esp_hack = 0;
7293 /* select memory access functions */
7294 dc->mem_index = 0;
7295 if (flags & HF_SOFTMMU_MASK) {
7296 if (dc->cpl == 3)
7297 dc->mem_index = 2 * 4;
7298 else
7299 dc->mem_index = 1 * 4;
7300 }
7301 dc->cpuid_features = env->cpuid_features;
7302 dc->cpuid_ext_features = env->cpuid_ext_features;
7303 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7304 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7305 #ifdef TARGET_X86_64
7306 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7307 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7308 #endif
7309 dc->flags = flags;
7310 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7311 (flags & HF_INHIBIT_IRQ_MASK)
7312 #ifndef CONFIG_SOFTMMU
7313 || (flags & HF_SOFTMMU_MASK)
7314 #endif
7315 );
7316 #if 0
7317 /* check addseg logic */
7318 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7319 printf("ERROR addseg\n");
7320 #endif
7321
7322 cpu_T[0] = tcg_temp_new(TCG_TYPE_TL);
7323 cpu_T[1] = tcg_temp_new(TCG_TYPE_TL);
7324 cpu_A0 = tcg_temp_new(TCG_TYPE_TL);
7325 cpu_T3 = tcg_temp_new(TCG_TYPE_TL);
7326
7327 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
7328 cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64);
7329 cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32);
7330 cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32);
7331 cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL);
7332 cpu_tmp5 = tcg_temp_new(TCG_TYPE_TL);
7333 cpu_tmp6 = tcg_temp_new(TCG_TYPE_TL);
7334 cpu_ptr0 = tcg_temp_new(TCG_TYPE_PTR);
7335 cpu_ptr1 = tcg_temp_new(TCG_TYPE_PTR);
7336
7337 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7338
7339 dc->is_jmp = DISAS_NEXT;
7340 pc_ptr = pc_start;
7341 lj = -1;
7342 num_insns = 0;
7343 max_insns = tb->cflags & CF_COUNT_MASK;
7344 if (max_insns == 0)
7345 max_insns = CF_COUNT_MASK;
7346
7347 gen_icount_start();
7348 for(;;) {
7349 if (env->nb_breakpoints > 0) {
7350 for(j = 0; j < env->nb_breakpoints; j++) {
7351 if (env->breakpoints[j] == pc_ptr) {
7352 gen_debug(dc, pc_ptr - dc->cs_base);
7353 break;
7354 }
7355 }
7356 }
7357 if (search_pc) {
7358 j = gen_opc_ptr - gen_opc_buf;
7359 if (lj < j) {
7360 lj++;
7361 while (lj < j)
7362 gen_opc_instr_start[lj++] = 0;
7363 }
7364 gen_opc_pc[lj] = pc_ptr;
7365 gen_opc_cc_op[lj] = dc->cc_op;
7366 gen_opc_instr_start[lj] = 1;
7367 gen_opc_icount[lj] = num_insns;
7368 }
7369 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7370 gen_io_start();
7371
7372 pc_ptr = disas_insn(dc, pc_ptr);
7373 num_insns++;
7374 /* stop translation if indicated */
7375 if (dc->is_jmp)
7376 break;
7377 /* if single step mode, we generate only one instruction and
7378 generate an exception */
7379 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7380 the flag and abort the translation to give the irqs a
7381 change to be happen */
7382 if (dc->tf || dc->singlestep_enabled ||
7383 (flags & HF_INHIBIT_IRQ_MASK)) {
7384 gen_jmp_im(pc_ptr - dc->cs_base);
7385 gen_eob(dc);
7386 break;
7387 }
7388 /* if too long translation, stop generation too */
7389 if (gen_opc_ptr >= gen_opc_end ||
7390 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7391 num_insns >= max_insns) {
7392 gen_jmp_im(pc_ptr - dc->cs_base);
7393 gen_eob(dc);
7394 break;
7395 }
7396 }
7397 if (tb->cflags & CF_LAST_IO)
7398 gen_io_end();
7399 gen_icount_end(tb, num_insns);
7400 *gen_opc_ptr = INDEX_op_end;
7401 /* we don't forget to fill the last values */
7402 if (search_pc) {
7403 j = gen_opc_ptr - gen_opc_buf;
7404 lj++;
7405 while (lj <= j)
7406 gen_opc_instr_start[lj++] = 0;
7407 }
7408
7409 #ifdef DEBUG_DISAS
7410 if (loglevel & CPU_LOG_TB_CPU) {
7411 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
7412 }
7413 if (loglevel & CPU_LOG_TB_IN_ASM) {
7414 int disas_flags;
7415 fprintf(logfile, "----------------\n");
7416 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7417 #ifdef TARGET_X86_64
7418 if (dc->code64)
7419 disas_flags = 2;
7420 else
7421 #endif
7422 disas_flags = !dc->code32;
7423 target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
7424 fprintf(logfile, "\n");
7425 }
7426 #endif
7427
7428 if (!search_pc) {
7429 tb->size = pc_ptr - pc_start;
7430 tb->icount = num_insns;
7431 }
7432 }
7433
7434 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7435 {
7436 gen_intermediate_code_internal(env, tb, 0);
7437 }
7438
7439 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7440 {
7441 gen_intermediate_code_internal(env, tb, 1);
7442 }
7443
7444 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7445 unsigned long searched_pc, int pc_pos, void *puc)
7446 {
7447 int cc_op;
7448 #ifdef DEBUG_DISAS
7449 if (loglevel & CPU_LOG_TB_OP) {
7450 int i;
7451 fprintf(logfile, "RESTORE:\n");
7452 for(i = 0;i <= pc_pos; i++) {
7453 if (gen_opc_instr_start[i]) {
7454 fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7455 }
7456 }
7457 fprintf(logfile, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7458 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7459 (uint32_t)tb->cs_base);
7460 }
7461 #endif
7462 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7463 cc_op = gen_opc_cc_op[pc_pos];
7464 if (cc_op != CC_OP_DYNAMIC)
7465 env->cc_op = cc_op;
7466 }
Samsung s3c2440 and arm920t support for the mini2440 dev board