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Preliminary AIX support
[qemu/mini2440.git] / hw / omap1.c
blob0c3b5cd234ab279ef955b6d62d76a9a1a20423a1
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21 #include "hw.h"
22 #include "arm-misc.h"
23 #include "omap.h"
24 #include "sysemu.h"
25 #include "qemu-timer.h"
26 #include "qemu-char.h"
27 #include "soc_dma.h"
28 /* We use pc-style serial ports. */
29 #include "pc.h"
30
31 /* Should signal the TCMI/GPMC */
32 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
33 {
34 uint8_t ret;
35
36 OMAP_8B_REG(addr);
37 cpu_physical_memory_read(addr, (void *) &ret, 1);
38 return ret;
39 }
40
41 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
42 uint32_t value)
43 {
44 uint8_t val8 = value;
45
46 OMAP_8B_REG(addr);
47 cpu_physical_memory_write(addr, (void *) &val8, 1);
48 }
49
50 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
51 {
52 uint16_t ret;
53
54 OMAP_16B_REG(addr);
55 cpu_physical_memory_read(addr, (void *) &ret, 2);
56 return ret;
57 }
58
59 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
60 uint32_t value)
61 {
62 uint16_t val16 = value;
63
64 OMAP_16B_REG(addr);
65 cpu_physical_memory_write(addr, (void *) &val16, 2);
66 }
67
68 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
69 {
70 uint32_t ret;
71
72 OMAP_32B_REG(addr);
73 cpu_physical_memory_read(addr, (void *) &ret, 4);
74 return ret;
75 }
76
77 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
78 uint32_t value)
79 {
80 OMAP_32B_REG(addr);
81 cpu_physical_memory_write(addr, (void *) &value, 4);
82 }
83
84 /* Interrupt Handlers */
85 struct omap_intr_handler_bank_s {
86 uint32_t irqs;
87 uint32_t inputs;
88 uint32_t mask;
89 uint32_t fiq;
90 uint32_t sens_edge;
91 uint32_t swi;
92 unsigned char priority[32];
93 };
94
95 struct omap_intr_handler_s {
96 qemu_irq *pins;
97 qemu_irq parent_intr[2];
98 target_phys_addr_t base;
99 unsigned char nbanks;
100 int level_only;
101
102 /* state */
103 uint32_t new_agr[2];
104 int sir_intr[2];
105 int autoidle;
106 uint32_t mask;
107 struct omap_intr_handler_bank_s bank[];
108 };
109
110 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
111 {
112 int i, j, sir_intr, p_intr, p, f;
113 uint32_t level;
114 sir_intr = 0;
115 p_intr = 255;
116
117 /* Find the interrupt line with the highest dynamic priority.
118 * Note: 0 denotes the hightest priority.
119 * If all interrupts have the same priority, the default order is IRQ_N,
120 * IRQ_N-1,...,IRQ_0. */
121 for (j = 0; j < s->nbanks; ++j) {
122 level = s->bank[j].irqs & ~s->bank[j].mask &
123 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
124 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
125 level >>= f) {
126 p = s->bank[j].priority[i];
127 if (p <= p_intr) {
128 p_intr = p;
129 sir_intr = 32 * j + i;
130 }
131 f = ffs(level >> 1);
132 }
133 }
134 s->sir_intr[is_fiq] = sir_intr;
135 }
136
137 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
138 {
139 int i;
140 uint32_t has_intr = 0;
141
142 for (i = 0; i < s->nbanks; ++i)
143 has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
144 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
145
146 if (s->new_agr[is_fiq] & has_intr & s->mask) {
147 s->new_agr[is_fiq] = 0;
148 omap_inth_sir_update(s, is_fiq);
149 qemu_set_irq(s->parent_intr[is_fiq], 1);
150 }
151 }
152
153 #define INT_FALLING_EDGE 0
154 #define INT_LOW_LEVEL 1
155
156 static void omap_set_intr(void *opaque, int irq, int req)
157 {
158 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
159 uint32_t rise;
160
161 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
162 int n = irq & 31;
163
164 if (req) {
165 rise = ~bank->irqs & (1 << n);
166 if (~bank->sens_edge & (1 << n))
167 rise &= ~bank->inputs;
168
169 bank->inputs |= (1 << n);
170 if (rise) {
171 bank->irqs |= rise;
172 omap_inth_update(ih, 0);
173 omap_inth_update(ih, 1);
174 }
175 } else {
176 rise = bank->sens_edge & bank->irqs & (1 << n);
177 bank->irqs &= ~rise;
178 bank->inputs &= ~(1 << n);
179 }
180 }
181
182 /* Simplified version with no edge detection */
183 static void omap_set_intr_noedge(void *opaque, int irq, int req)
184 {
185 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
186 uint32_t rise;
187
188 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
189 int n = irq & 31;
190
191 if (req) {
192 rise = ~bank->inputs & (1 << n);
193 if (rise) {
194 bank->irqs |= bank->inputs |= rise;
195 omap_inth_update(ih, 0);
196 omap_inth_update(ih, 1);
197 }
198 } else
199 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
200 }
201
202 static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
203 {
204 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
205 int i, offset = addr - s->base;
206 int bank_no = offset >> 8;
207 int line_no;
208 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
209 offset &= 0xff;
210
211 switch (offset) {
212 case 0x00: /* ITR */
213 return bank->irqs;
214
215 case 0x04: /* MIR */
216 return bank->mask;
217
218 case 0x10: /* SIR_IRQ_CODE */
219 case 0x14: /* SIR_FIQ_CODE */
220 if (bank_no != 0)
221 break;
222 line_no = s->sir_intr[(offset - 0x10) >> 2];
223 bank = &s->bank[line_no >> 5];
224 i = line_no & 31;
225 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
226 bank->irqs &= ~(1 << i);
227 return line_no;
228
229 case 0x18: /* CONTROL_REG */
230 if (bank_no != 0)
231 break;
232 return 0;
233
234 case 0x1c: /* ILR0 */
235 case 0x20: /* ILR1 */
236 case 0x24: /* ILR2 */
237 case 0x28: /* ILR3 */
238 case 0x2c: /* ILR4 */
239 case 0x30: /* ILR5 */
240 case 0x34: /* ILR6 */
241 case 0x38: /* ILR7 */
242 case 0x3c: /* ILR8 */
243 case 0x40: /* ILR9 */
244 case 0x44: /* ILR10 */
245 case 0x48: /* ILR11 */
246 case 0x4c: /* ILR12 */
247 case 0x50: /* ILR13 */
248 case 0x54: /* ILR14 */
249 case 0x58: /* ILR15 */
250 case 0x5c: /* ILR16 */
251 case 0x60: /* ILR17 */
252 case 0x64: /* ILR18 */
253 case 0x68: /* ILR19 */
254 case 0x6c: /* ILR20 */
255 case 0x70: /* ILR21 */
256 case 0x74: /* ILR22 */
257 case 0x78: /* ILR23 */
258 case 0x7c: /* ILR24 */
259 case 0x80: /* ILR25 */
260 case 0x84: /* ILR26 */
261 case 0x88: /* ILR27 */
262 case 0x8c: /* ILR28 */
263 case 0x90: /* ILR29 */
264 case 0x94: /* ILR30 */
265 case 0x98: /* ILR31 */
266 i = (offset - 0x1c) >> 2;
267 return (bank->priority[i] << 2) |
268 (((bank->sens_edge >> i) & 1) << 1) |
269 ((bank->fiq >> i) & 1);
270
271 case 0x9c: /* ISR */
272 return 0x00000000;
273
274 }
275 OMAP_BAD_REG(addr);
276 return 0;
277 }
278
279 static void omap_inth_write(void *opaque, target_phys_addr_t addr,
280 uint32_t value)
281 {
282 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
283 int i, offset = addr - s->base;
284 int bank_no = offset >> 8;
285 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
286 offset &= 0xff;
287
288 switch (offset) {
289 case 0x00: /* ITR */
290 /* Important: ignore the clearing if the IRQ is level-triggered and
291 the input bit is 1 */
292 bank->irqs &= value | (bank->inputs & bank->sens_edge);
293 return;
294
295 case 0x04: /* MIR */
296 bank->mask = value;
297 omap_inth_update(s, 0);
298 omap_inth_update(s, 1);
299 return;
300
301 case 0x10: /* SIR_IRQ_CODE */
302 case 0x14: /* SIR_FIQ_CODE */
303 OMAP_RO_REG(addr);
304 break;
305
306 case 0x18: /* CONTROL_REG */
307 if (bank_no != 0)
308 break;
309 if (value & 2) {
310 qemu_set_irq(s->parent_intr[1], 0);
311 s->new_agr[1] = ~0;
312 omap_inth_update(s, 1);
313 }
314 if (value & 1) {
315 qemu_set_irq(s->parent_intr[0], 0);
316 s->new_agr[0] = ~0;
317 omap_inth_update(s, 0);
318 }
319 return;
320
321 case 0x1c: /* ILR0 */
322 case 0x20: /* ILR1 */
323 case 0x24: /* ILR2 */
324 case 0x28: /* ILR3 */
325 case 0x2c: /* ILR4 */
326 case 0x30: /* ILR5 */
327 case 0x34: /* ILR6 */
328 case 0x38: /* ILR7 */
329 case 0x3c: /* ILR8 */
330 case 0x40: /* ILR9 */
331 case 0x44: /* ILR10 */
332 case 0x48: /* ILR11 */
333 case 0x4c: /* ILR12 */
334 case 0x50: /* ILR13 */
335 case 0x54: /* ILR14 */
336 case 0x58: /* ILR15 */
337 case 0x5c: /* ILR16 */
338 case 0x60: /* ILR17 */
339 case 0x64: /* ILR18 */
340 case 0x68: /* ILR19 */
341 case 0x6c: /* ILR20 */
342 case 0x70: /* ILR21 */
343 case 0x74: /* ILR22 */
344 case 0x78: /* ILR23 */
345 case 0x7c: /* ILR24 */
346 case 0x80: /* ILR25 */
347 case 0x84: /* ILR26 */
348 case 0x88: /* ILR27 */
349 case 0x8c: /* ILR28 */
350 case 0x90: /* ILR29 */
351 case 0x94: /* ILR30 */
352 case 0x98: /* ILR31 */
353 i = (offset - 0x1c) >> 2;
354 bank->priority[i] = (value >> 2) & 0x1f;
355 bank->sens_edge &= ~(1 << i);
356 bank->sens_edge |= ((value >> 1) & 1) << i;
357 bank->fiq &= ~(1 << i);
358 bank->fiq |= (value & 1) << i;
359 return;
360
361 case 0x9c: /* ISR */
362 for (i = 0; i < 32; i ++)
363 if (value & (1 << i)) {
364 omap_set_intr(s, 32 * bank_no + i, 1);
365 return;
366 }
367 return;
368 }
369 OMAP_BAD_REG(addr);
370 }
371
372 static CPUReadMemoryFunc *omap_inth_readfn[] = {
373 omap_badwidth_read32,
374 omap_badwidth_read32,
375 omap_inth_read,
376 };
377
378 static CPUWriteMemoryFunc *omap_inth_writefn[] = {
379 omap_inth_write,
380 omap_inth_write,
381 omap_inth_write,
382 };
383
384 void omap_inth_reset(struct omap_intr_handler_s *s)
385 {
386 int i;
387
388 for (i = 0; i < s->nbanks; ++i){
389 s->bank[i].irqs = 0x00000000;
390 s->bank[i].mask = 0xffffffff;
391 s->bank[i].sens_edge = 0x00000000;
392 s->bank[i].fiq = 0x00000000;
393 s->bank[i].inputs = 0x00000000;
394 s->bank[i].swi = 0x00000000;
395 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
396
397 if (s->level_only)
398 s->bank[i].sens_edge = 0xffffffff;
399 }
400
401 s->new_agr[0] = ~0;
402 s->new_agr[1] = ~0;
403 s->sir_intr[0] = 0;
404 s->sir_intr[1] = 0;
405 s->autoidle = 0;
406 s->mask = ~0;
407
408 qemu_set_irq(s->parent_intr[0], 0);
409 qemu_set_irq(s->parent_intr[1], 0);
410 }
411
412 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
413 unsigned long size, unsigned char nbanks, qemu_irq **pins,
414 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
415 {
416 int iomemtype;
417 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
418 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
419 sizeof(struct omap_intr_handler_bank_s) * nbanks);
420
421 s->parent_intr[0] = parent_irq;
422 s->parent_intr[1] = parent_fiq;
423 s->base = base;
424 s->nbanks = nbanks;
425 s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
426 if (pins)
427 *pins = s->pins;
428
429 omap_inth_reset(s);
430
431 iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
432 omap_inth_writefn, s);
433 cpu_register_physical_memory(s->base, size, iomemtype);
434
435 return s;
436 }
437
438 static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
439 {
440 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
441 int offset = addr - s->base;
442 int bank_no, line_no;
443 struct omap_intr_handler_bank_s *bank = 0;
444
445 if ((offset & 0xf80) == 0x80) {
446 bank_no = (offset & 0x60) >> 5;
447 if (bank_no < s->nbanks) {
448 offset &= ~0x60;
449 bank = &s->bank[bank_no];
450 }
451 }
452
453 switch (offset) {
454 case 0x00: /* INTC_REVISION */
455 return 0x21;
456
457 case 0x10: /* INTC_SYSCONFIG */
458 return (s->autoidle >> 2) & 1;
459
460 case 0x14: /* INTC_SYSSTATUS */
461 return 1; /* RESETDONE */
462
463 case 0x40: /* INTC_SIR_IRQ */
464 return s->sir_intr[0];
465
466 case 0x44: /* INTC_SIR_FIQ */
467 return s->sir_intr[1];
468
469 case 0x48: /* INTC_CONTROL */
470 return (!s->mask) << 2; /* GLOBALMASK */
471
472 case 0x4c: /* INTC_PROTECTION */
473 return 0;
474
475 case 0x50: /* INTC_IDLE */
476 return s->autoidle & 3;
477
478 /* Per-bank registers */
479 case 0x80: /* INTC_ITR */
480 return bank->inputs;
481
482 case 0x84: /* INTC_MIR */
483 return bank->mask;
484
485 case 0x88: /* INTC_MIR_CLEAR */
486 case 0x8c: /* INTC_MIR_SET */
487 return 0;
488
489 case 0x90: /* INTC_ISR_SET */
490 return bank->swi;
491
492 case 0x94: /* INTC_ISR_CLEAR */
493 return 0;
494
495 case 0x98: /* INTC_PENDING_IRQ */
496 return bank->irqs & ~bank->mask & ~bank->fiq;
497
498 case 0x9c: /* INTC_PENDING_FIQ */
499 return bank->irqs & ~bank->mask & bank->fiq;
500
501 /* Per-line registers */
502 case 0x100 ... 0x300: /* INTC_ILR */
503 bank_no = (offset - 0x100) >> 7;
504 if (bank_no > s->nbanks)
505 break;
506 bank = &s->bank[bank_no];
507 line_no = (offset & 0x7f) >> 2;
508 return (bank->priority[line_no] << 2) |
509 ((bank->fiq >> line_no) & 1);
510 }
511 OMAP_BAD_REG(addr);
512 return 0;
513 }
514
515 static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
516 uint32_t value)
517 {
518 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
519 int offset = addr - s->base;
520 int bank_no, line_no;
521 struct omap_intr_handler_bank_s *bank = 0;
522
523 if ((offset & 0xf80) == 0x80) {
524 bank_no = (offset & 0x60) >> 5;
525 if (bank_no < s->nbanks) {
526 offset &= ~0x60;
527 bank = &s->bank[bank_no];
528 }
529 }
530
531 switch (offset) {
532 case 0x10: /* INTC_SYSCONFIG */
533 s->autoidle &= 4;
534 s->autoidle |= (value & 1) << 2;
535 if (value & 2) /* SOFTRESET */
536 omap_inth_reset(s);
537 return;
538
539 case 0x48: /* INTC_CONTROL */
540 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
541 if (value & 2) { /* NEWFIQAGR */
542 qemu_set_irq(s->parent_intr[1], 0);
543 s->new_agr[1] = ~0;
544 omap_inth_update(s, 1);
545 }
546 if (value & 1) { /* NEWIRQAGR */
547 qemu_set_irq(s->parent_intr[0], 0);
548 s->new_agr[0] = ~0;
549 omap_inth_update(s, 0);
550 }
551 return;
552
553 case 0x4c: /* INTC_PROTECTION */
554 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
555 * for every register, see Chapter 3 and 4 for privileged mode. */
556 if (value & 1)
557 fprintf(stderr, "%s: protection mode enable attempt\n",
558 __FUNCTION__);
559 return;
560
561 case 0x50: /* INTC_IDLE */
562 s->autoidle &= ~3;
563 s->autoidle |= value & 3;
564 return;
565
566 /* Per-bank registers */
567 case 0x84: /* INTC_MIR */
568 bank->mask = value;
569 omap_inth_update(s, 0);
570 omap_inth_update(s, 1);
571 return;
572
573 case 0x88: /* INTC_MIR_CLEAR */
574 bank->mask &= ~value;
575 omap_inth_update(s, 0);
576 omap_inth_update(s, 1);
577 return;
578
579 case 0x8c: /* INTC_MIR_SET */
580 bank->mask |= value;
581 return;
582
583 case 0x90: /* INTC_ISR_SET */
584 bank->irqs |= bank->swi |= value;
585 omap_inth_update(s, 0);
586 omap_inth_update(s, 1);
587 return;
588
589 case 0x94: /* INTC_ISR_CLEAR */
590 bank->swi &= ~value;
591 bank->irqs = bank->swi & bank->inputs;
592 return;
593
594 /* Per-line registers */
595 case 0x100 ... 0x300: /* INTC_ILR */
596 bank_no = (offset - 0x100) >> 7;
597 if (bank_no > s->nbanks)
598 break;
599 bank = &s->bank[bank_no];
600 line_no = (offset & 0x7f) >> 2;
601 bank->priority[line_no] = (value >> 2) & 0x3f;
602 bank->fiq &= ~(1 << line_no);
603 bank->fiq |= (value & 1) << line_no;
604 return;
605
606 case 0x00: /* INTC_REVISION */
607 case 0x14: /* INTC_SYSSTATUS */
608 case 0x40: /* INTC_SIR_IRQ */
609 case 0x44: /* INTC_SIR_FIQ */
610 case 0x80: /* INTC_ITR */
611 case 0x98: /* INTC_PENDING_IRQ */
612 case 0x9c: /* INTC_PENDING_FIQ */
613 OMAP_RO_REG(addr);
614 return;
615 }
616 OMAP_BAD_REG(addr);
617 }
618
619 static CPUReadMemoryFunc *omap2_inth_readfn[] = {
620 omap_badwidth_read32,
621 omap_badwidth_read32,
622 omap2_inth_read,
623 };
624
625 static CPUWriteMemoryFunc *omap2_inth_writefn[] = {
626 omap2_inth_write,
627 omap2_inth_write,
628 omap2_inth_write,
629 };
630
631 struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
632 int size, int nbanks, qemu_irq **pins,
633 qemu_irq parent_irq, qemu_irq parent_fiq,
634 omap_clk fclk, omap_clk iclk)
635 {
636 int iomemtype;
637 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
638 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
639 sizeof(struct omap_intr_handler_bank_s) * nbanks);
640
641 s->parent_intr[0] = parent_irq;
642 s->parent_intr[1] = parent_fiq;
643 s->base = base;
644 s->nbanks = nbanks;
645 s->level_only = 1;
646 s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
647 if (pins)
648 *pins = s->pins;
649
650 omap_inth_reset(s);
651
652 iomemtype = cpu_register_io_memory(0, omap2_inth_readfn,
653 omap2_inth_writefn, s);
654 cpu_register_physical_memory(s->base, size, iomemtype);
655
656 return s;
657 }
658
659 /* MPU OS timers */
660 struct omap_mpu_timer_s {
661 qemu_irq irq;
662 omap_clk clk;
663 target_phys_addr_t base;
664 uint32_t val;
665 int64_t time;
666 QEMUTimer *timer;
667 QEMUBH *tick;
668 int64_t rate;
669 int it_ena;
670
671 int enable;
672 int ptv;
673 int ar;
674 int st;
675 uint32_t reset_val;
676 };
677
678 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
679 {
680 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
681
682 if (timer->st && timer->enable && timer->rate)
683 return timer->val - muldiv64(distance >> (timer->ptv + 1),
684 timer->rate, ticks_per_sec);
685 else
686 return timer->val;
687 }
688
689 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
690 {
691 timer->val = omap_timer_read(timer);
692 timer->time = qemu_get_clock(vm_clock);
693 }
694
695 static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
696 {
697 int64_t expires;
698
699 if (timer->enable && timer->st && timer->rate) {
700 timer->val = timer->reset_val; /* Should skip this on clk enable */
701 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
702 ticks_per_sec, timer->rate);
703
704 /* If timer expiry would be sooner than in about 1 ms and
705 * auto-reload isn't set, then fire immediately. This is a hack
706 * to make systems like PalmOS run in acceptable time. PalmOS
707 * sets the interval to a very low value and polls the status bit
708 * in a busy loop when it wants to sleep just a couple of CPU
709 * ticks. */
710 if (expires > (ticks_per_sec >> 10) || timer->ar)
711 qemu_mod_timer(timer->timer, timer->time + expires);
712 else
713 qemu_bh_schedule(timer->tick);
714 } else
715 qemu_del_timer(timer->timer);
716 }
717
718 static void omap_timer_fire(void *opaque)
719 {
720 struct omap_mpu_timer_s *timer = opaque;
721
722 if (!timer->ar) {
723 timer->val = 0;
724 timer->st = 0;
725 }
726
727 if (timer->it_ena)
728 /* Edge-triggered irq */
729 qemu_irq_pulse(timer->irq);
730 }
731
732 static void omap_timer_tick(void *opaque)
733 {
734 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
735
736 omap_timer_sync(timer);
737 omap_timer_fire(timer);
738 omap_timer_update(timer);
739 }
740
741 static void omap_timer_clk_update(void *opaque, int line, int on)
742 {
743 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
744
745 omap_timer_sync(timer);
746 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
747 omap_timer_update(timer);
748 }
749
750 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
751 {
752 omap_clk_adduser(timer->clk,
753 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
754 timer->rate = omap_clk_getrate(timer->clk);
755 }
756
757 static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
758 {
759 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
760 int offset = addr - s->base;
761
762 switch (offset) {
763 case 0x00: /* CNTL_TIMER */
764 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
765
766 case 0x04: /* LOAD_TIM */
767 break;
768
769 case 0x08: /* READ_TIM */
770 return omap_timer_read(s);
771 }
772
773 OMAP_BAD_REG(addr);
774 return 0;
775 }
776
777 static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
778 uint32_t value)
779 {
780 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
781 int offset = addr - s->base;
782
783 switch (offset) {
784 case 0x00: /* CNTL_TIMER */
785 omap_timer_sync(s);
786 s->enable = (value >> 5) & 1;
787 s->ptv = (value >> 2) & 7;
788 s->ar = (value >> 1) & 1;
789 s->st = value & 1;
790 omap_timer_update(s);
791 return;
792
793 case 0x04: /* LOAD_TIM */
794 s->reset_val = value;
795 return;
796
797 case 0x08: /* READ_TIM */
798 OMAP_RO_REG(addr);
799 break;
800
801 default:
802 OMAP_BAD_REG(addr);
803 }
804 }
805
806 static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
807 omap_badwidth_read32,
808 omap_badwidth_read32,
809 omap_mpu_timer_read,
810 };
811
812 static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
813 omap_badwidth_write32,
814 omap_badwidth_write32,
815 omap_mpu_timer_write,
816 };
817
818 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
819 {
820 qemu_del_timer(s->timer);
821 s->enable = 0;
822 s->reset_val = 31337;
823 s->val = 0;
824 s->ptv = 0;
825 s->ar = 0;
826 s->st = 0;
827 s->it_ena = 1;
828 }
829
830 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
831 qemu_irq irq, omap_clk clk)
832 {
833 int iomemtype;
834 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
835 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
836
837 s->irq = irq;
838 s->clk = clk;
839 s->base = base;
840 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
841 s->tick = qemu_bh_new(omap_timer_fire, s);
842 omap_mpu_timer_reset(s);
843 omap_timer_clk_setup(s);
844
845 iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
846 omap_mpu_timer_writefn, s);
847 cpu_register_physical_memory(s->base, 0x100, iomemtype);
848
849 return s;
850 }
851
852 /* Watchdog timer */
853 struct omap_watchdog_timer_s {
854 struct omap_mpu_timer_s timer;
855 uint8_t last_wr;
856 int mode;
857 int free;
858 int reset;
859 };
860
861 static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
862 {
863 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
864 int offset = addr - s->timer.base;
865
866 switch (offset) {
867 case 0x00: /* CNTL_TIMER */
868 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
869 (s->timer.st << 7) | (s->free << 1);
870
871 case 0x04: /* READ_TIMER */
872 return omap_timer_read(&s->timer);
873
874 case 0x08: /* TIMER_MODE */
875 return s->mode << 15;
876 }
877
878 OMAP_BAD_REG(addr);
879 return 0;
880 }
881
882 static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
883 uint32_t value)
884 {
885 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
886 int offset = addr - s->timer.base;
887
888 switch (offset) {
889 case 0x00: /* CNTL_TIMER */
890 omap_timer_sync(&s->timer);
891 s->timer.ptv = (value >> 9) & 7;
892 s->timer.ar = (value >> 8) & 1;
893 s->timer.st = (value >> 7) & 1;
894 s->free = (value >> 1) & 1;
895 omap_timer_update(&s->timer);
896 break;
897
898 case 0x04: /* LOAD_TIMER */
899 s->timer.reset_val = value & 0xffff;
900 break;
901
902 case 0x08: /* TIMER_MODE */
903 if (!s->mode && ((value >> 15) & 1))
904 omap_clk_get(s->timer.clk);
905 s->mode |= (value >> 15) & 1;
906 if (s->last_wr == 0xf5) {
907 if ((value & 0xff) == 0xa0) {
908 if (s->mode) {
909 s->mode = 0;
910 omap_clk_put(s->timer.clk);
911 }
912 } else {
913 /* XXX: on T|E hardware somehow this has no effect,
914 * on Zire 71 it works as specified. */
915 s->reset = 1;
916 qemu_system_reset_request();
917 }
918 }
919 s->last_wr = value & 0xff;
920 break;
921
922 default:
923 OMAP_BAD_REG(addr);
924 }
925 }
926
927 static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
928 omap_badwidth_read16,
929 omap_wd_timer_read,
930 omap_badwidth_read16,
931 };
932
933 static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
934 omap_badwidth_write16,
935 omap_wd_timer_write,
936 omap_badwidth_write16,
937 };
938
939 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
940 {
941 qemu_del_timer(s->timer.timer);
942 if (!s->mode)
943 omap_clk_get(s->timer.clk);
944 s->mode = 1;
945 s->free = 1;
946 s->reset = 0;
947 s->timer.enable = 1;
948 s->timer.it_ena = 1;
949 s->timer.reset_val = 0xffff;
950 s->timer.val = 0;
951 s->timer.st = 0;
952 s->timer.ptv = 0;
953 s->timer.ar = 0;
954 omap_timer_update(&s->timer);
955 }
956
957 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
958 qemu_irq irq, omap_clk clk)
959 {
960 int iomemtype;
961 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
962 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
963
964 s->timer.irq = irq;
965 s->timer.clk = clk;
966 s->timer.base = base;
967 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
968 omap_wd_timer_reset(s);
969 omap_timer_clk_setup(&s->timer);
970
971 iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
972 omap_wd_timer_writefn, s);
973 cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
974
975 return s;
976 }
977
978 /* 32-kHz timer */
979 struct omap_32khz_timer_s {
980 struct omap_mpu_timer_s timer;
981 };
982
983 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
984 {
985 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
986 int offset = addr & OMAP_MPUI_REG_MASK;
987
988 switch (offset) {
989 case 0x00: /* TVR */
990 return s->timer.reset_val;
991
992 case 0x04: /* TCR */
993 return omap_timer_read(&s->timer);
994
995 case 0x08: /* CR */
996 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
997
998 default:
999 break;
1000 }
1001 OMAP_BAD_REG(addr);
1002 return 0;
1003 }
1004
1005 static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
1006 uint32_t value)
1007 {
1008 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1009 int offset = addr & OMAP_MPUI_REG_MASK;
1010
1011 switch (offset) {
1012 case 0x00: /* TVR */
1013 s->timer.reset_val = value & 0x00ffffff;
1014 break;
1015
1016 case 0x04: /* TCR */
1017 OMAP_RO_REG(addr);
1018 break;
1019
1020 case 0x08: /* CR */
1021 s->timer.ar = (value >> 3) & 1;
1022 s->timer.it_ena = (value >> 2) & 1;
1023 if (s->timer.st != (value & 1) || (value & 2)) {
1024 omap_timer_sync(&s->timer);
1025 s->timer.enable = value & 1;
1026 s->timer.st = value & 1;
1027 omap_timer_update(&s->timer);
1028 }
1029 break;
1030
1031 default:
1032 OMAP_BAD_REG(addr);
1033 }
1034 }
1035
1036 static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
1037 omap_badwidth_read32,
1038 omap_badwidth_read32,
1039 omap_os_timer_read,
1040 };
1041
1042 static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
1043 omap_badwidth_write32,
1044 omap_badwidth_write32,
1045 omap_os_timer_write,
1046 };
1047
1048 static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
1049 {
1050 qemu_del_timer(s->timer.timer);
1051 s->timer.enable = 0;
1052 s->timer.it_ena = 0;
1053 s->timer.reset_val = 0x00ffffff;
1054 s->timer.val = 0;
1055 s->timer.st = 0;
1056 s->timer.ptv = 0;
1057 s->timer.ar = 1;
1058 }
1059
1060 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
1061 qemu_irq irq, omap_clk clk)
1062 {
1063 int iomemtype;
1064 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
1065 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
1066
1067 s->timer.irq = irq;
1068 s->timer.clk = clk;
1069 s->timer.base = base;
1070 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1071 omap_os_timer_reset(s);
1072 omap_timer_clk_setup(&s->timer);
1073
1074 iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
1075 omap_os_timer_writefn, s);
1076 cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
1077
1078 return s;
1079 }
1080
1081 /* Ultra Low-Power Device Module */
1082 static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
1083 {
1084 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1085 int offset = addr - s->ulpd_pm_base;
1086 uint16_t ret;
1087
1088 switch (offset) {
1089 case 0x14: /* IT_STATUS */
1090 ret = s->ulpd_pm_regs[offset >> 2];
1091 s->ulpd_pm_regs[offset >> 2] = 0;
1092 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
1093 return ret;
1094
1095 case 0x18: /* Reserved */
1096 case 0x1c: /* Reserved */
1097 case 0x20: /* Reserved */
1098 case 0x28: /* Reserved */
1099 case 0x2c: /* Reserved */
1100 OMAP_BAD_REG(addr);
1101 case 0x00: /* COUNTER_32_LSB */
1102 case 0x04: /* COUNTER_32_MSB */
1103 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1104 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1105 case 0x10: /* GAUGING_CTRL */
1106 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1107 case 0x30: /* CLOCK_CTRL */
1108 case 0x34: /* SOFT_REQ */
1109 case 0x38: /* COUNTER_32_FIQ */
1110 case 0x3c: /* DPLL_CTRL */
1111 case 0x40: /* STATUS_REQ */
1112 /* XXX: check clk::usecount state for every clock */
1113 case 0x48: /* LOCL_TIME */
1114 case 0x4c: /* APLL_CTRL */
1115 case 0x50: /* POWER_CTRL */
1116 return s->ulpd_pm_regs[offset >> 2];
1117 }
1118
1119 OMAP_BAD_REG(addr);
1120 return 0;
1121 }
1122
1123 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
1124 uint16_t diff, uint16_t value)
1125 {
1126 if (diff & (1 << 4)) /* USB_MCLK_EN */
1127 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
1128 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
1129 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
1130 }
1131
1132 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
1133 uint16_t diff, uint16_t value)
1134 {
1135 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
1136 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
1137 if (diff & (1 << 1)) /* SOFT_COM_REQ */
1138 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
1139 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
1140 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
1141 if (diff & (1 << 3)) /* SOFT_USB_REQ */
1142 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
1143 }
1144
1145 static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
1146 uint32_t value)
1147 {
1148 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1149 int offset = addr - s->ulpd_pm_base;
1150 int64_t now, ticks;
1151 int div, mult;
1152 static const int bypass_div[4] = { 1, 2, 4, 4 };
1153 uint16_t diff;
1154
1155 switch (offset) {
1156 case 0x00: /* COUNTER_32_LSB */
1157 case 0x04: /* COUNTER_32_MSB */
1158 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1159 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1160 case 0x14: /* IT_STATUS */
1161 case 0x40: /* STATUS_REQ */
1162 OMAP_RO_REG(addr);
1163 break;
1164
1165 case 0x10: /* GAUGING_CTRL */
1166 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
1167 if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
1168 now = qemu_get_clock(vm_clock);
1169
1170 if (value & 1)
1171 s->ulpd_gauge_start = now;
1172 else {
1173 now -= s->ulpd_gauge_start;
1174
1175 /* 32-kHz ticks */
1176 ticks = muldiv64(now, 32768, ticks_per_sec);
1177 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
1178 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
1179 if (ticks >> 32) /* OVERFLOW_32K */
1180 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
1181
1182 /* High frequency ticks */
1183 ticks = muldiv64(now, 12000000, ticks_per_sec);
1184 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
1185 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
1186 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
1187 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
1188
1189 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1190 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
1191 }
1192 }
1193 s->ulpd_pm_regs[offset >> 2] = value;
1194 break;
1195
1196 case 0x18: /* Reserved */
1197 case 0x1c: /* Reserved */
1198 case 0x20: /* Reserved */
1199 case 0x28: /* Reserved */
1200 case 0x2c: /* Reserved */
1201 OMAP_BAD_REG(addr);
1202 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1203 case 0x38: /* COUNTER_32_FIQ */
1204 case 0x48: /* LOCL_TIME */
1205 case 0x50: /* POWER_CTRL */
1206 s->ulpd_pm_regs[offset >> 2] = value;
1207 break;
1208
1209 case 0x30: /* CLOCK_CTRL */
1210 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1211 s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
1212 omap_ulpd_clk_update(s, diff, value);
1213 break;
1214
1215 case 0x34: /* SOFT_REQ */
1216 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1217 s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
1218 omap_ulpd_req_update(s, diff, value);
1219 break;
1220
1221 case 0x3c: /* DPLL_CTRL */
1222 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1223 * omitted altogether, probably a typo. */
1224 /* This register has identical semantics with DPLL(1:3) control
1225 * registers, see omap_dpll_write() */
1226 diff = s->ulpd_pm_regs[offset >> 2] & value;
1227 s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
1228 if (diff & (0x3ff << 2)) {
1229 if (value & (1 << 4)) { /* PLL_ENABLE */
1230 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1231 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1232 } else {
1233 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1234 mult = 1;
1235 }
1236 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
1237 }
1238
1239 /* Enter the desired mode. */
1240 s->ulpd_pm_regs[offset >> 2] =
1241 (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
1242 ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
1243
1244 /* Act as if the lock is restored. */
1245 s->ulpd_pm_regs[offset >> 2] |= 2;
1246 break;
1247
1248 case 0x4c: /* APLL_CTRL */
1249 diff = s->ulpd_pm_regs[offset >> 2] & value;
1250 s->ulpd_pm_regs[offset >> 2] = value & 0xf;
1251 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
1252 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
1253 (value & (1 << 0)) ? "apll" : "dpll4"));
1254 break;
1255
1256 default:
1257 OMAP_BAD_REG(addr);
1258 }
1259 }
1260
1261 static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
1262 omap_badwidth_read16,
1263 omap_ulpd_pm_read,
1264 omap_badwidth_read16,
1265 };
1266
1267 static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
1268 omap_badwidth_write16,
1269 omap_ulpd_pm_write,
1270 omap_badwidth_write16,
1271 };
1272
1273 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
1274 {
1275 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
1276 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
1277 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
1278 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
1279 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
1280 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
1281 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
1282 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
1283 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
1284 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
1285 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
1286 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
1287 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
1288 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
1289 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
1290 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
1291 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
1292 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1293 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
1294 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
1295 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
1296 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
1297 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
1298 }
1299
1300 static void omap_ulpd_pm_init(target_phys_addr_t base,
1301 struct omap_mpu_state_s *mpu)
1302 {
1303 int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
1304 omap_ulpd_pm_writefn, mpu);
1305
1306 mpu->ulpd_pm_base = base;
1307 cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
1308 omap_ulpd_pm_reset(mpu);
1309 }
1310
1311 /* OMAP Pin Configuration */
1312 static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
1313 {
1314 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1315 int offset = addr - s->pin_cfg_base;
1316
1317 switch (offset) {
1318 case 0x00: /* FUNC_MUX_CTRL_0 */
1319 case 0x04: /* FUNC_MUX_CTRL_1 */
1320 case 0x08: /* FUNC_MUX_CTRL_2 */
1321 return s->func_mux_ctrl[offset >> 2];
1322
1323 case 0x0c: /* COMP_MODE_CTRL_0 */
1324 return s->comp_mode_ctrl[0];
1325
1326 case 0x10: /* FUNC_MUX_CTRL_3 */
1327 case 0x14: /* FUNC_MUX_CTRL_4 */
1328 case 0x18: /* FUNC_MUX_CTRL_5 */
1329 case 0x1c: /* FUNC_MUX_CTRL_6 */
1330 case 0x20: /* FUNC_MUX_CTRL_7 */
1331 case 0x24: /* FUNC_MUX_CTRL_8 */
1332 case 0x28: /* FUNC_MUX_CTRL_9 */
1333 case 0x2c: /* FUNC_MUX_CTRL_A */
1334 case 0x30: /* FUNC_MUX_CTRL_B */
1335 case 0x34: /* FUNC_MUX_CTRL_C */
1336 case 0x38: /* FUNC_MUX_CTRL_D */
1337 return s->func_mux_ctrl[(offset >> 2) - 1];
1338
1339 case 0x40: /* PULL_DWN_CTRL_0 */
1340 case 0x44: /* PULL_DWN_CTRL_1 */
1341 case 0x48: /* PULL_DWN_CTRL_2 */
1342 case 0x4c: /* PULL_DWN_CTRL_3 */
1343 return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
1344
1345 case 0x50: /* GATE_INH_CTRL_0 */
1346 return s->gate_inh_ctrl[0];
1347
1348 case 0x60: /* VOLTAGE_CTRL_0 */
1349 return s->voltage_ctrl[0];
1350
1351 case 0x70: /* TEST_DBG_CTRL_0 */
1352 return s->test_dbg_ctrl[0];
1353
1354 case 0x80: /* MOD_CONF_CTRL_0 */
1355 return s->mod_conf_ctrl[0];
1356 }
1357
1358 OMAP_BAD_REG(addr);
1359 return 0;
1360 }
1361
1362 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
1363 uint32_t diff, uint32_t value)
1364 {
1365 if (s->compat1509) {
1366 if (diff & (1 << 9)) /* BLUETOOTH */
1367 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
1368 (~value >> 9) & 1);
1369 if (diff & (1 << 7)) /* USB.CLKO */
1370 omap_clk_onoff(omap_findclk(s, "usb.clko"),
1371 (value >> 7) & 1);
1372 }
1373 }
1374
1375 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
1376 uint32_t diff, uint32_t value)
1377 {
1378 if (s->compat1509) {
1379 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1380 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
1381 (value >> 31) & 1);
1382 if (diff & (1 << 1)) /* CLK32K */
1383 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
1384 (~value >> 1) & 1);
1385 }
1386 }
1387
1388 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
1389 uint32_t diff, uint32_t value)
1390 {
1391 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1392 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
1393 omap_findclk(s, ((value >> 31) & 1) ?
1394 "ck_48m" : "armper_ck"));
1395 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1396 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
1397 omap_findclk(s, ((value >> 30) & 1) ?
1398 "ck_48m" : "armper_ck"));
1399 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1400 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
1401 omap_findclk(s, ((value >> 29) & 1) ?
1402 "ck_48m" : "armper_ck"));
1403 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1404 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
1405 omap_findclk(s, ((value >> 23) & 1) ?
1406 "ck_48m" : "armper_ck"));
1407 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1408 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
1409 omap_findclk(s, ((value >> 12) & 1) ?
1410 "ck_48m" : "armper_ck"));
1411 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1412 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
1413 }
1414
1415 static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
1416 uint32_t value)
1417 {
1418 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1419 int offset = addr - s->pin_cfg_base;
1420 uint32_t diff;
1421
1422 switch (offset) {
1423 case 0x00: /* FUNC_MUX_CTRL_0 */
1424 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1425 s->func_mux_ctrl[offset >> 2] = value;
1426 omap_pin_funcmux0_update(s, diff, value);
1427 return;
1428
1429 case 0x04: /* FUNC_MUX_CTRL_1 */
1430 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1431 s->func_mux_ctrl[offset >> 2] = value;
1432 omap_pin_funcmux1_update(s, diff, value);
1433 return;
1434
1435 case 0x08: /* FUNC_MUX_CTRL_2 */
1436 s->func_mux_ctrl[offset >> 2] = value;
1437 return;
1438
1439 case 0x0c: /* COMP_MODE_CTRL_0 */
1440 s->comp_mode_ctrl[0] = value;
1441 s->compat1509 = (value != 0x0000eaef);
1442 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
1443 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
1444 return;
1445
1446 case 0x10: /* FUNC_MUX_CTRL_3 */
1447 case 0x14: /* FUNC_MUX_CTRL_4 */
1448 case 0x18: /* FUNC_MUX_CTRL_5 */
1449 case 0x1c: /* FUNC_MUX_CTRL_6 */
1450 case 0x20: /* FUNC_MUX_CTRL_7 */
1451 case 0x24: /* FUNC_MUX_CTRL_8 */
1452 case 0x28: /* FUNC_MUX_CTRL_9 */
1453 case 0x2c: /* FUNC_MUX_CTRL_A */
1454 case 0x30: /* FUNC_MUX_CTRL_B */
1455 case 0x34: /* FUNC_MUX_CTRL_C */
1456 case 0x38: /* FUNC_MUX_CTRL_D */
1457 s->func_mux_ctrl[(offset >> 2) - 1] = value;
1458 return;
1459
1460 case 0x40: /* PULL_DWN_CTRL_0 */
1461 case 0x44: /* PULL_DWN_CTRL_1 */
1462 case 0x48: /* PULL_DWN_CTRL_2 */
1463 case 0x4c: /* PULL_DWN_CTRL_3 */
1464 s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
1465 return;
1466
1467 case 0x50: /* GATE_INH_CTRL_0 */
1468 s->gate_inh_ctrl[0] = value;
1469 return;
1470
1471 case 0x60: /* VOLTAGE_CTRL_0 */
1472 s->voltage_ctrl[0] = value;
1473 return;
1474
1475 case 0x70: /* TEST_DBG_CTRL_0 */
1476 s->test_dbg_ctrl[0] = value;
1477 return;
1478
1479 case 0x80: /* MOD_CONF_CTRL_0 */
1480 diff = s->mod_conf_ctrl[0] ^ value;
1481 s->mod_conf_ctrl[0] = value;
1482 omap_pin_modconf1_update(s, diff, value);
1483 return;
1484
1485 default:
1486 OMAP_BAD_REG(addr);
1487 }
1488 }
1489
1490 static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
1491 omap_badwidth_read32,
1492 omap_badwidth_read32,
1493 omap_pin_cfg_read,
1494 };
1495
1496 static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
1497 omap_badwidth_write32,
1498 omap_badwidth_write32,
1499 omap_pin_cfg_write,
1500 };
1501
1502 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
1503 {
1504 /* Start in Compatibility Mode. */
1505 mpu->compat1509 = 1;
1506 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
1507 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
1508 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
1509 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
1510 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
1511 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
1512 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
1513 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
1514 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
1515 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
1516 }
1517
1518 static void omap_pin_cfg_init(target_phys_addr_t base,
1519 struct omap_mpu_state_s *mpu)
1520 {
1521 int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
1522 omap_pin_cfg_writefn, mpu);
1523
1524 mpu->pin_cfg_base = base;
1525 cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
1526 omap_pin_cfg_reset(mpu);
1527 }
1528
1529 /* Device Identification, Die Identification */
1530 static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
1531 {
1532 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1533
1534 switch (addr) {
1535 case 0xfffe1800: /* DIE_ID_LSB */
1536 return 0xc9581f0e;
1537 case 0xfffe1804: /* DIE_ID_MSB */
1538 return 0xa8858bfa;
1539
1540 case 0xfffe2000: /* PRODUCT_ID_LSB */
1541 return 0x00aaaafc;
1542 case 0xfffe2004: /* PRODUCT_ID_MSB */
1543 return 0xcafeb574;
1544
1545 case 0xfffed400: /* JTAG_ID_LSB */
1546 switch (s->mpu_model) {
1547 case omap310:
1548 return 0x03310315;
1549 case omap1510:
1550 return 0x03310115;
1551 default:
1552 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
1553 }
1554 break;
1555
1556 case 0xfffed404: /* JTAG_ID_MSB */
1557 switch (s->mpu_model) {
1558 case omap310:
1559 return 0xfb57402f;
1560 case omap1510:
1561 return 0xfb47002f;
1562 default:
1563 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__);
1564 }
1565 break;
1566 }
1567
1568 OMAP_BAD_REG(addr);
1569 return 0;
1570 }
1571
1572 static void omap_id_write(void *opaque, target_phys_addr_t addr,
1573 uint32_t value)
1574 {
1575 OMAP_BAD_REG(addr);
1576 }
1577
1578 static CPUReadMemoryFunc *omap_id_readfn[] = {
1579 omap_badwidth_read32,
1580 omap_badwidth_read32,
1581 omap_id_read,
1582 };
1583
1584 static CPUWriteMemoryFunc *omap_id_writefn[] = {
1585 omap_badwidth_write32,
1586 omap_badwidth_write32,
1587 omap_id_write,
1588 };
1589
1590 static void omap_id_init(struct omap_mpu_state_s *mpu)
1591 {
1592 int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
1593 omap_id_writefn, mpu);
1594 cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
1595 cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
1596 if (!cpu_is_omap15xx(mpu))
1597 cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
1598 }
1599
1600 /* MPUI Control (Dummy) */
1601 static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
1602 {
1603 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1604 int offset = addr - s->mpui_base;
1605
1606 switch (offset) {
1607 case 0x00: /* CTRL */
1608 return s->mpui_ctrl;
1609 case 0x04: /* DEBUG_ADDR */
1610 return 0x01ffffff;
1611 case 0x08: /* DEBUG_DATA */
1612 return 0xffffffff;
1613 case 0x0c: /* DEBUG_FLAG */
1614 return 0x00000800;
1615 case 0x10: /* STATUS */
1616 return 0x00000000;
1617
1618 /* Not in OMAP310 */
1619 case 0x14: /* DSP_STATUS */
1620 case 0x18: /* DSP_BOOT_CONFIG */
1621 return 0x00000000;
1622 case 0x1c: /* DSP_MPUI_CONFIG */
1623 return 0x0000ffff;
1624 }
1625
1626 OMAP_BAD_REG(addr);
1627 return 0;
1628 }
1629
1630 static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
1631 uint32_t value)
1632 {
1633 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1634 int offset = addr - s->mpui_base;
1635
1636 switch (offset) {
1637 case 0x00: /* CTRL */
1638 s->mpui_ctrl = value & 0x007fffff;
1639 break;
1640
1641 case 0x04: /* DEBUG_ADDR */
1642 case 0x08: /* DEBUG_DATA */
1643 case 0x0c: /* DEBUG_FLAG */
1644 case 0x10: /* STATUS */
1645 /* Not in OMAP310 */
1646 case 0x14: /* DSP_STATUS */
1647 OMAP_RO_REG(addr);
1648 case 0x18: /* DSP_BOOT_CONFIG */
1649 case 0x1c: /* DSP_MPUI_CONFIG */
1650 break;
1651
1652 default:
1653 OMAP_BAD_REG(addr);
1654 }
1655 }
1656
1657 static CPUReadMemoryFunc *omap_mpui_readfn[] = {
1658 omap_badwidth_read32,
1659 omap_badwidth_read32,
1660 omap_mpui_read,
1661 };
1662
1663 static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
1664 omap_badwidth_write32,
1665 omap_badwidth_write32,
1666 omap_mpui_write,
1667 };
1668
1669 static void omap_mpui_reset(struct omap_mpu_state_s *s)
1670 {
1671 s->mpui_ctrl = 0x0003ff1b;
1672 }
1673
1674 static void omap_mpui_init(target_phys_addr_t base,
1675 struct omap_mpu_state_s *mpu)
1676 {
1677 int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
1678 omap_mpui_writefn, mpu);
1679
1680 mpu->mpui_base = base;
1681 cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
1682
1683 omap_mpui_reset(mpu);
1684 }
1685
1686 /* TIPB Bridges */
1687 struct omap_tipb_bridge_s {
1688 target_phys_addr_t base;
1689 qemu_irq abort;
1690
1691 int width_intr;
1692 uint16_t control;
1693 uint16_t alloc;
1694 uint16_t buffer;
1695 uint16_t enh_control;
1696 };
1697
1698 static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
1699 {
1700 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1701 int offset = addr - s->base;
1702
1703 switch (offset) {
1704 case 0x00: /* TIPB_CNTL */
1705 return s->control;
1706 case 0x04: /* TIPB_BUS_ALLOC */
1707 return s->alloc;
1708 case 0x08: /* MPU_TIPB_CNTL */
1709 return s->buffer;
1710 case 0x0c: /* ENHANCED_TIPB_CNTL */
1711 return s->enh_control;
1712 case 0x10: /* ADDRESS_DBG */
1713 case 0x14: /* DATA_DEBUG_LOW */
1714 case 0x18: /* DATA_DEBUG_HIGH */
1715 return 0xffff;
1716 case 0x1c: /* DEBUG_CNTR_SIG */
1717 return 0x00f8;
1718 }
1719
1720 OMAP_BAD_REG(addr);
1721 return 0;
1722 }
1723
1724 static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
1725 uint32_t value)
1726 {
1727 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
1728 int offset = addr - s->base;
1729
1730 switch (offset) {
1731 case 0x00: /* TIPB_CNTL */
1732 s->control = value & 0xffff;
1733 break;
1734
1735 case 0x04: /* TIPB_BUS_ALLOC */
1736 s->alloc = value & 0x003f;
1737 break;
1738
1739 case 0x08: /* MPU_TIPB_CNTL */
1740 s->buffer = value & 0x0003;
1741 break;
1742
1743 case 0x0c: /* ENHANCED_TIPB_CNTL */
1744 s->width_intr = !(value & 2);
1745 s->enh_control = value & 0x000f;
1746 break;
1747
1748 case 0x10: /* ADDRESS_DBG */
1749 case 0x14: /* DATA_DEBUG_LOW */
1750 case 0x18: /* DATA_DEBUG_HIGH */
1751 case 0x1c: /* DEBUG_CNTR_SIG */
1752 OMAP_RO_REG(addr);
1753 break;
1754
1755 default:
1756 OMAP_BAD_REG(addr);
1757 }
1758 }
1759
1760 static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
1761 omap_badwidth_read16,
1762 omap_tipb_bridge_read,
1763 omap_tipb_bridge_read,
1764 };
1765
1766 static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
1767 omap_badwidth_write16,
1768 omap_tipb_bridge_write,
1769 omap_tipb_bridge_write,
1770 };
1771
1772 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1773 {
1774 s->control = 0xffff;
1775 s->alloc = 0x0009;
1776 s->buffer = 0x0000;
1777 s->enh_control = 0x000f;
1778 }
1779
1780 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
1781 qemu_irq abort_irq, omap_clk clk)
1782 {
1783 int iomemtype;
1784 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
1785 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
1786
1787 s->abort = abort_irq;
1788 s->base = base;
1789 omap_tipb_bridge_reset(s);
1790
1791 iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
1792 omap_tipb_bridge_writefn, s);
1793 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1794
1795 return s;
1796 }
1797
1798 /* Dummy Traffic Controller's Memory Interface */
1799 static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
1800 {
1801 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1802 int offset = addr - s->tcmi_base;
1803 uint32_t ret;
1804
1805 switch (offset) {
1806 case 0x00: /* IMIF_PRIO */
1807 case 0x04: /* EMIFS_PRIO */
1808 case 0x08: /* EMIFF_PRIO */
1809 case 0x0c: /* EMIFS_CONFIG */
1810 case 0x10: /* EMIFS_CS0_CONFIG */
1811 case 0x14: /* EMIFS_CS1_CONFIG */
1812 case 0x18: /* EMIFS_CS2_CONFIG */
1813 case 0x1c: /* EMIFS_CS3_CONFIG */
1814 case 0x24: /* EMIFF_MRS */
1815 case 0x28: /* TIMEOUT1 */
1816 case 0x2c: /* TIMEOUT2 */
1817 case 0x30: /* TIMEOUT3 */
1818 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1819 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1820 return s->tcmi_regs[offset >> 2];
1821
1822 case 0x20: /* EMIFF_SDRAM_CONFIG */
1823 ret = s->tcmi_regs[offset >> 2];
1824 s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1825 /* XXX: We can try using the VGA_DIRTY flag for this */
1826 return ret;
1827 }
1828
1829 OMAP_BAD_REG(addr);
1830 return 0;
1831 }
1832
1833 static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
1834 uint32_t value)
1835 {
1836 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1837 int offset = addr - s->tcmi_base;
1838
1839 switch (offset) {
1840 case 0x00: /* IMIF_PRIO */
1841 case 0x04: /* EMIFS_PRIO */
1842 case 0x08: /* EMIFF_PRIO */
1843 case 0x10: /* EMIFS_CS0_CONFIG */
1844 case 0x14: /* EMIFS_CS1_CONFIG */
1845 case 0x18: /* EMIFS_CS2_CONFIG */
1846 case 0x1c: /* EMIFS_CS3_CONFIG */
1847 case 0x20: /* EMIFF_SDRAM_CONFIG */
1848 case 0x24: /* EMIFF_MRS */
1849 case 0x28: /* TIMEOUT1 */
1850 case 0x2c: /* TIMEOUT2 */
1851 case 0x30: /* TIMEOUT3 */
1852 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1853 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1854 s->tcmi_regs[offset >> 2] = value;
1855 break;
1856 case 0x0c: /* EMIFS_CONFIG */
1857 s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
1858 break;
1859
1860 default:
1861 OMAP_BAD_REG(addr);
1862 }
1863 }
1864
1865 static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
1866 omap_badwidth_read32,
1867 omap_badwidth_read32,
1868 omap_tcmi_read,
1869 };
1870
1871 static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
1872 omap_badwidth_write32,
1873 omap_badwidth_write32,
1874 omap_tcmi_write,
1875 };
1876
1877 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1878 {
1879 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1880 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1881 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1882 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1883 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1884 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1885 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1886 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1887 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1888 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1889 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1890 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1891 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1892 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1893 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1894 }
1895
1896 static void omap_tcmi_init(target_phys_addr_t base,
1897 struct omap_mpu_state_s *mpu)
1898 {
1899 int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
1900 omap_tcmi_writefn, mpu);
1901
1902 mpu->tcmi_base = base;
1903 cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
1904 omap_tcmi_reset(mpu);
1905 }
1906
1907 /* Digital phase-locked loops control */
1908 static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
1909 {
1910 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1911 int offset = addr - s->base;
1912
1913 if (offset == 0x00) /* CTL_REG */
1914 return s->mode;
1915
1916 OMAP_BAD_REG(addr);
1917 return 0;
1918 }
1919
1920 static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
1921 uint32_t value)
1922 {
1923 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1924 uint16_t diff;
1925 int offset = addr - s->base;
1926 static const int bypass_div[4] = { 1, 2, 4, 4 };
1927 int div, mult;
1928
1929 if (offset == 0x00) { /* CTL_REG */
1930 /* See omap_ulpd_pm_write() too */
1931 diff = s->mode & value;
1932 s->mode = value & 0x2fff;
1933 if (diff & (0x3ff << 2)) {
1934 if (value & (1 << 4)) { /* PLL_ENABLE */
1935 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1936 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1937 } else {
1938 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1939 mult = 1;
1940 }
1941 omap_clk_setrate(s->dpll, div, mult);
1942 }
1943
1944 /* Enter the desired mode. */
1945 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1946
1947 /* Act as if the lock is restored. */
1948 s->mode |= 2;
1949 } else {
1950 OMAP_BAD_REG(addr);
1951 }
1952 }
1953
1954 static CPUReadMemoryFunc *omap_dpll_readfn[] = {
1955 omap_badwidth_read16,
1956 omap_dpll_read,
1957 omap_badwidth_read16,
1958 };
1959
1960 static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
1961 omap_badwidth_write16,
1962 omap_dpll_write,
1963 omap_badwidth_write16,
1964 };
1965
1966 static void omap_dpll_reset(struct dpll_ctl_s *s)
1967 {
1968 s->mode = 0x2002;
1969 omap_clk_setrate(s->dpll, 1, 1);
1970 }
1971
1972 static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
1973 omap_clk clk)
1974 {
1975 int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
1976 omap_dpll_writefn, s);
1977
1978 s->base = base;
1979 s->dpll = clk;
1980 omap_dpll_reset(s);
1981
1982 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1983 }
1984
1985 /* UARTs */
1986 struct omap_uart_s {
1987 SerialState *serial; /* TODO */
1988 struct omap_target_agent_s *ta;
1989 target_phys_addr_t base;
1990 omap_clk fclk;
1991 qemu_irq irq;
1992
1993 uint8_t eblr;
1994 uint8_t syscontrol;
1995 uint8_t wkup;
1996 uint8_t cfps;
1997 uint8_t mdr[2];
1998 uint8_t scr;
1999 };
2000
2001 void omap_uart_reset(struct omap_uart_s *s)
2002 {
2003 s->eblr = 0x00;
2004 s->syscontrol = 0;
2005 s->wkup = 0x3f;
2006 s->cfps = 0x69;
2007 }
2008
2009 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
2010 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2011 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2012 {
2013 struct omap_uart_s *s = (struct omap_uart_s *)
2014 qemu_mallocz(sizeof(struct omap_uart_s));
2015
2016 s->base = base;
2017 s->fclk = fclk;
2018 s->irq = irq;
2019 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
2020 chr ?: qemu_chr_open("null", "null"), 1);
2021
2022 return s;
2023 }
2024
2025 static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
2026 {
2027 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
2028 int offset = addr - s->base;
2029
2030 switch (offset) {
2031 case 0x20: /* MDR1 */
2032 return s->mdr[0];
2033 case 0x24: /* MDR2 */
2034 return s->mdr[1];
2035 case 0x40: /* SCR */
2036 return s->scr;
2037 case 0x44: /* SSR */
2038 return 0x0;
2039 case 0x48: /* EBLR */
2040 return s->eblr;
2041 case 0x50: /* MVR */
2042 return 0x30;
2043 case 0x54: /* SYSC */
2044 return s->syscontrol;
2045 case 0x58: /* SYSS */
2046 return 1;
2047 case 0x5c: /* WER */
2048 return s->wkup;
2049 case 0x60: /* CFPS */
2050 return s->cfps;
2051 }
2052
2053 OMAP_BAD_REG(addr);
2054 return 0;
2055 }
2056
2057 static void omap_uart_write(void *opaque, target_phys_addr_t addr,
2058 uint32_t value)
2059 {
2060 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
2061 int offset = addr - s->base;
2062
2063 switch (offset) {
2064 case 0x20: /* MDR1 */
2065 s->mdr[0] = value & 0x7f;
2066 break;
2067 case 0x24: /* MDR2 */
2068 s->mdr[1] = value & 0xff;
2069 break;
2070 case 0x40: /* SCR */
2071 s->scr = value & 0xff;
2072 break;
2073 case 0x48: /* EBLR */
2074 s->eblr = value & 0xff;
2075 break;
2076 case 0x44: /* SSR */
2077 case 0x50: /* MVR */
2078 case 0x58: /* SYSS */
2079 OMAP_RO_REG(addr);
2080 break;
2081 case 0x54: /* SYSC */
2082 s->syscontrol = value & 0x1d;
2083 if (value & 2)
2084 omap_uart_reset(s);
2085 break;
2086 case 0x5c: /* WER */
2087 s->wkup = value & 0x7f;
2088 break;
2089 case 0x60: /* CFPS */
2090 s->cfps = value & 0xff;
2091 break;
2092 default:
2093 OMAP_BAD_REG(addr);
2094 }
2095 }
2096
2097 static CPUReadMemoryFunc *omap_uart_readfn[] = {
2098 omap_uart_read,
2099 omap_uart_read,
2100 omap_badwidth_read8,
2101 };
2102
2103 static CPUWriteMemoryFunc *omap_uart_writefn[] = {
2104 omap_uart_write,
2105 omap_uart_write,
2106 omap_badwidth_write8,
2107 };
2108
2109 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
2110 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2111 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2112 {
2113 target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
2114 struct omap_uart_s *s = omap_uart_init(base, irq,
2115 fclk, iclk, txdma, rxdma, chr);
2116 int iomemtype = cpu_register_io_memory(0, omap_uart_readfn,
2117 omap_uart_writefn, s);
2118
2119 s->ta = ta;
2120
2121 cpu_register_physical_memory(s->base + 0x20, 0x100, iomemtype);
2122
2123 return s;
2124 }
2125
2126 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
2127 {
2128 /* TODO: Should reuse or destroy current s->serial */
2129 s->serial = serial_mm_init(s->base, 2, s->irq,
2130 omap_clk_getrate(s->fclk) / 16,
2131 chr ?: qemu_chr_open("null", "null"), 1);
2132 }
2133
2134 /* MPU Clock/Reset/Power Mode Control */
2135 static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
2136 {
2137 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2138 int offset = addr - s->clkm.mpu_base;
2139
2140 switch (offset) {
2141 case 0x00: /* ARM_CKCTL */
2142 return s->clkm.arm_ckctl;
2143
2144 case 0x04: /* ARM_IDLECT1 */
2145 return s->clkm.arm_idlect1;
2146
2147 case 0x08: /* ARM_IDLECT2 */
2148 return s->clkm.arm_idlect2;
2149
2150 case 0x0c: /* ARM_EWUPCT */
2151 return s->clkm.arm_ewupct;
2152
2153 case 0x10: /* ARM_RSTCT1 */
2154 return s->clkm.arm_rstct1;
2155
2156 case 0x14: /* ARM_RSTCT2 */
2157 return s->clkm.arm_rstct2;
2158
2159 case 0x18: /* ARM_SYSST */
2160 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
2161
2162 case 0x1c: /* ARM_CKOUT1 */
2163 return s->clkm.arm_ckout1;
2164
2165 case 0x20: /* ARM_CKOUT2 */
2166 break;
2167 }
2168
2169 OMAP_BAD_REG(addr);
2170 return 0;
2171 }
2172
2173 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
2174 uint16_t diff, uint16_t value)
2175 {
2176 omap_clk clk;
2177
2178 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
2179 if (value & (1 << 14))
2180 /* Reserved */;
2181 else {
2182 clk = omap_findclk(s, "arminth_ck");
2183 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2184 }
2185 }
2186 if (diff & (1 << 12)) { /* ARM_TIMXO */
2187 clk = omap_findclk(s, "armtim_ck");
2188 if (value & (1 << 12))
2189 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
2190 else
2191 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2192 }
2193 /* XXX: en_dspck */
2194 if (diff & (3 << 10)) { /* DSPMMUDIV */
2195 clk = omap_findclk(s, "dspmmu_ck");
2196 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
2197 }
2198 if (diff & (3 << 8)) { /* TCDIV */
2199 clk = omap_findclk(s, "tc_ck");
2200 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
2201 }
2202 if (diff & (3 << 6)) { /* DSPDIV */
2203 clk = omap_findclk(s, "dsp_ck");
2204 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
2205 }
2206 if (diff & (3 << 4)) { /* ARMDIV */
2207 clk = omap_findclk(s, "arm_ck");
2208 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
2209 }
2210 if (diff & (3 << 2)) { /* LCDDIV */
2211 clk = omap_findclk(s, "lcd_ck");
2212 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
2213 }
2214 if (diff & (3 << 0)) { /* PERDIV */
2215 clk = omap_findclk(s, "armper_ck");
2216 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
2217 }
2218 }
2219
2220 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
2221 uint16_t diff, uint16_t value)
2222 {
2223 omap_clk clk;
2224
2225 if (value & (1 << 11)) /* SETARM_IDLE */
2226 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
2227 if (!(value & (1 << 10))) /* WKUP_MODE */
2228 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2229
2230 #define SET_CANIDLE(clock, bit) \
2231 if (diff & (1 << bit)) { \
2232 clk = omap_findclk(s, clock); \
2233 omap_clk_canidle(clk, (value >> bit) & 1); \
2234 }
2235 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2236 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2237 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2238 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2239 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2240 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2241 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2242 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2243 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2244 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2245 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2246 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2247 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2248 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2249 }
2250
2251 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
2252 uint16_t diff, uint16_t value)
2253 {
2254 omap_clk clk;
2255
2256 #define SET_ONOFF(clock, bit) \
2257 if (diff & (1 << bit)) { \
2258 clk = omap_findclk(s, clock); \
2259 omap_clk_onoff(clk, (value >> bit) & 1); \
2260 }
2261 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2262 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2263 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2264 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2265 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2266 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2267 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2268 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2269 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2270 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2271 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2272 }
2273
2274 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
2275 uint16_t diff, uint16_t value)
2276 {
2277 omap_clk clk;
2278
2279 if (diff & (3 << 4)) { /* TCLKOUT */
2280 clk = omap_findclk(s, "tclk_out");
2281 switch ((value >> 4) & 3) {
2282 case 1:
2283 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
2284 omap_clk_onoff(clk, 1);
2285 break;
2286 case 2:
2287 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2288 omap_clk_onoff(clk, 1);
2289 break;
2290 default:
2291 omap_clk_onoff(clk, 0);
2292 }
2293 }
2294 if (diff & (3 << 2)) { /* DCLKOUT */
2295 clk = omap_findclk(s, "dclk_out");
2296 switch ((value >> 2) & 3) {
2297 case 0:
2298 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
2299 break;
2300 case 1:
2301 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
2302 break;
2303 case 2:
2304 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
2305 break;
2306 case 3:
2307 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2308 break;
2309 }
2310 }
2311 if (diff & (3 << 0)) { /* ACLKOUT */
2312 clk = omap_findclk(s, "aclk_out");
2313 switch ((value >> 0) & 3) {
2314 case 1:
2315 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2316 omap_clk_onoff(clk, 1);
2317 break;
2318 case 2:
2319 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
2320 omap_clk_onoff(clk, 1);
2321 break;
2322 case 3:
2323 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2324 omap_clk_onoff(clk, 1);
2325 break;
2326 default:
2327 omap_clk_onoff(clk, 0);
2328 }
2329 }
2330 }
2331
2332 static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
2333 uint32_t value)
2334 {
2335 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2336 int offset = addr - s->clkm.mpu_base;
2337 uint16_t diff;
2338 omap_clk clk;
2339 static const char *clkschemename[8] = {
2340 "fully synchronous", "fully asynchronous", "synchronous scalable",
2341 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2342 };
2343
2344 switch (offset) {
2345 case 0x00: /* ARM_CKCTL */
2346 diff = s->clkm.arm_ckctl ^ value;
2347 s->clkm.arm_ckctl = value & 0x7fff;
2348 omap_clkm_ckctl_update(s, diff, value);
2349 return;
2350
2351 case 0x04: /* ARM_IDLECT1 */
2352 diff = s->clkm.arm_idlect1 ^ value;
2353 s->clkm.arm_idlect1 = value & 0x0fff;
2354 omap_clkm_idlect1_update(s, diff, value);
2355 return;
2356
2357 case 0x08: /* ARM_IDLECT2 */
2358 diff = s->clkm.arm_idlect2 ^ value;
2359 s->clkm.arm_idlect2 = value & 0x07ff;
2360 omap_clkm_idlect2_update(s, diff, value);
2361 return;
2362
2363 case 0x0c: /* ARM_EWUPCT */
2364 diff = s->clkm.arm_ewupct ^ value;
2365 s->clkm.arm_ewupct = value & 0x003f;
2366 return;
2367
2368 case 0x10: /* ARM_RSTCT1 */
2369 diff = s->clkm.arm_rstct1 ^ value;
2370 s->clkm.arm_rstct1 = value & 0x0007;
2371 if (value & 9) {
2372 qemu_system_reset_request();
2373 s->clkm.cold_start = 0xa;
2374 }
2375 if (diff & ~value & 4) { /* DSP_RST */
2376 omap_mpui_reset(s);
2377 omap_tipb_bridge_reset(s->private_tipb);
2378 omap_tipb_bridge_reset(s->public_tipb);
2379 }
2380 if (diff & 2) { /* DSP_EN */
2381 clk = omap_findclk(s, "dsp_ck");
2382 omap_clk_canidle(clk, (~value >> 1) & 1);
2383 }
2384 return;
2385
2386 case 0x14: /* ARM_RSTCT2 */
2387 s->clkm.arm_rstct2 = value & 0x0001;
2388 return;
2389
2390 case 0x18: /* ARM_SYSST */
2391 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
2392 s->clkm.clocking_scheme = (value >> 11) & 7;
2393 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
2394 clkschemename[s->clkm.clocking_scheme]);
2395 }
2396 s->clkm.cold_start &= value & 0x3f;
2397 return;
2398
2399 case 0x1c: /* ARM_CKOUT1 */
2400 diff = s->clkm.arm_ckout1 ^ value;
2401 s->clkm.arm_ckout1 = value & 0x003f;
2402 omap_clkm_ckout1_update(s, diff, value);
2403 return;
2404
2405 case 0x20: /* ARM_CKOUT2 */
2406 default:
2407 OMAP_BAD_REG(addr);
2408 }
2409 }
2410
2411 static CPUReadMemoryFunc *omap_clkm_readfn[] = {
2412 omap_badwidth_read16,
2413 omap_clkm_read,
2414 omap_badwidth_read16,
2415 };
2416
2417 static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
2418 omap_badwidth_write16,
2419 omap_clkm_write,
2420 omap_badwidth_write16,
2421 };
2422
2423 static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
2424 {
2425 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2426 int offset = addr - s->clkm.dsp_base;
2427
2428 switch (offset) {
2429 case 0x04: /* DSP_IDLECT1 */
2430 return s->clkm.dsp_idlect1;
2431
2432 case 0x08: /* DSP_IDLECT2 */
2433 return s->clkm.dsp_idlect2;
2434
2435 case 0x14: /* DSP_RSTCT2 */
2436 return s->clkm.dsp_rstct2;
2437
2438 case 0x18: /* DSP_SYSST */
2439 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
2440 (s->env->halted << 6); /* Quite useless... */
2441 }
2442
2443 OMAP_BAD_REG(addr);
2444 return 0;
2445 }
2446
2447 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
2448 uint16_t diff, uint16_t value)
2449 {
2450 omap_clk clk;
2451
2452 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2453 }
2454
2455 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
2456 uint16_t diff, uint16_t value)
2457 {
2458 omap_clk clk;
2459
2460 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2461 }
2462
2463 static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
2464 uint32_t value)
2465 {
2466 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2467 int offset = addr - s->clkm.dsp_base;
2468 uint16_t diff;
2469
2470 switch (offset) {
2471 case 0x04: /* DSP_IDLECT1 */
2472 diff = s->clkm.dsp_idlect1 ^ value;
2473 s->clkm.dsp_idlect1 = value & 0x01f7;
2474 omap_clkdsp_idlect1_update(s, diff, value);
2475 break;
2476
2477 case 0x08: /* DSP_IDLECT2 */
2478 s->clkm.dsp_idlect2 = value & 0x0037;
2479 diff = s->clkm.dsp_idlect1 ^ value;
2480 omap_clkdsp_idlect2_update(s, diff, value);
2481 break;
2482
2483 case 0x14: /* DSP_RSTCT2 */
2484 s->clkm.dsp_rstct2 = value & 0x0001;
2485 break;
2486
2487 case 0x18: /* DSP_SYSST */
2488 s->clkm.cold_start &= value & 0x3f;
2489 break;
2490
2491 default:
2492 OMAP_BAD_REG(addr);
2493 }
2494 }
2495
2496 static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
2497 omap_badwidth_read16,
2498 omap_clkdsp_read,
2499 omap_badwidth_read16,
2500 };
2501
2502 static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
2503 omap_badwidth_write16,
2504 omap_clkdsp_write,
2505 omap_badwidth_write16,
2506 };
2507
2508 static void omap_clkm_reset(struct omap_mpu_state_s *s)
2509 {
2510 if (s->wdt && s->wdt->reset)
2511 s->clkm.cold_start = 0x6;
2512 s->clkm.clocking_scheme = 0;
2513 omap_clkm_ckctl_update(s, ~0, 0x3000);
2514 s->clkm.arm_ckctl = 0x3000;
2515 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
2516 s->clkm.arm_idlect1 = 0x0400;
2517 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
2518 s->clkm.arm_idlect2 = 0x0100;
2519 s->clkm.arm_ewupct = 0x003f;
2520 s->clkm.arm_rstct1 = 0x0000;
2521 s->clkm.arm_rstct2 = 0x0000;
2522 s->clkm.arm_ckout1 = 0x0015;
2523 s->clkm.dpll1_mode = 0x2002;
2524 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
2525 s->clkm.dsp_idlect1 = 0x0040;
2526 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
2527 s->clkm.dsp_idlect2 = 0x0000;
2528 s->clkm.dsp_rstct2 = 0x0000;
2529 }
2530
2531 static void omap_clkm_init(target_phys_addr_t mpu_base,
2532 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
2533 {
2534 int iomemtype[2] = {
2535 cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
2536 cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
2537 };
2538
2539 s->clkm.mpu_base = mpu_base;
2540 s->clkm.dsp_base = dsp_base;
2541 s->clkm.arm_idlect1 = 0x03ff;
2542 s->clkm.arm_idlect2 = 0x0100;
2543 s->clkm.dsp_idlect1 = 0x0002;
2544 omap_clkm_reset(s);
2545 s->clkm.cold_start = 0x3a;
2546
2547 cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
2548 cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
2549 }
2550
2551 /* MPU I/O */
2552 struct omap_mpuio_s {
2553 target_phys_addr_t base;
2554 qemu_irq irq;
2555 qemu_irq kbd_irq;
2556 qemu_irq *in;
2557 qemu_irq handler[16];
2558 qemu_irq wakeup;
2559
2560 uint16_t inputs;
2561 uint16_t outputs;
2562 uint16_t dir;
2563 uint16_t edge;
2564 uint16_t mask;
2565 uint16_t ints;
2566
2567 uint16_t debounce;
2568 uint16_t latch;
2569 uint8_t event;
2570
2571 uint8_t buttons[5];
2572 uint8_t row_latch;
2573 uint8_t cols;
2574 int kbd_mask;
2575 int clk;
2576 };
2577
2578 static void omap_mpuio_set(void *opaque, int line, int level)
2579 {
2580 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2581 uint16_t prev = s->inputs;
2582
2583 if (level)
2584 s->inputs |= 1 << line;
2585 else
2586 s->inputs &= ~(1 << line);
2587
2588 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
2589 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
2590 s->ints |= 1 << line;
2591 qemu_irq_raise(s->irq);
2592 /* TODO: wakeup */
2593 }
2594 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2595 (s->event >> 1) == line) /* PIN_SELECT */
2596 s->latch = s->inputs;
2597 }
2598 }
2599
2600 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
2601 {
2602 int i;
2603 uint8_t *row, rows = 0, cols = ~s->cols;
2604
2605 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
2606 if (*row & cols)
2607 rows |= i;
2608
2609 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
2610 s->row_latch = ~rows;
2611 }
2612
2613 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
2614 {
2615 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2616 int offset = addr & OMAP_MPUI_REG_MASK;
2617 uint16_t ret;
2618
2619 switch (offset) {
2620 case 0x00: /* INPUT_LATCH */
2621 return s->inputs;
2622
2623 case 0x04: /* OUTPUT_REG */
2624 return s->outputs;
2625
2626 case 0x08: /* IO_CNTL */
2627 return s->dir;
2628
2629 case 0x10: /* KBR_LATCH */
2630 return s->row_latch;
2631
2632 case 0x14: /* KBC_REG */
2633 return s->cols;
2634
2635 case 0x18: /* GPIO_EVENT_MODE_REG */
2636 return s->event;
2637
2638 case 0x1c: /* GPIO_INT_EDGE_REG */
2639 return s->edge;
2640
2641 case 0x20: /* KBD_INT */
2642 return (~s->row_latch & 0x1f) && !s->kbd_mask;
2643
2644 case 0x24: /* GPIO_INT */
2645 ret = s->ints;
2646 s->ints &= s->mask;
2647 if (ret)
2648 qemu_irq_lower(s->irq);
2649 return ret;
2650
2651 case 0x28: /* KBD_MASKIT */
2652 return s->kbd_mask;
2653
2654 case 0x2c: /* GPIO_MASKIT */
2655 return s->mask;
2656
2657 case 0x30: /* GPIO_DEBOUNCING_REG */
2658 return s->debounce;
2659
2660 case 0x34: /* GPIO_LATCH_REG */
2661 return s->latch;
2662 }
2663
2664 OMAP_BAD_REG(addr);
2665 return 0;
2666 }
2667
2668 static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
2669 uint32_t value)
2670 {
2671 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2672 int offset = addr & OMAP_MPUI_REG_MASK;
2673 uint16_t diff;
2674 int ln;
2675
2676 switch (offset) {
2677 case 0x04: /* OUTPUT_REG */
2678 diff = (s->outputs ^ value) & ~s->dir;
2679 s->outputs = value;
2680 while ((ln = ffs(diff))) {
2681 ln --;
2682 if (s->handler[ln])
2683 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2684 diff &= ~(1 << ln);
2685 }
2686 break;
2687
2688 case 0x08: /* IO_CNTL */
2689 diff = s->outputs & (s->dir ^ value);
2690 s->dir = value;
2691
2692 value = s->outputs & ~s->dir;
2693 while ((ln = ffs(diff))) {
2694 ln --;
2695 if (s->handler[ln])
2696 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2697 diff &= ~(1 << ln);
2698 }
2699 break;
2700
2701 case 0x14: /* KBC_REG */
2702 s->cols = value;
2703 omap_mpuio_kbd_update(s);
2704 break;
2705
2706 case 0x18: /* GPIO_EVENT_MODE_REG */
2707 s->event = value & 0x1f;
2708 break;
2709
2710 case 0x1c: /* GPIO_INT_EDGE_REG */
2711 s->edge = value;
2712 break;
2713
2714 case 0x28: /* KBD_MASKIT */
2715 s->kbd_mask = value & 1;
2716 omap_mpuio_kbd_update(s);
2717 break;
2718
2719 case 0x2c: /* GPIO_MASKIT */
2720 s->mask = value;
2721 break;
2722
2723 case 0x30: /* GPIO_DEBOUNCING_REG */
2724 s->debounce = value & 0x1ff;
2725 break;
2726
2727 case 0x00: /* INPUT_LATCH */
2728 case 0x10: /* KBR_LATCH */
2729 case 0x20: /* KBD_INT */
2730 case 0x24: /* GPIO_INT */
2731 case 0x34: /* GPIO_LATCH_REG */
2732 OMAP_RO_REG(addr);
2733 return;
2734
2735 default:
2736 OMAP_BAD_REG(addr);
2737 return;
2738 }
2739 }
2740
2741 static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
2742 omap_badwidth_read16,
2743 omap_mpuio_read,
2744 omap_badwidth_read16,
2745 };
2746
2747 static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
2748 omap_badwidth_write16,
2749 omap_mpuio_write,
2750 omap_badwidth_write16,
2751 };
2752
2753 static void omap_mpuio_reset(struct omap_mpuio_s *s)
2754 {
2755 s->inputs = 0;
2756 s->outputs = 0;
2757 s->dir = ~0;
2758 s->event = 0;
2759 s->edge = 0;
2760 s->kbd_mask = 0;
2761 s->mask = 0;
2762 s->debounce = 0;
2763 s->latch = 0;
2764 s->ints = 0;
2765 s->row_latch = 0x1f;
2766 s->clk = 1;
2767 }
2768
2769 static void omap_mpuio_onoff(void *opaque, int line, int on)
2770 {
2771 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2772
2773 s->clk = on;
2774 if (on)
2775 omap_mpuio_kbd_update(s);
2776 }
2777
2778 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
2779 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2780 omap_clk clk)
2781 {
2782 int iomemtype;
2783 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
2784 qemu_mallocz(sizeof(struct omap_mpuio_s));
2785
2786 s->base = base;
2787 s->irq = gpio_int;
2788 s->kbd_irq = kbd_int;
2789 s->wakeup = wakeup;
2790 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2791 omap_mpuio_reset(s);
2792
2793 iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn,
2794 omap_mpuio_writefn, s);
2795 cpu_register_physical_memory(s->base, 0x800, iomemtype);
2796
2797 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2798
2799 return s;
2800 }
2801
2802 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2803 {
2804 return s->in;
2805 }
2806
2807 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2808 {
2809 if (line >= 16 || line < 0)
2810 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
2811 s->handler[line] = handler;
2812 }
2813
2814 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2815 {
2816 if (row >= 5 || row < 0)
2817 cpu_abort(cpu_single_env, "%s: No key %i-%i\n",
2818 __FUNCTION__, col, row);
2819
2820 if (down)
2821 s->buttons[row] |= 1 << col;
2822 else
2823 s->buttons[row] &= ~(1 << col);
2824
2825 omap_mpuio_kbd_update(s);
2826 }
2827
2828 /* General-Purpose I/O */
2829 struct omap_gpio_s {
2830 target_phys_addr_t base;
2831 qemu_irq irq;
2832 qemu_irq *in;
2833 qemu_irq handler[16];
2834
2835 uint16_t inputs;
2836 uint16_t outputs;
2837 uint16_t dir;
2838 uint16_t edge;
2839 uint16_t mask;
2840 uint16_t ints;
2841 uint16_t pins;
2842 };
2843
2844 static void omap_gpio_set(void *opaque, int line, int level)
2845 {
2846 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2847 uint16_t prev = s->inputs;
2848
2849 if (level)
2850 s->inputs |= 1 << line;
2851 else
2852 s->inputs &= ~(1 << line);
2853
2854 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
2855 (1 << line) & s->dir & ~s->mask) {
2856 s->ints |= 1 << line;
2857 qemu_irq_raise(s->irq);
2858 }
2859 }
2860
2861 static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
2862 {
2863 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2864 int offset = addr & OMAP_MPUI_REG_MASK;
2865
2866 switch (offset) {
2867 case 0x00: /* DATA_INPUT */
2868 return s->inputs & s->pins;
2869
2870 case 0x04: /* DATA_OUTPUT */
2871 return s->outputs;
2872
2873 case 0x08: /* DIRECTION_CONTROL */
2874 return s->dir;
2875
2876 case 0x0c: /* INTERRUPT_CONTROL */
2877 return s->edge;
2878
2879 case 0x10: /* INTERRUPT_MASK */
2880 return s->mask;
2881
2882 case 0x14: /* INTERRUPT_STATUS */
2883 return s->ints;
2884
2885 case 0x18: /* PIN_CONTROL (not in OMAP310) */
2886 OMAP_BAD_REG(addr);
2887 return s->pins;
2888 }
2889
2890 OMAP_BAD_REG(addr);
2891 return 0;
2892 }
2893
2894 static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
2895 uint32_t value)
2896 {
2897 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
2898 int offset = addr & OMAP_MPUI_REG_MASK;
2899 uint16_t diff;
2900 int ln;
2901
2902 switch (offset) {
2903 case 0x00: /* DATA_INPUT */
2904 OMAP_RO_REG(addr);
2905 return;
2906
2907 case 0x04: /* DATA_OUTPUT */
2908 diff = (s->outputs ^ value) & ~s->dir;
2909 s->outputs = value;
2910 while ((ln = ffs(diff))) {
2911 ln --;
2912 if (s->handler[ln])
2913 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2914 diff &= ~(1 << ln);
2915 }
2916 break;
2917
2918 case 0x08: /* DIRECTION_CONTROL */
2919 diff = s->outputs & (s->dir ^ value);
2920 s->dir = value;
2921
2922 value = s->outputs & ~s->dir;
2923 while ((ln = ffs(diff))) {
2924 ln --;
2925 if (s->handler[ln])
2926 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2927 diff &= ~(1 << ln);
2928 }
2929 break;
2930
2931 case 0x0c: /* INTERRUPT_CONTROL */
2932 s->edge = value;
2933 break;
2934
2935 case 0x10: /* INTERRUPT_MASK */
2936 s->mask = value;
2937 break;
2938
2939 case 0x14: /* INTERRUPT_STATUS */
2940 s->ints &= ~value;
2941 if (!s->ints)
2942 qemu_irq_lower(s->irq);
2943 break;
2944
2945 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
2946 OMAP_BAD_REG(addr);
2947 s->pins = value;
2948 break;
2949
2950 default:
2951 OMAP_BAD_REG(addr);
2952 return;
2953 }
2954 }
2955
2956 /* *Some* sources say the memory region is 32-bit. */
2957 static CPUReadMemoryFunc *omap_gpio_readfn[] = {
2958 omap_badwidth_read16,
2959 omap_gpio_read,
2960 omap_badwidth_read16,
2961 };
2962
2963 static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
2964 omap_badwidth_write16,
2965 omap_gpio_write,
2966 omap_badwidth_write16,
2967 };
2968
2969 static void omap_gpio_reset(struct omap_gpio_s *s)
2970 {
2971 s->inputs = 0;
2972 s->outputs = ~0;
2973 s->dir = ~0;
2974 s->edge = ~0;
2975 s->mask = ~0;
2976 s->ints = 0;
2977 s->pins = ~0;
2978 }
2979
2980 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
2981 qemu_irq irq, omap_clk clk)
2982 {
2983 int iomemtype;
2984 struct omap_gpio_s *s = (struct omap_gpio_s *)
2985 qemu_mallocz(sizeof(struct omap_gpio_s));
2986
2987 s->base = base;
2988 s->irq = irq;
2989 s->in = qemu_allocate_irqs(omap_gpio_set, s, 16);
2990 omap_gpio_reset(s);
2991
2992 iomemtype = cpu_register_io_memory(0, omap_gpio_readfn,
2993 omap_gpio_writefn, s);
2994 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
2995
2996 return s;
2997 }
2998
2999 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s)
3000 {
3001 return s->in;
3002 }
3003
3004 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler)
3005 {
3006 if (line >= 16 || line < 0)
3007 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
3008 s->handler[line] = handler;
3009 }
3010
3011 /* MicroWire Interface */
3012 struct omap_uwire_s {
3013 target_phys_addr_t base;
3014 qemu_irq txirq;
3015 qemu_irq rxirq;
3016 qemu_irq txdrq;
3017
3018 uint16_t txbuf;
3019 uint16_t rxbuf;
3020 uint16_t control;
3021 uint16_t setup[5];
3022
3023 struct uwire_slave_s *chip[4];
3024 };
3025
3026 static void omap_uwire_transfer_start(struct omap_uwire_s *s)
3027 {
3028 int chipselect = (s->control >> 10) & 3; /* INDEX */
3029 struct uwire_slave_s *slave = s->chip[chipselect];
3030
3031 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
3032 if (s->control & (1 << 12)) /* CS_CMD */
3033 if (slave && slave->send)
3034 slave->send(slave->opaque,
3035 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
3036 s->control &= ~(1 << 14); /* CSRB */
3037 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3038 * a DRQ. When is the level IRQ supposed to be reset? */
3039 }
3040
3041 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
3042 if (s->control & (1 << 12)) /* CS_CMD */
3043 if (slave && slave->receive)
3044 s->rxbuf = slave->receive(slave->opaque);
3045 s->control |= 1 << 15; /* RDRB */
3046 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3047 * a DRQ. When is the level IRQ supposed to be reset? */
3048 }
3049 }
3050
3051 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
3052 {
3053 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3054 int offset = addr & OMAP_MPUI_REG_MASK;
3055
3056 switch (offset) {
3057 case 0x00: /* RDR */
3058 s->control &= ~(1 << 15); /* RDRB */
3059 return s->rxbuf;
3060
3061 case 0x04: /* CSR */
3062 return s->control;
3063
3064 case 0x08: /* SR1 */
3065 return s->setup[0];
3066 case 0x0c: /* SR2 */
3067 return s->setup[1];
3068 case 0x10: /* SR3 */
3069 return s->setup[2];
3070 case 0x14: /* SR4 */
3071 return s->setup[3];
3072 case 0x18: /* SR5 */
3073 return s->setup[4];
3074 }
3075
3076 OMAP_BAD_REG(addr);
3077 return 0;
3078 }
3079
3080 static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
3081 uint32_t value)
3082 {
3083 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
3084 int offset = addr & OMAP_MPUI_REG_MASK;
3085
3086 switch (offset) {
3087 case 0x00: /* TDR */
3088 s->txbuf = value; /* TD */
3089 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
3090 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
3091 (s->control & (1 << 12)))) { /* CS_CMD */
3092 s->control |= 1 << 14; /* CSRB */
3093 omap_uwire_transfer_start(s);
3094 }
3095 break;
3096
3097 case 0x04: /* CSR */
3098 s->control = value & 0x1fff;
3099 if (value & (1 << 13)) /* START */
3100 omap_uwire_transfer_start(s);
3101 break;
3102
3103 case 0x08: /* SR1 */
3104 s->setup[0] = value & 0x003f;
3105 break;
3106
3107 case 0x0c: /* SR2 */
3108 s->setup[1] = value & 0x0fc0;
3109 break;
3110
3111 case 0x10: /* SR3 */
3112 s->setup[2] = value & 0x0003;
3113 break;
3114
3115 case 0x14: /* SR4 */
3116 s->setup[3] = value & 0x0001;
3117 break;
3118
3119 case 0x18: /* SR5 */
3120 s->setup[4] = value & 0x000f;
3121 break;
3122
3123 default:
3124 OMAP_BAD_REG(addr);
3125 return;
3126 }
3127 }
3128
3129 static CPUReadMemoryFunc *omap_uwire_readfn[] = {
3130 omap_badwidth_read16,
3131 omap_uwire_read,
3132 omap_badwidth_read16,
3133 };
3134
3135 static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
3136 omap_badwidth_write16,
3137 omap_uwire_write,
3138 omap_badwidth_write16,
3139 };
3140
3141 static void omap_uwire_reset(struct omap_uwire_s *s)
3142 {
3143 s->control = 0;
3144 s->setup[0] = 0;
3145 s->setup[1] = 0;
3146 s->setup[2] = 0;
3147 s->setup[3] = 0;
3148 s->setup[4] = 0;
3149 }
3150
3151 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
3152 qemu_irq *irq, qemu_irq dma, omap_clk clk)
3153 {
3154 int iomemtype;
3155 struct omap_uwire_s *s = (struct omap_uwire_s *)
3156 qemu_mallocz(sizeof(struct omap_uwire_s));
3157
3158 s->base = base;
3159 s->txirq = irq[0];
3160 s->rxirq = irq[1];
3161 s->txdrq = dma;
3162 omap_uwire_reset(s);
3163
3164 iomemtype = cpu_register_io_memory(0, omap_uwire_readfn,
3165 omap_uwire_writefn, s);
3166 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3167
3168 return s;
3169 }
3170
3171 void omap_uwire_attach(struct omap_uwire_s *s,
3172 struct uwire_slave_s *slave, int chipselect)
3173 {
3174 if (chipselect < 0 || chipselect > 3) {
3175 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
3176 exit(-1);
3177 }
3178
3179 s->chip[chipselect] = slave;
3180 }
3181
3182 /* Pseudonoise Pulse-Width Light Modulator */
3183 static void omap_pwl_update(struct omap_mpu_state_s *s)
3184 {
3185 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
3186
3187 if (output != s->pwl.output) {
3188 s->pwl.output = output;
3189 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
3190 }
3191 }
3192
3193 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
3194 {
3195 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3196 int offset = addr & OMAP_MPUI_REG_MASK;
3197
3198 switch (offset) {
3199 case 0x00: /* PWL_LEVEL */
3200 return s->pwl.level;
3201 case 0x04: /* PWL_CTRL */
3202 return s->pwl.enable;
3203 }
3204 OMAP_BAD_REG(addr);
3205 return 0;
3206 }
3207
3208 static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
3209 uint32_t value)
3210 {
3211 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3212 int offset = addr & OMAP_MPUI_REG_MASK;
3213
3214 switch (offset) {
3215 case 0x00: /* PWL_LEVEL */
3216 s->pwl.level = value;
3217 omap_pwl_update(s);
3218 break;
3219 case 0x04: /* PWL_CTRL */
3220 s->pwl.enable = value & 1;
3221 omap_pwl_update(s);
3222 break;
3223 default:
3224 OMAP_BAD_REG(addr);
3225 return;
3226 }
3227 }
3228
3229 static CPUReadMemoryFunc *omap_pwl_readfn[] = {
3230 omap_pwl_read,
3231 omap_badwidth_read8,
3232 omap_badwidth_read8,
3233 };
3234
3235 static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
3236 omap_pwl_write,
3237 omap_badwidth_write8,
3238 omap_badwidth_write8,
3239 };
3240
3241 static void omap_pwl_reset(struct omap_mpu_state_s *s)
3242 {
3243 s->pwl.output = 0;
3244 s->pwl.level = 0;
3245 s->pwl.enable = 0;
3246 s->pwl.clk = 1;
3247 omap_pwl_update(s);
3248 }
3249
3250 static void omap_pwl_clk_update(void *opaque, int line, int on)
3251 {
3252 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3253
3254 s->pwl.clk = on;
3255 omap_pwl_update(s);
3256 }
3257
3258 static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3259 omap_clk clk)
3260 {
3261 int iomemtype;
3262
3263 omap_pwl_reset(s);
3264
3265 iomemtype = cpu_register_io_memory(0, omap_pwl_readfn,
3266 omap_pwl_writefn, s);
3267 cpu_register_physical_memory(base, 0x800, iomemtype);
3268
3269 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
3270 }
3271
3272 /* Pulse-Width Tone module */
3273 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
3274 {
3275 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3276 int offset = addr & OMAP_MPUI_REG_MASK;
3277
3278 switch (offset) {
3279 case 0x00: /* FRC */
3280 return s->pwt.frc;
3281 case 0x04: /* VCR */
3282 return s->pwt.vrc;
3283 case 0x08: /* GCR */
3284 return s->pwt.gcr;
3285 }
3286 OMAP_BAD_REG(addr);
3287 return 0;
3288 }
3289
3290 static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
3291 uint32_t value)
3292 {
3293 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3294 int offset = addr & OMAP_MPUI_REG_MASK;
3295
3296 switch (offset) {
3297 case 0x00: /* FRC */
3298 s->pwt.frc = value & 0x3f;
3299 break;
3300 case 0x04: /* VRC */
3301 if ((value ^ s->pwt.vrc) & 1) {
3302 if (value & 1)
3303 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
3304 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3305 ((omap_clk_getrate(s->pwt.clk) >> 3) /
3306 /* Pre-multiplexer divider */
3307 ((s->pwt.gcr & 2) ? 1 : 154) /
3308 /* Octave multiplexer */
3309 (2 << (value & 3)) *
3310 /* 101/107 divider */
3311 ((value & (1 << 2)) ? 101 : 107) *
3312 /* 49/55 divider */
3313 ((value & (1 << 3)) ? 49 : 55) *
3314 /* 50/63 divider */
3315 ((value & (1 << 4)) ? 50 : 63) *
3316 /* 80/127 divider */
3317 ((value & (1 << 5)) ? 80 : 127) /
3318 (107 * 55 * 63 * 127)));
3319 else
3320 printf("%s: silence!\n", __FUNCTION__);
3321 }
3322 s->pwt.vrc = value & 0x7f;
3323 break;
3324 case 0x08: /* GCR */
3325 s->pwt.gcr = value & 3;
3326 break;
3327 default:
3328 OMAP_BAD_REG(addr);
3329 return;
3330 }
3331 }
3332
3333 static CPUReadMemoryFunc *omap_pwt_readfn[] = {
3334 omap_pwt_read,
3335 omap_badwidth_read8,
3336 omap_badwidth_read8,
3337 };
3338
3339 static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
3340 omap_pwt_write,
3341 omap_badwidth_write8,
3342 omap_badwidth_write8,
3343 };
3344
3345 static void omap_pwt_reset(struct omap_mpu_state_s *s)
3346 {
3347 s->pwt.frc = 0;
3348 s->pwt.vrc = 0;
3349 s->pwt.gcr = 0;
3350 }
3351
3352 static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
3353 omap_clk clk)
3354 {
3355 int iomemtype;
3356
3357 s->pwt.clk = clk;
3358 omap_pwt_reset(s);
3359
3360 iomemtype = cpu_register_io_memory(0, omap_pwt_readfn,
3361 omap_pwt_writefn, s);
3362 cpu_register_physical_memory(base, 0x800, iomemtype);
3363 }
3364
3365 /* Real-time Clock module */
3366 struct omap_rtc_s {
3367 target_phys_addr_t base;
3368 qemu_irq irq;
3369 qemu_irq alarm;
3370 QEMUTimer *clk;
3371
3372 uint8_t interrupts;
3373 uint8_t status;
3374 int16_t comp_reg;
3375 int running;
3376 int pm_am;
3377 int auto_comp;
3378 int round;
3379 struct tm alarm_tm;
3380 time_t alarm_ti;
3381
3382 struct tm current_tm;
3383 time_t ti;
3384 uint64_t tick;
3385 };
3386
3387 static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
3388 {
3389 /* s->alarm is level-triggered */
3390 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
3391 }
3392
3393 static void omap_rtc_alarm_update(struct omap_rtc_s *s)
3394 {
3395 s->alarm_ti = mktime(&s->alarm_tm);
3396 if (s->alarm_ti == -1)
3397 printf("%s: conversion failed\n", __FUNCTION__);
3398 }
3399
3400 static inline uint8_t omap_rtc_bcd(int num)
3401 {
3402 return ((num / 10) << 4) | (num % 10);
3403 }
3404
3405 static inline int omap_rtc_bin(uint8_t num)
3406 {
3407 return (num & 15) + 10 * (num >> 4);
3408 }
3409
3410 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
3411 {
3412 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3413 int offset = addr & OMAP_MPUI_REG_MASK;
3414 uint8_t i;
3415
3416 switch (offset) {
3417 case 0x00: /* SECONDS_REG */
3418 return omap_rtc_bcd(s->current_tm.tm_sec);
3419
3420 case 0x04: /* MINUTES_REG */
3421 return omap_rtc_bcd(s->current_tm.tm_min);
3422
3423 case 0x08: /* HOURS_REG */
3424 if (s->pm_am)
3425 return ((s->current_tm.tm_hour > 11) << 7) |
3426 omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
3427 else
3428 return omap_rtc_bcd(s->current_tm.tm_hour);
3429
3430 case 0x0c: /* DAYS_REG */
3431 return omap_rtc_bcd(s->current_tm.tm_mday);
3432
3433 case 0x10: /* MONTHS_REG */
3434 return omap_rtc_bcd(s->current_tm.tm_mon + 1);
3435
3436 case 0x14: /* YEARS_REG */
3437 return omap_rtc_bcd(s->current_tm.tm_year % 100);
3438
3439 case 0x18: /* WEEK_REG */
3440 return s->current_tm.tm_wday;
3441
3442 case 0x20: /* ALARM_SECONDS_REG */
3443 return omap_rtc_bcd(s->alarm_tm.tm_sec);
3444
3445 case 0x24: /* ALARM_MINUTES_REG */
3446 return omap_rtc_bcd(s->alarm_tm.tm_min);
3447
3448 case 0x28: /* ALARM_HOURS_REG */
3449 if (s->pm_am)
3450 return ((s->alarm_tm.tm_hour > 11) << 7) |
3451 omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
3452 else
3453 return omap_rtc_bcd(s->alarm_tm.tm_hour);
3454
3455 case 0x2c: /* ALARM_DAYS_REG */
3456 return omap_rtc_bcd(s->alarm_tm.tm_mday);
3457
3458 case 0x30: /* ALARM_MONTHS_REG */
3459 return omap_rtc_bcd(s->alarm_tm.tm_mon + 1);
3460
3461 case 0x34: /* ALARM_YEARS_REG */
3462 return omap_rtc_bcd(s->alarm_tm.tm_year % 100);
3463
3464 case 0x40: /* RTC_CTRL_REG */
3465 return (s->pm_am << 3) | (s->auto_comp << 2) |
3466 (s->round << 1) | s->running;
3467
3468 case 0x44: /* RTC_STATUS_REG */
3469 i = s->status;
3470 s->status &= ~0x3d;
3471 return i;
3472
3473 case 0x48: /* RTC_INTERRUPTS_REG */
3474 return s->interrupts;
3475
3476 case 0x4c: /* RTC_COMP_LSB_REG */
3477 return ((uint16_t) s->comp_reg) & 0xff;
3478
3479 case 0x50: /* RTC_COMP_MSB_REG */
3480 return ((uint16_t) s->comp_reg) >> 8;
3481 }
3482
3483 OMAP_BAD_REG(addr);
3484 return 0;
3485 }
3486
3487 static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
3488 uint32_t value)
3489 {
3490 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
3491 int offset = addr & OMAP_MPUI_REG_MASK;
3492 struct tm new_tm;
3493 time_t ti[2];
3494
3495 switch (offset) {
3496 case 0x00: /* SECONDS_REG */
3497 #ifdef ALMDEBUG
3498 printf("RTC SEC_REG <-- %02x\n", value);
3499 #endif
3500 s->ti -= s->current_tm.tm_sec;
3501 s->ti += omap_rtc_bin(value);
3502 return;
3503
3504 case 0x04: /* MINUTES_REG */
3505 #ifdef ALMDEBUG
3506 printf("RTC MIN_REG <-- %02x\n", value);
3507 #endif
3508 s->ti -= s->current_tm.tm_min * 60;
3509 s->ti += omap_rtc_bin(value) * 60;
3510 return;
3511
3512 case 0x08: /* HOURS_REG */
3513 #ifdef ALMDEBUG
3514 printf("RTC HRS_REG <-- %02x\n", value);
3515 #endif
3516 s->ti -= s->current_tm.tm_hour * 3600;
3517 if (s->pm_am) {
3518 s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600;
3519 s->ti += ((value >> 7) & 1) * 43200;
3520 } else
3521 s->ti += omap_rtc_bin(value & 0x3f) * 3600;
3522 return;
3523
3524 case 0x0c: /* DAYS_REG */
3525 #ifdef ALMDEBUG
3526 printf("RTC DAY_REG <-- %02x\n", value);
3527 #endif
3528 s->ti -= s->current_tm.tm_mday * 86400;
3529 s->ti += omap_rtc_bin(value) * 86400;
3530 return;
3531
3532 case 0x10: /* MONTHS_REG */
3533 #ifdef ALMDEBUG
3534 printf("RTC MTH_REG <-- %02x\n", value);
3535 #endif
3536 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3537 new_tm.tm_mon = omap_rtc_bin(value);
3538 ti[0] = mktime(&s->current_tm);
3539 ti[1] = mktime(&new_tm);
3540
3541 if (ti[0] != -1 && ti[1] != -1) {
3542 s->ti -= ti[0];
3543 s->ti += ti[1];
3544 } else {
3545 /* A less accurate version */
3546 s->ti -= s->current_tm.tm_mon * 2592000;
3547 s->ti += omap_rtc_bin(value) * 2592000;
3548 }
3549 return;
3550
3551 case 0x14: /* YEARS_REG */
3552 #ifdef ALMDEBUG
3553 printf("RTC YRS_REG <-- %02x\n", value);
3554 #endif
3555 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
3556 new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100);
3557 ti[0] = mktime(&s->current_tm);
3558 ti[1] = mktime(&new_tm);
3559
3560 if (ti[0] != -1 && ti[1] != -1) {
3561 s->ti -= ti[0];
3562 s->ti += ti[1];
3563 } else {
3564 /* A less accurate version */
3565 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
3566 s->ti += omap_rtc_bin(value) * 31536000;
3567 }
3568 return;
3569
3570 case 0x18: /* WEEK_REG */
3571 return; /* Ignored */
3572
3573 case 0x20: /* ALARM_SECONDS_REG */
3574 #ifdef ALMDEBUG
3575 printf("ALM SEC_REG <-- %02x\n", value);
3576 #endif
3577 s->alarm_tm.tm_sec = omap_rtc_bin(value);
3578 omap_rtc_alarm_update(s);
3579 return;
3580
3581 case 0x24: /* ALARM_MINUTES_REG */
3582 #ifdef ALMDEBUG
3583 printf("ALM MIN_REG <-- %02x\n", value);
3584 #endif
3585 s->alarm_tm.tm_min = omap_rtc_bin(value);
3586 omap_rtc_alarm_update(s);
3587 return;
3588
3589 case 0x28: /* ALARM_HOURS_REG */
3590 #ifdef ALMDEBUG
3591 printf("ALM HRS_REG <-- %02x\n", value);
3592 #endif
3593 if (s->pm_am)
3594 s->alarm_tm.tm_hour =
3595 ((omap_rtc_bin(value & 0x3f)) % 12) +
3596 ((value >> 7) & 1) * 12;
3597 else
3598 s->alarm_tm.tm_hour = omap_rtc_bin(value);
3599 omap_rtc_alarm_update(s);
3600 return;
3601
3602 case 0x2c: /* ALARM_DAYS_REG */
3603 #ifdef ALMDEBUG
3604 printf("ALM DAY_REG <-- %02x\n", value);
3605 #endif
3606 s->alarm_tm.tm_mday = omap_rtc_bin(value);
3607 omap_rtc_alarm_update(s);
3608 return;
3609
3610 case 0x30: /* ALARM_MONTHS_REG */
3611 #ifdef ALMDEBUG
3612 printf("ALM MON_REG <-- %02x\n", value);
3613 #endif
3614 s->alarm_tm.tm_mon = omap_rtc_bin(value);
3615 omap_rtc_alarm_update(s);
3616 return;
3617
3618 case 0x34: /* ALARM_YEARS_REG */
3619 #ifdef ALMDEBUG
3620 printf("ALM YRS_REG <-- %02x\n", value);
3621 #endif
3622 s->alarm_tm.tm_year = omap_rtc_bin(value);
3623 omap_rtc_alarm_update(s);
3624 return;
3625
3626 case 0x40: /* RTC_CTRL_REG */
3627 #ifdef ALMDEBUG
3628 printf("RTC CONTROL <-- %02x\n", value);
3629 #endif
3630 s->pm_am = (value >> 3) & 1;
3631 s->auto_comp = (value >> 2) & 1;
3632 s->round = (value >> 1) & 1;
3633 s->running = value & 1;
3634 s->status &= 0xfd;
3635 s->status |= s->running << 1;
3636 return;
3637
3638 case 0x44: /* RTC_STATUS_REG */
3639 #ifdef ALMDEBUG
3640 printf("RTC STATUSL <-- %02x\n", value);
3641 #endif
3642 s->status &= ~((value & 0xc0) ^ 0x80);
3643 omap_rtc_interrupts_update(s);
3644 return;
3645
3646 case 0x48: /* RTC_INTERRUPTS_REG */
3647 #ifdef ALMDEBUG
3648 printf("RTC INTRS <-- %02x\n", value);
3649 #endif
3650 s->interrupts = value;
3651 return;
3652
3653 case 0x4c: /* RTC_COMP_LSB_REG */
3654 #ifdef ALMDEBUG
3655 printf("RTC COMPLSB <-- %02x\n", value);
3656 #endif
3657 s->comp_reg &= 0xff00;
3658 s->comp_reg |= 0x00ff & value;
3659 return;
3660
3661 case 0x50: /* RTC_COMP_MSB_REG */
3662 #ifdef ALMDEBUG
3663 printf("RTC COMPMSB <-- %02x\n", value);
3664 #endif
3665 s->comp_reg &= 0x00ff;
3666 s->comp_reg |= 0xff00 & (value << 8);
3667 return;
3668
3669 default:
3670 OMAP_BAD_REG(addr);
3671 return;
3672 }
3673 }
3674
3675 static CPUReadMemoryFunc *omap_rtc_readfn[] = {
3676 omap_rtc_read,
3677 omap_badwidth_read8,
3678 omap_badwidth_read8,
3679 };
3680
3681 static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
3682 omap_rtc_write,
3683 omap_badwidth_write8,
3684 omap_badwidth_write8,
3685 };
3686
3687 static void omap_rtc_tick(void *opaque)
3688 {
3689 struct omap_rtc_s *s = opaque;
3690
3691 if (s->round) {
3692 /* Round to nearest full minute. */
3693 if (s->current_tm.tm_sec < 30)
3694 s->ti -= s->current_tm.tm_sec;
3695 else
3696 s->ti += 60 - s->current_tm.tm_sec;
3697
3698 s->round = 0;
3699 }
3700
3701 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
3702
3703 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
3704 s->status |= 0x40;
3705 omap_rtc_interrupts_update(s);
3706 }
3707
3708 if (s->interrupts & 0x04)
3709 switch (s->interrupts & 3) {
3710 case 0:
3711 s->status |= 0x04;
3712 qemu_irq_pulse(s->irq);
3713 break;
3714 case 1:
3715 if (s->current_tm.tm_sec)
3716 break;
3717 s->status |= 0x08;
3718 qemu_irq_pulse(s->irq);
3719 break;
3720 case 2:
3721 if (s->current_tm.tm_sec || s->current_tm.tm_min)
3722 break;
3723 s->status |= 0x10;
3724 qemu_irq_pulse(s->irq);
3725 break;
3726 case 3:
3727 if (s->current_tm.tm_sec ||
3728 s->current_tm.tm_min || s->current_tm.tm_hour)
3729 break;
3730 s->status |= 0x20;
3731 qemu_irq_pulse(s->irq);
3732 break;
3733 }
3734
3735 /* Move on */
3736 if (s->running)
3737 s->ti ++;
3738 s->tick += 1000;
3739
3740 /*
3741 * Every full hour add a rough approximation of the compensation
3742 * register to the 32kHz Timer (which drives the RTC) value.
3743 */
3744 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
3745 s->tick += s->comp_reg * 1000 / 32768;
3746
3747 qemu_mod_timer(s->clk, s->tick);
3748 }
3749
3750 static void omap_rtc_reset(struct omap_rtc_s *s)
3751 {
3752 struct tm tm;
3753
3754 s->interrupts = 0;
3755 s->comp_reg = 0;
3756 s->running = 0;
3757 s->pm_am = 0;
3758 s->auto_comp = 0;
3759 s->round = 0;
3760 s->tick = qemu_get_clock(rt_clock);
3761 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
3762 s->alarm_tm.tm_mday = 0x01;
3763 s->status = 1 << 7;
3764 qemu_get_timedate(&tm, 0);
3765 s->ti = mktime(&tm);
3766
3767 omap_rtc_alarm_update(s);
3768 omap_rtc_tick(s);
3769 }
3770
3771 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
3772 qemu_irq *irq, omap_clk clk)
3773 {
3774 int iomemtype;
3775 struct omap_rtc_s *s = (struct omap_rtc_s *)
3776 qemu_mallocz(sizeof(struct omap_rtc_s));
3777
3778 s->base = base;
3779 s->irq = irq[0];
3780 s->alarm = irq[1];
3781 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
3782
3783 omap_rtc_reset(s);
3784
3785 iomemtype = cpu_register_io_memory(0, omap_rtc_readfn,
3786 omap_rtc_writefn, s);
3787 cpu_register_physical_memory(s->base, 0x800, iomemtype);
3788
3789 return s;
3790 }
3791
3792 /* Multi-channel Buffered Serial Port interfaces */
3793 struct omap_mcbsp_s {
3794 target_phys_addr_t base;
3795 qemu_irq txirq;
3796 qemu_irq rxirq;
3797 qemu_irq txdrq;
3798 qemu_irq rxdrq;
3799
3800 uint16_t spcr[2];
3801 uint16_t rcr[2];
3802 uint16_t xcr[2];
3803 uint16_t srgr[2];
3804 uint16_t mcr[2];
3805 uint16_t pcr;
3806 uint16_t rcer[8];
3807 uint16_t xcer[8];
3808 int tx_rate;
3809 int rx_rate;
3810 int tx_req;
3811 int rx_req;
3812
3813 struct i2s_codec_s *codec;
3814 QEMUTimer *source_timer;
3815 QEMUTimer *sink_timer;
3816 };
3817
3818 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
3819 {
3820 int irq;
3821
3822 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
3823 case 0:
3824 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
3825 break;
3826 case 3:
3827 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
3828 break;
3829 default:
3830 irq = 0;
3831 break;
3832 }
3833
3834 if (irq)
3835 qemu_irq_pulse(s->rxirq);
3836
3837 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
3838 case 0:
3839 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
3840 break;
3841 case 3:
3842 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
3843 break;
3844 default:
3845 irq = 0;
3846 break;
3847 }
3848
3849 if (irq)
3850 qemu_irq_pulse(s->txirq);
3851 }
3852
3853 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
3854 {
3855 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3856 s->spcr[0] |= 1 << 2; /* RFULL */
3857 s->spcr[0] |= 1 << 1; /* RRDY */
3858 qemu_irq_raise(s->rxdrq);
3859 omap_mcbsp_intr_update(s);
3860 }
3861
3862 static void omap_mcbsp_source_tick(void *opaque)
3863 {
3864 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3865 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3866
3867 if (!s->rx_rate)
3868 return;
3869 if (s->rx_req)
3870 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
3871
3872 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
3873
3874 omap_mcbsp_rx_newdata(s);
3875 qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
3876 }
3877
3878 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3879 {
3880 if (!s->codec || !s->codec->rts)
3881 omap_mcbsp_source_tick(s);
3882 else if (s->codec->in.len) {
3883 s->rx_req = s->codec->in.len;
3884 omap_mcbsp_rx_newdata(s);
3885 }
3886 }
3887
3888 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
3889 {
3890 qemu_del_timer(s->source_timer);
3891 }
3892
3893 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
3894 {
3895 s->spcr[0] &= ~(1 << 1); /* RRDY */
3896 qemu_irq_lower(s->rxdrq);
3897 omap_mcbsp_intr_update(s);
3898 }
3899
3900 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3901 {
3902 s->spcr[1] |= 1 << 1; /* XRDY */
3903 qemu_irq_raise(s->txdrq);
3904 omap_mcbsp_intr_update(s);
3905 }
3906
3907 static void omap_mcbsp_sink_tick(void *opaque)
3908 {
3909 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3910 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3911
3912 if (!s->tx_rate)
3913 return;
3914 if (s->tx_req)
3915 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
3916
3917 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3918
3919 omap_mcbsp_tx_newdata(s);
3920 qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec);
3921 }
3922
3923 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3924 {
3925 if (!s->codec || !s->codec->cts)
3926 omap_mcbsp_sink_tick(s);
3927 else if (s->codec->out.size) {
3928 s->tx_req = s->codec->out.size;
3929 omap_mcbsp_tx_newdata(s);
3930 }
3931 }
3932
3933 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3934 {
3935 s->spcr[1] &= ~(1 << 1); /* XRDY */
3936 qemu_irq_lower(s->txdrq);
3937 omap_mcbsp_intr_update(s);
3938 if (s->codec && s->codec->cts)
3939 s->codec->tx_swallow(s->codec->opaque);
3940 }
3941
3942 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3943 {
3944 s->tx_req = 0;
3945 omap_mcbsp_tx_done(s);
3946 qemu_del_timer(s->sink_timer);
3947 }
3948
3949 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3950 {
3951 int prev_rx_rate, prev_tx_rate;
3952 int rx_rate = 0, tx_rate = 0;
3953 int cpu_rate = 1500000; /* XXX */
3954
3955 /* TODO: check CLKSTP bit */
3956 if (s->spcr[1] & (1 << 6)) { /* GRST */
3957 if (s->spcr[0] & (1 << 0)) { /* RRST */
3958 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3959 (s->pcr & (1 << 8))) { /* CLKRM */
3960 if (~s->pcr & (1 << 7)) /* SCLKME */
3961 rx_rate = cpu_rate /
3962 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3963 } else
3964 if (s->codec)
3965 rx_rate = s->codec->rx_rate;
3966 }
3967
3968 if (s->spcr[1] & (1 << 0)) { /* XRST */
3969 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3970 (s->pcr & (1 << 9))) { /* CLKXM */
3971 if (~s->pcr & (1 << 7)) /* SCLKME */
3972 tx_rate = cpu_rate /
3973 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3974 } else
3975 if (s->codec)
3976 tx_rate = s->codec->tx_rate;
3977 }
3978 }
3979 prev_tx_rate = s->tx_rate;
3980 prev_rx_rate = s->rx_rate;
3981 s->tx_rate = tx_rate;
3982 s->rx_rate = rx_rate;
3983
3984 if (s->codec)
3985 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3986
3987 if (!prev_tx_rate && tx_rate)
3988 omap_mcbsp_tx_start(s);
3989 else if (s->tx_rate && !tx_rate)
3990 omap_mcbsp_tx_stop(s);
3991
3992 if (!prev_rx_rate && rx_rate)
3993 omap_mcbsp_rx_start(s);
3994 else if (prev_tx_rate && !tx_rate)
3995 omap_mcbsp_rx_stop(s);
3996 }
3997
3998 static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
3999 {
4000 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4001 int offset = addr & OMAP_MPUI_REG_MASK;
4002 uint16_t ret;
4003
4004 switch (offset) {
4005 case 0x00: /* DRR2 */
4006 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
4007 return 0x0000;
4008 /* Fall through. */
4009 case 0x02: /* DRR1 */
4010 if (s->rx_req < 2) {
4011 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
4012 omap_mcbsp_rx_done(s);
4013 } else {
4014 s->tx_req -= 2;
4015 if (s->codec && s->codec->in.len >= 2) {
4016 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
4017 ret |= s->codec->in.fifo[s->codec->in.start ++];
4018 s->codec->in.len -= 2;
4019 } else
4020 ret = 0x0000;
4021 if (!s->tx_req)
4022 omap_mcbsp_rx_done(s);
4023 return ret;
4024 }
4025 return 0x0000;
4026
4027 case 0x04: /* DXR2 */
4028 case 0x06: /* DXR1 */
4029 return 0x0000;
4030
4031 case 0x08: /* SPCR2 */
4032 return s->spcr[1];
4033 case 0x0a: /* SPCR1 */
4034 return s->spcr[0];
4035 case 0x0c: /* RCR2 */
4036 return s->rcr[1];
4037 case 0x0e: /* RCR1 */
4038 return s->rcr[0];
4039 case 0x10: /* XCR2 */
4040 return s->xcr[1];
4041 case 0x12: /* XCR1 */
4042 return s->xcr[0];
4043 case 0x14: /* SRGR2 */
4044 return s->srgr[1];
4045 case 0x16: /* SRGR1 */
4046 return s->srgr[0];
4047 case 0x18: /* MCR2 */
4048 return s->mcr[1];
4049 case 0x1a: /* MCR1 */
4050 return s->mcr[0];
4051 case 0x1c: /* RCERA */
4052 return s->rcer[0];
4053 case 0x1e: /* RCERB */
4054 return s->rcer[1];
4055 case 0x20: /* XCERA */
4056 return s->xcer[0];
4057 case 0x22: /* XCERB */
4058 return s->xcer[1];
4059 case 0x24: /* PCR0 */
4060 return s->pcr;
4061 case 0x26: /* RCERC */
4062 return s->rcer[2];
4063 case 0x28: /* RCERD */
4064 return s->rcer[3];
4065 case 0x2a: /* XCERC */
4066 return s->xcer[2];
4067 case 0x2c: /* XCERD */
4068 return s->xcer[3];
4069 case 0x2e: /* RCERE */
4070 return s->rcer[4];
4071 case 0x30: /* RCERF */
4072 return s->rcer[5];
4073 case 0x32: /* XCERE */
4074 return s->xcer[4];
4075 case 0x34: /* XCERF */
4076 return s->xcer[5];
4077 case 0x36: /* RCERG */
4078 return s->rcer[6];
4079 case 0x38: /* RCERH */
4080 return s->rcer[7];
4081 case 0x3a: /* XCERG */
4082 return s->xcer[6];
4083 case 0x3c: /* XCERH */
4084 return s->xcer[7];
4085 }
4086
4087 OMAP_BAD_REG(addr);
4088 return 0;
4089 }
4090
4091 static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
4092 uint32_t value)
4093 {
4094 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4095 int offset = addr & OMAP_MPUI_REG_MASK;
4096
4097 switch (offset) {
4098 case 0x00: /* DRR2 */
4099 case 0x02: /* DRR1 */
4100 OMAP_RO_REG(addr);
4101 return;
4102
4103 case 0x04: /* DXR2 */
4104 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4105 return;
4106 /* Fall through. */
4107 case 0x06: /* DXR1 */
4108 if (s->tx_req > 1) {
4109 s->tx_req -= 2;
4110 if (s->codec && s->codec->cts) {
4111 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
4112 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
4113 }
4114 if (s->tx_req < 2)
4115 omap_mcbsp_tx_done(s);
4116 } else
4117 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4118 return;
4119
4120 case 0x08: /* SPCR2 */
4121 s->spcr[1] &= 0x0002;
4122 s->spcr[1] |= 0x03f9 & value;
4123 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
4124 if (~value & 1) /* XRST */
4125 s->spcr[1] &= ~6;
4126 omap_mcbsp_req_update(s);
4127 return;
4128 case 0x0a: /* SPCR1 */
4129 s->spcr[0] &= 0x0006;
4130 s->spcr[0] |= 0xf8f9 & value;
4131 if (value & (1 << 15)) /* DLB */
4132 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
4133 if (~value & 1) { /* RRST */
4134 s->spcr[0] &= ~6;
4135 s->rx_req = 0;
4136 omap_mcbsp_rx_done(s);
4137 }
4138 omap_mcbsp_req_update(s);
4139 return;
4140
4141 case 0x0c: /* RCR2 */
4142 s->rcr[1] = value & 0xffff;
4143 return;
4144 case 0x0e: /* RCR1 */
4145 s->rcr[0] = value & 0x7fe0;
4146 return;
4147 case 0x10: /* XCR2 */
4148 s->xcr[1] = value & 0xffff;
4149 return;
4150 case 0x12: /* XCR1 */
4151 s->xcr[0] = value & 0x7fe0;
4152 return;
4153 case 0x14: /* SRGR2 */
4154 s->srgr[1] = value & 0xffff;
4155 omap_mcbsp_req_update(s);
4156 return;
4157 case 0x16: /* SRGR1 */
4158 s->srgr[0] = value & 0xffff;
4159 omap_mcbsp_req_update(s);
4160 return;
4161 case 0x18: /* MCR2 */
4162 s->mcr[1] = value & 0x03e3;
4163 if (value & 3) /* XMCM */
4164 printf("%s: Tx channel selection mode enable attempt\n",
4165 __FUNCTION__);
4166 return;
4167 case 0x1a: /* MCR1 */
4168 s->mcr[0] = value & 0x03e1;
4169 if (value & 1) /* RMCM */
4170 printf("%s: Rx channel selection mode enable attempt\n",
4171 __FUNCTION__);
4172 return;
4173 case 0x1c: /* RCERA */
4174 s->rcer[0] = value & 0xffff;
4175 return;
4176 case 0x1e: /* RCERB */
4177 s->rcer[1] = value & 0xffff;
4178 return;
4179 case 0x20: /* XCERA */
4180 s->xcer[0] = value & 0xffff;
4181 return;
4182 case 0x22: /* XCERB */
4183 s->xcer[1] = value & 0xffff;
4184 return;
4185 case 0x24: /* PCR0 */
4186 s->pcr = value & 0x7faf;
4187 return;
4188 case 0x26: /* RCERC */
4189 s->rcer[2] = value & 0xffff;
4190 return;
4191 case 0x28: /* RCERD */
4192 s->rcer[3] = value & 0xffff;
4193 return;
4194 case 0x2a: /* XCERC */
4195 s->xcer[2] = value & 0xffff;
4196 return;
4197 case 0x2c: /* XCERD */
4198 s->xcer[3] = value & 0xffff;
4199 return;
4200 case 0x2e: /* RCERE */
4201 s->rcer[4] = value & 0xffff;
4202 return;
4203 case 0x30: /* RCERF */
4204 s->rcer[5] = value & 0xffff;
4205 return;
4206 case 0x32: /* XCERE */
4207 s->xcer[4] = value & 0xffff;
4208 return;
4209 case 0x34: /* XCERF */
4210 s->xcer[5] = value & 0xffff;
4211 return;
4212 case 0x36: /* RCERG */
4213 s->rcer[6] = value & 0xffff;
4214 return;
4215 case 0x38: /* RCERH */
4216 s->rcer[7] = value & 0xffff;
4217 return;
4218 case 0x3a: /* XCERG */
4219 s->xcer[6] = value & 0xffff;
4220 return;
4221 case 0x3c: /* XCERH */
4222 s->xcer[7] = value & 0xffff;
4223 return;
4224 }
4225
4226 OMAP_BAD_REG(addr);
4227 }
4228
4229 static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
4230 uint32_t value)
4231 {
4232 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4233 int offset = addr & OMAP_MPUI_REG_MASK;
4234
4235 if (offset == 0x04) { /* DXR */
4236 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4237 return;
4238 if (s->tx_req > 3) {
4239 s->tx_req -= 4;
4240 if (s->codec && s->codec->cts) {
4241 s->codec->out.fifo[s->codec->out.len ++] =
4242 (value >> 24) & 0xff;
4243 s->codec->out.fifo[s->codec->out.len ++] =
4244 (value >> 16) & 0xff;
4245 s->codec->out.fifo[s->codec->out.len ++] =
4246 (value >> 8) & 0xff;
4247 s->codec->out.fifo[s->codec->out.len ++] =
4248 (value >> 0) & 0xff;
4249 }
4250 if (s->tx_req < 4)
4251 omap_mcbsp_tx_done(s);
4252 } else
4253 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4254 return;
4255 }
4256
4257 omap_badwidth_write16(opaque, addr, value);
4258 }
4259
4260 static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
4261 omap_badwidth_read16,
4262 omap_mcbsp_read,
4263 omap_badwidth_read16,
4264 };
4265
4266 static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
4267 omap_badwidth_write16,
4268 omap_mcbsp_writeh,
4269 omap_mcbsp_writew,
4270 };
4271
4272 static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
4273 {
4274 memset(&s->spcr, 0, sizeof(s->spcr));
4275 memset(&s->rcr, 0, sizeof(s->rcr));
4276 memset(&s->xcr, 0, sizeof(s->xcr));
4277 s->srgr[0] = 0x0001;
4278 s->srgr[1] = 0x2000;
4279 memset(&s->mcr, 0, sizeof(s->mcr));
4280 memset(&s->pcr, 0, sizeof(s->pcr));
4281 memset(&s->rcer, 0, sizeof(s->rcer));
4282 memset(&s->xcer, 0, sizeof(s->xcer));
4283 s->tx_req = 0;
4284 s->rx_req = 0;
4285 s->tx_rate = 0;
4286 s->rx_rate = 0;
4287 qemu_del_timer(s->source_timer);
4288 qemu_del_timer(s->sink_timer);
4289 }
4290
4291 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
4292 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
4293 {
4294 int iomemtype;
4295 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
4296 qemu_mallocz(sizeof(struct omap_mcbsp_s));
4297
4298 s->base = base;
4299 s->txirq = irq[0];
4300 s->rxirq = irq[1];
4301 s->txdrq = dma[0];
4302 s->rxdrq = dma[1];
4303 s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s);
4304 s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
4305 omap_mcbsp_reset(s);
4306
4307 iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn,
4308 omap_mcbsp_writefn, s);
4309 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4310
4311 return s;
4312 }
4313
4314 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
4315 {
4316 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4317
4318 if (s->rx_rate) {
4319 s->rx_req = s->codec->in.len;
4320 omap_mcbsp_rx_newdata(s);
4321 }
4322 }
4323
4324 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
4325 {
4326 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4327
4328 if (s->tx_rate) {
4329 s->tx_req = s->codec->out.size;
4330 omap_mcbsp_tx_newdata(s);
4331 }
4332 }
4333
4334 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave)
4335 {
4336 s->codec = slave;
4337 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
4338 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
4339 }
4340
4341 /* LED Pulse Generators */
4342 struct omap_lpg_s {
4343 target_phys_addr_t base;
4344 QEMUTimer *tm;
4345
4346 uint8_t control;
4347 uint8_t power;
4348 int64_t on;
4349 int64_t period;
4350 int clk;
4351 int cycle;
4352 };
4353
4354 static void omap_lpg_tick(void *opaque)
4355 {
4356 struct omap_lpg_s *s = opaque;
4357
4358 if (s->cycle)
4359 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on);
4360 else
4361 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on);
4362
4363 s->cycle = !s->cycle;
4364 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
4365 }
4366
4367 static void omap_lpg_update(struct omap_lpg_s *s)
4368 {
4369 int64_t on, period = 1, ticks = 1000;
4370 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
4371
4372 if (~s->control & (1 << 6)) /* LPGRES */
4373 on = 0;
4374 else if (s->control & (1 << 7)) /* PERM_ON */
4375 on = period;
4376 else {
4377 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
4378 256 / 32);
4379 on = (s->clk && s->power) ? muldiv64(ticks,
4380 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
4381 }
4382
4383 qemu_del_timer(s->tm);
4384 if (on == period && s->on < s->period)
4385 printf("%s: LED is on\n", __FUNCTION__);
4386 else if (on == 0 && s->on)
4387 printf("%s: LED is off\n", __FUNCTION__);
4388 else if (on && (on != s->on || period != s->period)) {
4389 s->cycle = 0;
4390 s->on = on;
4391 s->period = period;
4392 omap_lpg_tick(s);
4393 return;
4394 }
4395
4396 s->on = on;
4397 s->period = period;
4398 }
4399
4400 static void omap_lpg_reset(struct omap_lpg_s *s)
4401 {
4402 s->control = 0x00;
4403 s->power = 0x00;
4404 s->clk = 1;
4405 omap_lpg_update(s);
4406 }
4407
4408 static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
4409 {
4410 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4411 int offset = addr & OMAP_MPUI_REG_MASK;
4412
4413 switch (offset) {
4414 case 0x00: /* LCR */
4415 return s->control;
4416
4417 case 0x04: /* PMR */
4418 return s->power;
4419 }
4420
4421 OMAP_BAD_REG(addr);
4422 return 0;
4423 }
4424
4425 static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
4426 uint32_t value)
4427 {
4428 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4429 int offset = addr & OMAP_MPUI_REG_MASK;
4430
4431 switch (offset) {
4432 case 0x00: /* LCR */
4433 if (~value & (1 << 6)) /* LPGRES */
4434 omap_lpg_reset(s);
4435 s->control = value & 0xff;
4436 omap_lpg_update(s);
4437 return;
4438
4439 case 0x04: /* PMR */
4440 s->power = value & 0x01;
4441 omap_lpg_update(s);
4442 return;
4443
4444 default:
4445 OMAP_BAD_REG(addr);
4446 return;
4447 }
4448 }
4449
4450 static CPUReadMemoryFunc *omap_lpg_readfn[] = {
4451 omap_lpg_read,
4452 omap_badwidth_read8,
4453 omap_badwidth_read8,
4454 };
4455
4456 static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
4457 omap_lpg_write,
4458 omap_badwidth_write8,
4459 omap_badwidth_write8,
4460 };
4461
4462 static void omap_lpg_clk_update(void *opaque, int line, int on)
4463 {
4464 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4465
4466 s->clk = on;
4467 omap_lpg_update(s);
4468 }
4469
4470 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
4471 {
4472 int iomemtype;
4473 struct omap_lpg_s *s = (struct omap_lpg_s *)
4474 qemu_mallocz(sizeof(struct omap_lpg_s));
4475
4476 s->base = base;
4477 s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
4478
4479 omap_lpg_reset(s);
4480
4481 iomemtype = cpu_register_io_memory(0, omap_lpg_readfn,
4482 omap_lpg_writefn, s);
4483 cpu_register_physical_memory(s->base, 0x800, iomemtype);
4484
4485 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
4486
4487 return s;
4488 }
4489
4490 /* MPUI Peripheral Bridge configuration */
4491 static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
4492 {
4493 if (addr == OMAP_MPUI_BASE) /* CMR */
4494 return 0xfe4d;
4495
4496 OMAP_BAD_REG(addr);
4497 return 0;
4498 }
4499
4500 static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
4501 omap_badwidth_read16,
4502 omap_mpui_io_read,
4503 omap_badwidth_read16,
4504 };
4505
4506 static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
4507 omap_badwidth_write16,
4508 omap_badwidth_write16,
4509 omap_badwidth_write16,
4510 };
4511
4512 static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
4513 {
4514 int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn,
4515 omap_mpui_io_writefn, mpu);
4516 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
4517 }
4518
4519 /* General chip reset */
4520 static void omap1_mpu_reset(void *opaque)
4521 {
4522 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4523
4524 omap_inth_reset(mpu->ih[0]);
4525 omap_inth_reset(mpu->ih[1]);
4526 omap_dma_reset(mpu->dma);
4527 omap_mpu_timer_reset(mpu->timer[0]);
4528 omap_mpu_timer_reset(mpu->timer[1]);
4529 omap_mpu_timer_reset(mpu->timer[2]);
4530 omap_wd_timer_reset(mpu->wdt);
4531 omap_os_timer_reset(mpu->os_timer);
4532 omap_lcdc_reset(mpu->lcd);
4533 omap_ulpd_pm_reset(mpu);
4534 omap_pin_cfg_reset(mpu);
4535 omap_mpui_reset(mpu);
4536 omap_tipb_bridge_reset(mpu->private_tipb);
4537 omap_tipb_bridge_reset(mpu->public_tipb);
4538 omap_dpll_reset(&mpu->dpll[0]);
4539 omap_dpll_reset(&mpu->dpll[1]);
4540 omap_dpll_reset(&mpu->dpll[2]);
4541 omap_uart_reset(mpu->uart[0]);
4542 omap_uart_reset(mpu->uart[1]);
4543 omap_uart_reset(mpu->uart[2]);
4544 omap_mmc_reset(mpu->mmc);
4545 omap_mpuio_reset(mpu->mpuio);
4546 omap_gpio_reset(mpu->gpio);
4547 omap_uwire_reset(mpu->microwire);
4548 omap_pwl_reset(mpu);
4549 omap_pwt_reset(mpu);
4550 omap_i2c_reset(mpu->i2c[0]);
4551 omap_rtc_reset(mpu->rtc);
4552 omap_mcbsp_reset(mpu->mcbsp1);
4553 omap_mcbsp_reset(mpu->mcbsp2);
4554 omap_mcbsp_reset(mpu->mcbsp3);
4555 omap_lpg_reset(mpu->led[0]);
4556 omap_lpg_reset(mpu->led[1]);
4557 omap_clkm_reset(mpu);
4558 cpu_reset(mpu->env);
4559 }
4560
4561 static const struct omap_map_s {
4562 target_phys_addr_t phys_dsp;
4563 target_phys_addr_t phys_mpu;
4564 uint32_t size;
4565 const char *name;
4566 } omap15xx_dsp_mm[] = {
4567 /* Strobe 0 */
4568 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
4569 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
4570 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
4571 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
4572 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
4573 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
4574 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
4575 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
4576 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
4577 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
4578 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
4579 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
4580 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
4581 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
4582 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
4583 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
4584 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
4585 /* Strobe 1 */
4586 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
4587
4588 { 0 }
4589 };
4590
4591 static void omap_setup_dsp_mapping(const struct omap_map_s *map)
4592 {
4593 int io;
4594
4595 for (; map->phys_dsp; map ++) {
4596 io = cpu_get_physical_page_desc(map->phys_mpu);
4597
4598 cpu_register_physical_memory(map->phys_dsp, map->size, io);
4599 }
4600 }
4601
4602 void omap_mpu_wakeup(void *opaque, int irq, int req)
4603 {
4604 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4605
4606 if (mpu->env->halted)
4607 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
4608 }
4609
4610 static const struct dma_irq_map omap1_dma_irq_map[] = {
4611 { 0, OMAP_INT_DMA_CH0_6 },
4612 { 0, OMAP_INT_DMA_CH1_7 },
4613 { 0, OMAP_INT_DMA_CH2_8 },
4614 { 0, OMAP_INT_DMA_CH3 },
4615 { 0, OMAP_INT_DMA_CH4 },
4616 { 0, OMAP_INT_DMA_CH5 },
4617 { 1, OMAP_INT_1610_DMA_CH6 },
4618 { 1, OMAP_INT_1610_DMA_CH7 },
4619 { 1, OMAP_INT_1610_DMA_CH8 },
4620 { 1, OMAP_INT_1610_DMA_CH9 },
4621 { 1, OMAP_INT_1610_DMA_CH10 },
4622 { 1, OMAP_INT_1610_DMA_CH11 },
4623 { 1, OMAP_INT_1610_DMA_CH12 },
4624 { 1, OMAP_INT_1610_DMA_CH13 },
4625 { 1, OMAP_INT_1610_DMA_CH14 },
4626 { 1, OMAP_INT_1610_DMA_CH15 }
4627 };
4628
4629 /* DMA ports for OMAP1 */
4630 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
4631 target_phys_addr_t addr)
4632 {
4633 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
4634 }
4635
4636 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
4637 target_phys_addr_t addr)
4638 {
4639 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
4640 }
4641
4642 static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
4643 target_phys_addr_t addr)
4644 {
4645 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
4646 }
4647
4648 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
4649 target_phys_addr_t addr)
4650 {
4651 return addr >= 0xfffb0000 && addr < 0xffff0000;
4652 }
4653
4654 static int omap_validate_local_addr(struct omap_mpu_state_s *s,
4655 target_phys_addr_t addr)
4656 {
4657 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
4658 }
4659
4660 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
4661 target_phys_addr_t addr)
4662 {
4663 return addr >= 0xe1010000 && addr < 0xe1020004;
4664 }
4665
4666 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
4667 DisplayState *ds, const char *core)
4668 {
4669 int i;
4670 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4671 qemu_mallocz(sizeof(struct omap_mpu_state_s));
4672 ram_addr_t imif_base, emiff_base;
4673 qemu_irq *cpu_irq;
4674 qemu_irq dma_irqs[6];
4675 int sdindex;
4676
4677 if (!core)
4678 core = "ti925t";
4679
4680 /* Core */
4681 s->mpu_model = omap310;
4682 s->env = cpu_init(core);
4683 if (!s->env) {
4684 fprintf(stderr, "Unable to find CPU definition\n");
4685 exit(1);
4686 }
4687 s->sdram_size = sdram_size;
4688 s->sram_size = OMAP15XX_SRAM_SIZE;
4689
4690 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4691
4692 /* Clocks */
4693 omap_clk_init(s);
4694
4695 /* Memory-mapped stuff */
4696 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
4697 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4698 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
4699 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4700
4701 omap_clkm_init(0xfffece00, 0xe1008000, s);
4702
4703 cpu_irq = arm_pic_init_cpu(s->env);
4704 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
4705 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
4706 omap_findclk(s, "arminth_ck"));
4707 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
4708 s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL,
4709 omap_findclk(s, "arminth_ck"));
4710
4711 for (i = 0; i < 6; i ++)
4712 dma_irqs[i] =
4713 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
4714 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
4715 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
4716
4717 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
4718 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
4719 s->port[imif ].addr_valid = omap_validate_imif_addr;
4720 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
4721 s->port[local ].addr_valid = omap_validate_local_addr;
4722 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
4723
4724 /* Register SDRAM and SRAM DMA ports for fast transfers. */
4725 soc_dma_port_add_mem_ram(s->dma,
4726 emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
4727 soc_dma_port_add_mem_ram(s->dma,
4728 imif_base, OMAP_IMIF_BASE, s->sram_size);
4729
4730 s->timer[0] = omap_mpu_timer_init(0xfffec500,
4731 s->irq[0][OMAP_INT_TIMER1],
4732 omap_findclk(s, "mputim_ck"));
4733 s->timer[1] = omap_mpu_timer_init(0xfffec600,
4734 s->irq[0][OMAP_INT_TIMER2],
4735 omap_findclk(s, "mputim_ck"));
4736 s->timer[2] = omap_mpu_timer_init(0xfffec700,
4737 s->irq[0][OMAP_INT_TIMER3],
4738 omap_findclk(s, "mputim_ck"));
4739
4740 s->wdt = omap_wd_timer_init(0xfffec800,
4741 s->irq[0][OMAP_INT_WD_TIMER],
4742 omap_findclk(s, "armwdt_ck"));
4743
4744 s->os_timer = omap_os_timer_init(0xfffb9000,
4745 s->irq[1][OMAP_INT_OS_TIMER],
4746 omap_findclk(s, "clk32-kHz"));
4747
4748 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
4749 omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base,
4750 omap_findclk(s, "lcd_ck"));
4751
4752 omap_ulpd_pm_init(0xfffe0800, s);
4753 omap_pin_cfg_init(0xfffe1000, s);
4754 omap_id_init(s);
4755
4756 omap_mpui_init(0xfffec900, s);
4757
4758 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
4759 s->irq[0][OMAP_INT_BRIDGE_PRIV],
4760 omap_findclk(s, "tipb_ck"));
4761 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
4762 s->irq[0][OMAP_INT_BRIDGE_PUB],
4763 omap_findclk(s, "tipb_ck"));
4764
4765 omap_tcmi_init(0xfffecc00, s);
4766
4767 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
4768 omap_findclk(s, "uart1_ck"),
4769 omap_findclk(s, "uart1_ck"),
4770 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
4771 serial_hds[0]);
4772 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
4773 omap_findclk(s, "uart2_ck"),
4774 omap_findclk(s, "uart2_ck"),
4775 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
4776 serial_hds[0] ? serial_hds[1] : 0);
4777 s->uart[2] = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3],
4778 omap_findclk(s, "uart3_ck"),
4779 omap_findclk(s, "uart3_ck"),
4780 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
4781 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
4782
4783 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
4784 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
4785 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
4786
4787 sdindex = drive_get_index(IF_SD, 0, 0);
4788 if (sdindex == -1) {
4789 fprintf(stderr, "qemu: missing SecureDigital device\n");
4790 exit(1);
4791 }
4792 s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv,
4793 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
4794 omap_findclk(s, "mmc_ck"));
4795
4796 s->mpuio = omap_mpuio_init(0xfffb5000,
4797 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
4798 s->wakeup, omap_findclk(s, "clk32-kHz"));
4799
4800 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1],
4801 omap_findclk(s, "arm_gpio_ck"));
4802
4803 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
4804 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4805
4806 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
4807 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
4808
4809 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
4810 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
4811
4812 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
4813 omap_findclk(s, "clk32-kHz"));
4814
4815 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
4816 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4817 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
4818 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4819 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
4820 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4821
4822 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
4823 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
4824
4825 /* Register mappings not currenlty implemented:
4826 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4827 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4828 * USB W2FC fffb4000 - fffb47ff
4829 * Camera Interface fffb6800 - fffb6fff
4830 * USB Host fffba000 - fffba7ff
4831 * FAC fffba800 - fffbafff
4832 * HDQ/1-Wire fffbc000 - fffbc7ff
4833 * TIPB switches fffbc800 - fffbcfff
4834 * Mailbox fffcf000 - fffcf7ff
4835 * Local bus IF fffec100 - fffec1ff
4836 * Local bus MMU fffec200 - fffec2ff
4837 * DSP MMU fffed200 - fffed2ff
4838 */
4839
4840 omap_setup_dsp_mapping(omap15xx_dsp_mm);
4841 omap_setup_mpui_io(s);
4842
4843 qemu_register_reset(omap1_mpu_reset, s);
4844
4845 return s;
4846 }
Samsung s3c2440 and arm920t support for the mini2440 dev board