hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "nvram.h"
  29 #include "pc.h"
  30 #include "sysemu.h"
  31 #include "net.h"
  32 #include "isa.h"
  33 #include "pci.h"
  34 #include "boards.h"
  35
  36 #define MAX_IDE_BUS 2
  37 #define VGA_BIOS_SIZE 65536
  38
  39 /* temporary frame buffer OSI calls for the video.x driver. The right
  40    solution is to modify the driver to use VGA PCI I/Os */
  41 /* XXX: to be removed. This is no way related to emulation */
  42 static int vga_osi_call (CPUState *env)
  43 {
  44     static int vga_vbl_enabled;
  45     int linesize;
  46
  47     //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
  48
  49     /* same handler as PearPC, coming from the original MOL video
  50        driver. */
  51     switch(env->gpr[5]) {
  52     case 4:
  53         break;
  54     case 28: /* set_vmode */
  55         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  56             env->gpr[3] = 1;
  57         else
  58             env->gpr[3] = 0;
  59         break;
  60     case 29: /* get_vmode_info */
  61         if (env->gpr[6] != 0) {
  62             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  63                 env->gpr[3] = 1;
  64                 break;
  65             }
  66         }
  67         env->gpr[3] = 0;
  68         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  69         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  70         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  71         env->gpr[7] = 85 << 16; /* refresh rate */
  72         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  73         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  74         linesize = (linesize + 3) & ~3;
  75         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  76         break;
  77     case 31: /* set_video power */
  78         env->gpr[3] = 0;
  79         break;
  80     case 39: /* video_ctrl */
  81         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  82             vga_vbl_enabled = env->gpr[6];
  83         env->gpr[3] = 0;
  84         break;
  85     case 47:
  86         break;
  87     case 59: /* set_color */
  88         /* R6 = index, R7 = RGB */
  89         env->gpr[3] = 0;
  90         break;
  91     case 64: /* get color */
  92         /* R6 = index */
  93         env->gpr[3] = 0;
  94         break;
  95     case 116: /* set hwcursor */
  96         /* R6 = x, R7 = y, R8 = visible, R9 = data */
  97         break;
  98     default:
  99         fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
 100                 ppc_dump_gpr(env, 5));
 101         break;
 102     }
 103
 104     return 1; /* osi_call handled */
 105 }
 106
 107 static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
 108                                const char *boot_device, DisplayState *ds,
 109                                const char *kernel_filename,
 110                                const char *kernel_cmdline,
 111                                const char *initrd_filename,
 112                                const char *cpu_model)
 113 {
 114     CPUState *env = NULL, *envs[MAX_CPUS];
 115     char buf[1024];
 116     qemu_irq *pic, **heathrow_irqs;
 117     nvram_t nvram;
 118     m48t59_t *m48t59;
 119     int linux_boot, i;
 120     ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
 121     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 122     PCIBus *pci_bus;
 123     MacIONVRAMState *nvr;
 124     int vga_bios_size, bios_size;
 125     qemu_irq *dummy_irq;
 126     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 127     int ide_mem_index[2];
 128     int ppc_boot_device;
 129     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 130     int index;
 131
 132     linux_boot = (kernel_filename != NULL);
 133
 134     /* init CPUs */
 135     if (cpu_model == NULL)
 136         cpu_model = "G3";
 137     for (i = 0; i < smp_cpus; i++) {
 138         env = cpu_init(cpu_model);
 139         if (!env) {
 140             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 141             exit(1);
 142         }
 143         /* Set time-base frequency to 100 Mhz */
 144         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 145         env->osi_call = vga_osi_call;
 146         qemu_register_reset(&cpu_ppc_reset, env);
 147         envs[i] = env;
 148     }
 149     if (env->nip < 0xFFF80000) {
 150         /* Special test for PowerPC 601:
 151          * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
 152          * But the NVRAM is located at 0xFFF04000...
 153          */
 154         cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
 155     }
 156
 157     /* allocate RAM */
 158     ram_offset = qemu_ram_alloc(ram_size);
 159     cpu_register_physical_memory(0, ram_size, ram_offset);
 160
 161     /* allocate VGA RAM */
 162     vga_ram_offset = qemu_ram_alloc(vga_ram_size);
 163
 164     /* allocate and load BIOS */
 165     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 166     if (bios_name == NULL)
 167         bios_name = BIOS_FILENAME;
 168     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 169     bios_size = load_image(buf, phys_ram_base + bios_offset);
 170     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 171         cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
 172         exit(1);
 173     }
 174     if (bios_size > 0x00080000) {
 175         /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
 176         cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
 177     }
 178     cpu_register_physical_memory((uint32_t)(-bios_size),
 179                                  bios_size, bios_offset | IO_MEM_ROM);
 180
 181     /* allocate and load VGA BIOS */
 182     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 183     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 184     vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
 185     if (vga_bios_size < 0) {
 186         /* if no bios is present, we can still work */
 187         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
 188         vga_bios_size = 0;
 189     } else {
 190         /* set a specific header (XXX: find real Apple format for NDRV
 191            drivers) */
 192         phys_ram_base[vga_bios_offset] = 'N';
 193         phys_ram_base[vga_bios_offset + 1] = 'D';
 194         phys_ram_base[vga_bios_offset + 2] = 'R';
 195         phys_ram_base[vga_bios_offset + 3] = 'V';
 196         cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
 197                      vga_bios_size);
 198         vga_bios_size += 8;
 199     }
 200
 201     if (linux_boot) {
 202         kernel_base = KERNEL_LOAD_ADDR;
 203         /* now we can load the kernel */
 204         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 205         if (kernel_size < 0) {
 206             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 207                       kernel_filename);
 208             exit(1);
 209         }
 210         /* load initrd */
 211         if (initrd_filename) {
 212             initrd_base = INITRD_LOAD_ADDR;
 213             initrd_size = load_image(initrd_filename,
 214                                      phys_ram_base + initrd_base);
 215             if (initrd_size < 0) {
 216                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 217                           initrd_filename);
 218                 exit(1);
 219             }
 220         } else {
 221             initrd_base = 0;
 222             initrd_size = 0;
 223         }
 224         ppc_boot_device = 'm';
 225     } else {
 226         kernel_base = 0;
 227         kernel_size = 0;
 228         initrd_base = 0;
 229         initrd_size = 0;
 230         ppc_boot_device = '\0';
 231         for (i = 0; boot_device[i] != '\0'; i++) {
 232             /* TOFIX: for now, the second IDE channel is not properly
 233              *        used by OHW. The Mac floppy disk are not emulated.
 234              *        For now, OHW cannot boot from the network.
 235              */
 236 #if 0
 237             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 238                 ppc_boot_device = boot_device[i];
 239                 break;
 240             }
 241 #else
 242             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 243                 ppc_boot_device = boot_device[i];
 244                 break;
 245             }
 246 #endif
 247         }
 248         if (ppc_boot_device == '\0') {
 249             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 250             exit(1);
 251         }
 252     }
 253
 254     isa_mem_base = 0x80000000;
 255
 256     /* Register 2 MB of ISA IO space */
 257     isa_mmio_init(0xfe000000, 0x00200000);
 258
 259     /* XXX: we register only 1 output pin for heathrow PIC */
 260     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 261     heathrow_irqs[0] =
 262         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 263     /* Connect the heathrow PIC outputs to the 6xx bus */
 264     for (i = 0; i < smp_cpus; i++) {
 265         switch (PPC_INPUT(env)) {
 266         case PPC_FLAGS_INPUT_6xx:
 267             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 268             heathrow_irqs[i][0] =
 269                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 270             break;
 271         default:
 272             cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
 273             exit(1);
 274         }
 275     }
 276
 277     /* init basic PC hardware */
 278     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 279         cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
 280         exit(1);
 281     }
 282     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 283     pci_bus = pci_grackle_init(0xfec00000, pic);
 284     pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
 285                  vga_ram_offset, vga_ram_size,
 286                  vga_bios_offset, vga_bios_size);
 287
 288     /* XXX: suppress that */
 289     dummy_irq = i8259_init(NULL);
 290
 291     /* XXX: use Mac Serial port */
 292     serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
 293
 294     for(i = 0; i < nb_nics; i++) {
 295         if (!nd_table[i].model)
 296             nd_table[i].model = "ne2k_pci";
 297         pci_nic_init(pci_bus, &nd_table[i], -1);
 298     }
 299
 300     /* First IDE channel is a CMD646 on the PCI bus */
 301
 302     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 303         fprintf(stderr, "qemu: too many IDE bus\n");
 304         exit(1);
 305     }
 306     index = drive_get_index(IF_IDE, 0, 0);
 307     if (index == -1)
 308         hd[0] = NULL;
 309     else
 310         hd[0] =  drives_table[index].bdrv;
 311     index = drive_get_index(IF_IDE, 0, 1);
 312     if (index == -1)
 313         hd[1] = NULL;
 314     else
 315         hd[1] =  drives_table[index].bdrv;
 316     hd[3] = hd[2] = NULL;
 317     pci_cmd646_ide_init(pci_bus, hd, 0);
 318
 319     /* Second IDE channel is a MAC IDE on the MacIO bus */
 320     index = drive_get_index(IF_IDE, 1, 0);
 321     if (index == -1)
 322         hd[0] = NULL;
 323     else
 324         hd[0] =  drives_table[index].bdrv;
 325     index = drive_get_index(IF_IDE, 1, 1);
 326     if (index == -1)
 327         hd[1] = NULL;
 328     else
 329         hd[1] =  drives_table[index].bdrv;
 330     ide_mem_index[0] = -1;
 331     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D]);
 332
 333     /* cuda also initialize ADB */
 334     cuda_init(&cuda_mem_index, pic[0x12]);
 335
 336     adb_kbd_init(&adb_bus);
 337     adb_mouse_init(&adb_bus);
 338
 339     nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
 340     pmac_format_nvram_partition(nvr, 0x2000);
 341
 342     dbdma_init(&dbdma_mem_index);
 343
 344     macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
 345                cuda_mem_index, nvr, 2, ide_mem_index);
 346
 347     if (usb_enabled) {
 348         usb_ohci_init_pci(pci_bus, 3, -1);
 349     }
 350
 351     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 352         graphic_depth = 15;
 353
 354     m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
 355     nvram.opaque = m48t59;
 356     nvram.read_fn = &m48t59_read;
 357     nvram.write_fn = &m48t59_write;
 358     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
 359                          ppc_boot_device, kernel_base, kernel_size,
 360                          kernel_cmdline,
 361                          initrd_base, initrd_size,
 362                          /* XXX: need an option to load a NVRAM image */
 363                          0,
 364                          graphic_width, graphic_height, graphic_depth);
 365     /* No PCI init: the BIOS will do it */
 366
 367     /* Special port to get debug messages from Open-Firmware */
 368     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 369 }
 370
 371 QEMUMachine heathrow_machine = {
 372     .name = "g3bw",
 373     .desc = "Heathrow based PowerMAC",
 374     .init = ppc_heathrow_init,
 375     .ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE,
 376     .max_cpus = MAX_CPUS,
 377 };