hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "virtio-net.h"
  29 #include "sysemu.h"
  30
  31 //#define DEBUG_PCI
  32
  33 struct PCIBus {
  34     int bus_num;
  35     int devfn_min;
  36     pci_set_irq_fn set_irq;
  37     pci_map_irq_fn map_irq;
  38     uint32_t config_reg; /* XXX: suppress */
  39     /* low level pic */
  40     SetIRQFunc *low_set_irq;
  41     qemu_irq *irq_opaque;
  42     PCIDevice *devices[256];
  43     PCIDevice *parent_dev;
  44     PCIBus *next;
  45     /* The bus IRQ state is the logical OR of the connected devices.
  46        Keep a count of the number of devices with raised IRQs.  */
  47     int nirq;
  48     int irq_count[];
  49 };
  50
  51 static void pci_update_mappings(PCIDevice *d);
  52 static void pci_set_irq(void *opaque, int irq_num, int level);
  53
  54 target_phys_addr_t pci_mem_base;
  55 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  56 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  57 static int pci_irq_index;
  58 static PCIBus *first_bus;
  59
  60 static void pcibus_save(QEMUFile *f, void *opaque)
  61 {
  62     PCIBus *bus = (PCIBus *)opaque;
  63     int i;
  64
  65     qemu_put_be32(f, bus->nirq);
  66     for (i = 0; i < bus->nirq; i++)
  67         qemu_put_be32(f, bus->irq_count[i]);
  68 }
  69
  70 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  71 {
  72     PCIBus *bus = (PCIBus *)opaque;
  73     int i, nirq;
  74
  75     if (version_id != 1)
  76         return -EINVAL;
  77
  78     nirq = qemu_get_be32(f);
  79     if (bus->nirq != nirq) {
  80         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  81                 nirq, bus->nirq);
  82         return -EINVAL;
  83     }
  84
  85     for (i = 0; i < nirq; i++)
  86         bus->irq_count[i] = qemu_get_be32(f);
  87
  88     return 0;
  89 }
  90
  91 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  92                          qemu_irq *pic, int devfn_min, int nirq)
  93 {
  94     PCIBus *bus;
  95     static int nbus = 0;
  96
  97     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  98     bus->set_irq = set_irq;
  99     bus->map_irq = map_irq;
 100     bus->irq_opaque = pic;
 101     bus->devfn_min = devfn_min;
 102     bus->nirq = nirq;
 103     bus->next = first_bus;
 104     first_bus = bus;
 105     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 106     return bus;
 107 }
 108
 109 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 110 {
 111     PCIBus *bus;
 112     bus = qemu_mallocz(sizeof(PCIBus));
 113     bus->map_irq = map_irq;
 114     bus->parent_dev = dev;
 115     bus->next = dev->bus->next;
 116     dev->bus->next = bus;
 117     return bus;
 118 }
 119
 120 int pci_bus_num(PCIBus *s)
 121 {
 122     return s->bus_num;
 123 }
 124
 125 void pci_device_save(PCIDevice *s, QEMUFile *f)
 126 {
 127     int i;
 128
 129     qemu_put_be32(f, 2); /* PCI device version */
 130     qemu_put_buffer(f, s->config, 256);
 131     for (i = 0; i < 4; i++)
 132         qemu_put_be32(f, s->irq_state[i]);
 133 }
 134
 135 int pci_device_load(PCIDevice *s, QEMUFile *f)
 136 {
 137     uint32_t version_id;
 138     int i;
 139
 140     version_id = qemu_get_be32(f);
 141     if (version_id > 2)
 142         return -EINVAL;
 143     qemu_get_buffer(f, s->config, 256);
 144     pci_update_mappings(s);
 145
 146     if (version_id >= 2)
 147         for (i = 0; i < 4; i ++)
 148             s->irq_state[i] = qemu_get_be32(f);
 149
 150     return 0;
 151 }
 152
 153 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 154 {
 155     uint16_t *id;
 156
 157     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 158     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 159     id[1] = cpu_to_le16(pci_default_sub_device_id);
 160     return 0;
 161 }
 162
 163 /*
 164  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 165  */
 166 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 167 {
 168     const char *p;
 169     char *e;
 170     unsigned long val;
 171     unsigned long dom = 0, bus = 0;
 172     unsigned slot = 0;
 173
 174     p = addr;
 175     val = strtoul(p, &e, 16);
 176     if (e == p)
 177         return -1;
 178     if (*e == ':') {
 179         bus = val;
 180         p = e + 1;
 181         val = strtoul(p, &e, 16);
 182         if (e == p)
 183             return -1;
 184         if (*e == ':') {
 185             dom = bus;
 186             bus = val;
 187             p = e + 1;
 188             val = strtoul(p, &e, 16);
 189             if (e == p)
 190                 return -1;
 191         }
 192     }
 193
 194     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 195         return -1;
 196
 197     slot = val;
 198
 199     if (*e)
 200         return -1;
 201
 202     /* Note: QEMU doesn't implement domains other than 0 */
 203     if (dom != 0 || pci_find_bus(bus) == NULL)
 204         return -1;
 205
 206     *domp = dom;
 207     *busp = bus;
 208     *slotp = slot;
 209     return 0;
 210 }
 211
 212 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 213 {
 214     char devaddr[32];
 215
 216     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 217         return -1;
 218
 219     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 220 }
 221
 222 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 223 {
 224     char devaddr[32];
 225
 226     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 227         return -1;
 228
 229     if (!strcmp(devaddr, "auto")) {
 230         *domp = *busp = 0;
 231         *slotp = -1;
 232         /* want to support dom/bus auto-assign at some point */
 233         return 0;
 234     }
 235
 236     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 237 }
 238
 239 /* -1 for devfn means auto assign */
 240 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 241                                          const char *name, int devfn,
 242                                          PCIConfigReadFunc *config_read,
 243                                          PCIConfigWriteFunc *config_write)
 244 {
 245     if (pci_irq_index >= PCI_DEVICES_MAX)
 246         return NULL;
 247
 248     if (devfn < 0) {
 249         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 250             if (!bus->devices[devfn])
 251                 goto found;
 252         }
 253         return NULL;
 254     found: ;
 255     }
 256     pci_dev->bus = bus;
 257     pci_dev->devfn = devfn;
 258     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 259     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 260     pci_set_default_subsystem_id(pci_dev);
 261
 262     if (!config_read)
 263         config_read = pci_default_read_config;
 264     if (!config_write)
 265         config_write = pci_default_write_config;
 266     pci_dev->config_read = config_read;
 267     pci_dev->config_write = config_write;
 268     pci_dev->irq_index = pci_irq_index++;
 269     bus->devices[devfn] = pci_dev;
 270     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 271     return pci_dev;
 272 }
 273
 274 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 275                                int instance_size, int devfn,
 276                                PCIConfigReadFunc *config_read,
 277                                PCIConfigWriteFunc *config_write)
 278 {
 279     PCIDevice *pci_dev;
 280
 281     pci_dev = qemu_mallocz(instance_size);
 282     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 283                                      config_read, config_write);
 284     return pci_dev;
 285 }
 286 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 287 {
 288     return addr + pci_mem_base;
 289 }
 290
 291 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 292 {
 293     PCIIORegion *r;
 294     int i;
 295
 296     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 297         r = &pci_dev->io_regions[i];
 298         if (!r->size || r->addr == -1)
 299             continue;
 300         if (r->type == PCI_ADDRESS_SPACE_IO) {
 301             isa_unassign_ioport(r->addr, r->size);
 302         } else {
 303             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 304                                                      r->size,
 305                                                      IO_MEM_UNASSIGNED);
 306         }
 307     }
 308 }
 309
 310 int pci_unregister_device(PCIDevice *pci_dev)
 311 {
 312     int ret = 0;
 313
 314     if (pci_dev->unregister)
 315         ret = pci_dev->unregister(pci_dev);
 316     if (ret)
 317         return ret;
 318
 319     pci_unregister_io_regions(pci_dev);
 320
 321     qemu_free_irqs(pci_dev->irq);
 322     pci_irq_index--;
 323     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 324     qemu_free(pci_dev);
 325     return 0;
 326 }
 327
 328 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 329                             uint32_t size, int type,
 330                             PCIMapIORegionFunc *map_func)
 331 {
 332     PCIIORegion *r;
 333     uint32_t addr;
 334
 335     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 336         return;
 337
 338     if (size & (size-1)) {
 339         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 340                     "type=0x%x, size=0x%x\n", type, size);
 341         exit(1);
 342     }
 343
 344     r = &pci_dev->io_regions[region_num];
 345     r->addr = -1;
 346     r->size = size;
 347     r->type = type;
 348     r->map_func = map_func;
 349     if (region_num == PCI_ROM_SLOT) {
 350         addr = 0x30;
 351     } else {
 352         addr = 0x10 + region_num * 4;
 353     }
 354     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 355 }
 356
 357 static void pci_update_mappings(PCIDevice *d)
 358 {
 359     PCIIORegion *r;
 360     int cmd, i;
 361     uint32_t last_addr, new_addr, config_ofs;
 362
 363     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 364     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 365         r = &d->io_regions[i];
 366         if (i == PCI_ROM_SLOT) {
 367             config_ofs = 0x30;
 368         } else {
 369             config_ofs = 0x10 + i * 4;
 370         }
 371         if (r->size != 0) {
 372             if (r->type & PCI_ADDRESS_SPACE_IO) {
 373                 if (cmd & PCI_COMMAND_IO) {
 374                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 375                                                          config_ofs));
 376                     new_addr = new_addr & ~(r->size - 1);
 377                     last_addr = new_addr + r->size - 1;
 378                     /* NOTE: we have only 64K ioports on PC */
 379                     if (last_addr <= new_addr || new_addr == 0 ||
 380                         last_addr >= 0x10000) {
 381                         new_addr = -1;
 382                     }
 383                 } else {
 384                     new_addr = -1;
 385                 }
 386             } else {
 387                 if (cmd & PCI_COMMAND_MEMORY) {
 388                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 389                                                          config_ofs));
 390                     /* the ROM slot has a specific enable bit */
 391                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 392                         goto no_mem_map;
 393                     new_addr = new_addr & ~(r->size - 1);
 394                     last_addr = new_addr + r->size - 1;
 395                     /* NOTE: we do not support wrapping */
 396                     /* XXX: as we cannot support really dynamic
 397                        mappings, we handle specific values as invalid
 398                        mappings. */
 399                     if (last_addr <= new_addr || new_addr == 0 ||
 400                         last_addr == -1) {
 401                         new_addr = -1;
 402                     }
 403                 } else {
 404                 no_mem_map:
 405                     new_addr = -1;
 406                 }
 407             }
 408             /* now do the real mapping */
 409             if (new_addr != r->addr) {
 410                 if (r->addr != -1) {
 411                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 412                         int class;
 413                         /* NOTE: specific hack for IDE in PC case:
 414                            only one byte must be mapped. */
 415                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 416                         if (class == 0x0101 && r->size == 4) {
 417                             isa_unassign_ioport(r->addr + 2, 1);
 418                         } else {
 419                             isa_unassign_ioport(r->addr, r->size);
 420                         }
 421                     } else {
 422                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 423                                                      r->size,
 424                                                      IO_MEM_UNASSIGNED);
 425                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 426                     }
 427                 }
 428                 r->addr = new_addr;
 429                 if (r->addr != -1) {
 430                     r->map_func(d, i, r->addr, r->size, r->type);
 431                 }
 432             }
 433         }
 434     }
 435 }
 436
 437 uint32_t pci_default_read_config(PCIDevice *d,
 438                                  uint32_t address, int len)
 439 {
 440     uint32_t val;
 441
 442     switch(len) {
 443     default:
 444     case 4:
 445         if (address <= 0xfc) {
 446             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 447             break;
 448         }
 449         /* fall through */
 450     case 2:
 451         if (address <= 0xfe) {
 452             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 453             break;
 454         }
 455         /* fall through */
 456     case 1:
 457         val = d->config[address];
 458         break;
 459     }
 460     return val;
 461 }
 462
 463 void pci_default_write_config(PCIDevice *d,
 464                               uint32_t address, uint32_t val, int len)
 465 {
 466     int can_write, i;
 467     uint32_t end, addr;
 468
 469     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 470                      (address >= 0x30 && address < 0x34))) {
 471         PCIIORegion *r;
 472         int reg;
 473
 474         if ( address >= 0x30 ) {
 475             reg = PCI_ROM_SLOT;
 476         }else{
 477             reg = (address - 0x10) >> 2;
 478         }
 479         r = &d->io_regions[reg];
 480         if (r->size == 0)
 481             goto default_config;
 482         /* compute the stored value */
 483         if (reg == PCI_ROM_SLOT) {
 484             /* keep ROM enable bit */
 485             val &= (~(r->size - 1)) | 1;
 486         } else {
 487             val &= ~(r->size - 1);
 488             val |= r->type;
 489         }
 490         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 491         pci_update_mappings(d);
 492         return;
 493     }
 494  default_config:
 495     /* not efficient, but simple */
 496     addr = address;
 497     for(i = 0; i < len; i++) {
 498         /* default read/write accesses */
 499         switch(d->config[0x0e]) {
 500         case 0x00:
 501         case 0x80:
 502             switch(addr) {
 503             case 0x00:
 504             case 0x01:
 505             case 0x02:
 506             case 0x03:
 507             case 0x06:
 508             case 0x07:
 509             case 0x08:
 510             case 0x09:
 511             case 0x0a:
 512             case 0x0b:
 513             case 0x0e:
 514             case 0x10 ... 0x27: /* base */
 515             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 516             case 0x30 ... 0x33: /* rom */
 517             case 0x3d:
 518                 can_write = 0;
 519                 break;
 520             default:
 521                 can_write = 1;
 522                 break;
 523             }
 524             break;
 525         default:
 526         case 0x01:
 527             switch(addr) {
 528             case 0x00:
 529             case 0x01:
 530             case 0x02:
 531             case 0x03:
 532             case 0x06:
 533             case 0x07:
 534             case 0x08:
 535             case 0x09:
 536             case 0x0a:
 537             case 0x0b:
 538             case 0x0e:
 539             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 540             case 0x38 ... 0x3b: /* rom */
 541             case 0x3d:
 542                 can_write = 0;
 543                 break;
 544             default:
 545                 can_write = 1;
 546                 break;
 547             }
 548             break;
 549         }
 550         if (can_write) {
 551             /* Mask out writes to reserved bits in registers */
 552             switch (addr) {
 553             case 0x05:
 554                 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
 555                 break;
 556             case 0x06:
 557                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
 558                 break;
 559             case 0x07:
 560                 val &= ~PCI_STATUS_RESERVED_MASK_HI;
 561                 break;
 562             }
 563             d->config[addr] = val;
 564         }
 565         if (++addr > 0xff)
 566                 break;
 567         val >>= 8;
 568     }
 569
 570     end = address + len;
 571     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 572         /* if the command register is modified, we must modify the mappings */
 573         pci_update_mappings(d);
 574     }
 575 }
 576
 577 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 578 {
 579     PCIBus *s = opaque;
 580     PCIDevice *pci_dev;
 581     int config_addr, bus_num;
 582
 583 #if defined(DEBUG_PCI) && 0
 584     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 585            addr, val, len);
 586 #endif
 587     bus_num = (addr >> 16) & 0xff;
 588     while (s && s->bus_num != bus_num)
 589         s = s->next;
 590     if (!s)
 591         return;
 592     pci_dev = s->devices[(addr >> 8) & 0xff];
 593     if (!pci_dev)
 594         return;
 595     config_addr = addr & 0xff;
 596 #if defined(DEBUG_PCI)
 597     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 598            pci_dev->name, config_addr, val, len);
 599 #endif
 600     pci_dev->config_write(pci_dev, config_addr, val, len);
 601 }
 602
 603 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 604 {
 605     PCIBus *s = opaque;
 606     PCIDevice *pci_dev;
 607     int config_addr, bus_num;
 608     uint32_t val;
 609
 610     bus_num = (addr >> 16) & 0xff;
 611     while (s && s->bus_num != bus_num)
 612         s= s->next;
 613     if (!s)
 614         goto fail;
 615     pci_dev = s->devices[(addr >> 8) & 0xff];
 616     if (!pci_dev) {
 617     fail:
 618         switch(len) {
 619         case 1:
 620             val = 0xff;
 621             break;
 622         case 2:
 623             val = 0xffff;
 624             break;
 625         default:
 626         case 4:
 627             val = 0xffffffff;
 628             break;
 629         }
 630         goto the_end;
 631     }
 632     config_addr = addr & 0xff;
 633     val = pci_dev->config_read(pci_dev, config_addr, len);
 634 #if defined(DEBUG_PCI)
 635     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 636            pci_dev->name, config_addr, val, len);
 637 #endif
 638  the_end:
 639 #if defined(DEBUG_PCI) && 0
 640     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 641            addr, val, len);
 642 #endif
 643     return val;
 644 }
 645
 646 /***********************************************************/
 647 /* generic PCI irq support */
 648
 649 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 650 static void pci_set_irq(void *opaque, int irq_num, int level)
 651 {
 652     PCIDevice *pci_dev = (PCIDevice *)opaque;
 653     PCIBus *bus;
 654     int change;
 655
 656     change = level - pci_dev->irq_state[irq_num];
 657     if (!change)
 658         return;
 659
 660     pci_dev->irq_state[irq_num] = level;
 661     for (;;) {
 662         bus = pci_dev->bus;
 663         irq_num = bus->map_irq(pci_dev, irq_num);
 664         if (bus->set_irq)
 665             break;
 666         pci_dev = bus->parent_dev;
 667     }
 668     bus->irq_count[irq_num] += change;
 669     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 670 }
 671
 672 /***********************************************************/
 673 /* monitor info on PCI */
 674
 675 typedef struct {
 676     uint16_t class;
 677     const char *desc;
 678 } pci_class_desc;
 679
 680 static const pci_class_desc pci_class_descriptions[] =
 681 {
 682     { 0x0100, "SCSI controller"},
 683     { 0x0101, "IDE controller"},
 684     { 0x0102, "Floppy controller"},
 685     { 0x0103, "IPI controller"},
 686     { 0x0104, "RAID controller"},
 687     { 0x0106, "SATA controller"},
 688     { 0x0107, "SAS controller"},
 689     { 0x0180, "Storage controller"},
 690     { 0x0200, "Ethernet controller"},
 691     { 0x0201, "Token Ring controller"},
 692     { 0x0202, "FDDI controller"},
 693     { 0x0203, "ATM controller"},
 694     { 0x0280, "Network controller"},
 695     { 0x0300, "VGA controller"},
 696     { 0x0301, "XGA controller"},
 697     { 0x0302, "3D controller"},
 698     { 0x0380, "Display controller"},
 699     { 0x0400, "Video controller"},
 700     { 0x0401, "Audio controller"},
 701     { 0x0402, "Phone"},
 702     { 0x0480, "Multimedia controller"},
 703     { 0x0500, "RAM controller"},
 704     { 0x0501, "Flash controller"},
 705     { 0x0580, "Memory controller"},
 706     { 0x0600, "Host bridge"},
 707     { 0x0601, "ISA bridge"},
 708     { 0x0602, "EISA bridge"},
 709     { 0x0603, "MC bridge"},
 710     { 0x0604, "PCI bridge"},
 711     { 0x0605, "PCMCIA bridge"},
 712     { 0x0606, "NUBUS bridge"},
 713     { 0x0607, "CARDBUS bridge"},
 714     { 0x0608, "RACEWAY bridge"},
 715     { 0x0680, "Bridge"},
 716     { 0x0c03, "USB controller"},
 717     { 0, NULL}
 718 };
 719
 720 static void pci_info_device(PCIDevice *d)
 721 {
 722     Monitor *mon = cur_mon;
 723     int i, class;
 724     PCIIORegion *r;
 725     const pci_class_desc *desc;
 726
 727     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 728                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 729     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 730     monitor_printf(mon, "    ");
 731     desc = pci_class_descriptions;
 732     while (desc->desc && class != desc->class)
 733         desc++;
 734     if (desc->desc) {
 735         monitor_printf(mon, "%s", desc->desc);
 736     } else {
 737         monitor_printf(mon, "Class %04x", class);
 738     }
 739     monitor_printf(mon, ": PCI device %04x:%04x\n",
 740            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 741            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 742
 743     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 744         monitor_printf(mon, "      IRQ %d.\n",
 745                        d->config[PCI_INTERRUPT_LINE]);
 746     }
 747     if (class == 0x0604) {
 748         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 749     }
 750     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 751         r = &d->io_regions[i];
 752         if (r->size != 0) {
 753             monitor_printf(mon, "      BAR%d: ", i);
 754             if (r->type & PCI_ADDRESS_SPACE_IO) {
 755                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 756                                r->addr, r->addr + r->size - 1);
 757             } else {
 758                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 759                                r->addr, r->addr + r->size - 1);
 760             }
 761         }
 762     }
 763     if (class == 0x0604 && d->config[0x19] != 0) {
 764         pci_for_each_device(d->config[0x19], pci_info_device);
 765     }
 766 }
 767
 768 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 769 {
 770     PCIBus *bus = first_bus;
 771     PCIDevice *d;
 772     int devfn;
 773
 774     while (bus && bus->bus_num != bus_num)
 775         bus = bus->next;
 776     if (bus) {
 777         for(devfn = 0; devfn < 256; devfn++) {
 778             d = bus->devices[devfn];
 779             if (d)
 780                 fn(d);
 781         }
 782     }
 783 }
 784
 785 void pci_info(Monitor *mon)
 786 {
 787     pci_for_each_device(0, pci_info_device);
 788 }
 789
 790 static const char * const pci_nic_models[] = {
 791     "ne2k_pci",
 792     "i82551",
 793     "i82557b",
 794     "i82559er",
 795     "rtl8139",
 796     "e1000",
 797     "pcnet",
 798     "virtio",
 799     NULL
 800 };
 801
 802 typedef PCIDevice *(*PCINICInitFn)(PCIBus *, NICInfo *, int);
 803
 804 static PCINICInitFn pci_nic_init_fns[] = {
 805     pci_ne2000_init,
 806     pci_i82551_init,
 807     pci_i82557b_init,
 808     pci_i82559er_init,
 809     pci_rtl8139_init,
 810     pci_e1000_init,
 811     pci_pcnet_init,
 812     virtio_net_init,
 813     NULL
 814 };
 815
 816 /* Initialize a PCI NIC.  */
 817 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 818                   const char *default_model)
 819 {
 820     PCIDevice *pci_dev;
 821     int i;
 822
 823     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 824
 825     for (i = 0; pci_nic_models[i]; i++)
 826         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 827             pci_dev = pci_nic_init_fns[i](bus, nd, devfn);
 828             if (pci_dev)
 829                 nd->private = pci_dev;
 830             return pci_dev;
 831         }
 832
 833     return NULL;
 834 }
 835
 836 typedef struct {
 837     PCIDevice dev;
 838     PCIBus *bus;
 839 } PCIBridge;
 840
 841 static void pci_bridge_write_config(PCIDevice *d,
 842                              uint32_t address, uint32_t val, int len)
 843 {
 844     PCIBridge *s = (PCIBridge *)d;
 845
 846     if (address == 0x19 || (address == 0x18 && len > 1)) {
 847         if (address == 0x19)
 848             s->bus->bus_num = val & 0xff;
 849         else
 850             s->bus->bus_num = (val >> 8) & 0xff;
 851 #if defined(DEBUG_PCI)
 852         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 853 #endif
 854     }
 855     pci_default_write_config(d, address, val, len);
 856 }
 857
 858 PCIBus *pci_find_bus(int bus_num)
 859 {
 860     PCIBus *bus = first_bus;
 861
 862     while (bus && bus->bus_num != bus_num)
 863         bus = bus->next;
 864
 865     return bus;
 866 }
 867
 868 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 869 {
 870     PCIBus *bus = pci_find_bus(bus_num);
 871
 872     if (!bus)
 873         return NULL;
 874
 875     return bus->devices[PCI_DEVFN(slot, function)];
 876 }
 877
 878 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 879                         pci_map_irq_fn map_irq, const char *name)
 880 {
 881     PCIBridge *s;
 882     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 883                                          devfn, NULL, pci_bridge_write_config);
 884
 885     pci_config_set_vendor_id(s->dev.config, vid);
 886     pci_config_set_device_id(s->dev.config, did);
 887
 888     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 889     s->dev.config[0x05] = 0x00;
 890     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 891     s->dev.config[0x07] = 0x00; // status = fast devsel
 892     s->dev.config[0x08] = 0x00; // revision
 893     s->dev.config[0x09] = 0x00; // programming i/f
 894     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 895     s->dev.config[0x0D] = 0x10; // latency_timer
 896     s->dev.config[PCI_HEADER_TYPE] =
 897         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 898     s->dev.config[0x1E] = 0xa0; // secondary status
 899
 900     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 901     return s->bus;
 902 }
 903
 904 static void pci_qdev_init(DeviceState *qdev, void *opaque)
 905 {
 906     PCIDevice *pci_dev = (PCIDevice *)qdev;
 907     pci_qdev_initfn init;
 908     PCIBus *bus;
 909     int devfn;
 910
 911     init = opaque;
 912     bus = qdev_get_bus(qdev);
 913     devfn = qdev_get_prop_int(qdev, "devfn", -1);
 914     pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
 915                                      NULL, NULL);//FIXME:config_read, config_write);
 916     assert(pci_dev);
 917     init(pci_dev);
 918 }
 919
 920 void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
 921 {
 922     qdev_register(name, size, pci_qdev_init, init);
 923 }
 924
 925 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 926 {
 927     DeviceState *dev;
 928
 929     dev = qdev_create(bus, name);
 930     qdev_set_prop_int(dev, "devfn", devfn);
 931     qdev_init(dev);
 932
 933     return (PCIDevice *)dev;
 934 }