target-i386/exec.h

   1 /*
   2  *  i386 execution defines
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #include "dyngen-exec.h"
  22
  23 /* XXX: factorize this mess */
  24 #ifdef TARGET_X86_64
  25 #define TARGET_LONG_BITS 64
  26 #else
  27 #define TARGET_LONG_BITS 32
  28 #endif
  29
  30 #include "cpu-defs.h"
  31
  32 register struct CPUX86State *env asm(AREG0);
  33
  34 extern FILE *logfile;
  35 extern int loglevel;
  36
  37 #define EAX (env->regs[R_EAX])
  38 #define ECX (env->regs[R_ECX])
  39 #define EDX (env->regs[R_EDX])
  40 #define EBX (env->regs[R_EBX])
  41 #define ESP (env->regs[R_ESP])
  42 #define EBP (env->regs[R_EBP])
  43 #define ESI (env->regs[R_ESI])
  44 #define EDI (env->regs[R_EDI])
  45 #define EIP (env->eip)
  46 #define DF  (env->df)
  47
  48 #define CC_SRC (env->cc_src)
  49 #define CC_DST (env->cc_dst)
  50 #define CC_OP  (env->cc_op)
  51
  52 /* float macros */
  53 #define FT0    (env->ft0)
  54 #define ST0    (env->fpregs[env->fpstt].d)
  55 #define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
  56 #define ST1    ST(1)
  57
  58 #include "cpu.h"
  59 #include "exec-all.h"
  60
  61 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
  62 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
  63 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
  64 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
  65                              int is_write, int mmu_idx, int is_softmmu);
  66 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
  67               void *retaddr);
  68 void __hidden cpu_lock(void);
  69 void __hidden cpu_unlock(void);
  70 void do_interrupt(int intno, int is_int, int error_code,
  71                   target_ulong next_eip, int is_hw);
  72 void do_interrupt_user(int intno, int is_int, int error_code,
  73                        target_ulong next_eip);
  74 void raise_interrupt(int intno, int is_int, int error_code,
  75                      int next_eip_addend);
  76 void raise_exception_err(int exception_index, int error_code);
  77 void raise_exception(int exception_index);
  78 void do_smm_enter(void);
  79 void __hidden cpu_loop_exit(void);
  80
  81 void OPPROTO op_movl_eflags_T0(void);
  82 void OPPROTO op_movl_T0_eflags(void);
  83
  84 /* n must be a constant to be efficient */
  85 static inline target_long lshift(target_long x, int n)
  86 {
  87     if (n >= 0)
  88         return x << n;
  89     else
  90         return x >> (-n);
  91 }
  92
  93 #include "helper.h"
  94
  95 static inline void svm_check_intercept(uint32_t type)
  96 {
  97     helper_svm_check_intercept_param(type, 0);
  98 }
  99
 100 #if !defined(CONFIG_USER_ONLY)
 101
 102 #include "softmmu_exec.h"
 103
 104 #endif /* !defined(CONFIG_USER_ONLY) */
 105
 106 #ifdef USE_X86LDOUBLE
 107 /* use long double functions */
 108 #define floatx_to_int32 floatx80_to_int32
 109 #define floatx_to_int64 floatx80_to_int64
 110 #define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
 111 #define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
 112 #define int32_to_floatx int32_to_floatx80
 113 #define int64_to_floatx int64_to_floatx80
 114 #define float32_to_floatx float32_to_floatx80
 115 #define float64_to_floatx float64_to_floatx80
 116 #define floatx_to_float32 floatx80_to_float32
 117 #define floatx_to_float64 floatx80_to_float64
 118 #define floatx_abs floatx80_abs
 119 #define floatx_chs floatx80_chs
 120 #define floatx_round_to_int floatx80_round_to_int
 121 #define floatx_compare floatx80_compare
 122 #define floatx_compare_quiet floatx80_compare_quiet
 123 #define sin sinl
 124 #define cos cosl
 125 #define sqrt sqrtl
 126 #define pow powl
 127 #define log logl
 128 #define tan tanl
 129 #define atan2 atan2l
 130 #define floor floorl
 131 #define ceil ceill
 132 #define ldexp ldexpl
 133 #else
 134 #define floatx_to_int32 float64_to_int32
 135 #define floatx_to_int64 float64_to_int64
 136 #define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
 137 #define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
 138 #define int32_to_floatx int32_to_float64
 139 #define int64_to_floatx int64_to_float64
 140 #define float32_to_floatx float32_to_float64
 141 #define float64_to_floatx(x, e) (x)
 142 #define floatx_to_float32 float64_to_float32
 143 #define floatx_to_float64(x, e) (x)
 144 #define floatx_abs float64_abs
 145 #define floatx_chs float64_chs
 146 #define floatx_round_to_int float64_round_to_int
 147 #define floatx_compare float64_compare
 148 #define floatx_compare_quiet float64_compare_quiet
 149 #endif
 150
 151 extern CPU86_LDouble sin(CPU86_LDouble x);
 152 extern CPU86_LDouble cos(CPU86_LDouble x);
 153 extern CPU86_LDouble sqrt(CPU86_LDouble x);
 154 extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
 155 extern CPU86_LDouble log(CPU86_LDouble x);
 156 extern CPU86_LDouble tan(CPU86_LDouble x);
 157 extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
 158 extern CPU86_LDouble floor(CPU86_LDouble x);
 159 extern CPU86_LDouble ceil(CPU86_LDouble x);
 160
 161 #define RC_MASK         0xc00
 162 #define RC_NEAR         0x000
 163 #define RC_DOWN         0x400
 164 #define RC_UP           0x800
 165 #define RC_CHOP         0xc00
 166
 167 #define MAXTAN 9223372036854775808.0
 168
 169 #ifdef USE_X86LDOUBLE
 170
 171 /* only for x86 */
 172 typedef union {
 173     long double d;
 174     struct {
 175         unsigned long long lower;
 176         unsigned short upper;
 177     } l;
 178 } CPU86_LDoubleU;
 179
 180 /* the following deal with x86 long double-precision numbers */
 181 #define MAXEXPD 0x7fff
 182 #define EXPBIAS 16383
 183 #define EXPD(fp)        (fp.l.upper & 0x7fff)
 184 #define SIGND(fp)       ((fp.l.upper) & 0x8000)
 185 #define MANTD(fp)       (fp.l.lower)
 186 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
 187
 188 #else
 189
 190 /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
 191 typedef union {
 192     double d;
 193 #if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
 194     struct {
 195         uint32_t lower;
 196         int32_t upper;
 197     } l;
 198 #else
 199     struct {
 200         int32_t upper;
 201         uint32_t lower;
 202     } l;
 203 #endif
 204 #ifndef __arm__
 205     int64_t ll;
 206 #endif
 207 } CPU86_LDoubleU;
 208
 209 /* the following deal with IEEE double-precision numbers */
 210 #define MAXEXPD 0x7ff
 211 #define EXPBIAS 1023
 212 #define EXPD(fp)        (((fp.l.upper) >> 20) & 0x7FF)
 213 #define SIGND(fp)       ((fp.l.upper) & 0x80000000)
 214 #ifdef __arm__
 215 #define MANTD(fp)       (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
 216 #else
 217 #define MANTD(fp)       (fp.ll & ((1LL << 52) - 1))
 218 #endif
 219 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
 220 #endif
 221
 222 static inline void fpush(void)
 223 {
 224     env->fpstt = (env->fpstt - 1) & 7;
 225     env->fptags[env->fpstt] = 0; /* validate stack entry */
 226 }
 227
 228 static inline void fpop(void)
 229 {
 230     env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
 231     env->fpstt = (env->fpstt + 1) & 7;
 232 }
 233
 234 #ifndef USE_X86LDOUBLE
 235 static inline CPU86_LDouble helper_fldt(target_ulong ptr)
 236 {
 237     CPU86_LDoubleU temp;
 238     int upper, e;
 239     uint64_t ll;
 240
 241     /* mantissa */
 242     upper = lduw(ptr + 8);
 243     /* XXX: handle overflow ? */
 244     e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
 245     e |= (upper >> 4) & 0x800; /* sign */
 246     ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
 247 #ifdef __arm__
 248     temp.l.upper = (e << 20) | (ll >> 32);
 249     temp.l.lower = ll;
 250 #else
 251     temp.ll = ll | ((uint64_t)e << 52);
 252 #endif
 253     return temp.d;
 254 }
 255
 256 static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
 257 {
 258     CPU86_LDoubleU temp;
 259     int e;
 260
 261     temp.d = f;
 262     /* mantissa */
 263     stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
 264     /* exponent + sign */
 265     e = EXPD(temp) - EXPBIAS + 16383;
 266     e |= SIGND(temp) >> 16;
 267     stw(ptr + 8, e);
 268 }
 269 #else
 270
 271 /* we use memory access macros */
 272
 273 static inline CPU86_LDouble helper_fldt(target_ulong ptr)
 274 {
 275     CPU86_LDoubleU temp;
 276
 277     temp.l.lower = ldq(ptr);
 278     temp.l.upper = lduw(ptr + 8);
 279     return temp.d;
 280 }
 281
 282 static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
 283 {
 284     CPU86_LDoubleU temp;
 285
 286     temp.d = f;
 287     stq(ptr, temp.l.lower);
 288     stw(ptr + 8, temp.l.upper);
 289 }
 290
 291 #endif /* USE_X86LDOUBLE */
 292
 293 #define FPUS_IE (1 << 0)
 294 #define FPUS_DE (1 << 1)
 295 #define FPUS_ZE (1 << 2)
 296 #define FPUS_OE (1 << 3)
 297 #define FPUS_UE (1 << 4)
 298 #define FPUS_PE (1 << 5)
 299 #define FPUS_SF (1 << 6)
 300 #define FPUS_SE (1 << 7)
 301 #define FPUS_B  (1 << 15)
 302
 303 #define FPUC_EM 0x3f
 304
 305 extern const CPU86_LDouble f15rk[7];
 306
 307 void fpu_raise_exception(void);
 308 void restore_native_fp_state(CPUState *env);
 309 void save_native_fp_state(CPUState *env);
 310
 311 extern const uint8_t parity_table[256];
 312 extern const uint8_t rclw_table[32];
 313 extern const uint8_t rclb_table[32];
 314
 315 static inline uint32_t compute_eflags(void)
 316 {
 317     return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 318 }
 319
 320 /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
 321 static inline void load_eflags(int eflags, int update_mask)
 322 {
 323     CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 324     DF = 1 - (2 * ((eflags >> 10) & 1));
 325     env->eflags = (env->eflags & ~update_mask) |
 326         (eflags & update_mask) | 0x2;
 327 }
 328
 329 static inline void env_to_regs(void)
 330 {
 331 #ifdef reg_EAX
 332     EAX = env->regs[R_EAX];
 333 #endif
 334 #ifdef reg_ECX
 335     ECX = env->regs[R_ECX];
 336 #endif
 337 #ifdef reg_EDX
 338     EDX = env->regs[R_EDX];
 339 #endif
 340 #ifdef reg_EBX
 341     EBX = env->regs[R_EBX];
 342 #endif
 343 #ifdef reg_ESP
 344     ESP = env->regs[R_ESP];
 345 #endif
 346 #ifdef reg_EBP
 347     EBP = env->regs[R_EBP];
 348 #endif
 349 #ifdef reg_ESI
 350     ESI = env->regs[R_ESI];
 351 #endif
 352 #ifdef reg_EDI
 353     EDI = env->regs[R_EDI];
 354 #endif
 355 }
 356
 357 static inline void regs_to_env(void)
 358 {
 359 #ifdef reg_EAX
 360     env->regs[R_EAX] = EAX;
 361 #endif
 362 #ifdef reg_ECX
 363     env->regs[R_ECX] = ECX;
 364 #endif
 365 #ifdef reg_EDX
 366     env->regs[R_EDX] = EDX;
 367 #endif
 368 #ifdef reg_EBX
 369     env->regs[R_EBX] = EBX;
 370 #endif
 371 #ifdef reg_ESP
 372     env->regs[R_ESP] = ESP;
 373 #endif
 374 #ifdef reg_EBP
 375     env->regs[R_EBP] = EBP;
 376 #endif
 377 #ifdef reg_ESI
 378     env->regs[R_ESI] = ESI;
 379 #endif
 380 #ifdef reg_EDI
 381     env->regs[R_EDI] = EDI;
 382 #endif
 383 }
 384
 385 static inline int cpu_halted(CPUState *env) {
 386     /* handle exit of HALTED state */
 387     if (!env->halted)
 388         return 0;
 389     /* disable halt condition */
 390     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 391          (env->eflags & IF_MASK)) ||
 392         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
 393         env->halted = 0;
 394         return 0;
 395     }
 396     return EXCP_HALTED;
 397 }
 398
 399 /* load efer and update the corresponding hflags. XXX: do consistency
 400    checks with cpuid bits ? */
 401 static inline void cpu_load_efer(CPUState *env, uint64_t val)
 402 {
 403     env->efer = val;
 404     env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
 405     if (env->efer & MSR_EFER_LMA)
 406         env->hflags |= HF_LMA_MASK;
 407     if (env->efer & MSR_EFER_SVME)
 408         env->hflags |= HF_SVME_MASK;
 409 }