hw/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL
   8  */
   9
  10 #include "vl.h"
  11 #include "arm_pic.h"
  12
  13 void DMA_run (void)
  14 {
  15 }
  16
  17 typedef struct {
  18     uint32_t flash_offset;
  19     uint32_t cm_osc;
  20     uint32_t cm_ctrl;
  21     uint32_t cm_lock;
  22     uint32_t cm_auxosc;
  23     uint32_t cm_sdram;
  24     uint32_t cm_init;
  25     uint32_t cm_flags;
  26     uint32_t cm_nvflags;
  27     uint32_t int_level;
  28     uint32_t irq_enabled;
  29     uint32_t fiq_enabled;
  30 } integratorcm_state;
  31
  32 static uint8_t integrator_spd[128] = {
  33    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  34    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  35 };
  36
  37 static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
  38 {
  39     integratorcm_state *s = (integratorcm_state *)opaque;
  40     offset -= 0x10000000;
  41     if (offset >= 0x100 && offset < 0x200) {
  42         /* CM_SPD */
  43         if (offset >= 0x180)
  44             return 0;
  45         return integrator_spd[offset >> 2];
  46     }
  47     switch (offset >> 2) {
  48     case 0: /* CM_ID */
  49         return 0x411a3001;
  50     case 1: /* CM_PROC */
  51         return 0;
  52     case 2: /* CM_OSC */
  53         return s->cm_osc;
  54     case 3: /* CM_CTRL */
  55         return s->cm_ctrl;
  56     case 4: /* CM_STAT */
  57         return 0x00100000;
  58     case 5: /* CM_LOCK */
  59         if (s->cm_lock == 0xa05f) {
  60             return 0x1a05f;
  61         } else {
  62             return s->cm_lock;
  63         }
  64     case 6: /* CM_LMBUSCNT */
  65         /* ??? High frequency timer.  */
  66         cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
  67     case 7: /* CM_AUXOSC */
  68         return s->cm_auxosc;
  69     case 8: /* CM_SDRAM */
  70         return s->cm_sdram;
  71     case 9: /* CM_INIT */
  72         return s->cm_init;
  73     case 10: /* CM_REFCT */
  74         /* ??? High frequency timer.  */
  75         cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
  76     case 12: /* CM_FLAGS */
  77         return s->cm_flags;
  78     case 14: /* CM_NVFLAGS */
  79         return s->cm_nvflags;
  80     case 16: /* CM_IRQ_STAT */
  81         return s->int_level & s->irq_enabled;
  82     case 17: /* CM_IRQ_RSTAT */
  83         return s->int_level;
  84     case 18: /* CM_IRQ_ENSET */
  85         return s->irq_enabled;
  86     case 20: /* CM_SOFT_INTSET */
  87         return s->int_level & 1;
  88     case 24: /* CM_FIQ_STAT */
  89         return s->int_level & s->fiq_enabled;
  90     case 25: /* CM_FIQ_RSTAT */
  91         return s->int_level;
  92     case 26: /* CM_FIQ_ENSET */
  93         return s->fiq_enabled;
  94     case 32: /* CM_VOLTAGE_CTL0 */
  95     case 33: /* CM_VOLTAGE_CTL1 */
  96     case 34: /* CM_VOLTAGE_CTL2 */
  97     case 35: /* CM_VOLTAGE_CTL3 */
  98         /* ??? Voltage control unimplemented.  */
  99         return 0;
 100     default:
 101         cpu_abort (cpu_single_env,
 102             "integratorcm_read: Unimplemented offset 0x%x\n", offset);
 103         return 0;
 104     }
 105 }
 106
 107 static void integratorcm_do_remap(integratorcm_state *s, int flash)
 108 {
 109     if (flash) {
 110         cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
 111     } else {
 112         cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
 113     }
 114     //??? tlb_flush (cpu_single_env, 1);
 115 }
 116
 117 static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
 118 {
 119     if (value & 8) {
 120         cpu_abort(cpu_single_env, "Board reset\n");
 121     }
 122     if ((s->cm_init ^ value) & 4) {
 123         integratorcm_do_remap(s, (value & 4) == 0);
 124     }
 125     if ((s->cm_init ^ value) & 1) {
 126         printf("Green LED %s\n", (value & 1) ? "on" : "off");
 127     }
 128     s->cm_init = (s->cm_init & ~ 5) | (value ^ 5);
 129 }
 130
 131 static void integratorcm_update(integratorcm_state *s)
 132 {
 133     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 134        are active.  */
 135     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 136         cpu_abort(cpu_single_env, "Core module interrupt\n");
 137 }
 138
 139 static void integratorcm_write(void *opaque, target_phys_addr_t offset,
 140                                uint32_t value)
 141 {
 142     integratorcm_state *s = (integratorcm_state *)opaque;
 143     offset -= 0x10000000;
 144     switch (offset >> 2) {
 145     case 2: /* CM_OSC */
 146         if (s->cm_lock == 0xa05f)
 147             s->cm_osc = value;
 148         break;
 149     case 3: /* CM_CTRL */
 150         integratorcm_set_ctrl(s, value);
 151         break;
 152     case 5: /* CM_LOCK */
 153         s->cm_lock = value & 0xffff;
 154         break;
 155     case 7: /* CM_AUXOSC */
 156         if (s->cm_lock == 0xa05f)
 157             s->cm_auxosc = value;
 158         break;
 159     case 8: /* CM_SDRAM */
 160         s->cm_sdram = value;
 161         break;
 162     case 9: /* CM_INIT */
 163         /* ??? This can change the memory bus frequency.  */
 164         s->cm_init = value;
 165         break;
 166     case 12: /* CM_FLAGSS */
 167         s->cm_flags |= value;
 168         break;
 169     case 13: /* CM_FLAGSC */
 170         s->cm_flags &= ~value;
 171         break;
 172     case 14: /* CM_NVFLAGSS */
 173         s->cm_nvflags |= value;
 174         break;
 175     case 15: /* CM_NVFLAGSS */
 176         s->cm_nvflags &= ~value;
 177         break;
 178     case 18: /* CM_IRQ_ENSET */
 179         s->irq_enabled |= value;
 180         integratorcm_update(s);
 181         break;
 182     case 19: /* CM_IRQ_ENCLR */
 183         s->irq_enabled &= ~value;
 184         integratorcm_update(s);
 185         break;
 186     case 20: /* CM_SOFT_INTSET */
 187         s->int_level |= (value & 1);
 188         integratorcm_update(s);
 189         break;
 190     case 21: /* CM_SOFT_INTCLR */
 191         s->int_level &= ~(value & 1);
 192         integratorcm_update(s);
 193         break;
 194     case 26: /* CM_FIQ_ENSET */
 195         s->fiq_enabled |= value;
 196         integratorcm_update(s);
 197         break;
 198     case 27: /* CM_FIQ_ENCLR */
 199         s->fiq_enabled &= ~value;
 200         integratorcm_update(s);
 201         break;
 202     case 32: /* CM_VOLTAGE_CTL0 */
 203     case 33: /* CM_VOLTAGE_CTL1 */
 204     case 34: /* CM_VOLTAGE_CTL2 */
 205     case 35: /* CM_VOLTAGE_CTL3 */
 206         /* ??? Voltage control unimplemented.  */
 207         break;
 208     default:
 209         cpu_abort (cpu_single_env,
 210             "integratorcm_write: Unimplemented offset 0x%x\n", offset);
 211         break;
 212     }
 213 }
 214
 215 /* Integrator/CM control registers.  */
 216
 217 static CPUReadMemoryFunc *integratorcm_readfn[] = {
 218    integratorcm_read,
 219    integratorcm_read,
 220    integratorcm_read
 221 };
 222
 223 static CPUWriteMemoryFunc *integratorcm_writefn[] = {
 224    integratorcm_write,
 225    integratorcm_write,
 226    integratorcm_write
 227 };
 228
 229 static void integratorcm_init(int memsz, uint32_t flash_offset)
 230 {
 231     int iomemtype;
 232     integratorcm_state *s;
 233
 234     s = (integratorcm_state *)qemu_mallocz(sizeof(integratorcm_state));
 235     s->cm_osc = 0x01000048;
 236     /* ??? What should the high bits of this value be?  */
 237     s->cm_auxosc = 0x0007feff;
 238     s->cm_sdram = 0x00011122;
 239     if (memsz >= 256) {
 240         integrator_spd[31] = 64;
 241         s->cm_sdram |= 0x10;
 242     } else if (memsz >= 128) {
 243         integrator_spd[31] = 32;
 244         s->cm_sdram |= 0x0c;
 245     } else if (memsz >= 64) {
 246         integrator_spd[31] = 16;
 247         s->cm_sdram |= 0x08;
 248     } else if (memsz >= 32) {
 249         integrator_spd[31] = 4;
 250         s->cm_sdram |= 0x04;
 251     } else {
 252         integrator_spd[31] = 2;
 253     }
 254     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 255     s->cm_init = 0x00000112;
 256     s->flash_offset = flash_offset;
 257
 258     iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
 259                                        integratorcm_writefn, s);
 260     cpu_register_physical_memory(0x10000000, 0x007fffff, iomemtype);
 261     integratorcm_do_remap(s, 1);
 262     /* ??? Save/restore.  */
 263 }
 264
 265 /* Integrator/CP hardware emulation.  */
 266 /* Primary interrupt controller.  */
 267
 268 typedef struct icp_pic_state
 269 {
 270   arm_pic_handler handler;
 271   uint32_t base;
 272   uint32_t level;
 273   uint32_t irq_enabled;
 274   uint32_t fiq_enabled;
 275   void *parent;
 276   int parent_irq;
 277   int parent_fiq;
 278 } icp_pic_state;
 279
 280 static void icp_pic_update(icp_pic_state *s)
 281 {
 282     uint32_t flags;
 283
 284     if (s->parent_irq != -1) {
 285         flags = (s->level & s->irq_enabled);
 286         pic_set_irq_new(s->parent, s->parent_irq, flags != 0);
 287     }
 288     if (s->parent_fiq != -1) {
 289         flags = (s->level & s->fiq_enabled);
 290         pic_set_irq_new(s->parent, s->parent_fiq, flags != 0);
 291     }
 292 }
 293
 294 static void icp_pic_set_irq(void *opaque, int irq, int level)
 295 {
 296     icp_pic_state *s = (icp_pic_state *)opaque;
 297     if (level)
 298         s->level |= 1 << irq;
 299     else
 300         s->level &= ~(1 << irq);
 301     icp_pic_update(s);
 302 }
 303
 304 static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
 305 {
 306     icp_pic_state *s = (icp_pic_state *)opaque;
 307
 308     offset -= s->base;
 309     switch (offset >> 2) {
 310     case 0: /* IRQ_STATUS */
 311         return s->level & s->irq_enabled;
 312     case 1: /* IRQ_RAWSTAT */
 313         return s->level;
 314     case 2: /* IRQ_ENABLESET */
 315         return s->irq_enabled;
 316     case 4: /* INT_SOFTSET */
 317         return s->level & 1;
 318     case 8: /* FRQ_STATUS */
 319         return s->level & s->fiq_enabled;
 320     case 9: /* FRQ_RAWSTAT */
 321         return s->level;
 322     case 10: /* FRQ_ENABLESET */
 323         return s->fiq_enabled;
 324     case 3: /* IRQ_ENABLECLR */
 325     case 5: /* INT_SOFTCLR */
 326     case 11: /* FRQ_ENABLECLR */
 327     default:
 328         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 329         return 0;
 330     }
 331 }
 332
 333 static void icp_pic_write(void *opaque, target_phys_addr_t offset,
 334                           uint32_t value)
 335 {
 336     icp_pic_state *s = (icp_pic_state *)opaque;
 337     offset -= s->base;
 338
 339     switch (offset >> 2) {
 340     case 2: /* IRQ_ENABLESET */
 341         s->irq_enabled |= value;
 342         break;
 343     case 3: /* IRQ_ENABLECLR */
 344         s->irq_enabled &= ~value;
 345         break;
 346     case 4: /* INT_SOFTSET */
 347         if (value & 1)
 348             pic_set_irq_new(s, 0, 1);
 349         break;
 350     case 5: /* INT_SOFTCLR */
 351         if (value & 1)
 352             pic_set_irq_new(s, 0, 0);
 353         break;
 354     case 10: /* FRQ_ENABLESET */
 355         s->fiq_enabled |= value;
 356         break;
 357     case 11: /* FRQ_ENABLECLR */
 358         s->fiq_enabled &= ~value;
 359         break;
 360     case 0: /* IRQ_STATUS */
 361     case 1: /* IRQ_RAWSTAT */
 362     case 8: /* FRQ_STATUS */
 363     case 9: /* FRQ_RAWSTAT */
 364     default:
 365         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 366         return;
 367     }
 368     icp_pic_update(s);
 369 }
 370
 371 static CPUReadMemoryFunc *icp_pic_readfn[] = {
 372    icp_pic_read,
 373    icp_pic_read,
 374    icp_pic_read
 375 };
 376
 377 static CPUWriteMemoryFunc *icp_pic_writefn[] = {
 378    icp_pic_write,
 379    icp_pic_write,
 380    icp_pic_write
 381 };
 382
 383 static icp_pic_state *icp_pic_init(uint32_t base, void *parent,
 384                                    int parent_irq, int parent_fiq)
 385 {
 386     icp_pic_state *s;
 387     int iomemtype;
 388
 389     s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));
 390     if (!s)
 391         return NULL;
 392     s->handler = icp_pic_set_irq;
 393     s->base = base;
 394     s->parent = parent;
 395     s->parent_irq = parent_irq;
 396     s->parent_fiq = parent_fiq;
 397     iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
 398                                        icp_pic_writefn, s);
 399     cpu_register_physical_memory(base, 0x007fffff, iomemtype);
 400     /* ??? Save/restore.  */
 401     return s;
 402 }
 403
 404 /* CP control registers.  */
 405 typedef struct {
 406     uint32_t base;
 407 } icp_control_state;
 408
 409 static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
 410 {
 411     icp_control_state *s = (icp_control_state *)opaque;
 412     offset -= s->base;
 413     switch (offset >> 2) {
 414     case 0: /* CP_IDFIELD */
 415         return 0x41034003;
 416     case 1: /* CP_FLASHPROG */
 417         return 0;
 418     case 2: /* CP_INTREG */
 419         return 0;
 420     case 3: /* CP_DECODE */
 421         return 0x11;
 422     default:
 423         cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset);
 424         return 0;
 425     }
 426 }
 427
 428 static void icp_control_write(void *opaque, target_phys_addr_t offset,
 429                           uint32_t value)
 430 {
 431     icp_control_state *s = (icp_control_state *)opaque;
 432     offset -= s->base;
 433     switch (offset >> 2) {
 434     case 1: /* CP_FLASHPROG */
 435     case 2: /* CP_INTREG */
 436     case 3: /* CP_DECODE */
 437         /* Nothing interesting implemented yet.  */
 438         break;
 439     default:
 440         cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset);
 441     }
 442 }
 443 static CPUReadMemoryFunc *icp_control_readfn[] = {
 444    icp_control_read,
 445    icp_control_read,
 446    icp_control_read
 447 };
 448
 449 static CPUWriteMemoryFunc *icp_control_writefn[] = {
 450    icp_control_write,
 451    icp_control_write,
 452    icp_control_write
 453 };
 454
 455 static void icp_control_init(uint32_t base)
 456 {
 457     int iomemtype;
 458     icp_control_state *s;
 459
 460     s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));
 461     iomemtype = cpu_register_io_memory(0, icp_control_readfn,
 462                                        icp_control_writefn, s);
 463     cpu_register_physical_memory(base, 0x007fffff, iomemtype);
 464     s->base = base;
 465     /* ??? Save/restore.  */
 466 }
 467
 468
 469 /* Board init.  */
 470
 471 static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device,
 472                      DisplayState *ds, const char **fd_filename, int snapshot,
 473                      const char *kernel_filename, const char *kernel_cmdline,
 474                      const char *initrd_filename, const char *cpu_model)
 475 {
 476     CPUState *env;
 477     uint32_t bios_offset;
 478     icp_pic_state *pic;
 479     void *cpu_pic;
 480
 481     env = cpu_init();
 482     if (!cpu_model)
 483         cpu_model = "arm926";
 484     cpu_arm_set_model(env, cpu_model);
 485     bios_offset = ram_size + vga_ram_size;
 486     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 487     /* ??? RAM shoud repeat to fill physical memory space.  */
 488     /* SDRAM at address zero*/
 489     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 490     /* And again at address 0x80000000 */
 491     cpu_register_physical_memory(0x80000000, ram_size, IO_MEM_RAM);
 492
 493     integratorcm_init(ram_size >> 20, bios_offset);
 494     cpu_pic = arm_pic_init_cpu(env);
 495     pic = icp_pic_init(0x14000000, cpu_pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
 496     icp_pic_init(0xca000000, pic, 26, -1);
 497     icp_pit_init(0x13000000, pic, 5);
 498     pl011_init(0x16000000, pic, 1, serial_hds[0]);
 499     pl011_init(0x17000000, pic, 2, serial_hds[1]);
 500     icp_control_init(0xcb000000);
 501     pl050_init(0x18000000, pic, 3, 0);
 502     pl050_init(0x19000000, pic, 4, 1);
 503     pl181_init(0x1c000000, sd_bdrv, pic, 23, 24);
 504     if (nd_table[0].vlan) {
 505         if (nd_table[0].model == NULL
 506             || strcmp(nd_table[0].model, "smc91c111") == 0) {
 507             smc91c111_init(&nd_table[0], 0xc8000000, pic, 27);
 508         } else {
 509             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 510             exit (1);
 511         }
 512     }
 513     pl110_init(ds, 0xc0000000, pic, 22, 0);
 514
 515     arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,
 516                     initrd_filename, 0x113);
 517 }
 518
 519 QEMUMachine integratorcp_machine = {
 520     "integratorcp",
 521     "ARM Integrator/CP (ARM926EJ-S)",
 522     integratorcp_init,
 523 };