target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25
  26 //#define DEBUG_KVM
  27
  28 #ifdef DEBUG_KVM
  29 #define dprintf(fmt, ...) \
  30     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  31 #else
  32 #define dprintf(fmt, ...) \
  33     do { } while (0)
  34 #endif
  35
  36 int kvm_arch_init_vcpu(CPUState *env)
  37 {
  38     struct {
  39         struct kvm_cpuid2 cpuid;
  40         struct kvm_cpuid_entry2 entries[100];
  41     } __attribute__((packed)) cpuid_data;
  42     uint32_t limit, i, j, cpuid_i;
  43     uint32_t eax, ebx, ecx, edx;
  44
  45     cpuid_i = 0;
  46
  47     cpu_x86_cpuid(env, 0, 0, &eax, &ebx, &ecx, &edx);
  48     limit = eax;
  49
  50     for (i = 0; i <= limit; i++) {
  51         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
  52
  53         switch (i) {
  54         case 2: {
  55             /* Keep reading function 2 till all the input is received */
  56             int times;
  57
  58             cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
  59             times = eax & 0xff;
  60
  61             c->function = i;
  62             c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
  63             c->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
  64             c->eax = eax;
  65             c->ebx = ebx;
  66             c->ecx = ecx;
  67             c->edx = edx;
  68
  69             for (j = 1; j < times; ++j) {
  70                 cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
  71                 c->function = i;
  72                 c->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
  73                 c->eax = eax;
  74                 c->ebx = ebx;
  75                 c->ecx = ecx;
  76                 c->edx = edx;
  77                 c = &cpuid_data.entries[++cpuid_i];
  78             }
  79             break;
  80         }
  81         case 4:
  82         case 0xb:
  83         case 0xd:
  84             for (j = 0; ; j++) {
  85                 cpu_x86_cpuid(env, i, j, &eax, &ebx, &ecx, &edx);
  86                 c->function = i;
  87                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  88                 c->index = j;
  89                 c->eax = eax;
  90                 c->ebx = ebx;
  91                 c->ecx = ecx;
  92                 c->edx = edx;
  93                 c = &cpuid_data.entries[++cpuid_i];
  94
  95                 if (i == 4 && eax == 0)
  96                     break;
  97                 if (i == 0xb && !(ecx & 0xff00))
  98                     break;
  99                 if (i == 0xd && eax == 0)
 100                     break;
 101             }
 102             break;
 103         default:
 104             cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
 105             c->function = i;
 106             c->eax = eax;
 107             c->ebx = ebx;
 108             c->ecx = ecx;
 109             c->edx = edx;
 110             break;
 111         }
 112     }
 113     cpu_x86_cpuid(env, 0x80000000, 0, &eax, &ebx, &ecx, &edx);
 114     limit = eax;
 115
 116     for (i = 0x80000000; i <= limit; i++) {
 117         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 118
 119         cpu_x86_cpuid(env, i, 0, &eax, &ebx, &ecx, &edx);
 120         c->function = i;
 121         c->eax = eax;
 122         c->ebx = ebx;
 123         c->ecx = ecx;
 124         c->edx = edx;
 125     }
 126
 127     cpuid_data.cpuid.nent = cpuid_i;
 128
 129     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 130 }
 131
 132 static int kvm_has_msr_star(CPUState *env)
 133 {
 134     static int has_msr_star;
 135     int ret;
 136
 137     /* first time */
 138     if (has_msr_star == 0) {
 139         struct kvm_msr_list msr_list, *kvm_msr_list;
 140
 141         has_msr_star = -1;
 142
 143         /* Obtain MSR list from KVM.  These are the MSRs that we must
 144          * save/restore */
 145         msr_list.nmsrs = 0;
 146         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 147         if (ret < 0)
 148             return 0;
 149
 150         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 151                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 152
 153         kvm_msr_list->nmsrs = msr_list.nmsrs;
 154         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 155         if (ret >= 0) {
 156             int i;
 157
 158             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 159                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 160                     has_msr_star = 1;
 161                     break;
 162                 }
 163             }
 164         }
 165
 166         free(kvm_msr_list);
 167     }
 168
 169     if (has_msr_star == 1)
 170         return 1;
 171     return 0;
 172 }
 173
 174 int kvm_arch_init(KVMState *s, int smp_cpus)
 175 {
 176     int ret;
 177
 178     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 179      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 180      * must be part of guest physical memory, we need to allocate it.  Older
 181      * versions of KVM just assumed that it would be at the end of physical
 182      * memory but that doesn't work with more than 4GB of memory.  We simply
 183      * refuse to work with those older versions of KVM. */
 184     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 185     if (ret <= 0) {
 186         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 187         return ret;
 188     }
 189
 190     /* this address is 3 pages before the bios, and the bios should present
 191      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 192      * this?
 193      */
 194     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 195 }
 196
 197 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 198 {
 199     lhs->selector = rhs->selector;
 200     lhs->base = rhs->base;
 201     lhs->limit = rhs->limit;
 202     lhs->type = 3;
 203     lhs->present = 1;
 204     lhs->dpl = 3;
 205     lhs->db = 0;
 206     lhs->s = 1;
 207     lhs->l = 0;
 208     lhs->g = 0;
 209     lhs->avl = 0;
 210     lhs->unusable = 0;
 211 }
 212
 213 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 214 {
 215     unsigned flags = rhs->flags;
 216     lhs->selector = rhs->selector;
 217     lhs->base = rhs->base;
 218     lhs->limit = rhs->limit;
 219     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 220     lhs->present = (flags & DESC_P_MASK) != 0;
 221     lhs->dpl = rhs->selector & 3;
 222     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 223     lhs->s = (flags & DESC_S_MASK) != 0;
 224     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 225     lhs->g = (flags & DESC_G_MASK) != 0;
 226     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 227     lhs->unusable = 0;
 228 }
 229
 230 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 231 {
 232     lhs->selector = rhs->selector;
 233     lhs->base = rhs->base;
 234     lhs->limit = rhs->limit;
 235     lhs->flags =
 236         (rhs->type << DESC_TYPE_SHIFT)
 237         | (rhs->present * DESC_P_MASK)
 238         | (rhs->dpl << DESC_DPL_SHIFT)
 239         | (rhs->db << DESC_B_SHIFT)
 240         | (rhs->s * DESC_S_MASK)
 241         | (rhs->l << DESC_L_SHIFT)
 242         | (rhs->g * DESC_G_MASK)
 243         | (rhs->avl * DESC_AVL_MASK);
 244 }
 245
 246 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 247 {
 248     if (set)
 249         *kvm_reg = *qemu_reg;
 250     else
 251         *qemu_reg = *kvm_reg;
 252 }
 253
 254 static int kvm_getput_regs(CPUState *env, int set)
 255 {
 256     struct kvm_regs regs;
 257     int ret = 0;
 258
 259     if (!set) {
 260         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 261         if (ret < 0)
 262             return ret;
 263     }
 264
 265     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 266     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 267     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 268     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 269     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 270     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 271     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 272     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 273 #ifdef TARGET_X86_64
 274     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 275     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 276     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 277     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 278     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 279     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 280     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 281     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 282 #endif
 283
 284     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 285     kvm_getput_reg(&regs.rip, &env->eip, set);
 286
 287     if (set)
 288         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 289
 290     return ret;
 291 }
 292
 293 static int kvm_put_fpu(CPUState *env)
 294 {
 295     struct kvm_fpu fpu;
 296     int i;
 297
 298     memset(&fpu, 0, sizeof fpu);
 299     fpu.fsw = env->fpus & ~(7 << 11);
 300     fpu.fsw |= (env->fpstt & 7) << 11;
 301     fpu.fcw = env->fpuc;
 302     for (i = 0; i < 8; ++i)
 303         fpu.ftwx |= (!env->fptags[i]) << i;
 304     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 305     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 306     fpu.mxcsr = env->mxcsr;
 307
 308     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 309 }
 310
 311 static int kvm_put_sregs(CPUState *env)
 312 {
 313     struct kvm_sregs sregs;
 314
 315     memcpy(sregs.interrupt_bitmap,
 316            env->interrupt_bitmap,
 317            sizeof(sregs.interrupt_bitmap));
 318
 319     if ((env->eflags & VM_MASK)) {
 320             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 321             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 322             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 323             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 324             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 325             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 326     } else {
 327             set_seg(&sregs.cs, &env->segs[R_CS]);
 328             set_seg(&sregs.ds, &env->segs[R_DS]);
 329             set_seg(&sregs.es, &env->segs[R_ES]);
 330             set_seg(&sregs.fs, &env->segs[R_FS]);
 331             set_seg(&sregs.gs, &env->segs[R_GS]);
 332             set_seg(&sregs.ss, &env->segs[R_SS]);
 333
 334             if (env->cr[0] & CR0_PE_MASK) {
 335                 /* force ss cpl to cs cpl */
 336                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 337                         (sregs.cs.selector & 3);
 338                 sregs.ss.dpl = sregs.ss.selector & 3;
 339             }
 340     }
 341
 342     set_seg(&sregs.tr, &env->tr);
 343     set_seg(&sregs.ldt, &env->ldt);
 344
 345     sregs.idt.limit = env->idt.limit;
 346     sregs.idt.base = env->idt.base;
 347     sregs.gdt.limit = env->gdt.limit;
 348     sregs.gdt.base = env->gdt.base;
 349
 350     sregs.cr0 = env->cr[0];
 351     sregs.cr2 = env->cr[2];
 352     sregs.cr3 = env->cr[3];
 353     sregs.cr4 = env->cr[4];
 354
 355     sregs.cr8 = cpu_get_apic_tpr(env);
 356     sregs.apic_base = cpu_get_apic_base(env);
 357
 358     sregs.efer = env->efer;
 359
 360     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 361 }
 362
 363 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 364                               uint32_t index, uint64_t value)
 365 {
 366     entry->index = index;
 367     entry->data = value;
 368 }
 369
 370 static int kvm_put_msrs(CPUState *env)
 371 {
 372     struct {
 373         struct kvm_msrs info;
 374         struct kvm_msr_entry entries[100];
 375     } msr_data;
 376     struct kvm_msr_entry *msrs = msr_data.entries;
 377     int n = 0;
 378
 379     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 380     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 381     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 382     if (kvm_has_msr_star(env))
 383         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 384     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 385 #ifdef TARGET_X86_64
 386     /* FIXME if lm capable */
 387     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 388     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 389     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 390     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 391 #endif
 392     msr_data.info.nmsrs = n;
 393
 394     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 395
 396 }
 397
 398
 399 static int kvm_get_fpu(CPUState *env)
 400 {
 401     struct kvm_fpu fpu;
 402     int i, ret;
 403
 404     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 405     if (ret < 0)
 406         return ret;
 407
 408     env->fpstt = (fpu.fsw >> 11) & 7;
 409     env->fpus = fpu.fsw;
 410     env->fpuc = fpu.fcw;
 411     for (i = 0; i < 8; ++i)
 412         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 413     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 414     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 415     env->mxcsr = fpu.mxcsr;
 416
 417     return 0;
 418 }
 419
 420 static int kvm_get_sregs(CPUState *env)
 421 {
 422     struct kvm_sregs sregs;
 423     uint32_t hflags;
 424     int ret;
 425
 426     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 427     if (ret < 0)
 428         return ret;
 429
 430     memcpy(env->interrupt_bitmap,
 431            sregs.interrupt_bitmap,
 432            sizeof(sregs.interrupt_bitmap));
 433
 434     get_seg(&env->segs[R_CS], &sregs.cs);
 435     get_seg(&env->segs[R_DS], &sregs.ds);
 436     get_seg(&env->segs[R_ES], &sregs.es);
 437     get_seg(&env->segs[R_FS], &sregs.fs);
 438     get_seg(&env->segs[R_GS], &sregs.gs);
 439     get_seg(&env->segs[R_SS], &sregs.ss);
 440
 441     get_seg(&env->tr, &sregs.tr);
 442     get_seg(&env->ldt, &sregs.ldt);
 443
 444     env->idt.limit = sregs.idt.limit;
 445     env->idt.base = sregs.idt.base;
 446     env->gdt.limit = sregs.gdt.limit;
 447     env->gdt.base = sregs.gdt.base;
 448
 449     env->cr[0] = sregs.cr0;
 450     env->cr[2] = sregs.cr2;
 451     env->cr[3] = sregs.cr3;
 452     env->cr[4] = sregs.cr4;
 453
 454     cpu_set_apic_base(env, sregs.apic_base);
 455
 456     env->efer = sregs.efer;
 457     //cpu_set_apic_tpr(env, sregs.cr8);
 458
 459 #define HFLAG_COPY_MASK ~( \
 460                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 461                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 462                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 463                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 464
 465
 466
 467     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 468     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 469     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 470             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 471     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 472     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 473             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 474
 475     if (env->efer & MSR_EFER_LMA) {
 476         hflags |= HF_LMA_MASK;
 477     }
 478
 479     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 480         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 481     } else {
 482         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 483                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 484         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 485                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 486         if (!(env->cr[0] & CR0_PE_MASK) ||
 487                    (env->eflags & VM_MASK) ||
 488                    !(hflags & HF_CS32_MASK)) {
 489                 hflags |= HF_ADDSEG_MASK;
 490             } else {
 491                 hflags |= ((env->segs[R_DS].base |
 492                                 env->segs[R_ES].base |
 493                                 env->segs[R_SS].base) != 0) <<
 494                     HF_ADDSEG_SHIFT;
 495             }
 496     }
 497     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 498
 499     return 0;
 500 }
 501
 502 static int kvm_get_msrs(CPUState *env)
 503 {
 504     struct {
 505         struct kvm_msrs info;
 506         struct kvm_msr_entry entries[100];
 507     } msr_data;
 508     struct kvm_msr_entry *msrs = msr_data.entries;
 509     int ret, i, n;
 510
 511     n = 0;
 512     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 513     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 514     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 515     if (kvm_has_msr_star(env))
 516         msrs[n++].index = MSR_STAR;
 517     msrs[n++].index = MSR_IA32_TSC;
 518 #ifdef TARGET_X86_64
 519     /* FIXME lm_capable_kernel */
 520     msrs[n++].index = MSR_CSTAR;
 521     msrs[n++].index = MSR_KERNELGSBASE;
 522     msrs[n++].index = MSR_FMASK;
 523     msrs[n++].index = MSR_LSTAR;
 524 #endif
 525     msr_data.info.nmsrs = n;
 526     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 527     if (ret < 0)
 528         return ret;
 529
 530     for (i = 0; i < ret; i++) {
 531         switch (msrs[i].index) {
 532         case MSR_IA32_SYSENTER_CS:
 533             env->sysenter_cs = msrs[i].data;
 534             break;
 535         case MSR_IA32_SYSENTER_ESP:
 536             env->sysenter_esp = msrs[i].data;
 537             break;
 538         case MSR_IA32_SYSENTER_EIP:
 539             env->sysenter_eip = msrs[i].data;
 540             break;
 541         case MSR_STAR:
 542             env->star = msrs[i].data;
 543             break;
 544 #ifdef TARGET_X86_64
 545         case MSR_CSTAR:
 546             env->cstar = msrs[i].data;
 547             break;
 548         case MSR_KERNELGSBASE:
 549             env->kernelgsbase = msrs[i].data;
 550             break;
 551         case MSR_FMASK:
 552             env->fmask = msrs[i].data;
 553             break;
 554         case MSR_LSTAR:
 555             env->lstar = msrs[i].data;
 556             break;
 557 #endif
 558         case MSR_IA32_TSC:
 559             env->tsc = msrs[i].data;
 560             break;
 561         }
 562     }
 563
 564     return 0;
 565 }
 566
 567 int kvm_arch_put_registers(CPUState *env)
 568 {
 569     int ret;
 570
 571     ret = kvm_getput_regs(env, 1);
 572     if (ret < 0)
 573         return ret;
 574
 575     ret = kvm_put_fpu(env);
 576     if (ret < 0)
 577         return ret;
 578
 579     ret = kvm_put_sregs(env);
 580     if (ret < 0)
 581         return ret;
 582
 583     ret = kvm_put_msrs(env);
 584     if (ret < 0)
 585         return ret;
 586
 587     return 0;
 588 }
 589
 590 int kvm_arch_get_registers(CPUState *env)
 591 {
 592     int ret;
 593
 594     ret = kvm_getput_regs(env, 0);
 595     if (ret < 0)
 596         return ret;
 597
 598     ret = kvm_get_fpu(env);
 599     if (ret < 0)
 600         return ret;
 601
 602     ret = kvm_get_sregs(env);
 603     if (ret < 0)
 604         return ret;
 605
 606     ret = kvm_get_msrs(env);
 607     if (ret < 0)
 608         return ret;
 609
 610     return 0;
 611 }
 612
 613 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 614 {
 615     /* Try to inject an interrupt if the guest can accept it */
 616     if (run->ready_for_interrupt_injection &&
 617         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 618         (env->eflags & IF_MASK)) {
 619         int irq;
 620
 621         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 622         irq = cpu_get_pic_interrupt(env);
 623         if (irq >= 0) {
 624             struct kvm_interrupt intr;
 625             intr.irq = irq;
 626             /* FIXME: errors */
 627             dprintf("injected interrupt %d\n", irq);
 628             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 629         }
 630     }
 631
 632     /* If we have an interrupt but the guest is not ready to receive an
 633      * interrupt, request an interrupt window exit.  This will
 634      * cause a return to userspace as soon as the guest is ready to
 635      * receive interrupts. */
 636     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 637         run->request_interrupt_window = 1;
 638     else
 639         run->request_interrupt_window = 0;
 640
 641     dprintf("setting tpr\n");
 642     run->cr8 = cpu_get_apic_tpr(env);
 643
 644     return 0;
 645 }
 646
 647 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 648 {
 649     if (run->if_flag)
 650         env->eflags |= IF_MASK;
 651     else
 652         env->eflags &= ~IF_MASK;
 653
 654     cpu_set_apic_tpr(env, run->cr8);
 655     cpu_set_apic_base(env, run->apic_base);
 656
 657     return 0;
 658 }
 659
 660 static int kvm_handle_halt(CPUState *env)
 661 {
 662     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 663           (env->eflags & IF_MASK)) &&
 664         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 665         env->halted = 1;
 666         env->exception_index = EXCP_HLT;
 667         return 0;
 668     }
 669
 670     return 1;
 671 }
 672
 673 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 674 {
 675     int ret = 0;
 676
 677     switch (run->exit_reason) {
 678     case KVM_EXIT_HLT:
 679         dprintf("handle_hlt\n");
 680         ret = kvm_handle_halt(env);
 681         break;
 682     }
 683
 684     return ret;
 685 }