hw/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sparc32_dma.h"
  26 #include "sun4m.h"
  27
  28 /* debug DMA */
  29 //#define DEBUG_DMA
  30
  31 /*
  32  * This is the DMA controller part of chip STP2000 (Master I/O), also
  33  * produced as NCR89C100. See
  34  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  35  * and
  36  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  37  */
  38
  39 #ifdef DEBUG_DMA
  40 #define DPRINTF(fmt, args...) \
  41 do { printf("DMA: " fmt , ##args); } while (0)
  42 #else
  43 #define DPRINTF(fmt, args...)
  44 #endif
  45
  46 #define DMA_REGS 4
  47 #define DMA_SIZE (4 * sizeof(uint32_t))
  48 #define DMA_MAXADDR (DMA_SIZE - 1)
  49
  50 #define DMA_VER 0xa0000000
  51 #define DMA_INTR 1
  52 #define DMA_INTREN 0x10
  53 #define DMA_WRITE_MEM 0x100
  54 #define DMA_LOADED 0x04000000
  55 #define DMA_DRAIN_FIFO 0x40
  56 #define DMA_RESET 0x80
  57
  58 typedef struct DMAState DMAState;
  59
  60 struct DMAState {
  61     uint32_t dmaregs[DMA_REGS];
  62     qemu_irq irq;
  63     void *iommu;
  64     qemu_irq dev_reset;
  65 };
  66
  67 /* Note: on sparc, the lance 16 bit bus is swapped */
  68 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
  69                        uint8_t *buf, int len, int do_bswap)
  70 {
  71     DMAState *s = opaque;
  72     int i;
  73
  74     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
  75             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  76     addr |= s->dmaregs[3];
  77     if (do_bswap) {
  78         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  79     } else {
  80         addr &= ~1;
  81         len &= ~1;
  82         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  83         for(i = 0; i < len; i += 2) {
  84             bswap16s((uint16_t *)(buf + i));
  85         }
  86     }
  87 }
  88
  89 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
  90                         uint8_t *buf, int len, int do_bswap)
  91 {
  92     DMAState *s = opaque;
  93     int l, i;
  94     uint16_t tmp_buf[32];
  95
  96     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
  97             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  98     addr |= s->dmaregs[3];
  99     if (do_bswap) {
 100         sparc_iommu_memory_write(s->iommu, addr, buf, len);
 101     } else {
 102         addr &= ~1;
 103         len &= ~1;
 104         while (len > 0) {
 105             l = len;
 106             if (l > sizeof(tmp_buf))
 107                 l = sizeof(tmp_buf);
 108             for(i = 0; i < l; i += 2) {
 109                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 110             }
 111             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 112             len -= l;
 113             buf += l;
 114             addr += l;
 115         }
 116     }
 117 }
 118
 119 static void dma_set_irq(void *opaque, int irq, int level)
 120 {
 121     DMAState *s = opaque;
 122     if (level) {
 123         DPRINTF("Raise IRQ\n");
 124         s->dmaregs[0] |= DMA_INTR;
 125         qemu_irq_raise(s->irq);
 126     } else {
 127         s->dmaregs[0] &= ~DMA_INTR;
 128         DPRINTF("Lower IRQ\n");
 129         qemu_irq_lower(s->irq);
 130     }
 131 }
 132
 133 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 134 {
 135     DMAState *s = opaque;
 136
 137     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
 138             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 139     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 140     s->dmaregs[0] |= DMA_INTR;
 141     s->dmaregs[1] += len;
 142 }
 143
 144 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 145 {
 146     DMAState *s = opaque;
 147
 148     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
 149             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 150     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 151     s->dmaregs[0] |= DMA_INTR;
 152     s->dmaregs[1] += len;
 153 }
 154
 155 static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
 156 {
 157     DMAState *s = opaque;
 158     uint32_t saddr;
 159
 160     saddr = (addr & DMA_MAXADDR) >> 2;
 161     DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
 162             s->dmaregs[saddr]);
 163
 164     return s->dmaregs[saddr];
 165 }
 166
 167 static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 168 {
 169     DMAState *s = opaque;
 170     uint32_t saddr;
 171
 172     saddr = (addr & DMA_MAXADDR) >> 2;
 173     DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
 174             s->dmaregs[saddr], val);
 175     switch (saddr) {
 176     case 0:
 177         if (!(val & DMA_INTREN)) {
 178             DPRINTF("Lower IRQ\n");
 179             qemu_irq_lower(s->irq);
 180         }
 181         if (val & DMA_RESET) {
 182             qemu_irq_raise(s->dev_reset);
 183             qemu_irq_lower(s->dev_reset);
 184         } else if (val & DMA_DRAIN_FIFO) {
 185             val &= ~DMA_DRAIN_FIFO;
 186         } else if (val == 0)
 187             val = DMA_DRAIN_FIFO;
 188         val &= 0x0fffffff;
 189         val |= DMA_VER;
 190         break;
 191     case 1:
 192         s->dmaregs[0] |= DMA_LOADED;
 193         break;
 194     default:
 195         break;
 196     }
 197     s->dmaregs[saddr] = val;
 198 }
 199
 200 static CPUReadMemoryFunc *dma_mem_read[3] = {
 201     NULL,
 202     NULL,
 203     dma_mem_readl,
 204 };
 205
 206 static CPUWriteMemoryFunc *dma_mem_write[3] = {
 207     NULL,
 208     NULL,
 209     dma_mem_writel,
 210 };
 211
 212 static void dma_reset(void *opaque)
 213 {
 214     DMAState *s = opaque;
 215
 216     memset(s->dmaregs, 0, DMA_SIZE);
 217     s->dmaregs[0] = DMA_VER;
 218 }
 219
 220 static void dma_save(QEMUFile *f, void *opaque)
 221 {
 222     DMAState *s = opaque;
 223     unsigned int i;
 224
 225     for (i = 0; i < DMA_REGS; i++)
 226         qemu_put_be32s(f, &s->dmaregs[i]);
 227 }
 228
 229 static int dma_load(QEMUFile *f, void *opaque, int version_id)
 230 {
 231     DMAState *s = opaque;
 232     unsigned int i;
 233
 234     if (version_id != 2)
 235         return -EINVAL;
 236     for (i = 0; i < DMA_REGS; i++)
 237         qemu_get_be32s(f, &s->dmaregs[i]);
 238
 239     return 0;
 240 }
 241
 242 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
 243                        void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
 244 {
 245     DMAState *s;
 246     int dma_io_memory;
 247
 248     s = qemu_mallocz(sizeof(DMAState));
 249     if (!s)
 250         return NULL;
 251
 252     s->irq = parent_irq;
 253     s->iommu = iommu;
 254
 255     dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
 256     cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
 257
 258     register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
 259     qemu_register_reset(dma_reset, s);
 260     *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
 261
 262     *reset = &s->dev_reset;
 263
 264     return s;
 265 }