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Avoid (some) ppc cross-compilation problems
[qemu/mini2440.git] / hw / fdc.c
blobcd00420bd522586feddfb3c5184a0ff3993ede55
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29 #include "hw.h"
30 #include "fdc.h"
31 #include "block.h"
32 #include "qemu-timer.h"
33 #include "isa.h"
34
35 /********************************************************/
36 /* debug Floppy devices */
37 //#define DEBUG_FLOPPY
38
39 #ifdef DEBUG_FLOPPY
40 #define FLOPPY_DPRINTF(fmt, args...) \
41 do { printf("FLOPPY: " fmt , ##args); } while (0)
42 #else
43 #define FLOPPY_DPRINTF(fmt, args...)
44 #endif
45
46 #define FLOPPY_ERROR(fmt, args...) \
47 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0)
48
49 /********************************************************/
50 /* Floppy drive emulation */
51
52 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
53 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
54
55 /* Will always be a fixed parameter for us */
56 #define FD_SECTOR_LEN 512
57 #define FD_SECTOR_SC 2 /* Sector size code */
58
59 /* Floppy disk drive emulation */
60 typedef enum fdisk_type_t {
61 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
62 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
63 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
64 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
65 FDRIVE_DISK_NONE = 0x05, /* No disk */
66 } fdisk_type_t;
67
68 typedef enum fdrive_type_t {
69 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
70 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
71 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
72 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
73 } fdrive_type_t;
74
75 typedef enum fdisk_flags_t {
76 FDISK_DBL_SIDES = 0x01,
77 } fdisk_flags_t;
78
79 typedef struct fdrive_t {
80 BlockDriverState *bs;
81 /* Drive status */
82 fdrive_type_t drive;
83 uint8_t perpendicular; /* 2.88 MB access mode */
84 /* Position */
85 uint8_t head;
86 uint8_t track;
87 uint8_t sect;
88 /* Media */
89 fdisk_flags_t flags;
90 uint8_t last_sect; /* Nb sector per track */
91 uint8_t max_track; /* Nb of tracks */
92 uint16_t bps; /* Bytes per sector */
93 uint8_t ro; /* Is read-only */
94 } fdrive_t;
95
96 static void fd_init (fdrive_t *drv, BlockDriverState *bs)
97 {
98 /* Drive */
99 drv->bs = bs;
100 drv->drive = FDRIVE_DRV_NONE;
101 drv->perpendicular = 0;
102 /* Disk */
103 drv->last_sect = 0;
104 drv->max_track = 0;
105 }
106
107 static int _fd_sector (uint8_t head, uint8_t track,
108 uint8_t sect, uint8_t last_sect)
109 {
110 return (((track * 2) + head) * last_sect) + sect - 1;
111 }
112
113 /* Returns current position, in sectors, for given drive */
114 static int fd_sector (fdrive_t *drv)
115 {
116 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
117 }
118
119 /* Seek to a new position:
120 * returns 0 if already on right track
121 * returns 1 if track changed
122 * returns 2 if track is invalid
123 * returns 3 if sector is invalid
124 * returns 4 if seek is disabled
125 */
126 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
127 int enable_seek)
128 {
129 uint32_t sector;
130 int ret;
131
132 if (track > drv->max_track ||
133 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
134 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
135 head, track, sect, 1,
136 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
137 drv->max_track, drv->last_sect);
138 return 2;
139 }
140 if (sect > drv->last_sect) {
141 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
142 head, track, sect, 1,
143 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
144 drv->max_track, drv->last_sect);
145 return 3;
146 }
147 sector = _fd_sector(head, track, sect, drv->last_sect);
148 ret = 0;
149 if (sector != fd_sector(drv)) {
150 #if 0
151 if (!enable_seek) {
152 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
153 head, track, sect, 1, drv->max_track, drv->last_sect);
154 return 4;
155 }
156 #endif
157 drv->head = head;
158 if (drv->track != track)
159 ret = 1;
160 drv->track = track;
161 drv->sect = sect;
162 }
163
164 return ret;
165 }
166
167 /* Set drive back to track 0 */
168 static void fd_recalibrate (fdrive_t *drv)
169 {
170 FLOPPY_DPRINTF("recalibrate\n");
171 drv->head = 0;
172 drv->track = 0;
173 drv->sect = 1;
174 }
175
176 /* Recognize floppy formats */
177 typedef struct fd_format_t {
178 fdrive_type_t drive;
179 fdisk_type_t disk;
180 uint8_t last_sect;
181 uint8_t max_track;
182 uint8_t max_head;
183 const char *str;
184 } fd_format_t;
185
186 static const fd_format_t fd_formats[] = {
187 /* First entry is default format */
188 /* 1.44 MB 3"1/2 floppy disks */
189 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
190 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
191 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
192 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
193 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
197 /* 2.88 MB 3"1/2 floppy disks */
198 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
199 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
200 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
201 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
202 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
203 /* 720 kB 3"1/2 floppy disks */
204 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
205 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
206 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
207 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
208 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
210 /* 1.2 MB 5"1/4 floppy disks */
211 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
212 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
213 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
214 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
215 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
216 /* 720 kB 5"1/4 floppy disks */
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
219 /* 360 kB 5"1/4 floppy disks */
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
221 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
224 /* 320 kB 5"1/4 floppy disks */
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
227 /* 360 kB must match 5"1/4 better than 3"1/2... */
228 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
229 /* end */
230 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
231 };
232
233 /* Revalidate a disk drive after a disk change */
234 static void fd_revalidate (fdrive_t *drv)
235 {
236 const fd_format_t *parse;
237 uint64_t nb_sectors, size;
238 int i, first_match, match;
239 int nb_heads, max_track, last_sect, ro;
240
241 FLOPPY_DPRINTF("revalidate\n");
242 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
243 ro = bdrv_is_read_only(drv->bs);
244 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
245 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
246 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
247 nb_heads - 1, max_track, last_sect);
248 } else {
249 bdrv_get_geometry(drv->bs, &nb_sectors);
250 match = -1;
251 first_match = -1;
252 for (i = 0;; i++) {
253 parse = &fd_formats[i];
254 if (parse->drive == FDRIVE_DRV_NONE)
255 break;
256 if (drv->drive == parse->drive ||
257 drv->drive == FDRIVE_DRV_NONE) {
258 size = (parse->max_head + 1) * parse->max_track *
259 parse->last_sect;
260 if (nb_sectors == size) {
261 match = i;
262 break;
263 }
264 if (first_match == -1)
265 first_match = i;
266 }
267 }
268 if (match == -1) {
269 if (first_match == -1)
270 match = 1;
271 else
272 match = first_match;
273 parse = &fd_formats[match];
274 }
275 nb_heads = parse->max_head + 1;
276 max_track = parse->max_track;
277 last_sect = parse->last_sect;
278 drv->drive = parse->drive;
279 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
280 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
281 }
282 if (nb_heads == 1) {
283 drv->flags &= ~FDISK_DBL_SIDES;
284 } else {
285 drv->flags |= FDISK_DBL_SIDES;
286 }
287 drv->max_track = max_track;
288 drv->last_sect = last_sect;
289 drv->ro = ro;
290 } else {
291 FLOPPY_DPRINTF("No disk in drive\n");
292 drv->last_sect = 0;
293 drv->max_track = 0;
294 drv->flags &= ~FDISK_DBL_SIDES;
295 }
296 }
297
298 /********************************************************/
299 /* Intel 82078 floppy disk controller emulation */
300
301 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
302 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
303 static int fdctrl_transfer_handler (void *opaque, int nchan,
304 int dma_pos, int dma_len);
305 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
306
307 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
308 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
309 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
310 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
311 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
312 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
313 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
314 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
315 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
316 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
317 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
318
319 enum {
320 FD_DIR_WRITE = 0,
321 FD_DIR_READ = 1,
322 FD_DIR_SCANE = 2,
323 FD_DIR_SCANL = 3,
324 FD_DIR_SCANH = 4,
325 };
326
327 enum {
328 FD_STATE_MULTI = 0x01, /* multi track flag */
329 FD_STATE_FORMAT = 0x02, /* format flag */
330 FD_STATE_SEEK = 0x04, /* seek flag */
331 };
332
333 enum {
334 FD_REG_SRA = 0x00,
335 FD_REG_SRB = 0x01,
336 FD_REG_DOR = 0x02,
337 FD_REG_TDR = 0x03,
338 FD_REG_MSR = 0x04,
339 FD_REG_DSR = 0x04,
340 FD_REG_FIFO = 0x05,
341 FD_REG_DIR = 0x07,
342 };
343
344 enum {
345 FD_CMD_READ_TRACK = 0x02,
346 FD_CMD_SPECIFY = 0x03,
347 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
348 FD_CMD_WRITE = 0x05,
349 FD_CMD_READ = 0x06,
350 FD_CMD_RECALIBRATE = 0x07,
351 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
352 FD_CMD_WRITE_DELETED = 0x09,
353 FD_CMD_READ_ID = 0x0a,
354 FD_CMD_READ_DELETED = 0x0c,
355 FD_CMD_FORMAT_TRACK = 0x0d,
356 FD_CMD_DUMPREG = 0x0e,
357 FD_CMD_SEEK = 0x0f,
358 FD_CMD_VERSION = 0x10,
359 FD_CMD_SCAN_EQUAL = 0x11,
360 FD_CMD_PERPENDICULAR_MODE = 0x12,
361 FD_CMD_CONFIGURE = 0x13,
362 FD_CMD_LOCK = 0x14,
363 FD_CMD_VERIFY = 0x16,
364 FD_CMD_POWERDOWN_MODE = 0x17,
365 FD_CMD_PART_ID = 0x18,
366 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
367 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
368 FD_CMD_SAVE = 0x2c,
369 FD_CMD_OPTION = 0x33,
370 FD_CMD_RESTORE = 0x4c,
371 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
372 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
373 FD_CMD_FORMAT_AND_WRITE = 0xcd,
374 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
375 };
376
377 enum {
378 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
379 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
380 FD_CONFIG_POLL = 0x10, /* Poll enabled */
381 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
382 FD_CONFIG_EIS = 0x40, /* No implied seeks */
383 };
384
385 enum {
386 FD_SR0_EQPMT = 0x10,
387 FD_SR0_SEEK = 0x20,
388 FD_SR0_ABNTERM = 0x40,
389 FD_SR0_INVCMD = 0x80,
390 FD_SR0_RDYCHG = 0xc0,
391 };
392
393 enum {
394 FD_SR1_EC = 0x80, /* End of cylinder */
395 };
396
397 enum {
398 FD_SR2_SNS = 0x04, /* Scan not satisfied */
399 FD_SR2_SEH = 0x08, /* Scan equal hit */
400 };
401
402 enum {
403 FD_SRA_DIR = 0x01,
404 FD_SRA_nWP = 0x02,
405 FD_SRA_nINDX = 0x04,
406 FD_SRA_HDSEL = 0x08,
407 FD_SRA_nTRK0 = 0x10,
408 FD_SRA_STEP = 0x20,
409 FD_SRA_nDRV2 = 0x40,
410 FD_SRA_INTPEND = 0x80,
411 };
412
413 enum {
414 FD_SRB_MTR0 = 0x01,
415 FD_SRB_MTR1 = 0x02,
416 FD_SRB_WGATE = 0x04,
417 FD_SRB_RDATA = 0x08,
418 FD_SRB_WDATA = 0x10,
419 FD_SRB_DR0 = 0x20,
420 };
421
422 enum {
423 #if MAX_FD == 4
424 FD_DOR_SELMASK = 0x03,
425 #else
426 FD_DOR_SELMASK = 0x01,
427 #endif
428 FD_DOR_nRESET = 0x04,
429 FD_DOR_DMAEN = 0x08,
430 FD_DOR_MOTEN0 = 0x10,
431 FD_DOR_MOTEN1 = 0x20,
432 FD_DOR_MOTEN2 = 0x40,
433 FD_DOR_MOTEN3 = 0x80,
434 };
435
436 enum {
437 #if MAX_FD == 4
438 FD_TDR_BOOTSEL = 0x0c,
439 #else
440 FD_TDR_BOOTSEL = 0x04,
441 #endif
442 };
443
444 enum {
445 FD_DSR_DRATEMASK= 0x03,
446 FD_DSR_PWRDOWN = 0x40,
447 FD_DSR_SWRESET = 0x80,
448 };
449
450 enum {
451 FD_MSR_DRV0BUSY = 0x01,
452 FD_MSR_DRV1BUSY = 0x02,
453 FD_MSR_DRV2BUSY = 0x04,
454 FD_MSR_DRV3BUSY = 0x08,
455 FD_MSR_CMDBUSY = 0x10,
456 FD_MSR_NONDMA = 0x20,
457 FD_MSR_DIO = 0x40,
458 FD_MSR_RQM = 0x80,
459 };
460
461 enum {
462 FD_DIR_DSKCHG = 0x80,
463 };
464
465 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
466 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
467 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
468
469 struct fdctrl_t {
470 /* Controller's identification */
471 uint8_t version;
472 /* HW */
473 qemu_irq irq;
474 int dma_chann;
475 target_phys_addr_t io_base;
476 /* Controller state */
477 QEMUTimer *result_timer;
478 uint8_t sra;
479 uint8_t srb;
480 uint8_t dor;
481 uint8_t tdr;
482 uint8_t dsr;
483 uint8_t msr;
484 uint8_t cur_drv;
485 uint8_t status0;
486 uint8_t status1;
487 uint8_t status2;
488 /* Command FIFO */
489 uint8_t *fifo;
490 uint32_t data_pos;
491 uint32_t data_len;
492 uint8_t data_state;
493 uint8_t data_dir;
494 uint8_t eot; /* last wanted sector */
495 /* States kept only to be returned back */
496 /* Timers state */
497 uint8_t timer0;
498 uint8_t timer1;
499 /* precompensation */
500 uint8_t precomp_trk;
501 uint8_t config;
502 uint8_t lock;
503 /* Power down config (also with status regB access mode */
504 uint8_t pwrd;
505 /* Sun4m quirks? */
506 int sun4m;
507 /* Floppy drives */
508 fdrive_t drives[MAX_FD];
509 };
510
511 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
512 {
513 fdctrl_t *fdctrl = opaque;
514 uint32_t retval;
515
516 switch (reg & 0x07) {
517 case FD_REG_SRA:
518 retval = fdctrl_read_statusA(fdctrl);
519 break;
520 case FD_REG_SRB:
521 retval = fdctrl_read_statusB(fdctrl);
522 break;
523 case FD_REG_DOR:
524 retval = fdctrl_read_dor(fdctrl);
525 break;
526 case FD_REG_TDR:
527 retval = fdctrl_read_tape(fdctrl);
528 break;
529 case FD_REG_MSR:
530 retval = fdctrl_read_main_status(fdctrl);
531 break;
532 case FD_REG_FIFO:
533 retval = fdctrl_read_data(fdctrl);
534 break;
535 case FD_REG_DIR:
536 retval = fdctrl_read_dir(fdctrl);
537 break;
538 default:
539 retval = (uint32_t)(-1);
540 break;
541 }
542 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
543
544 return retval;
545 }
546
547 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
548 {
549 fdctrl_t *fdctrl = opaque;
550
551 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
552
553 switch (reg & 0x07) {
554 case FD_REG_DOR:
555 fdctrl_write_dor(fdctrl, value);
556 break;
557 case FD_REG_TDR:
558 fdctrl_write_tape(fdctrl, value);
559 break;
560 case FD_REG_DSR:
561 fdctrl_write_rate(fdctrl, value);
562 break;
563 case FD_REG_FIFO:
564 fdctrl_write_data(fdctrl, value);
565 break;
566 default:
567 break;
568 }
569 }
570
571 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
572 {
573 return fdctrl_read(opaque, (uint32_t)reg);
574 }
575
576 static void fdctrl_write_mem (void *opaque,
577 target_phys_addr_t reg, uint32_t value)
578 {
579 fdctrl_write(opaque, (uint32_t)reg, value);
580 }
581
582 static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
583 fdctrl_read_mem,
584 fdctrl_read_mem,
585 fdctrl_read_mem,
586 };
587
588 static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
589 fdctrl_write_mem,
590 fdctrl_write_mem,
591 fdctrl_write_mem,
592 };
593
594 static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
595 fdctrl_read_mem,
596 NULL,
597 NULL,
598 };
599
600 static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
601 fdctrl_write_mem,
602 NULL,
603 NULL,
604 };
605
606 static void fd_save (QEMUFile *f, fdrive_t *fd)
607 {
608 qemu_put_8s(f, &fd->head);
609 qemu_put_8s(f, &fd->track);
610 qemu_put_8s(f, &fd->sect);
611 }
612
613 static void fdc_save (QEMUFile *f, void *opaque)
614 {
615 fdctrl_t *s = opaque;
616 uint8_t tmp;
617 int i;
618 uint8_t dor = s->dor | GET_CUR_DRV(s);
619
620 /* Controller state */
621 qemu_put_8s(f, &s->sra);
622 qemu_put_8s(f, &s->srb);
623 qemu_put_8s(f, &dor);
624 qemu_put_8s(f, &s->tdr);
625 qemu_put_8s(f, &s->dsr);
626 qemu_put_8s(f, &s->msr);
627 qemu_put_8s(f, &s->status0);
628 qemu_put_8s(f, &s->status1);
629 qemu_put_8s(f, &s->status2);
630 /* Command FIFO */
631 qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
632 qemu_put_be32s(f, &s->data_pos);
633 qemu_put_be32s(f, &s->data_len);
634 qemu_put_8s(f, &s->data_state);
635 qemu_put_8s(f, &s->data_dir);
636 qemu_put_8s(f, &s->eot);
637 /* States kept only to be returned back */
638 qemu_put_8s(f, &s->timer0);
639 qemu_put_8s(f, &s->timer1);
640 qemu_put_8s(f, &s->precomp_trk);
641 qemu_put_8s(f, &s->config);
642 qemu_put_8s(f, &s->lock);
643 qemu_put_8s(f, &s->pwrd);
644
645 tmp = MAX_FD;
646 qemu_put_8s(f, &tmp);
647 for (i = 0; i < MAX_FD; i++)
648 fd_save(f, &s->drives[i]);
649 }
650
651 static int fd_load (QEMUFile *f, fdrive_t *fd)
652 {
653 qemu_get_8s(f, &fd->head);
654 qemu_get_8s(f, &fd->track);
655 qemu_get_8s(f, &fd->sect);
656
657 return 0;
658 }
659
660 static int fdc_load (QEMUFile *f, void *opaque, int version_id)
661 {
662 fdctrl_t *s = opaque;
663 int i, ret = 0;
664 uint8_t n;
665
666 if (version_id != 2)
667 return -EINVAL;
668
669 /* Controller state */
670 qemu_get_8s(f, &s->sra);
671 qemu_get_8s(f, &s->srb);
672 qemu_get_8s(f, &s->dor);
673 SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK);
674 s->dor &= ~FD_DOR_SELMASK;
675 qemu_get_8s(f, &s->tdr);
676 qemu_get_8s(f, &s->dsr);
677 qemu_get_8s(f, &s->msr);
678 qemu_get_8s(f, &s->status0);
679 qemu_get_8s(f, &s->status1);
680 qemu_get_8s(f, &s->status2);
681 /* Command FIFO */
682 qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
683 qemu_get_be32s(f, &s->data_pos);
684 qemu_get_be32s(f, &s->data_len);
685 qemu_get_8s(f, &s->data_state);
686 qemu_get_8s(f, &s->data_dir);
687 qemu_get_8s(f, &s->eot);
688 /* States kept only to be returned back */
689 qemu_get_8s(f, &s->timer0);
690 qemu_get_8s(f, &s->timer1);
691 qemu_get_8s(f, &s->precomp_trk);
692 qemu_get_8s(f, &s->config);
693 qemu_get_8s(f, &s->lock);
694 qemu_get_8s(f, &s->pwrd);
695 qemu_get_8s(f, &n);
696
697 if (n > MAX_FD)
698 return -EINVAL;
699
700 for (i = 0; i < n; i++) {
701 ret = fd_load(f, &s->drives[i]);
702 if (ret != 0)
703 break;
704 }
705
706 return ret;
707 }
708
709 static void fdctrl_external_reset(void *opaque)
710 {
711 fdctrl_t *s = opaque;
712
713 fdctrl_reset(s, 0);
714 }
715
716 static void fdctrl_handle_tc(void *opaque, int irq, int level)
717 {
718 //fdctrl_t *s = opaque;
719
720 if (level) {
721 // XXX
722 FLOPPY_DPRINTF("TC pulsed\n");
723 }
724 }
725
726 /* XXX: may change if moved to bdrv */
727 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
728 {
729 return fdctrl->drives[drive_num].drive;
730 }
731
732 /* Change IRQ state */
733 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
734 {
735 if (!(fdctrl->sra & FD_SRA_INTPEND))
736 return;
737 FLOPPY_DPRINTF("Reset interrupt\n");
738 qemu_set_irq(fdctrl->irq, 0);
739 fdctrl->sra &= ~FD_SRA_INTPEND;
740 }
741
742 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
743 {
744 /* Sparc mutation */
745 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
746 /* XXX: not sure */
747 fdctrl->msr &= ~FD_MSR_CMDBUSY;
748 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
749 fdctrl->status0 = status0;
750 return;
751 }
752 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
753 qemu_set_irq(fdctrl->irq, 1);
754 fdctrl->sra |= FD_SRA_INTPEND;
755 }
756 fdctrl->status0 = status0;
757 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
758 }
759
760 /* Reset controller */
761 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
762 {
763 int i;
764
765 FLOPPY_DPRINTF("reset controller\n");
766 fdctrl_reset_irq(fdctrl);
767 /* Initialise controller */
768 fdctrl->sra = 0;
769 fdctrl->srb = 0xc0;
770 if (!fdctrl->drives[1].bs)
771 fdctrl->sra |= FD_SRA_nDRV2;
772 fdctrl->cur_drv = 0;
773 fdctrl->dor = FD_DOR_nRESET;
774 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
775 fdctrl->msr = FD_MSR_RQM;
776 /* FIFO state */
777 fdctrl->data_pos = 0;
778 fdctrl->data_len = 0;
779 fdctrl->data_state = 0;
780 fdctrl->data_dir = FD_DIR_WRITE;
781 for (i = 0; i < MAX_FD; i++)
782 fd_recalibrate(&fdctrl->drives[i]);
783 fdctrl_reset_fifo(fdctrl);
784 if (do_irq) {
785 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
786 }
787 }
788
789 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
790 {
791 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
792 }
793
794 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
795 {
796 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
797 return &fdctrl->drives[1];
798 else
799 return &fdctrl->drives[0];
800 }
801
802 #if MAX_FD == 4
803 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
804 {
805 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
806 return &fdctrl->drives[2];
807 else
808 return &fdctrl->drives[1];
809 }
810
811 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
812 {
813 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
814 return &fdctrl->drives[3];
815 else
816 return &fdctrl->drives[2];
817 }
818 #endif
819
820 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
821 {
822 switch (fdctrl->cur_drv) {
823 case 0: return drv0(fdctrl);
824 case 1: return drv1(fdctrl);
825 #if MAX_FD == 4
826 case 2: return drv2(fdctrl);
827 case 3: return drv3(fdctrl);
828 #endif
829 default: return NULL;
830 }
831 }
832
833 /* Status A register : 0x00 (read-only) */
834 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
835 {
836 uint32_t retval = fdctrl->sra;
837
838 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
839
840 return retval;
841 }
842
843 /* Status B register : 0x01 (read-only) */
844 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
845 {
846 uint32_t retval = fdctrl->srb;
847
848 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
849
850 return retval;
851 }
852
853 /* Digital output register : 0x02 */
854 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
855 {
856 uint32_t retval = fdctrl->dor;
857
858 /* Selected drive */
859 retval |= fdctrl->cur_drv;
860 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
861
862 return retval;
863 }
864
865 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
866 {
867 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
868
869 /* Motors */
870 if (value & FD_DOR_MOTEN0)
871 fdctrl->srb |= FD_SRB_MTR0;
872 else
873 fdctrl->srb &= ~FD_SRB_MTR0;
874 if (value & FD_DOR_MOTEN1)
875 fdctrl->srb |= FD_SRB_MTR1;
876 else
877 fdctrl->srb &= ~FD_SRB_MTR1;
878
879 /* Drive */
880 if (value & 1)
881 fdctrl->srb |= FD_SRB_DR0;
882 else
883 fdctrl->srb &= ~FD_SRB_DR0;
884
885 /* Reset */
886 if (!(value & FD_DOR_nRESET)) {
887 if (fdctrl->dor & FD_DOR_nRESET) {
888 FLOPPY_DPRINTF("controller enter RESET state\n");
889 }
890 } else {
891 if (!(fdctrl->dor & FD_DOR_nRESET)) {
892 FLOPPY_DPRINTF("controller out of RESET state\n");
893 fdctrl_reset(fdctrl, 1);
894 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
895 }
896 }
897 /* Selected drive */
898 fdctrl->cur_drv = value & FD_DOR_SELMASK;
899
900 fdctrl->dor = value;
901 }
902
903 /* Tape drive register : 0x03 */
904 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
905 {
906 uint32_t retval = fdctrl->tdr;
907
908 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
909
910 return retval;
911 }
912
913 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
914 {
915 /* Reset mode */
916 if (!(fdctrl->dor & FD_DOR_nRESET)) {
917 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
918 return;
919 }
920 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
921 /* Disk boot selection indicator */
922 fdctrl->tdr = value & FD_TDR_BOOTSEL;
923 /* Tape indicators: never allow */
924 }
925
926 /* Main status register : 0x04 (read) */
927 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
928 {
929 uint32_t retval = fdctrl->msr;
930
931 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
932 fdctrl->dor |= FD_DOR_nRESET;
933
934 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
935
936 return retval;
937 }
938
939 /* Data select rate register : 0x04 (write) */
940 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
941 {
942 /* Reset mode */
943 if (!(fdctrl->dor & FD_DOR_nRESET)) {
944 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
945 return;
946 }
947 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
948 /* Reset: autoclear */
949 if (value & FD_DSR_SWRESET) {
950 fdctrl->dor &= ~FD_DOR_nRESET;
951 fdctrl_reset(fdctrl, 1);
952 fdctrl->dor |= FD_DOR_nRESET;
953 }
954 if (value & FD_DSR_PWRDOWN) {
955 fdctrl_reset(fdctrl, 1);
956 }
957 fdctrl->dsr = value;
958 }
959
960 static int fdctrl_media_changed(fdrive_t *drv)
961 {
962 int ret;
963
964 if (!drv->bs)
965 return 0;
966 ret = bdrv_media_changed(drv->bs);
967 if (ret) {
968 fd_revalidate(drv);
969 }
970 return ret;
971 }
972
973 /* Digital input register : 0x07 (read-only) */
974 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
975 {
976 uint32_t retval = 0;
977
978 if (fdctrl_media_changed(drv0(fdctrl))
979 || fdctrl_media_changed(drv1(fdctrl))
980 #if MAX_FD == 4
981 || fdctrl_media_changed(drv2(fdctrl))
982 || fdctrl_media_changed(drv3(fdctrl))
983 #endif
984 )
985 retval |= FD_DIR_DSKCHG;
986 if (retval != 0)
987 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
988
989 return retval;
990 }
991
992 /* FIFO state control */
993 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
994 {
995 fdctrl->data_dir = FD_DIR_WRITE;
996 fdctrl->data_pos = 0;
997 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
998 }
999
1000 /* Set FIFO status for the host to read */
1001 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1002 {
1003 fdctrl->data_dir = FD_DIR_READ;
1004 fdctrl->data_len = fifo_len;
1005 fdctrl->data_pos = 0;
1006 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1007 if (do_irq)
1008 fdctrl_raise_irq(fdctrl, 0x00);
1009 }
1010
1011 /* Set an error: unimplemented/unknown command */
1012 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1013 {
1014 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1015 fdctrl->fifo[0] = FD_SR0_INVCMD;
1016 fdctrl_set_fifo(fdctrl, 1, 0);
1017 }
1018
1019 /* Seek to next sector */
1020 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1021 {
1022 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1023 cur_drv->head, cur_drv->track, cur_drv->sect,
1024 fd_sector(cur_drv));
1025 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1026 error in fact */
1027 if (cur_drv->sect >= cur_drv->last_sect ||
1028 cur_drv->sect == fdctrl->eot) {
1029 cur_drv->sect = 1;
1030 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1031 if (cur_drv->head == 0 &&
1032 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1033 cur_drv->head = 1;
1034 } else {
1035 cur_drv->head = 0;
1036 cur_drv->track++;
1037 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1038 return 0;
1039 }
1040 } else {
1041 cur_drv->track++;
1042 return 0;
1043 }
1044 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1045 cur_drv->head, cur_drv->track,
1046 cur_drv->sect, fd_sector(cur_drv));
1047 } else {
1048 cur_drv->sect++;
1049 }
1050 return 1;
1051 }
1052
1053 /* Callback for transfer end (stop or abort) */
1054 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1055 uint8_t status1, uint8_t status2)
1056 {
1057 fdrive_t *cur_drv;
1058
1059 cur_drv = get_cur_drv(fdctrl);
1060 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1061 status0, status1, status2,
1062 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1063 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1064 fdctrl->fifo[1] = status1;
1065 fdctrl->fifo[2] = status2;
1066 fdctrl->fifo[3] = cur_drv->track;
1067 fdctrl->fifo[4] = cur_drv->head;
1068 fdctrl->fifo[5] = cur_drv->sect;
1069 fdctrl->fifo[6] = FD_SECTOR_SC;
1070 fdctrl->data_dir = FD_DIR_READ;
1071 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1072 DMA_release_DREQ(fdctrl->dma_chann);
1073 }
1074 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1075 fdctrl->msr &= ~FD_MSR_NONDMA;
1076 fdctrl_set_fifo(fdctrl, 7, 1);
1077 }
1078
1079 /* Prepare a data transfer (either DMA or FIFO) */
1080 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1081 {
1082 fdrive_t *cur_drv;
1083 uint8_t kh, kt, ks;
1084 int did_seek = 0;
1085
1086 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1087 cur_drv = get_cur_drv(fdctrl);
1088 kt = fdctrl->fifo[2];
1089 kh = fdctrl->fifo[3];
1090 ks = fdctrl->fifo[4];
1091 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1092 GET_CUR_DRV(fdctrl), kh, kt, ks,
1093 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1094 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1095 case 2:
1096 /* sect too big */
1097 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1098 fdctrl->fifo[3] = kt;
1099 fdctrl->fifo[4] = kh;
1100 fdctrl->fifo[5] = ks;
1101 return;
1102 case 3:
1103 /* track too big */
1104 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1105 fdctrl->fifo[3] = kt;
1106 fdctrl->fifo[4] = kh;
1107 fdctrl->fifo[5] = ks;
1108 return;
1109 case 4:
1110 /* No seek enabled */
1111 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1112 fdctrl->fifo[3] = kt;
1113 fdctrl->fifo[4] = kh;
1114 fdctrl->fifo[5] = ks;
1115 return;
1116 case 1:
1117 did_seek = 1;
1118 break;
1119 default:
1120 break;
1121 }
1122
1123 /* Set the FIFO state */
1124 fdctrl->data_dir = direction;
1125 fdctrl->data_pos = 0;
1126 fdctrl->msr |= FD_MSR_CMDBUSY;
1127 if (fdctrl->fifo[0] & 0x80)
1128 fdctrl->data_state |= FD_STATE_MULTI;
1129 else
1130 fdctrl->data_state &= ~FD_STATE_MULTI;
1131 if (did_seek)
1132 fdctrl->data_state |= FD_STATE_SEEK;
1133 else
1134 fdctrl->data_state &= ~FD_STATE_SEEK;
1135 if (fdctrl->fifo[5] == 00) {
1136 fdctrl->data_len = fdctrl->fifo[8];
1137 } else {
1138 int tmp;
1139 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1140 tmp = (fdctrl->fifo[6] - ks + 1);
1141 if (fdctrl->fifo[0] & 0x80)
1142 tmp += fdctrl->fifo[6];
1143 fdctrl->data_len *= tmp;
1144 }
1145 fdctrl->eot = fdctrl->fifo[6];
1146 if (fdctrl->dor & FD_DOR_DMAEN) {
1147 int dma_mode;
1148 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1149 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1150 dma_mode = (dma_mode >> 2) & 3;
1151 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1152 dma_mode, direction,
1153 (128 << fdctrl->fifo[5]) *
1154 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1155 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1156 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1157 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1158 (direction == FD_DIR_READ && dma_mode == 1)) {
1159 /* No access is allowed until DMA transfer has completed */
1160 fdctrl->msr &= ~FD_MSR_RQM;
1161 /* Now, we just have to wait for the DMA controller to
1162 * recall us...
1163 */
1164 DMA_hold_DREQ(fdctrl->dma_chann);
1165 DMA_schedule(fdctrl->dma_chann);
1166 return;
1167 } else {
1168 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1169 }
1170 }
1171 FLOPPY_DPRINTF("start non-DMA transfer\n");
1172 fdctrl->msr |= FD_MSR_NONDMA;
1173 if (direction != FD_DIR_WRITE)
1174 fdctrl->msr |= FD_MSR_DIO;
1175 /* IO based transfer: calculate len */
1176 fdctrl_raise_irq(fdctrl, 0x00);
1177
1178 return;
1179 }
1180
1181 /* Prepare a transfer of deleted data */
1182 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1183 {
1184 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1185
1186 /* We don't handle deleted data,
1187 * so we don't return *ANYTHING*
1188 */
1189 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1190 }
1191
1192 /* handlers for DMA transfers */
1193 static int fdctrl_transfer_handler (void *opaque, int nchan,
1194 int dma_pos, int dma_len)
1195 {
1196 fdctrl_t *fdctrl;
1197 fdrive_t *cur_drv;
1198 int len, start_pos, rel_pos;
1199 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1200
1201 fdctrl = opaque;
1202 if (fdctrl->msr & FD_MSR_RQM) {
1203 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1204 return 0;
1205 }
1206 cur_drv = get_cur_drv(fdctrl);
1207 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1208 fdctrl->data_dir == FD_DIR_SCANH)
1209 status2 = FD_SR2_SNS;
1210 if (dma_len > fdctrl->data_len)
1211 dma_len = fdctrl->data_len;
1212 if (cur_drv->bs == NULL) {
1213 if (fdctrl->data_dir == FD_DIR_WRITE)
1214 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1215 else
1216 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1217 len = 0;
1218 goto transfer_error;
1219 }
1220 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1221 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1222 len = dma_len - fdctrl->data_pos;
1223 if (len + rel_pos > FD_SECTOR_LEN)
1224 len = FD_SECTOR_LEN - rel_pos;
1225 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1226 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1227 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1228 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1229 fd_sector(cur_drv) * FD_SECTOR_LEN);
1230 if (fdctrl->data_dir != FD_DIR_WRITE ||
1231 len < FD_SECTOR_LEN || rel_pos != 0) {
1232 /* READ & SCAN commands and realign to a sector for WRITE */
1233 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1234 fdctrl->fifo, 1) < 0) {
1235 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1236 fd_sector(cur_drv));
1237 /* Sure, image size is too small... */
1238 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1239 }
1240 }
1241 switch (fdctrl->data_dir) {
1242 case FD_DIR_READ:
1243 /* READ commands */
1244 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1245 fdctrl->data_pos, len);
1246 break;
1247 case FD_DIR_WRITE:
1248 /* WRITE commands */
1249 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1250 fdctrl->data_pos, len);
1251 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1252 fdctrl->fifo, 1) < 0) {
1253 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1254 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1255 goto transfer_error;
1256 }
1257 break;
1258 default:
1259 /* SCAN commands */
1260 {
1261 uint8_t tmpbuf[FD_SECTOR_LEN];
1262 int ret;
1263 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1264 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1265 if (ret == 0) {
1266 status2 = FD_SR2_SEH;
1267 goto end_transfer;
1268 }
1269 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1270 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1271 status2 = 0x00;
1272 goto end_transfer;
1273 }
1274 }
1275 break;
1276 }
1277 fdctrl->data_pos += len;
1278 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1279 if (rel_pos == 0) {
1280 /* Seek to next sector */
1281 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1282 break;
1283 }
1284 }
1285 end_transfer:
1286 len = fdctrl->data_pos - start_pos;
1287 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1288 fdctrl->data_pos, len, fdctrl->data_len);
1289 if (fdctrl->data_dir == FD_DIR_SCANE ||
1290 fdctrl->data_dir == FD_DIR_SCANL ||
1291 fdctrl->data_dir == FD_DIR_SCANH)
1292 status2 = FD_SR2_SEH;
1293 if (FD_DID_SEEK(fdctrl->data_state))
1294 status0 |= FD_SR0_SEEK;
1295 fdctrl->data_len -= len;
1296 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1297 transfer_error:
1298
1299 return len;
1300 }
1301
1302 /* Data register : 0x05 */
1303 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1304 {
1305 fdrive_t *cur_drv;
1306 uint32_t retval = 0;
1307 int pos;
1308
1309 cur_drv = get_cur_drv(fdctrl);
1310 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1311 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1312 FLOPPY_ERROR("controller not ready for reading\n");
1313 return 0;
1314 }
1315 pos = fdctrl->data_pos;
1316 if (fdctrl->msr & FD_MSR_NONDMA) {
1317 pos %= FD_SECTOR_LEN;
1318 if (pos == 0) {
1319 if (fdctrl->data_pos != 0)
1320 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1321 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1322 fd_sector(cur_drv));
1323 return 0;
1324 }
1325 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1326 FLOPPY_DPRINTF("error getting sector %d\n",
1327 fd_sector(cur_drv));
1328 /* Sure, image size is too small... */
1329 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1330 }
1331 }
1332 }
1333 retval = fdctrl->fifo[pos];
1334 if (++fdctrl->data_pos == fdctrl->data_len) {
1335 fdctrl->data_pos = 0;
1336 /* Switch from transfer mode to status mode
1337 * then from status mode to command mode
1338 */
1339 if (fdctrl->msr & FD_MSR_NONDMA) {
1340 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1341 } else {
1342 fdctrl_reset_fifo(fdctrl);
1343 fdctrl_reset_irq(fdctrl);
1344 }
1345 }
1346 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1347
1348 return retval;
1349 }
1350
1351 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1352 {
1353 fdrive_t *cur_drv;
1354 uint8_t kh, kt, ks;
1355
1356 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1357 cur_drv = get_cur_drv(fdctrl);
1358 kt = fdctrl->fifo[6];
1359 kh = fdctrl->fifo[7];
1360 ks = fdctrl->fifo[8];
1361 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1362 GET_CUR_DRV(fdctrl), kh, kt, ks,
1363 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1364 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1365 case 2:
1366 /* sect too big */
1367 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1368 fdctrl->fifo[3] = kt;
1369 fdctrl->fifo[4] = kh;
1370 fdctrl->fifo[5] = ks;
1371 return;
1372 case 3:
1373 /* track too big */
1374 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1375 fdctrl->fifo[3] = kt;
1376 fdctrl->fifo[4] = kh;
1377 fdctrl->fifo[5] = ks;
1378 return;
1379 case 4:
1380 /* No seek enabled */
1381 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1382 fdctrl->fifo[3] = kt;
1383 fdctrl->fifo[4] = kh;
1384 fdctrl->fifo[5] = ks;
1385 return;
1386 case 1:
1387 fdctrl->data_state |= FD_STATE_SEEK;
1388 break;
1389 default:
1390 break;
1391 }
1392 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1393 if (cur_drv->bs == NULL ||
1394 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1395 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1396 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1397 } else {
1398 if (cur_drv->sect == cur_drv->last_sect) {
1399 fdctrl->data_state &= ~FD_STATE_FORMAT;
1400 /* Last sector done */
1401 if (FD_DID_SEEK(fdctrl->data_state))
1402 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1403 else
1404 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1405 } else {
1406 /* More to do */
1407 fdctrl->data_pos = 0;
1408 fdctrl->data_len = 4;
1409 }
1410 }
1411 }
1412
1413 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1414 {
1415 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1416 fdctrl->fifo[0] = fdctrl->lock << 4;
1417 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1418 }
1419
1420 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1421 {
1422 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1423
1424 /* Drives position */
1425 fdctrl->fifo[0] = drv0(fdctrl)->track;
1426 fdctrl->fifo[1] = drv1(fdctrl)->track;
1427 #if MAX_FD == 4
1428 fdctrl->fifo[2] = drv2(fdctrl)->track;
1429 fdctrl->fifo[3] = drv3(fdctrl)->track;
1430 #else
1431 fdctrl->fifo[2] = 0;
1432 fdctrl->fifo[3] = 0;
1433 #endif
1434 /* timers */
1435 fdctrl->fifo[4] = fdctrl->timer0;
1436 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1437 fdctrl->fifo[6] = cur_drv->last_sect;
1438 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1439 (cur_drv->perpendicular << 2);
1440 fdctrl->fifo[8] = fdctrl->config;
1441 fdctrl->fifo[9] = fdctrl->precomp_trk;
1442 fdctrl_set_fifo(fdctrl, 10, 0);
1443 }
1444
1445 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1446 {
1447 /* Controller's version */
1448 fdctrl->fifo[0] = fdctrl->version;
1449 fdctrl_set_fifo(fdctrl, 1, 1);
1450 }
1451
1452 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1453 {
1454 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1455 fdctrl_set_fifo(fdctrl, 1, 0);
1456 }
1457
1458 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1459 {
1460 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1461
1462 /* Drives position */
1463 drv0(fdctrl)->track = fdctrl->fifo[3];
1464 drv1(fdctrl)->track = fdctrl->fifo[4];
1465 #if MAX_FD == 4
1466 drv2(fdctrl)->track = fdctrl->fifo[5];
1467 drv3(fdctrl)->track = fdctrl->fifo[6];
1468 #endif
1469 /* timers */
1470 fdctrl->timer0 = fdctrl->fifo[7];
1471 fdctrl->timer1 = fdctrl->fifo[8];
1472 cur_drv->last_sect = fdctrl->fifo[9];
1473 fdctrl->lock = fdctrl->fifo[10] >> 7;
1474 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1475 fdctrl->config = fdctrl->fifo[11];
1476 fdctrl->precomp_trk = fdctrl->fifo[12];
1477 fdctrl->pwrd = fdctrl->fifo[13];
1478 fdctrl_reset_fifo(fdctrl);
1479 }
1480
1481 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1482 {
1483 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1484
1485 fdctrl->fifo[0] = 0;
1486 fdctrl->fifo[1] = 0;
1487 /* Drives position */
1488 fdctrl->fifo[2] = drv0(fdctrl)->track;
1489 fdctrl->fifo[3] = drv1(fdctrl)->track;
1490 #if MAX_FD == 4
1491 fdctrl->fifo[4] = drv2(fdctrl)->track;
1492 fdctrl->fifo[5] = drv3(fdctrl)->track;
1493 #else
1494 fdctrl->fifo[4] = 0;
1495 fdctrl->fifo[5] = 0;
1496 #endif
1497 /* timers */
1498 fdctrl->fifo[6] = fdctrl->timer0;
1499 fdctrl->fifo[7] = fdctrl->timer1;
1500 fdctrl->fifo[8] = cur_drv->last_sect;
1501 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1502 (cur_drv->perpendicular << 2);
1503 fdctrl->fifo[10] = fdctrl->config;
1504 fdctrl->fifo[11] = fdctrl->precomp_trk;
1505 fdctrl->fifo[12] = fdctrl->pwrd;
1506 fdctrl->fifo[13] = 0;
1507 fdctrl->fifo[14] = 0;
1508 fdctrl_set_fifo(fdctrl, 15, 1);
1509 }
1510
1511 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1512 {
1513 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1514
1515 /* XXX: should set main status register to busy */
1516 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1517 qemu_mod_timer(fdctrl->result_timer,
1518 qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1519 }
1520
1521 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1522 {
1523 fdrive_t *cur_drv;
1524
1525 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1526 cur_drv = get_cur_drv(fdctrl);
1527 fdctrl->data_state |= FD_STATE_FORMAT;
1528 if (fdctrl->fifo[0] & 0x80)
1529 fdctrl->data_state |= FD_STATE_MULTI;
1530 else
1531 fdctrl->data_state &= ~FD_STATE_MULTI;
1532 fdctrl->data_state &= ~FD_STATE_SEEK;
1533 cur_drv->bps =
1534 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1535 #if 0
1536 cur_drv->last_sect =
1537 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1538 fdctrl->fifo[3] / 2;
1539 #else
1540 cur_drv->last_sect = fdctrl->fifo[3];
1541 #endif
1542 /* TODO: implement format using DMA expected by the Bochs BIOS
1543 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1544 * the sector with the specified fill byte
1545 */
1546 fdctrl->data_state &= ~FD_STATE_FORMAT;
1547 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1548 }
1549
1550 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1551 {
1552 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1553 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1554 if (fdctrl->fifo[2] & 1)
1555 fdctrl->dor &= ~FD_DOR_DMAEN;
1556 else
1557 fdctrl->dor |= FD_DOR_DMAEN;
1558 /* No result back */
1559 fdctrl_reset_fifo(fdctrl);
1560 }
1561
1562 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1563 {
1564 fdrive_t *cur_drv;
1565
1566 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1567 cur_drv = get_cur_drv(fdctrl);
1568 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1569 /* 1 Byte status back */
1570 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1571 (cur_drv->track == 0 ? 0x10 : 0x00) |
1572 (cur_drv->head << 2) |
1573 GET_CUR_DRV(fdctrl) |
1574 0x28;
1575 fdctrl_set_fifo(fdctrl, 1, 0);
1576 }
1577
1578 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1579 {
1580 fdrive_t *cur_drv;
1581
1582 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1583 cur_drv = get_cur_drv(fdctrl);
1584 fd_recalibrate(cur_drv);
1585 fdctrl_reset_fifo(fdctrl);
1586 /* Raise Interrupt */
1587 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1588 }
1589
1590 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1591 {
1592 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1593
1594 #if 0
1595 fdctrl->fifo[0] =
1596 fdctrl->status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1597 #else
1598 /* XXX: status0 handling is broken for read/write
1599 commands, so we do this hack. It should be suppressed
1600 ASAP */
1601 fdctrl->fifo[0] =
1602 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1603 #endif
1604 fdctrl->fifo[1] = cur_drv->track;
1605 fdctrl_set_fifo(fdctrl, 2, 0);
1606 fdctrl_reset_irq(fdctrl);
1607 fdctrl->status0 = FD_SR0_RDYCHG;
1608 }
1609
1610 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1611 {
1612 fdrive_t *cur_drv;
1613
1614 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1615 cur_drv = get_cur_drv(fdctrl);
1616 fdctrl_reset_fifo(fdctrl);
1617 if (fdctrl->fifo[2] > cur_drv->max_track) {
1618 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1619 } else {
1620 cur_drv->track = fdctrl->fifo[2];
1621 /* Raise Interrupt */
1622 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1623 }
1624 }
1625
1626 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1627 {
1628 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1629
1630 if (fdctrl->fifo[1] & 0x80)
1631 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1632 /* No result back */
1633 fdctrl_reset_fifo(fdctrl);
1634 }
1635
1636 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1637 {
1638 fdctrl->config = fdctrl->fifo[2];
1639 fdctrl->precomp_trk = fdctrl->fifo[3];
1640 /* No result back */
1641 fdctrl_reset_fifo(fdctrl);
1642 }
1643
1644 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1645 {
1646 fdctrl->pwrd = fdctrl->fifo[1];
1647 fdctrl->fifo[0] = fdctrl->fifo[1];
1648 fdctrl_set_fifo(fdctrl, 1, 1);
1649 }
1650
1651 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1652 {
1653 /* No result back */
1654 fdctrl_reset_fifo(fdctrl);
1655 }
1656
1657 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1658 {
1659 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1660
1661 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1662 /* Command parameters done */
1663 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1664 fdctrl->fifo[0] = fdctrl->fifo[1];
1665 fdctrl->fifo[2] = 0;
1666 fdctrl->fifo[3] = 0;
1667 fdctrl_set_fifo(fdctrl, 4, 1);
1668 } else {
1669 fdctrl_reset_fifo(fdctrl);
1670 }
1671 } else if (fdctrl->data_len > 7) {
1672 /* ERROR */
1673 fdctrl->fifo[0] = 0x80 |
1674 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1675 fdctrl_set_fifo(fdctrl, 1, 1);
1676 }
1677 }
1678
1679 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1680 {
1681 fdrive_t *cur_drv;
1682
1683 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1684 cur_drv = get_cur_drv(fdctrl);
1685 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1686 cur_drv->track = cur_drv->max_track - 1;
1687 } else {
1688 cur_drv->track += fdctrl->fifo[2];
1689 }
1690 fdctrl_reset_fifo(fdctrl);
1691 /* Raise Interrupt */
1692 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1693 }
1694
1695 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1696 {
1697 fdrive_t *cur_drv;
1698
1699 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1700 cur_drv = get_cur_drv(fdctrl);
1701 if (fdctrl->fifo[2] > cur_drv->track) {
1702 cur_drv->track = 0;
1703 } else {
1704 cur_drv->track -= fdctrl->fifo[2];
1705 }
1706 fdctrl_reset_fifo(fdctrl);
1707 /* Raise Interrupt */
1708 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1709 }
1710
1711 static const struct {
1712 uint8_t value;
1713 uint8_t mask;
1714 const char* name;
1715 int parameters;
1716 void (*handler)(fdctrl_t *fdctrl, int direction);
1717 int direction;
1718 } handlers[] = {
1719 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1720 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1721 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1722 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1723 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1724 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1725 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1726 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1727 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1728 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1729 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1730 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1731 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1732 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1733 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1734 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1735 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1736 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1737 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1738 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1739 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1740 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1741 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1742 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1743 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1744 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1745 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1746 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1747 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1748 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1749 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1750 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1751 };
1752 /* Associate command to an index in the 'handlers' array */
1753 static uint8_t command_to_handler[256];
1754
1755 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1756 {
1757 fdrive_t *cur_drv;
1758 int pos;
1759
1760 /* Reset mode */
1761 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1762 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1763 return;
1764 }
1765 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1766 FLOPPY_ERROR("controller not ready for writing\n");
1767 return;
1768 }
1769 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1770 /* Is it write command time ? */
1771 if (fdctrl->msr & FD_MSR_NONDMA) {
1772 /* FIFO data write */
1773 pos = fdctrl->data_pos++;
1774 pos %= FD_SECTOR_LEN;
1775 fdctrl->fifo[pos] = value;
1776 if (pos == FD_SECTOR_LEN - 1 ||
1777 fdctrl->data_pos == fdctrl->data_len) {
1778 cur_drv = get_cur_drv(fdctrl);
1779 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1780 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1781 return;
1782 }
1783 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1784 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1785 fd_sector(cur_drv));
1786 return;
1787 }
1788 }
1789 /* Switch from transfer mode to status mode
1790 * then from status mode to command mode
1791 */
1792 if (fdctrl->data_pos == fdctrl->data_len)
1793 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1794 return;
1795 }
1796 if (fdctrl->data_pos == 0) {
1797 /* Command */
1798 pos = command_to_handler[value & 0xff];
1799 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1800 fdctrl->data_len = handlers[pos].parameters + 1;
1801 }
1802
1803 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1804 fdctrl->fifo[fdctrl->data_pos++] = value;
1805 if (fdctrl->data_pos == fdctrl->data_len) {
1806 /* We now have all parameters
1807 * and will be able to treat the command
1808 */
1809 if (fdctrl->data_state & FD_STATE_FORMAT) {
1810 fdctrl_format_sector(fdctrl);
1811 return;
1812 }
1813
1814 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1815 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1816 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1817 }
1818 }
1819
1820 static void fdctrl_result_timer(void *opaque)
1821 {
1822 fdctrl_t *fdctrl = opaque;
1823 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1824
1825 /* Pretend we are spinning.
1826 * This is needed for Coherent, which uses READ ID to check for
1827 * sector interleaving.
1828 */
1829 if (cur_drv->last_sect != 0) {
1830 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1831 }
1832 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1833 }
1834
1835 /* Init functions */
1836 static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
1837 target_phys_addr_t io_base,
1838 BlockDriverState **fds)
1839 {
1840 fdctrl_t *fdctrl;
1841 int i, j;
1842
1843 /* Fill 'command_to_handler' lookup table */
1844 for (i = sizeof(handlers)/sizeof(handlers[0]) - 1; i >= 0; i--) {
1845 for (j = 0; j < sizeof(command_to_handler); j++) {
1846 if ((j & handlers[i].mask) == handlers[i].value)
1847 command_to_handler[j] = i;
1848 }
1849 }
1850
1851 FLOPPY_DPRINTF("init controller\n");
1852 fdctrl = qemu_mallocz(sizeof(fdctrl_t));
1853 if (!fdctrl)
1854 return NULL;
1855 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1856 if (fdctrl->fifo == NULL) {
1857 qemu_free(fdctrl);
1858 return NULL;
1859 }
1860 fdctrl->result_timer = qemu_new_timer(vm_clock,
1861 fdctrl_result_timer, fdctrl);
1862
1863 fdctrl->version = 0x90; /* Intel 82078 controller */
1864 fdctrl->irq = irq;
1865 fdctrl->dma_chann = dma_chann;
1866 fdctrl->io_base = io_base;
1867 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1868 if (fdctrl->dma_chann != -1) {
1869 DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1870 }
1871 for (i = 0; i < MAX_FD; i++) {
1872 fd_init(&fdctrl->drives[i], fds[i]);
1873 }
1874 fdctrl_external_reset(fdctrl);
1875 register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1876 qemu_register_reset(fdctrl_external_reset, fdctrl);
1877 for (i = 0; i < MAX_FD; i++) {
1878 fd_revalidate(&fdctrl->drives[i]);
1879 }
1880
1881 return fdctrl;
1882 }
1883
1884 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1885 target_phys_addr_t io_base,
1886 BlockDriverState **fds)
1887 {
1888 fdctrl_t *fdctrl;
1889 int io_mem;
1890
1891 fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
1892
1893 fdctrl->sun4m = 0;
1894 if (mem_mapped) {
1895 io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
1896 fdctrl);
1897 cpu_register_physical_memory(io_base, 0x08, io_mem);
1898 } else {
1899 register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
1900 fdctrl);
1901 register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
1902 fdctrl);
1903 register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
1904 fdctrl);
1905 register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
1906 fdctrl);
1907 }
1908
1909 return fdctrl;
1910 }
1911
1912 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1913 BlockDriverState **fds, qemu_irq *fdc_tc)
1914 {
1915 fdctrl_t *fdctrl;
1916 int io_mem;
1917
1918 fdctrl = fdctrl_init_common(irq, -1, io_base, fds);
1919 fdctrl->sun4m = 1;
1920 io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
1921 fdctrl_mem_write_strict,
1922 fdctrl);
1923 cpu_register_physical_memory(io_base, 0x08, io_mem);
1924 *fdc_tc = *qemu_allocate_irqs(fdctrl_handle_tc, fdctrl, 1);
1925
1926 return fdctrl;
1927 }
Samsung s3c2440 and arm920t support for the mini2440 dev board