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Use trap shell builtin to remove temporary files
[qemu/mini2440.git] / hw / e1000.c
blob71781e6e998d5defda8710bf6f587961e74276b6
1 /*
2 * QEMU e1000 emulation
3 *
4 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
5 * Copyright (c) 2008 Qumranet
6 * Based on work done by:
7 * Copyright (c) 2007 Dan Aloni
8 * Copyright (c) 2004 Antony T Curtis
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25
26 #include "hw.h"
27 #include "pci.h"
28 #include "net.h"
29
30 #include "e1000_hw.h"
31
32 #define DEBUG
33
34 #ifdef DEBUG
35 enum {
36 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
37 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
38 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
39 DEBUG_RXFILTER, DEBUG_NOTYET,
40 };
41 #define DBGBIT(x) (1<<DEBUG_##x)
42 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
43
44 #define DBGOUT(what, fmt, params...) do { \
45 if (debugflags & DBGBIT(what)) \
46 fprintf(stderr, "e1000: " fmt, ##params); \
47 } while (0)
48 #else
49 #define DBGOUT(what, fmt, params...) do {} while (0)
50 #endif
51
52 #define IOPORT_SIZE 0x40
53 #define PNPMMIO_SIZE 0x20000
54
55 /*
56 * HW models:
57 * E1000_DEV_ID_82540EM works with Windows and Linux
58 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
59 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
60 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
61 * Others never tested
62 */
63 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
64
65 /*
66 * May need to specify additional MAC-to-PHY entries --
67 * Intel's Windows driver refuses to initialize unless they match
68 */
69 enum {
70 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
71 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
72 /* default to E1000_DEV_ID_82540EM */ 0xc20
73 };
74
75 typedef struct E1000State_st {
76 PCIDevice dev;
77 VLANClientState *vc;
78 NICInfo *nd;
79 uint32_t mmio_base;
80 int mmio_index;
81
82 uint32_t mac_reg[0x8000];
83 uint16_t phy_reg[0x20];
84 uint16_t eeprom_data[64];
85
86 uint32_t rxbuf_size;
87 uint32_t rxbuf_min_shift;
88 int check_rxov;
89 struct e1000_tx {
90 unsigned char header[256];
91 unsigned char vlan_header[4];
92 unsigned char vlan[4];
93 unsigned char data[0x10000];
94 uint16_t size;
95 unsigned char sum_needed;
96 unsigned char vlan_needed;
97 uint8_t ipcss;
98 uint8_t ipcso;
99 uint16_t ipcse;
100 uint8_t tucss;
101 uint8_t tucso;
102 uint16_t tucse;
103 uint8_t hdr_len;
104 uint16_t mss;
105 uint32_t paylen;
106 uint16_t tso_frames;
107 char tse;
108 int8_t ip;
109 int8_t tcp;
110 char cptse; // current packet tse bit
111 } tx;
112
113 struct {
114 uint32_t val_in; // shifted in from guest driver
115 uint16_t bitnum_in;
116 uint16_t bitnum_out;
117 uint16_t reading;
118 uint32_t old_eecd;
119 } eecd_state;
120 } E1000State;
121
122 #define defreg(x) x = (E1000_##x>>2)
123 enum {
124 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
125 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
126 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
127 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
128 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
129 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
130 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
131 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
132 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
133 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
134 defreg(VET),
135 };
136
137 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
138 static const char phy_regcap[0x20] = {
139 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
140 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
141 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
142 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
143 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
144 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
145 };
146
147 static void
148 ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
149 uint32_t size, int type)
150 {
151 DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
152 }
153
154 static void
155 set_interrupt_cause(E1000State *s, int index, uint32_t val)
156 {
157 if (val)
158 val |= E1000_ICR_INT_ASSERTED;
159 s->mac_reg[ICR] = val;
160 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
161 }
162
163 static void
164 set_ics(E1000State *s, int index, uint32_t val)
165 {
166 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
167 s->mac_reg[IMS]);
168 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
169 }
170
171 static int
172 rxbufsize(uint32_t v)
173 {
174 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
175 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
176 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
177 switch (v) {
178 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
179 return 16384;
180 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
181 return 8192;
182 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
183 return 4096;
184 case E1000_RCTL_SZ_1024:
185 return 1024;
186 case E1000_RCTL_SZ_512:
187 return 512;
188 case E1000_RCTL_SZ_256:
189 return 256;
190 }
191 return 2048;
192 }
193
194 static void
195 set_rx_control(E1000State *s, int index, uint32_t val)
196 {
197 s->mac_reg[RCTL] = val;
198 s->rxbuf_size = rxbufsize(val);
199 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
200 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
201 s->mac_reg[RCTL]);
202 }
203
204 static void
205 set_mdic(E1000State *s, int index, uint32_t val)
206 {
207 uint32_t data = val & E1000_MDIC_DATA_MASK;
208 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
209
210 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
211 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
212 else if (val & E1000_MDIC_OP_READ) {
213 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
214 if (!(phy_regcap[addr] & PHY_R)) {
215 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
216 val |= E1000_MDIC_ERROR;
217 } else
218 val = (val ^ data) | s->phy_reg[addr];
219 } else if (val & E1000_MDIC_OP_WRITE) {
220 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
221 if (!(phy_regcap[addr] & PHY_W)) {
222 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
223 val |= E1000_MDIC_ERROR;
224 } else
225 s->phy_reg[addr] = data;
226 }
227 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
228 set_ics(s, 0, E1000_ICR_MDAC);
229 }
230
231 static uint32_t
232 get_eecd(E1000State *s, int index)
233 {
234 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
235
236 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
237 s->eecd_state.bitnum_out, s->eecd_state.reading);
238 if (!s->eecd_state.reading ||
239 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
240 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
241 ret |= E1000_EECD_DO;
242 return ret;
243 }
244
245 static void
246 set_eecd(E1000State *s, int index, uint32_t val)
247 {
248 uint32_t oldval = s->eecd_state.old_eecd;
249
250 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
251 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
252 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
253 return;
254 if (!(E1000_EECD_SK & val)) { // falling edge
255 s->eecd_state.bitnum_out++;
256 return;
257 }
258 if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset)
259 memset(&s->eecd_state, 0, sizeof s->eecd_state);
260 return;
261 }
262 s->eecd_state.val_in <<= 1;
263 if (val & E1000_EECD_DI)
264 s->eecd_state.val_in |= 1;
265 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
266 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
267 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
268 EEPROM_READ_OPCODE_MICROWIRE);
269 }
270 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
271 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
272 s->eecd_state.reading);
273 }
274
275 static uint32_t
276 flash_eerd_read(E1000State *s, int x)
277 {
278 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
279
280 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
281 return 0;
282 return (s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
283 E1000_EEPROM_RW_REG_DONE | r;
284 }
285
286 static void
287 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
288 {
289 uint32_t sum;
290
291 if (cse && cse < n)
292 n = cse + 1;
293 if (sloc < n-1) {
294 sum = net_checksum_add(n-css, data+css);
295 cpu_to_be16wu((uint16_t *)(data + sloc),
296 net_checksum_finish(sum));
297 }
298 }
299
300 static inline int
301 vlan_enabled(E1000State *s)
302 {
303 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
304 }
305
306 static inline int
307 vlan_rx_filter_enabled(E1000State *s)
308 {
309 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
310 }
311
312 static inline int
313 is_vlan_packet(E1000State *s, const uint8_t *buf)
314 {
315 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
316 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
317 }
318
319 static inline int
320 is_vlan_txd(uint32_t txd_lower)
321 {
322 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
323 }
324
325 static void
326 xmit_seg(E1000State *s)
327 {
328 uint16_t len, *sp;
329 unsigned int frames = s->tx.tso_frames, css, sofar, n;
330 struct e1000_tx *tp = &s->tx;
331
332 if (tp->tse && tp->cptse) {
333 css = tp->ipcss;
334 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
335 frames, tp->size, css);
336 if (tp->ip) { // IPv4
337 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
338 tp->size - css);
339 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
340 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
341 } else // IPv6
342 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
343 tp->size - css);
344 css = tp->tucss;
345 len = tp->size - css;
346 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
347 if (tp->tcp) {
348 sofar = frames * tp->mss;
349 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
350 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
351 if (tp->paylen - sofar > tp->mss)
352 tp->data[css + 13] &= ~9; // PSH, FIN
353 } else // UDP
354 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
355 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
356 // add pseudo-header length before checksum calculation
357 sp = (uint16_t *)(tp->data + tp->tucso);
358 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
359 }
360 tp->tso_frames++;
361 }
362
363 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
364 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
365 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
366 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
367 if (tp->vlan_needed) {
368 memmove(tp->vlan, tp->data, 12);
369 memcpy(tp->data + 8, tp->vlan_header, 4);
370 qemu_send_packet(s->vc, tp->vlan, tp->size + 4);
371 } else
372 qemu_send_packet(s->vc, tp->data, tp->size);
373 s->mac_reg[TPT]++;
374 s->mac_reg[GPTC]++;
375 n = s->mac_reg[TOTL];
376 if ((s->mac_reg[TOTL] += s->tx.size) < n)
377 s->mac_reg[TOTH]++;
378 }
379
380 static void
381 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
382 {
383 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
384 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
385 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
386 unsigned int msh = 0xfffff, hdr = 0;
387 uint64_t addr;
388 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
389 struct e1000_tx *tp = &s->tx;
390
391 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
392 op = le32_to_cpu(xp->cmd_and_length);
393 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
394 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
395 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
396 tp->tucss = xp->upper_setup.tcp_fields.tucss;
397 tp->tucso = xp->upper_setup.tcp_fields.tucso;
398 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
399 tp->paylen = op & 0xfffff;
400 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
401 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
402 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
403 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
404 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
405 tp->tso_frames = 0;
406 if (tp->tucso == 0) { // this is probably wrong
407 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
408 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
409 }
410 return;
411 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
412 // data descriptor
413 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
414 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
415 } else
416 // legacy descriptor
417 tp->cptse = 0;
418
419 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
420 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
421 tp->vlan_needed = 1;
422 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
423 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
424 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
425 le16_to_cpu(dp->upper.fields.special));
426 }
427
428 addr = le64_to_cpu(dp->buffer_addr);
429 if (tp->tse && tp->cptse) {
430 hdr = tp->hdr_len;
431 msh = hdr + tp->mss;
432 do {
433 bytes = split_size;
434 if (tp->size + bytes > msh)
435 bytes = msh - tp->size;
436 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
437 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
438 memmove(tp->header, tp->data, hdr);
439 tp->size = sz;
440 addr += bytes;
441 if (sz == msh) {
442 xmit_seg(s);
443 memmove(tp->data, tp->header, hdr);
444 tp->size = hdr;
445 }
446 } while (split_size -= bytes);
447 } else if (!tp->tse && tp->cptse) {
448 // context descriptor TSE is not set, while data descriptor TSE is set
449 DBGOUT(TXERR, "TCP segmentaion Error\n");
450 } else {
451 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
452 tp->size += split_size;
453 }
454
455 if (!(txd_lower & E1000_TXD_CMD_EOP))
456 return;
457 if (!(tp->tse && tp->cptse && tp->size < hdr))
458 xmit_seg(s);
459 tp->tso_frames = 0;
460 tp->sum_needed = 0;
461 tp->vlan_needed = 0;
462 tp->size = 0;
463 tp->cptse = 0;
464 }
465
466 static uint32_t
467 txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
468 {
469 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
470
471 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
472 return 0;
473 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
474 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
475 dp->upper.data = cpu_to_le32(txd_upper);
476 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
477 (void *)&dp->upper, sizeof(dp->upper));
478 return E1000_ICR_TXDW;
479 }
480
481 static void
482 start_xmit(E1000State *s)
483 {
484 target_phys_addr_t base;
485 struct e1000_tx_desc desc;
486 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
487
488 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
489 DBGOUT(TX, "tx disabled\n");
490 return;
491 }
492
493 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
494 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
495 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
496 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
497
498 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
499 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
500 desc.upper.data);
501
502 process_tx_desc(s, &desc);
503 cause |= txdesc_writeback(base, &desc);
504
505 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
506 s->mac_reg[TDH] = 0;
507 /*
508 * the following could happen only if guest sw assigns
509 * bogus values to TDT/TDLEN.
510 * there's nothing too intelligent we could do about this.
511 */
512 if (s->mac_reg[TDH] == tdh_start) {
513 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
514 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
515 break;
516 }
517 }
518 set_ics(s, 0, cause);
519 }
520
521 static int
522 receive_filter(E1000State *s, const uint8_t *buf, int size)
523 {
524 static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
525 static int mta_shift[] = {4, 3, 2, 0};
526 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
527
528 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
529 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
530 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
531 ((vid >> 5) & 0x7f));
532 if ((vfta & (1 << (vid & 0x1f))) == 0)
533 return 0;
534 }
535
536 if (rctl & E1000_RCTL_UPE) // promiscuous
537 return 1;
538
539 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
540 return 1;
541
542 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
543 return 1;
544
545 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
546 if (!(rp[1] & E1000_RAH_AV))
547 continue;
548 ra[0] = cpu_to_le32(rp[0]);
549 ra[1] = cpu_to_le32(rp[1]);
550 if (!memcmp(buf, (uint8_t *)ra, 6)) {
551 DBGOUT(RXFILTER,
552 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
553 (int)(rp - s->mac_reg - RA)/2,
554 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
555 return 1;
556 }
557 }
558 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
559 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
560
561 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
562 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
563 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
564 return 1;
565 DBGOUT(RXFILTER,
566 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
567 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
568 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
569 s->mac_reg[MTA + (f >> 5)]);
570
571 return 0;
572 }
573
574 static int
575 e1000_can_receive(void *opaque)
576 {
577 E1000State *s = opaque;
578
579 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
580 }
581
582 static void
583 e1000_receive(void *opaque, const uint8_t *buf, int size)
584 {
585 E1000State *s = opaque;
586 struct e1000_rx_desc desc;
587 target_phys_addr_t base;
588 unsigned int n, rdt;
589 uint32_t rdh_start;
590 uint16_t vlan_special = 0;
591 uint8_t vlan_status = 0, vlan_offset = 0;
592
593 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
594 return;
595
596 if (size > s->rxbuf_size) {
597 DBGOUT(RX, "packet too large for buffers (%d > %d)\n", size,
598 s->rxbuf_size);
599 return;
600 }
601
602 if (!receive_filter(s, buf, size))
603 return;
604
605 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
606 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
607 memmove((void *)(buf + 4), buf, 12);
608 vlan_status = E1000_RXD_STAT_VP;
609 vlan_offset = 4;
610 size -= 4;
611 }
612
613 rdh_start = s->mac_reg[RDH];
614 size += 4; // for the header
615 do {
616 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
617 set_ics(s, 0, E1000_ICS_RXO);
618 return;
619 }
620 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
621 sizeof(desc) * s->mac_reg[RDH];
622 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
623 desc.special = vlan_special;
624 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
625 if (desc.buffer_addr) {
626 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
627 (void *)(buf + vlan_offset), size);
628 desc.length = cpu_to_le16(size);
629 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
630 } else // as per intel docs; skip descriptors with null buf addr
631 DBGOUT(RX, "Null RX descriptor!!\n");
632 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
633
634 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
635 s->mac_reg[RDH] = 0;
636 s->check_rxov = 1;
637 /* see comment in start_xmit; same here */
638 if (s->mac_reg[RDH] == rdh_start) {
639 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
640 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
641 set_ics(s, 0, E1000_ICS_RXO);
642 return;
643 }
644 } while (desc.buffer_addr == 0);
645
646 s->mac_reg[GPRC]++;
647 s->mac_reg[TPR]++;
648 n = s->mac_reg[TORL];
649 if ((s->mac_reg[TORL] += size) < n)
650 s->mac_reg[TORH]++;
651
652 n = E1000_ICS_RXT0;
653 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
654 rdt += s->mac_reg[RDLEN] / sizeof(desc);
655 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) << s->rxbuf_min_shift >=
656 s->mac_reg[RDLEN])
657 n |= E1000_ICS_RXDMT0;
658
659 set_ics(s, 0, n);
660 }
661
662 static uint32_t
663 mac_readreg(E1000State *s, int index)
664 {
665 return s->mac_reg[index];
666 }
667
668 static uint32_t
669 mac_icr_read(E1000State *s, int index)
670 {
671 uint32_t ret = s->mac_reg[ICR];
672
673 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
674 set_interrupt_cause(s, 0, 0);
675 return ret;
676 }
677
678 static uint32_t
679 mac_read_clr4(E1000State *s, int index)
680 {
681 uint32_t ret = s->mac_reg[index];
682
683 s->mac_reg[index] = 0;
684 return ret;
685 }
686
687 static uint32_t
688 mac_read_clr8(E1000State *s, int index)
689 {
690 uint32_t ret = s->mac_reg[index];
691
692 s->mac_reg[index] = 0;
693 s->mac_reg[index-1] = 0;
694 return ret;
695 }
696
697 static void
698 mac_writereg(E1000State *s, int index, uint32_t val)
699 {
700 s->mac_reg[index] = val;
701 }
702
703 static void
704 set_rdt(E1000State *s, int index, uint32_t val)
705 {
706 s->check_rxov = 0;
707 s->mac_reg[index] = val & 0xffff;
708 }
709
710 static void
711 set_16bit(E1000State *s, int index, uint32_t val)
712 {
713 s->mac_reg[index] = val & 0xffff;
714 }
715
716 static void
717 set_dlen(E1000State *s, int index, uint32_t val)
718 {
719 s->mac_reg[index] = val & 0xfff80;
720 }
721
722 static void
723 set_tctl(E1000State *s, int index, uint32_t val)
724 {
725 s->mac_reg[index] = val;
726 s->mac_reg[TDT] &= 0xffff;
727 start_xmit(s);
728 }
729
730 static void
731 set_icr(E1000State *s, int index, uint32_t val)
732 {
733 DBGOUT(INTERRUPT, "set_icr %x\n", val);
734 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
735 }
736
737 static void
738 set_imc(E1000State *s, int index, uint32_t val)
739 {
740 s->mac_reg[IMS] &= ~val;
741 set_ics(s, 0, 0);
742 }
743
744 static void
745 set_ims(E1000State *s, int index, uint32_t val)
746 {
747 s->mac_reg[IMS] |= val;
748 set_ics(s, 0, 0);
749 }
750
751 #define getreg(x) [x] = mac_readreg
752 static uint32_t (*macreg_readops[])(E1000State *, int) = {
753 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
754 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
755 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
756 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
757 getreg(RDH), getreg(RDT), getreg(VET),
758
759 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
760 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
761 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
762 [CRCERRS ... MPC] = &mac_readreg,
763 [RA ... RA+31] = &mac_readreg,
764 [MTA ... MTA+127] = &mac_readreg,
765 [VFTA ... VFTA+127] = &mac_readreg,
766 };
767 enum { NREADOPS = sizeof(macreg_readops) / sizeof(*macreg_readops) };
768
769 #define putreg(x) [x] = mac_writereg
770 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
771 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
772 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
773 putreg(RDBAL), putreg(LEDCTL), putreg(CTRL), putreg(VET),
774 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
775 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
776 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
777 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
778 [EECD] = set_eecd, [RCTL] = set_rx_control,
779 [RA ... RA+31] = &mac_writereg,
780 [MTA ... MTA+127] = &mac_writereg,
781 [VFTA ... VFTA+127] = &mac_writereg,
782 };
783 enum { NWRITEOPS = sizeof(macreg_writeops) / sizeof(*macreg_writeops) };
784
785 static void
786 e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
787 {
788 E1000State *s = opaque;
789 unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
790
791 #ifdef TARGET_WORDS_BIGENDIAN
792 val = bswap32(val);
793 #endif
794 if (index < NWRITEOPS && macreg_writeops[index])
795 macreg_writeops[index](s, index, val);
796 else if (index < NREADOPS && macreg_readops[index])
797 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
798 else
799 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
800 index<<2, val);
801 }
802
803 static void
804 e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
805 {
806 // emulate hw without byte enables: no RMW
807 e1000_mmio_writel(opaque, addr & ~3,
808 (val & 0xffff) << (8*(addr & 3)));
809 }
810
811 static void
812 e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
813 {
814 // emulate hw without byte enables: no RMW
815 e1000_mmio_writel(opaque, addr & ~3,
816 (val & 0xff) << (8*(addr & 3)));
817 }
818
819 static uint32_t
820 e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
821 {
822 E1000State *s = opaque;
823 unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
824
825 if (index < NREADOPS && macreg_readops[index])
826 {
827 uint32_t val = macreg_readops[index](s, index);
828 #ifdef TARGET_WORDS_BIGENDIAN
829 val = bswap32(val);
830 #endif
831 return val;
832 }
833 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
834 return 0;
835 }
836
837 static uint32_t
838 e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
839 {
840 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
841 (8 * (addr & 3))) & 0xff;
842 }
843
844 static uint32_t
845 e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
846 {
847 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
848 (8 * (addr & 3))) & 0xffff;
849 }
850
851 static const int mac_regtosave[] = {
852 CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS,
853 LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH,
854 RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN,
855 TDT, TORH, TORL, TOTH, TOTL, TPR, TPT, TXDCTL, WUFC,
856 VET,
857 };
858 enum { MAC_NSAVE = sizeof mac_regtosave/sizeof *mac_regtosave };
859
860 static const struct {
861 int size;
862 int array0;
863 } mac_regarraystosave[] = { {32, RA}, {128, MTA}, {128, VFTA} };
864 enum { MAC_NARRAYS = sizeof mac_regarraystosave/sizeof *mac_regarraystosave };
865
866 static void
867 nic_save(QEMUFile *f, void *opaque)
868 {
869 E1000State *s = (E1000State *)opaque;
870 int i, j;
871
872 pci_device_save(&s->dev, f);
873 qemu_put_be32s(f, &s->mmio_base);
874 qemu_put_be32s(f, &s->rxbuf_size);
875 qemu_put_be32s(f, &s->rxbuf_min_shift);
876 qemu_put_be32s(f, &s->eecd_state.val_in);
877 qemu_put_be16s(f, &s->eecd_state.bitnum_in);
878 qemu_put_be16s(f, &s->eecd_state.bitnum_out);
879 qemu_put_be16s(f, &s->eecd_state.reading);
880 qemu_put_be32s(f, &s->eecd_state.old_eecd);
881 qemu_put_8s(f, &s->tx.ipcss);
882 qemu_put_8s(f, &s->tx.ipcso);
883 qemu_put_be16s(f, &s->tx.ipcse);
884 qemu_put_8s(f, &s->tx.tucss);
885 qemu_put_8s(f, &s->tx.tucso);
886 qemu_put_be16s(f, &s->tx.tucse);
887 qemu_put_be32s(f, &s->tx.paylen);
888 qemu_put_8s(f, &s->tx.hdr_len);
889 qemu_put_be16s(f, &s->tx.mss);
890 qemu_put_be16s(f, &s->tx.size);
891 qemu_put_be16s(f, &s->tx.tso_frames);
892 qemu_put_8s(f, &s->tx.sum_needed);
893 qemu_put_s8s(f, &s->tx.ip);
894 qemu_put_s8s(f, &s->tx.tcp);
895 qemu_put_buffer(f, s->tx.header, sizeof s->tx.header);
896 qemu_put_buffer(f, s->tx.data, sizeof s->tx.data);
897 for (i = 0; i < 64; i++)
898 qemu_put_be16s(f, s->eeprom_data + i);
899 for (i = 0; i < 0x20; i++)
900 qemu_put_be16s(f, s->phy_reg + i);
901 for (i = 0; i < MAC_NSAVE; i++)
902 qemu_put_be32s(f, s->mac_reg + mac_regtosave[i]);
903 for (i = 0; i < MAC_NARRAYS; i++)
904 for (j = 0; j < mac_regarraystosave[i].size; j++)
905 qemu_put_be32s(f,
906 s->mac_reg + mac_regarraystosave[i].array0 + j);
907 }
908
909 static int
910 nic_load(QEMUFile *f, void *opaque, int version_id)
911 {
912 E1000State *s = (E1000State *)opaque;
913 int i, j, ret;
914
915 if ((ret = pci_device_load(&s->dev, f)) < 0)
916 return ret;
917 if (version_id == 1)
918 qemu_get_sbe32s(f, &i); /* once some unused instance id */
919 qemu_get_be32s(f, &s->mmio_base);
920 qemu_get_be32s(f, &s->rxbuf_size);
921 qemu_get_be32s(f, &s->rxbuf_min_shift);
922 qemu_get_be32s(f, &s->eecd_state.val_in);
923 qemu_get_be16s(f, &s->eecd_state.bitnum_in);
924 qemu_get_be16s(f, &s->eecd_state.bitnum_out);
925 qemu_get_be16s(f, &s->eecd_state.reading);
926 qemu_get_be32s(f, &s->eecd_state.old_eecd);
927 qemu_get_8s(f, &s->tx.ipcss);
928 qemu_get_8s(f, &s->tx.ipcso);
929 qemu_get_be16s(f, &s->tx.ipcse);
930 qemu_get_8s(f, &s->tx.tucss);
931 qemu_get_8s(f, &s->tx.tucso);
932 qemu_get_be16s(f, &s->tx.tucse);
933 qemu_get_be32s(f, &s->tx.paylen);
934 qemu_get_8s(f, &s->tx.hdr_len);
935 qemu_get_be16s(f, &s->tx.mss);
936 qemu_get_be16s(f, &s->tx.size);
937 qemu_get_be16s(f, &s->tx.tso_frames);
938 qemu_get_8s(f, &s->tx.sum_needed);
939 qemu_get_s8s(f, &s->tx.ip);
940 qemu_get_s8s(f, &s->tx.tcp);
941 qemu_get_buffer(f, s->tx.header, sizeof s->tx.header);
942 qemu_get_buffer(f, s->tx.data, sizeof s->tx.data);
943 for (i = 0; i < 64; i++)
944 qemu_get_be16s(f, s->eeprom_data + i);
945 for (i = 0; i < 0x20; i++)
946 qemu_get_be16s(f, s->phy_reg + i);
947 for (i = 0; i < MAC_NSAVE; i++)
948 qemu_get_be32s(f, s->mac_reg + mac_regtosave[i]);
949 for (i = 0; i < MAC_NARRAYS; i++)
950 for (j = 0; j < mac_regarraystosave[i].size; j++)
951 qemu_get_be32s(f,
952 s->mac_reg + mac_regarraystosave[i].array0 + j);
953 return 0;
954 }
955
956 static const uint16_t e1000_eeprom_template[64] = {
957 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
958 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
959 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
960 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
961 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
962 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
963 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
964 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
965 };
966
967 static const uint16_t phy_reg_init[] = {
968 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
969 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
970 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
971 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
972 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
973 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
974 };
975
976 static const uint32_t mac_reg_init[] = {
977 [PBA] = 0x00100030,
978 [LEDCTL] = 0x602,
979 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
980 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
981 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
982 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
983 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
984 E1000_STATUS_LU,
985 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
986 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
987 E1000_MANC_RMCP_EN,
988 };
989
990 /* PCI interface */
991
992 static CPUWriteMemoryFunc *e1000_mmio_write[] = {
993 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
994 };
995
996 static CPUReadMemoryFunc *e1000_mmio_read[] = {
997 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
998 };
999
1000 static void
1001 e1000_mmio_map(PCIDevice *pci_dev, int region_num,
1002 uint32_t addr, uint32_t size, int type)
1003 {
1004 E1000State *d = (E1000State *)pci_dev;
1005
1006 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
1007
1008 d->mmio_base = addr;
1009 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
1010 }
1011
1012 void
1013 pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn)
1014 {
1015 E1000State *d;
1016 uint8_t *pci_conf;
1017 uint16_t checksum = 0;
1018 static const char info_str[] = "e1000";
1019 int i;
1020
1021 d = (E1000State *)pci_register_device(bus, "e1000",
1022 sizeof(E1000State), devfn, NULL, NULL);
1023
1024 pci_conf = d->dev.config;
1025 memset(pci_conf, 0, 256);
1026
1027 *(uint16_t *)(pci_conf+0x00) = cpu_to_le16(0x8086);
1028 *(uint16_t *)(pci_conf+0x02) = cpu_to_le16(E1000_DEVID);
1029 *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407);
1030 *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010);
1031 pci_conf[0x08] = 0x03;
1032 pci_conf[0x0a] = 0x00; // ethernet network controller
1033 pci_conf[0x0b] = 0x02;
1034 pci_conf[0x0c] = 0x10;
1035
1036 pci_conf[0x3d] = 1; // interrupt pin 0
1037
1038 d->mmio_index = cpu_register_io_memory(0, e1000_mmio_read,
1039 e1000_mmio_write, d);
1040
1041 pci_register_io_region((PCIDevice *)d, 0, PNPMMIO_SIZE,
1042 PCI_ADDRESS_SPACE_MEM, e1000_mmio_map);
1043
1044 pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,
1045 PCI_ADDRESS_SPACE_IO, ioport_map);
1046
1047 d->nd = nd;
1048 memmove(d->eeprom_data, e1000_eeprom_template,
1049 sizeof e1000_eeprom_template);
1050 for (i = 0; i < 3; i++)
1051 d->eeprom_data[i] = (nd->macaddr[2*i+1]<<8) | nd->macaddr[2*i];
1052 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1053 checksum += d->eeprom_data[i];
1054 checksum = (uint16_t) EEPROM_SUM - checksum;
1055 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1056
1057 memset(d->phy_reg, 0, sizeof d->phy_reg);
1058 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1059 memset(d->mac_reg, 0, sizeof d->mac_reg);
1060 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1061 d->rxbuf_min_shift = 1;
1062 memset(&d->tx, 0, sizeof d->tx);
1063
1064 d->vc = qemu_new_vlan_client(nd->vlan, e1000_receive,
1065 e1000_can_receive, d);
1066
1067 snprintf(d->vc->info_str, sizeof(d->vc->info_str),
1068 "%s macaddr=%02x:%02x:%02x:%02x:%02x:%02x", info_str,
1069 d->nd->macaddr[0], d->nd->macaddr[1], d->nd->macaddr[2],
1070 d->nd->macaddr[3], d->nd->macaddr[4], d->nd->macaddr[5]);
1071
1072 register_savevm(info_str, -1, 2, nic_save, nic_load, d);
1073 }
Samsung s3c2440 and arm920t support for the mini2440 dev board