hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33
  34 #define BIOS_FILENAME "ppc405_rom.bin"
  35 #define BIOS_SIZE (2048 * 1024)
  36
  37 #define KERNEL_LOAD_ADDR 0x00000000
  38 #define INITRD_LOAD_ADDR 0x01800000
  39
  40 #define USE_FLASH_BIOS
  41
  42 #define DEBUG_BOARD_INIT
  43
  44 /*****************************************************************************/
  45 /* PPC405EP reference board (IBM) */
  46 /* Standalone board with:
  47  * - PowerPC 405EP CPU
  48  * - SDRAM (0x00000000)
  49  * - Flash (0xFFF80000)
  50  * - SRAM  (0xFFF00000)
  51  * - NVRAM (0xF0000000)
  52  * - FPGA  (0xF0300000)
  53  */
  54 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  55 struct ref405ep_fpga_t {
  56     uint8_t reg0;
  57     uint8_t reg1;
  58 };
  59
  60 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  61 {
  62     ref405ep_fpga_t *fpga;
  63     uint32_t ret;
  64
  65     fpga = opaque;
  66     switch (addr) {
  67     case 0x0:
  68         ret = fpga->reg0;
  69         break;
  70     case 0x1:
  71         ret = fpga->reg1;
  72         break;
  73     default:
  74         ret = 0;
  75         break;
  76     }
  77
  78     return ret;
  79 }
  80
  81 static void ref405ep_fpga_writeb (void *opaque,
  82                                   target_phys_addr_t addr, uint32_t value)
  83 {
  84     ref405ep_fpga_t *fpga;
  85
  86     fpga = opaque;
  87     switch (addr) {
  88     case 0x0:
  89         /* Read only */
  90         break;
  91     case 0x1:
  92         fpga->reg1 = value;
  93         break;
  94     default:
  95         break;
  96     }
  97 }
  98
  99 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 100 {
 101     uint32_t ret;
 102
 103     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 104     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 105
 106     return ret;
 107 }
 108
 109 static void ref405ep_fpga_writew (void *opaque,
 110                                   target_phys_addr_t addr, uint32_t value)
 111 {
 112     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 113     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 114 }
 115
 116 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 117 {
 118     uint32_t ret;
 119
 120     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 121     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 122     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 123     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 124
 125     return ret;
 126 }
 127
 128 static void ref405ep_fpga_writel (void *opaque,
 129                                   target_phys_addr_t addr, uint32_t value)
 130 {
 131     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 132     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 133     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 134     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 135 }
 136
 137 static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
 138     &ref405ep_fpga_readb,
 139     &ref405ep_fpga_readw,
 140     &ref405ep_fpga_readl,
 141 };
 142
 143 static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
 144     &ref405ep_fpga_writeb,
 145     &ref405ep_fpga_writew,
 146     &ref405ep_fpga_writel,
 147 };
 148
 149 static void ref405ep_fpga_reset (void *opaque)
 150 {
 151     ref405ep_fpga_t *fpga;
 152
 153     fpga = opaque;
 154     fpga->reg0 = 0x00;
 155     fpga->reg1 = 0x0F;
 156 }
 157
 158 static void ref405ep_fpga_init (uint32_t base)
 159 {
 160     ref405ep_fpga_t *fpga;
 161     int fpga_memory;
 162
 163     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 164     fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
 165                                          ref405ep_fpga_write, fpga);
 166     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 167     ref405ep_fpga_reset(fpga);
 168     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 169 }
 170
 171 static void ref405ep_init (ram_addr_t ram_size,
 172                            const char *boot_device,
 173                            const char *kernel_filename,
 174                            const char *kernel_cmdline,
 175                            const char *initrd_filename,
 176                            const char *cpu_model)
 177 {
 178     char buf[1024];
 179     ppc4xx_bd_info_t bd;
 180     CPUPPCState *env;
 181     qemu_irq *pic;
 182     ram_addr_t sram_offset, bios_offset, bdloc;
 183     target_phys_addr_t ram_bases[2], ram_sizes[2];
 184     target_ulong sram_size, bios_size;
 185     //int phy_addr = 0;
 186     //static int phy_addr = 1;
 187     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 188     int linux_boot;
 189     int fl_idx, fl_sectors, len;
 190     int ppc_boot_device = boot_device[0];
 191     int index;
 192
 193     /* XXX: fix this */
 194     ram_bases[0] = qemu_ram_alloc(0x08000000);
 195     ram_sizes[0] = 0x08000000;
 196     ram_bases[1] = 0x00000000;
 197     ram_sizes[1] = 0x00000000;
 198     ram_size = 128 * 1024 * 1024;
 199 #ifdef DEBUG_BOARD_INIT
 200     printf("%s: register cpu\n", __func__);
 201 #endif
 202     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 203                         kernel_filename == NULL ? 0 : 1);
 204     /* allocate SRAM */
 205     sram_size = 512 * 1024;
 206     sram_offset = qemu_ram_alloc(sram_size);
 207 #ifdef DEBUG_BOARD_INIT
 208     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 209 #endif
 210     cpu_register_physical_memory(0xFFF00000, sram_size,
 211                                  sram_offset | IO_MEM_RAM);
 212     /* allocate and load BIOS */
 213 #ifdef DEBUG_BOARD_INIT
 214     printf("%s: register BIOS\n", __func__);
 215 #endif
 216     fl_idx = 0;
 217 #ifdef USE_FLASH_BIOS
 218     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 219     if (index != -1) {
 220         bios_size = bdrv_getlength(drives_table[index].bdrv);
 221         bios_offset = qemu_ram_alloc(bios_size);
 222         fl_sectors = (bios_size + 65535) >> 16;
 223 #ifdef DEBUG_BOARD_INIT
 224         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 225                " addr " ADDRX " '%s' %d\n",
 226                fl_idx, bios_size, bios_offset, -bios_size,
 227                bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
 228 #endif
 229         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 230                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 231                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 232         fl_idx++;
 233     } else
 234 #endif
 235     {
 236 #ifdef DEBUG_BOARD_INIT
 237         printf("Load BIOS from file\n");
 238 #endif
 239         if (bios_name == NULL)
 240             bios_name = BIOS_FILENAME;
 241         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 242         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 243         bios_size = load_image(buf, qemu_get_ram_ptr(bios_offset));
 244         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 245             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
 246             exit(1);
 247         }
 248         bios_size = (bios_size + 0xfff) & ~0xfff;
 249         cpu_register_physical_memory((uint32_t)(-bios_size),
 250                                      bios_size, bios_offset | IO_MEM_ROM);
 251     }
 252     /* Register FPGA */
 253 #ifdef DEBUG_BOARD_INIT
 254     printf("%s: register FPGA\n", __func__);
 255 #endif
 256     ref405ep_fpga_init(0xF0300000);
 257     /* Register NVRAM */
 258 #ifdef DEBUG_BOARD_INIT
 259     printf("%s: register NVRAM\n", __func__);
 260 #endif
 261     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 262     /* Load kernel */
 263     linux_boot = (kernel_filename != NULL);
 264     if (linux_boot) {
 265 #ifdef DEBUG_BOARD_INIT
 266         printf("%s: load kernel\n", __func__);
 267 #endif
 268         memset(&bd, 0, sizeof(bd));
 269         bd.bi_memstart = 0x00000000;
 270         bd.bi_memsize = ram_size;
 271         bd.bi_flashstart = -bios_size;
 272         bd.bi_flashsize = -bios_size;
 273         bd.bi_flashoffset = 0;
 274         bd.bi_sramstart = 0xFFF00000;
 275         bd.bi_sramsize = sram_size;
 276         bd.bi_bootflags = 0;
 277         bd.bi_intfreq = 133333333;
 278         bd.bi_busfreq = 33333333;
 279         bd.bi_baudrate = 115200;
 280         bd.bi_s_version[0] = 'Q';
 281         bd.bi_s_version[1] = 'M';
 282         bd.bi_s_version[2] = 'U';
 283         bd.bi_s_version[3] = '\0';
 284         bd.bi_r_version[0] = 'Q';
 285         bd.bi_r_version[1] = 'E';
 286         bd.bi_r_version[2] = 'M';
 287         bd.bi_r_version[3] = 'U';
 288         bd.bi_r_version[4] = '\0';
 289         bd.bi_procfreq = 133333333;
 290         bd.bi_plb_busfreq = 33333333;
 291         bd.bi_pci_busfreq = 33333333;
 292         bd.bi_opbfreq = 33333333;
 293         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 294         env->gpr[3] = bdloc;
 295         kernel_base = KERNEL_LOAD_ADDR;
 296         /* now we can load the kernel */
 297         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 298                                           ram_size - kernel_base);
 299         if (kernel_size < 0) {
 300             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 301                     kernel_filename);
 302             exit(1);
 303         }
 304         printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
 305                kernel_size, kernel_base);
 306         /* load initrd */
 307         if (initrd_filename) {
 308             initrd_base = INITRD_LOAD_ADDR;
 309             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 310                                               ram_size - initrd_base);
 311             if (initrd_size < 0) {
 312                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 313                         initrd_filename);
 314                 exit(1);
 315             }
 316         } else {
 317             initrd_base = 0;
 318             initrd_size = 0;
 319         }
 320         env->gpr[4] = initrd_base;
 321         env->gpr[5] = initrd_size;
 322         ppc_boot_device = 'm';
 323         if (kernel_cmdline != NULL) {
 324             len = strlen(kernel_cmdline);
 325             bdloc -= ((len + 255) & ~255);
 326             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 327             env->gpr[6] = bdloc;
 328             env->gpr[7] = bdloc + len;
 329         } else {
 330             env->gpr[6] = 0;
 331             env->gpr[7] = 0;
 332         }
 333         env->nip = KERNEL_LOAD_ADDR;
 334     } else {
 335         kernel_base = 0;
 336         kernel_size = 0;
 337         initrd_base = 0;
 338         initrd_size = 0;
 339         bdloc = 0;
 340     }
 341 #ifdef DEBUG_BOARD_INIT
 342     printf("%s: Done\n", __func__);
 343 #endif
 344     printf("bdloc %016lx\n", (unsigned long)bdloc);
 345 }
 346
 347 QEMUMachine ref405ep_machine = {
 348     .name = "ref405ep",
 349     .desc = "ref405ep",
 350     .init = ref405ep_init,
 351 };
 352
 353 /*****************************************************************************/
 354 /* AMCC Taihu evaluation board */
 355 /* - PowerPC 405EP processor
 356  * - SDRAM               128 MB at 0x00000000
 357  * - Boot flash          2 MB   at 0xFFE00000
 358  * - Application flash   32 MB  at 0xFC000000
 359  * - 2 serial ports
 360  * - 2 ethernet PHY
 361  * - 1 USB 1.1 device    0x50000000
 362  * - 1 LCD display       0x50100000
 363  * - 1 CPLD              0x50100000
 364  * - 1 I2C EEPROM
 365  * - 1 I2C thermal sensor
 366  * - a set of LEDs
 367  * - bit-bang SPI port using GPIOs
 368  * - 1 EBC interface connector 0 0x50200000
 369  * - 1 cardbus controller + expansion slot.
 370  * - 1 PCI expansion slot.
 371  */
 372 typedef struct taihu_cpld_t taihu_cpld_t;
 373 struct taihu_cpld_t {
 374     uint8_t reg0;
 375     uint8_t reg1;
 376 };
 377
 378 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 379 {
 380     taihu_cpld_t *cpld;
 381     uint32_t ret;
 382
 383     cpld = opaque;
 384     switch (addr) {
 385     case 0x0:
 386         ret = cpld->reg0;
 387         break;
 388     case 0x1:
 389         ret = cpld->reg1;
 390         break;
 391     default:
 392         ret = 0;
 393         break;
 394     }
 395
 396     return ret;
 397 }
 398
 399 static void taihu_cpld_writeb (void *opaque,
 400                                target_phys_addr_t addr, uint32_t value)
 401 {
 402     taihu_cpld_t *cpld;
 403
 404     cpld = opaque;
 405     switch (addr) {
 406     case 0x0:
 407         /* Read only */
 408         break;
 409     case 0x1:
 410         cpld->reg1 = value;
 411         break;
 412     default:
 413         break;
 414     }
 415 }
 416
 417 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 418 {
 419     uint32_t ret;
 420
 421     ret = taihu_cpld_readb(opaque, addr) << 8;
 422     ret |= taihu_cpld_readb(opaque, addr + 1);
 423
 424     return ret;
 425 }
 426
 427 static void taihu_cpld_writew (void *opaque,
 428                                target_phys_addr_t addr, uint32_t value)
 429 {
 430     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 431     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 432 }
 433
 434 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 435 {
 436     uint32_t ret;
 437
 438     ret = taihu_cpld_readb(opaque, addr) << 24;
 439     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 440     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 441     ret |= taihu_cpld_readb(opaque, addr + 3);
 442
 443     return ret;
 444 }
 445
 446 static void taihu_cpld_writel (void *opaque,
 447                                target_phys_addr_t addr, uint32_t value)
 448 {
 449     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 450     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 451     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 452     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 453 }
 454
 455 static CPUReadMemoryFunc *taihu_cpld_read[] = {
 456     &taihu_cpld_readb,
 457     &taihu_cpld_readw,
 458     &taihu_cpld_readl,
 459 };
 460
 461 static CPUWriteMemoryFunc *taihu_cpld_write[] = {
 462     &taihu_cpld_writeb,
 463     &taihu_cpld_writew,
 464     &taihu_cpld_writel,
 465 };
 466
 467 static void taihu_cpld_reset (void *opaque)
 468 {
 469     taihu_cpld_t *cpld;
 470
 471     cpld = opaque;
 472     cpld->reg0 = 0x01;
 473     cpld->reg1 = 0x80;
 474 }
 475
 476 static void taihu_cpld_init (uint32_t base)
 477 {
 478     taihu_cpld_t *cpld;
 479     int cpld_memory;
 480
 481     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 482     cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
 483                                          taihu_cpld_write, cpld);
 484     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 485     taihu_cpld_reset(cpld);
 486     qemu_register_reset(&taihu_cpld_reset, cpld);
 487 }
 488
 489 static void taihu_405ep_init(ram_addr_t ram_size,
 490                              const char *boot_device,
 491                              const char *kernel_filename,
 492                              const char *kernel_cmdline,
 493                              const char *initrd_filename,
 494                              const char *cpu_model)
 495 {
 496     char buf[1024];
 497     CPUPPCState *env;
 498     qemu_irq *pic;
 499     ram_addr_t bios_offset;
 500     target_phys_addr_t ram_bases[2], ram_sizes[2];
 501     target_ulong bios_size;
 502     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 503     int linux_boot;
 504     int fl_idx, fl_sectors;
 505     int ppc_boot_device = boot_device[0];
 506     int index;
 507
 508     /* RAM is soldered to the board so the size cannot be changed */
 509     ram_bases[0] = qemu_ram_alloc(0x04000000);
 510     ram_sizes[0] = 0x04000000;
 511     ram_bases[1] = qemu_ram_alloc(0x04000000);
 512     ram_sizes[1] = 0x04000000;
 513     ram_size = 0x08000000;
 514 #ifdef DEBUG_BOARD_INIT
 515     printf("%s: register cpu\n", __func__);
 516 #endif
 517     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 518                         kernel_filename == NULL ? 0 : 1);
 519     /* allocate and load BIOS */
 520 #ifdef DEBUG_BOARD_INIT
 521     printf("%s: register BIOS\n", __func__);
 522 #endif
 523     fl_idx = 0;
 524 #if defined(USE_FLASH_BIOS)
 525     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 526     if (index != -1) {
 527         bios_size = bdrv_getlength(drives_table[index].bdrv);
 528         /* XXX: should check that size is 2MB */
 529         //        bios_size = 2 * 1024 * 1024;
 530         fl_sectors = (bios_size + 65535) >> 16;
 531         bios_offset = qemu_ram_alloc(bios_size);
 532 #ifdef DEBUG_BOARD_INIT
 533         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 534                " addr " ADDRX " '%s' %d\n",
 535                fl_idx, bios_size, bios_offset, -bios_size,
 536                bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
 537 #endif
 538         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 539                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 540                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 541         fl_idx++;
 542     } else
 543 #endif
 544     {
 545 #ifdef DEBUG_BOARD_INIT
 546         printf("Load BIOS from file\n");
 547 #endif
 548         if (bios_name == NULL)
 549             bios_name = BIOS_FILENAME;
 550         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 551         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 552         bios_size = load_image(buf, qemu_get_ram_ptr(bios_offset));
 553         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 554             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
 555             exit(1);
 556         }
 557         bios_size = (bios_size + 0xfff) & ~0xfff;
 558         cpu_register_physical_memory((uint32_t)(-bios_size),
 559                                      bios_size, bios_offset | IO_MEM_ROM);
 560     }
 561     /* Register Linux flash */
 562     index = drive_get_index(IF_PFLASH, 0, fl_idx);
 563     if (index != -1) {
 564         bios_size = bdrv_getlength(drives_table[index].bdrv);
 565         /* XXX: should check that size is 32MB */
 566         bios_size = 32 * 1024 * 1024;
 567         fl_sectors = (bios_size + 65535) >> 16;
 568 #ifdef DEBUG_BOARD_INIT
 569         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 570                " addr " ADDRX " '%s'\n",
 571                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 572                bdrv_get_device_name(drives_table[index].bdrv));
 573 #endif
 574         bios_offset = qemu_ram_alloc(bios_size);
 575         pflash_cfi02_register(0xfc000000, bios_offset,
 576                               drives_table[index].bdrv, 65536, fl_sectors, 1,
 577                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
 578         fl_idx++;
 579     }
 580     /* Register CLPD & LCD display */
 581 #ifdef DEBUG_BOARD_INIT
 582     printf("%s: register CPLD\n", __func__);
 583 #endif
 584     taihu_cpld_init(0x50100000);
 585     /* Load kernel */
 586     linux_boot = (kernel_filename != NULL);
 587     if (linux_boot) {
 588 #ifdef DEBUG_BOARD_INIT
 589         printf("%s: load kernel\n", __func__);
 590 #endif
 591         kernel_base = KERNEL_LOAD_ADDR;
 592         /* now we can load the kernel */
 593         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 594                                           ram_size - kernel_base);
 595         if (kernel_size < 0) {
 596             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 597                     kernel_filename);
 598             exit(1);
 599         }
 600         /* load initrd */
 601         if (initrd_filename) {
 602             initrd_base = INITRD_LOAD_ADDR;
 603             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 604                                               ram_size - initrd_base);
 605             if (initrd_size < 0) {
 606                 fprintf(stderr,
 607                         "qemu: could not load initial ram disk '%s'\n",
 608                         initrd_filename);
 609                 exit(1);
 610             }
 611         } else {
 612             initrd_base = 0;
 613             initrd_size = 0;
 614         }
 615         ppc_boot_device = 'm';
 616     } else {
 617         kernel_base = 0;
 618         kernel_size = 0;
 619         initrd_base = 0;
 620         initrd_size = 0;
 621     }
 622 #ifdef DEBUG_BOARD_INIT
 623     printf("%s: Done\n", __func__);
 624 #endif
 625 }
 626
 627 QEMUMachine taihu_machine = {
 628     .name = "taihu",
 629     .desc = "taihu",
 630     .init = taihu_405ep_init,
 631 };